nouveau_drv.h revision 573a2a37e8648a3249426c816f51e7ef50f6f73e
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58struct nouveau_grctx; 59 60#define MAX_NUM_DCB_ENTRIES 16 61 62#define NOUVEAU_MAX_CHANNEL_NR 128 63#define NOUVEAU_MAX_TILE_NR 15 64 65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 66#define NV50_VM_BLOCK (512*1024*1024ULL) 67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 68 69struct nouveau_vram { 70 struct drm_device *dev; 71 72 struct list_head regions; 73 u32 memtype; 74 u64 offset; 75 u64 size; 76}; 77 78struct nouveau_tile_reg { 79 bool used; 80 uint32_t addr; 81 uint32_t limit; 82 uint32_t pitch; 83 uint32_t zcomp; 84 struct drm_mm_node *tag_mem; 85 struct nouveau_fence *fence; 86}; 87 88struct nouveau_bo { 89 struct ttm_buffer_object bo; 90 struct ttm_placement placement; 91 u32 placements[3]; 92 u32 busy_placements[3]; 93 struct ttm_bo_kmap_obj kmap; 94 struct list_head head; 95 96 /* protected by ttm_bo_reserve() */ 97 struct drm_file *reserved_by; 98 struct list_head entry; 99 int pbbo_index; 100 bool validate_mapped; 101 102 struct nouveau_channel *channel; 103 104 bool mappable; 105 bool no_vm; 106 107 uint32_t tile_mode; 108 uint32_t tile_flags; 109 struct nouveau_tile_reg *tile; 110 111 struct drm_gem_object *gem; 112 int pin_refcnt; 113}; 114 115#define nouveau_bo_tile_layout(nvbo) \ 116 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 117 118static inline struct nouveau_bo * 119nouveau_bo(struct ttm_buffer_object *bo) 120{ 121 return container_of(bo, struct nouveau_bo, bo); 122} 123 124static inline struct nouveau_bo * 125nouveau_gem_object(struct drm_gem_object *gem) 126{ 127 return gem ? gem->driver_private : NULL; 128} 129 130/* TODO: submit equivalent to TTM generic API upstream? */ 131static inline void __iomem * 132nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 133{ 134 bool is_iomem; 135 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 136 &nvbo->kmap, &is_iomem); 137 WARN_ON_ONCE(ioptr && !is_iomem); 138 return ioptr; 139} 140 141enum nouveau_flags { 142 NV_NFORCE = 0x10000000, 143 NV_NFORCE2 = 0x20000000 144}; 145 146#define NVOBJ_ENGINE_SW 0 147#define NVOBJ_ENGINE_GR 1 148#define NVOBJ_ENGINE_PPP 2 149#define NVOBJ_ENGINE_COPY 3 150#define NVOBJ_ENGINE_VP 4 151#define NVOBJ_ENGINE_CRYPT 5 152#define NVOBJ_ENGINE_BSP 6 153#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 154#define NVOBJ_ENGINE_INT 0xdeadbeef 155 156#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 157#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 158 159#define NVOBJ_CINST_GLOBAL 0xdeadbeef 160 161struct nouveau_gpuobj { 162 struct drm_device *dev; 163 struct kref refcount; 164 struct list_head list; 165 166 void *node; 167 u32 *suspend; 168 169 uint32_t flags; 170 171 u32 size; 172 u32 pinst; 173 u32 cinst; 174 u64 vinst; 175 176 uint32_t engine; 177 uint32_t class; 178 179 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 180 void *priv; 181}; 182 183struct nouveau_page_flip_state { 184 struct list_head head; 185 struct drm_pending_vblank_event *event; 186 int crtc, bpp, pitch, x, y; 187 uint64_t offset; 188}; 189 190enum nouveau_channel_mutex_class { 191 NOUVEAU_UCHANNEL_MUTEX, 192 NOUVEAU_KCHANNEL_MUTEX 193}; 194 195struct nouveau_channel { 196 struct drm_device *dev; 197 int id; 198 199 /* references to the channel data structure */ 200 struct kref ref; 201 /* users of the hardware channel resources, the hardware 202 * context will be kicked off when it reaches zero. */ 203 atomic_t users; 204 struct mutex mutex; 205 206 /* owner of this fifo */ 207 struct drm_file *file_priv; 208 /* mapping of the fifo itself */ 209 struct drm_local_map *map; 210 211 /* mapping of the regs controling the fifo */ 212 void __iomem *user; 213 uint32_t user_get; 214 uint32_t user_put; 215 216 /* Fencing */ 217 struct { 218 /* lock protects the pending list only */ 219 spinlock_t lock; 220 struct list_head pending; 221 uint32_t sequence; 222 uint32_t sequence_ack; 223 atomic_t last_sequence_irq; 224 } fence; 225 226 /* DMA push buffer */ 227 struct nouveau_gpuobj *pushbuf; 228 struct nouveau_bo *pushbuf_bo; 229 uint32_t pushbuf_base; 230 231 /* Notifier memory */ 232 struct nouveau_bo *notifier_bo; 233 struct drm_mm notifier_heap; 234 235 /* PFIFO context */ 236 struct nouveau_gpuobj *ramfc; 237 struct nouveau_gpuobj *cache; 238 239 /* PGRAPH context */ 240 /* XXX may be merge 2 pointers as private data ??? */ 241 struct nouveau_gpuobj *ramin_grctx; 242 struct nouveau_gpuobj *crypt_ctx; 243 void *pgraph_ctx; 244 245 /* NV50 VM */ 246 struct nouveau_gpuobj *vm_pd; 247 struct nouveau_gpuobj *vm_gart_pt; 248 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 249 250 /* Objects */ 251 struct nouveau_gpuobj *ramin; /* Private instmem */ 252 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 253 struct nouveau_ramht *ramht; /* Hash table */ 254 255 /* GPU object info for stuff used in-kernel (mm_enabled) */ 256 uint32_t m2mf_ntfy; 257 uint32_t vram_handle; 258 uint32_t gart_handle; 259 bool accel_done; 260 261 /* Push buffer state (only for drm's channel on !mm_enabled) */ 262 struct { 263 int max; 264 int free; 265 int cur; 266 int put; 267 /* access via pushbuf_bo */ 268 269 int ib_base; 270 int ib_max; 271 int ib_free; 272 int ib_put; 273 } dma; 274 275 uint32_t sw_subchannel[8]; 276 277 struct { 278 struct nouveau_gpuobj *vblsem; 279 uint32_t vblsem_head; 280 uint32_t vblsem_offset; 281 uint32_t vblsem_rval; 282 struct list_head vbl_wait; 283 struct list_head flip; 284 } nvsw; 285 286 struct { 287 bool active; 288 char name[32]; 289 struct drm_info_list info; 290 } debugfs; 291}; 292 293struct nouveau_instmem_engine { 294 void *priv; 295 296 int (*init)(struct drm_device *dev); 297 void (*takedown)(struct drm_device *dev); 298 int (*suspend)(struct drm_device *dev); 299 void (*resume)(struct drm_device *dev); 300 301 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 302 void (*put)(struct nouveau_gpuobj *); 303 int (*map)(struct nouveau_gpuobj *); 304 void (*unmap)(struct nouveau_gpuobj *); 305 306 void (*flush)(struct drm_device *); 307}; 308 309struct nouveau_mc_engine { 310 int (*init)(struct drm_device *dev); 311 void (*takedown)(struct drm_device *dev); 312}; 313 314struct nouveau_timer_engine { 315 int (*init)(struct drm_device *dev); 316 void (*takedown)(struct drm_device *dev); 317 uint64_t (*read)(struct drm_device *dev); 318}; 319 320struct nouveau_fb_engine { 321 int num_tiles; 322 struct drm_mm tag_heap; 323 void *priv; 324 325 int (*init)(struct drm_device *dev); 326 void (*takedown)(struct drm_device *dev); 327 328 void (*init_tile_region)(struct drm_device *dev, int i, 329 uint32_t addr, uint32_t size, 330 uint32_t pitch, uint32_t flags); 331 void (*set_tile_region)(struct drm_device *dev, int i); 332 void (*free_tile_region)(struct drm_device *dev, int i); 333}; 334 335struct nouveau_fifo_engine { 336 int channels; 337 338 struct nouveau_gpuobj *playlist[2]; 339 int cur_playlist; 340 341 int (*init)(struct drm_device *); 342 void (*takedown)(struct drm_device *); 343 344 void (*disable)(struct drm_device *); 345 void (*enable)(struct drm_device *); 346 bool (*reassign)(struct drm_device *, bool enable); 347 bool (*cache_pull)(struct drm_device *dev, bool enable); 348 349 int (*channel_id)(struct drm_device *); 350 351 int (*create_context)(struct nouveau_channel *); 352 void (*destroy_context)(struct nouveau_channel *); 353 int (*load_context)(struct nouveau_channel *); 354 int (*unload_context)(struct drm_device *); 355 void (*tlb_flush)(struct drm_device *dev); 356}; 357 358struct nouveau_pgraph_engine { 359 bool accel_blocked; 360 bool registered; 361 int grctx_size; 362 363 /* NV2x/NV3x context table (0x400780) */ 364 struct nouveau_gpuobj *ctx_table; 365 366 int (*init)(struct drm_device *); 367 void (*takedown)(struct drm_device *); 368 369 void (*fifo_access)(struct drm_device *, bool); 370 371 struct nouveau_channel *(*channel)(struct drm_device *); 372 int (*create_context)(struct nouveau_channel *); 373 void (*destroy_context)(struct nouveau_channel *); 374 int (*load_context)(struct nouveau_channel *); 375 int (*unload_context)(struct drm_device *); 376 void (*tlb_flush)(struct drm_device *dev); 377 378 void (*set_tile_region)(struct drm_device *dev, int i); 379}; 380 381struct nouveau_display_engine { 382 int (*early_init)(struct drm_device *); 383 void (*late_takedown)(struct drm_device *); 384 int (*create)(struct drm_device *); 385 int (*init)(struct drm_device *); 386 void (*destroy)(struct drm_device *); 387}; 388 389struct nouveau_gpio_engine { 390 void *priv; 391 392 int (*init)(struct drm_device *); 393 void (*takedown)(struct drm_device *); 394 395 int (*get)(struct drm_device *, enum dcb_gpio_tag); 396 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 397 398 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 399 void (*)(void *, int), void *); 400 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 401 void (*)(void *, int), void *); 402 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 403}; 404 405struct nouveau_pm_voltage_level { 406 u8 voltage; 407 u8 vid; 408}; 409 410struct nouveau_pm_voltage { 411 bool supported; 412 u8 vid_mask; 413 414 struct nouveau_pm_voltage_level *level; 415 int nr_level; 416}; 417 418#define NOUVEAU_PM_MAX_LEVEL 8 419struct nouveau_pm_level { 420 struct device_attribute dev_attr; 421 char name[32]; 422 int id; 423 424 u32 core; 425 u32 memory; 426 u32 shader; 427 u32 unk05; 428 429 u8 voltage; 430 u8 fanspeed; 431 432 u16 memscript; 433}; 434 435struct nouveau_pm_temp_sensor_constants { 436 u16 offset_constant; 437 s16 offset_mult; 438 u16 offset_div; 439 u16 slope_mult; 440 u16 slope_div; 441}; 442 443struct nouveau_pm_threshold_temp { 444 s16 critical; 445 s16 down_clock; 446 s16 fan_boost; 447}; 448 449struct nouveau_pm_memtiming { 450 u32 reg_100220; 451 u32 reg_100224; 452 u32 reg_100228; 453 u32 reg_10022c; 454 u32 reg_100230; 455 u32 reg_100234; 456 u32 reg_100238; 457 u32 reg_10023c; 458}; 459 460struct nouveau_pm_memtimings { 461 bool supported; 462 struct nouveau_pm_memtiming *timing; 463 int nr_timing; 464}; 465 466struct nouveau_pm_engine { 467 struct nouveau_pm_voltage voltage; 468 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 469 int nr_perflvl; 470 struct nouveau_pm_memtimings memtimings; 471 struct nouveau_pm_temp_sensor_constants sensor_constants; 472 struct nouveau_pm_threshold_temp threshold_temp; 473 474 struct nouveau_pm_level boot; 475 struct nouveau_pm_level *cur; 476 477 struct device *hwmon; 478 struct notifier_block acpi_nb; 479 480 int (*clock_get)(struct drm_device *, u32 id); 481 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 482 u32 id, int khz); 483 void (*clock_set)(struct drm_device *, void *); 484 int (*voltage_get)(struct drm_device *); 485 int (*voltage_set)(struct drm_device *, int voltage); 486 int (*fanspeed_get)(struct drm_device *); 487 int (*fanspeed_set)(struct drm_device *, int fanspeed); 488 int (*temp_get)(struct drm_device *); 489}; 490 491struct nouveau_crypt_engine { 492 bool registered; 493 494 int (*init)(struct drm_device *); 495 void (*takedown)(struct drm_device *); 496 int (*create_context)(struct nouveau_channel *); 497 void (*destroy_context)(struct nouveau_channel *); 498 void (*tlb_flush)(struct drm_device *dev); 499}; 500 501struct nouveau_engine { 502 struct nouveau_instmem_engine instmem; 503 struct nouveau_mc_engine mc; 504 struct nouveau_timer_engine timer; 505 struct nouveau_fb_engine fb; 506 struct nouveau_pgraph_engine graph; 507 struct nouveau_fifo_engine fifo; 508 struct nouveau_display_engine display; 509 struct nouveau_gpio_engine gpio; 510 struct nouveau_pm_engine pm; 511 struct nouveau_crypt_engine crypt; 512}; 513 514struct nouveau_pll_vals { 515 union { 516 struct { 517#ifdef __BIG_ENDIAN 518 uint8_t N1, M1, N2, M2; 519#else 520 uint8_t M1, N1, M2, N2; 521#endif 522 }; 523 struct { 524 uint16_t NM1, NM2; 525 } __attribute__((packed)); 526 }; 527 int log2P; 528 529 int refclk; 530}; 531 532enum nv04_fp_display_regs { 533 FP_DISPLAY_END, 534 FP_TOTAL, 535 FP_CRTC, 536 FP_SYNC_START, 537 FP_SYNC_END, 538 FP_VALID_START, 539 FP_VALID_END 540}; 541 542struct nv04_crtc_reg { 543 unsigned char MiscOutReg; 544 uint8_t CRTC[0xa0]; 545 uint8_t CR58[0x10]; 546 uint8_t Sequencer[5]; 547 uint8_t Graphics[9]; 548 uint8_t Attribute[21]; 549 unsigned char DAC[768]; 550 551 /* PCRTC regs */ 552 uint32_t fb_start; 553 uint32_t crtc_cfg; 554 uint32_t cursor_cfg; 555 uint32_t gpio_ext; 556 uint32_t crtc_830; 557 uint32_t crtc_834; 558 uint32_t crtc_850; 559 uint32_t crtc_eng_ctrl; 560 561 /* PRAMDAC regs */ 562 uint32_t nv10_cursync; 563 struct nouveau_pll_vals pllvals; 564 uint32_t ramdac_gen_ctrl; 565 uint32_t ramdac_630; 566 uint32_t ramdac_634; 567 uint32_t tv_setup; 568 uint32_t tv_vtotal; 569 uint32_t tv_vskew; 570 uint32_t tv_vsync_delay; 571 uint32_t tv_htotal; 572 uint32_t tv_hskew; 573 uint32_t tv_hsync_delay; 574 uint32_t tv_hsync_delay2; 575 uint32_t fp_horiz_regs[7]; 576 uint32_t fp_vert_regs[7]; 577 uint32_t dither; 578 uint32_t fp_control; 579 uint32_t dither_regs[6]; 580 uint32_t fp_debug_0; 581 uint32_t fp_debug_1; 582 uint32_t fp_debug_2; 583 uint32_t fp_margin_color; 584 uint32_t ramdac_8c0; 585 uint32_t ramdac_a20; 586 uint32_t ramdac_a24; 587 uint32_t ramdac_a34; 588 uint32_t ctv_regs[38]; 589}; 590 591struct nv04_output_reg { 592 uint32_t output; 593 int head; 594}; 595 596struct nv04_mode_state { 597 struct nv04_crtc_reg crtc_reg[2]; 598 uint32_t pllsel; 599 uint32_t sel_clk; 600}; 601 602enum nouveau_card_type { 603 NV_04 = 0x00, 604 NV_10 = 0x10, 605 NV_20 = 0x20, 606 NV_30 = 0x30, 607 NV_40 = 0x40, 608 NV_50 = 0x50, 609 NV_C0 = 0xc0, 610}; 611 612struct drm_nouveau_private { 613 struct drm_device *dev; 614 615 /* the card type, takes NV_* as values */ 616 enum nouveau_card_type card_type; 617 /* exact chipset, derived from NV_PMC_BOOT_0 */ 618 int chipset; 619 int flags; 620 621 void __iomem *mmio; 622 623 spinlock_t ramin_lock; 624 void __iomem *ramin; 625 u32 ramin_size; 626 u32 ramin_base; 627 bool ramin_available; 628 struct drm_mm ramin_heap; 629 struct list_head gpuobj_list; 630 struct list_head classes; 631 632 struct nouveau_bo *vga_ram; 633 634 /* interrupt handling */ 635 void (*irq_handler[32])(struct drm_device *); 636 bool msi_enabled; 637 struct workqueue_struct *wq; 638 struct work_struct irq_work; 639 640 struct list_head vbl_waiting; 641 642 struct { 643 struct drm_global_reference mem_global_ref; 644 struct ttm_bo_global_ref bo_global_ref; 645 struct ttm_bo_device bdev; 646 atomic_t validate_sequence; 647 } ttm; 648 649 struct { 650 spinlock_t lock; 651 struct drm_mm heap; 652 struct nouveau_bo *bo; 653 } fence; 654 655 struct { 656 spinlock_t lock; 657 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 658 } channels; 659 660 struct nouveau_engine engine; 661 struct nouveau_channel *channel; 662 663 /* For PFIFO and PGRAPH. */ 664 spinlock_t context_switch_lock; 665 666 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 667 struct nouveau_ramht *ramht; 668 struct nouveau_gpuobj *ramfc; 669 struct nouveau_gpuobj *ramro; 670 671 uint32_t ramin_rsvd_vram; 672 673 struct { 674 enum { 675 NOUVEAU_GART_NONE = 0, 676 NOUVEAU_GART_AGP, 677 NOUVEAU_GART_SGDMA 678 } type; 679 uint64_t aper_base; 680 uint64_t aper_size; 681 uint64_t aper_free; 682 683 struct nouveau_gpuobj *sg_ctxdma; 684 } gart_info; 685 686 /* nv10-nv40 tiling regions */ 687 struct { 688 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 689 spinlock_t lock; 690 } tile; 691 692 /* VRAM/fb configuration */ 693 uint64_t vram_size; 694 uint64_t vram_sys_base; 695 u32 vram_rblock_size; 696 697 uint64_t fb_phys; 698 uint64_t fb_available_size; 699 uint64_t fb_mappable_pages; 700 uint64_t fb_aper_free; 701 int fb_mtrr; 702 703 /* G8x/G9x virtual address space */ 704 uint64_t vm_gart_base; 705 uint64_t vm_gart_size; 706 uint64_t vm_vram_base; 707 uint64_t vm_vram_size; 708 uint64_t vm_end; 709 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 710 int vm_vram_pt_nr; 711 712 struct nvbios vbios; 713 714 struct nv04_mode_state mode_reg; 715 struct nv04_mode_state saved_reg; 716 uint32_t saved_vga_font[4][16384]; 717 uint32_t crtc_owner; 718 uint32_t dac_users[4]; 719 720 struct nouveau_suspend_resume { 721 uint32_t *ramin_copy; 722 } susres; 723 724 struct backlight_device *backlight; 725 726 struct nouveau_channel *evo; 727 u32 evo_alloc; 728 struct { 729 struct dcb_entry *dcb; 730 u16 script; 731 u32 pclk; 732 } evo_irq; 733 734 struct { 735 struct dentry *channel_root; 736 } debugfs; 737 738 struct nouveau_fbdev *nfbdev; 739 struct apertures_struct *apertures; 740}; 741 742static inline struct drm_nouveau_private * 743nouveau_private(struct drm_device *dev) 744{ 745 return dev->dev_private; 746} 747 748static inline struct drm_nouveau_private * 749nouveau_bdev(struct ttm_bo_device *bd) 750{ 751 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 752} 753 754static inline int 755nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 756{ 757 struct nouveau_bo *prev; 758 759 if (!pnvbo) 760 return -EINVAL; 761 prev = *pnvbo; 762 763 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 764 if (prev) { 765 struct ttm_buffer_object *bo = &prev->bo; 766 767 ttm_bo_unref(&bo); 768 } 769 770 return 0; 771} 772 773/* nouveau_drv.c */ 774extern int nouveau_agpmode; 775extern int nouveau_duallink; 776extern int nouveau_uscript_lvds; 777extern int nouveau_uscript_tmds; 778extern int nouveau_vram_pushbuf; 779extern int nouveau_vram_notify; 780extern int nouveau_fbpercrtc; 781extern int nouveau_tv_disable; 782extern char *nouveau_tv_norm; 783extern int nouveau_reg_debug; 784extern char *nouveau_vbios; 785extern int nouveau_ignorelid; 786extern int nouveau_nofbaccel; 787extern int nouveau_noaccel; 788extern int nouveau_force_post; 789extern int nouveau_override_conntype; 790extern char *nouveau_perflvl; 791extern int nouveau_perflvl_wr; 792extern int nouveau_msi; 793 794extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 795extern int nouveau_pci_resume(struct pci_dev *pdev); 796 797/* nouveau_state.c */ 798extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 799extern int nouveau_load(struct drm_device *, unsigned long flags); 800extern int nouveau_firstopen(struct drm_device *); 801extern void nouveau_lastclose(struct drm_device *); 802extern int nouveau_unload(struct drm_device *); 803extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 804 struct drm_file *); 805extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 806 struct drm_file *); 807extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 808 uint32_t reg, uint32_t mask, uint32_t val); 809extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 810 uint32_t reg, uint32_t mask, uint32_t val); 811extern bool nouveau_wait_for_idle(struct drm_device *); 812extern int nouveau_card_init(struct drm_device *); 813 814/* nouveau_mem.c */ 815extern int nouveau_mem_vram_init(struct drm_device *); 816extern void nouveau_mem_vram_fini(struct drm_device *); 817extern int nouveau_mem_gart_init(struct drm_device *); 818extern void nouveau_mem_gart_fini(struct drm_device *); 819extern int nouveau_mem_init_agp(struct drm_device *); 820extern int nouveau_mem_reset_agp(struct drm_device *); 821extern void nouveau_mem_close(struct drm_device *); 822extern struct nouveau_tile_reg *nv10_mem_set_tiling( 823 struct drm_device *dev, uint32_t addr, uint32_t size, 824 uint32_t pitch, uint32_t flags); 825extern void nv10_mem_put_tile_region(struct drm_device *dev, 826 struct nouveau_tile_reg *tile, 827 struct nouveau_fence *fence); 828extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 829 uint32_t size, uint32_t flags, 830 uint64_t phys); 831extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 832 uint32_t size); 833extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 834 835/* nouveau_notifier.c */ 836extern int nouveau_notifier_init_channel(struct nouveau_channel *); 837extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 838extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 839 int cout, uint32_t *offset); 840extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 841extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 842 struct drm_file *); 843extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 844 struct drm_file *); 845 846/* nouveau_channel.c */ 847extern struct drm_ioctl_desc nouveau_ioctls[]; 848extern int nouveau_max_ioctl; 849extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 850extern int nouveau_channel_alloc(struct drm_device *dev, 851 struct nouveau_channel **chan, 852 struct drm_file *file_priv, 853 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 854extern struct nouveau_channel * 855nouveau_channel_get_unlocked(struct nouveau_channel *); 856extern struct nouveau_channel * 857nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 858extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 859extern void nouveau_channel_put(struct nouveau_channel **); 860extern void nouveau_channel_ref(struct nouveau_channel *chan, 861 struct nouveau_channel **pchan); 862extern void nouveau_channel_idle(struct nouveau_channel *chan); 863 864/* nouveau_object.c */ 865#define NVOBJ_CLASS(d,c,e) do { \ 866 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 867 if (ret) \ 868 return ret; \ 869} while(0) 870 871#define NVOBJ_MTHD(d,c,m,e) do { \ 872 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 873 if (ret) \ 874 return ret; \ 875} while(0) 876 877extern int nouveau_gpuobj_early_init(struct drm_device *); 878extern int nouveau_gpuobj_init(struct drm_device *); 879extern void nouveau_gpuobj_takedown(struct drm_device *); 880extern int nouveau_gpuobj_suspend(struct drm_device *dev); 881extern void nouveau_gpuobj_resume(struct drm_device *dev); 882extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 883extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 884 int (*exec)(struct nouveau_channel *, 885 u32 class, u32 mthd, u32 data)); 886extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 887extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 888extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 889 uint32_t vram_h, uint32_t tt_h); 890extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 891extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 892 uint32_t size, int align, uint32_t flags, 893 struct nouveau_gpuobj **); 894extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 895 struct nouveau_gpuobj **); 896extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 897 u32 size, u32 flags, 898 struct nouveau_gpuobj **); 899extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 900 uint64_t offset, uint64_t size, int access, 901 int target, struct nouveau_gpuobj **); 902extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 903extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 904 u64 size, int target, int access, u32 type, 905 u32 comp, struct nouveau_gpuobj **pobj); 906extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 907 int class, u64 base, u64 size, int target, 908 int access, u32 type, u32 comp); 909extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 910 struct drm_file *); 911extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 912 struct drm_file *); 913 914/* nouveau_irq.c */ 915extern int nouveau_irq_init(struct drm_device *); 916extern void nouveau_irq_fini(struct drm_device *); 917extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 918extern void nouveau_irq_register(struct drm_device *, int status_bit, 919 void (*)(struct drm_device *)); 920extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 921extern void nouveau_irq_preinstall(struct drm_device *); 922extern int nouveau_irq_postinstall(struct drm_device *); 923extern void nouveau_irq_uninstall(struct drm_device *); 924 925/* nouveau_sgdma.c */ 926extern int nouveau_sgdma_init(struct drm_device *); 927extern void nouveau_sgdma_takedown(struct drm_device *); 928extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 929 uint32_t *page); 930extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 931 932/* nouveau_debugfs.c */ 933#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 934extern int nouveau_debugfs_init(struct drm_minor *); 935extern void nouveau_debugfs_takedown(struct drm_minor *); 936extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 937extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 938#else 939static inline int 940nouveau_debugfs_init(struct drm_minor *minor) 941{ 942 return 0; 943} 944 945static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 946{ 947} 948 949static inline int 950nouveau_debugfs_channel_init(struct nouveau_channel *chan) 951{ 952 return 0; 953} 954 955static inline void 956nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 957{ 958} 959#endif 960 961/* nouveau_dma.c */ 962extern void nouveau_dma_pre_init(struct nouveau_channel *); 963extern int nouveau_dma_init(struct nouveau_channel *); 964extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 965 966/* nouveau_acpi.c */ 967#define ROM_BIOS_PAGE 4096 968#if defined(CONFIG_ACPI) 969void nouveau_register_dsm_handler(void); 970void nouveau_unregister_dsm_handler(void); 971int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 972bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 973int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 974#else 975static inline void nouveau_register_dsm_handler(void) {} 976static inline void nouveau_unregister_dsm_handler(void) {} 977static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 978static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 979static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 980#endif 981 982/* nouveau_backlight.c */ 983#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 984extern int nouveau_backlight_init(struct drm_device *); 985extern void nouveau_backlight_exit(struct drm_device *); 986#else 987static inline int nouveau_backlight_init(struct drm_device *dev) 988{ 989 return 0; 990} 991 992static inline void nouveau_backlight_exit(struct drm_device *dev) { } 993#endif 994 995/* nouveau_bios.c */ 996extern int nouveau_bios_init(struct drm_device *); 997extern void nouveau_bios_takedown(struct drm_device *dev); 998extern int nouveau_run_vbios_init(struct drm_device *); 999extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1000 struct dcb_entry *); 1001extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1002 enum dcb_gpio_tag); 1003extern struct dcb_connector_table_entry * 1004nouveau_bios_connector_entry(struct drm_device *, int index); 1005extern u32 get_pll_register(struct drm_device *, enum pll_types); 1006extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1007 struct pll_lims *); 1008extern int nouveau_bios_run_display_table(struct drm_device *, 1009 struct dcb_entry *, 1010 uint32_t script, int pxclk); 1011extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1012 int *length); 1013extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1014extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1015extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1016 bool *dl, bool *if_is_24bit); 1017extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1018 int head, int pxclk); 1019extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1020 enum LVDS_script, int pxclk); 1021 1022/* nouveau_ttm.c */ 1023int nouveau_ttm_global_init(struct drm_nouveau_private *); 1024void nouveau_ttm_global_release(struct drm_nouveau_private *); 1025int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1026 1027/* nouveau_dp.c */ 1028int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1029 uint8_t *data, int data_nr); 1030bool nouveau_dp_detect(struct drm_encoder *); 1031bool nouveau_dp_link_train(struct drm_encoder *); 1032 1033/* nv04_fb.c */ 1034extern int nv04_fb_init(struct drm_device *); 1035extern void nv04_fb_takedown(struct drm_device *); 1036 1037/* nv10_fb.c */ 1038extern int nv10_fb_init(struct drm_device *); 1039extern void nv10_fb_takedown(struct drm_device *); 1040extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1041 uint32_t addr, uint32_t size, 1042 uint32_t pitch, uint32_t flags); 1043extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1044extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1045 1046/* nv30_fb.c */ 1047extern int nv30_fb_init(struct drm_device *); 1048extern void nv30_fb_takedown(struct drm_device *); 1049extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1050 uint32_t addr, uint32_t size, 1051 uint32_t pitch, uint32_t flags); 1052extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1053 1054/* nv40_fb.c */ 1055extern int nv40_fb_init(struct drm_device *); 1056extern void nv40_fb_takedown(struct drm_device *); 1057extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1058 1059/* nv50_fb.c */ 1060extern int nv50_fb_init(struct drm_device *); 1061extern void nv50_fb_takedown(struct drm_device *); 1062extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1063 1064/* nvc0_fb.c */ 1065extern int nvc0_fb_init(struct drm_device *); 1066extern void nvc0_fb_takedown(struct drm_device *); 1067 1068/* nv04_fifo.c */ 1069extern int nv04_fifo_init(struct drm_device *); 1070extern void nv04_fifo_fini(struct drm_device *); 1071extern void nv04_fifo_disable(struct drm_device *); 1072extern void nv04_fifo_enable(struct drm_device *); 1073extern bool nv04_fifo_reassign(struct drm_device *, bool); 1074extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1075extern int nv04_fifo_channel_id(struct drm_device *); 1076extern int nv04_fifo_create_context(struct nouveau_channel *); 1077extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1078extern int nv04_fifo_load_context(struct nouveau_channel *); 1079extern int nv04_fifo_unload_context(struct drm_device *); 1080extern void nv04_fifo_isr(struct drm_device *); 1081 1082/* nv10_fifo.c */ 1083extern int nv10_fifo_init(struct drm_device *); 1084extern int nv10_fifo_channel_id(struct drm_device *); 1085extern int nv10_fifo_create_context(struct nouveau_channel *); 1086extern int nv10_fifo_load_context(struct nouveau_channel *); 1087extern int nv10_fifo_unload_context(struct drm_device *); 1088 1089/* nv40_fifo.c */ 1090extern int nv40_fifo_init(struct drm_device *); 1091extern int nv40_fifo_create_context(struct nouveau_channel *); 1092extern int nv40_fifo_load_context(struct nouveau_channel *); 1093extern int nv40_fifo_unload_context(struct drm_device *); 1094 1095/* nv50_fifo.c */ 1096extern int nv50_fifo_init(struct drm_device *); 1097extern void nv50_fifo_takedown(struct drm_device *); 1098extern int nv50_fifo_channel_id(struct drm_device *); 1099extern int nv50_fifo_create_context(struct nouveau_channel *); 1100extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1101extern int nv50_fifo_load_context(struct nouveau_channel *); 1102extern int nv50_fifo_unload_context(struct drm_device *); 1103extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1104 1105/* nvc0_fifo.c */ 1106extern int nvc0_fifo_init(struct drm_device *); 1107extern void nvc0_fifo_takedown(struct drm_device *); 1108extern void nvc0_fifo_disable(struct drm_device *); 1109extern void nvc0_fifo_enable(struct drm_device *); 1110extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1111extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1112extern int nvc0_fifo_channel_id(struct drm_device *); 1113extern int nvc0_fifo_create_context(struct nouveau_channel *); 1114extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1115extern int nvc0_fifo_load_context(struct nouveau_channel *); 1116extern int nvc0_fifo_unload_context(struct drm_device *); 1117 1118/* nv04_graph.c */ 1119extern int nv04_graph_init(struct drm_device *); 1120extern void nv04_graph_takedown(struct drm_device *); 1121extern void nv04_graph_fifo_access(struct drm_device *, bool); 1122extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1123extern int nv04_graph_create_context(struct nouveau_channel *); 1124extern void nv04_graph_destroy_context(struct nouveau_channel *); 1125extern int nv04_graph_load_context(struct nouveau_channel *); 1126extern int nv04_graph_unload_context(struct drm_device *); 1127extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1128 u32 class, u32 mthd, u32 data); 1129extern struct nouveau_bitfield nv04_graph_nsource[]; 1130 1131/* nv10_graph.c */ 1132extern int nv10_graph_init(struct drm_device *); 1133extern void nv10_graph_takedown(struct drm_device *); 1134extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1135extern int nv10_graph_create_context(struct nouveau_channel *); 1136extern void nv10_graph_destroy_context(struct nouveau_channel *); 1137extern int nv10_graph_load_context(struct nouveau_channel *); 1138extern int nv10_graph_unload_context(struct drm_device *); 1139extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1140extern struct nouveau_bitfield nv10_graph_intr[]; 1141extern struct nouveau_bitfield nv10_graph_nstatus[]; 1142 1143/* nv20_graph.c */ 1144extern int nv20_graph_create_context(struct nouveau_channel *); 1145extern void nv20_graph_destroy_context(struct nouveau_channel *); 1146extern int nv20_graph_load_context(struct nouveau_channel *); 1147extern int nv20_graph_unload_context(struct drm_device *); 1148extern int nv20_graph_init(struct drm_device *); 1149extern void nv20_graph_takedown(struct drm_device *); 1150extern int nv30_graph_init(struct drm_device *); 1151extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1152 1153/* nv40_graph.c */ 1154extern int nv40_graph_init(struct drm_device *); 1155extern void nv40_graph_takedown(struct drm_device *); 1156extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1157extern int nv40_graph_create_context(struct nouveau_channel *); 1158extern void nv40_graph_destroy_context(struct nouveau_channel *); 1159extern int nv40_graph_load_context(struct nouveau_channel *); 1160extern int nv40_graph_unload_context(struct drm_device *); 1161extern void nv40_grctx_init(struct nouveau_grctx *); 1162extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1163 1164/* nv50_graph.c */ 1165extern int nv50_graph_init(struct drm_device *); 1166extern void nv50_graph_takedown(struct drm_device *); 1167extern void nv50_graph_fifo_access(struct drm_device *, bool); 1168extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1169extern int nv50_graph_create_context(struct nouveau_channel *); 1170extern void nv50_graph_destroy_context(struct nouveau_channel *); 1171extern int nv50_graph_load_context(struct nouveau_channel *); 1172extern int nv50_graph_unload_context(struct drm_device *); 1173extern int nv50_grctx_init(struct nouveau_grctx *); 1174extern void nv50_graph_tlb_flush(struct drm_device *dev); 1175extern void nv86_graph_tlb_flush(struct drm_device *dev); 1176 1177/* nvc0_graph.c */ 1178extern int nvc0_graph_init(struct drm_device *); 1179extern void nvc0_graph_takedown(struct drm_device *); 1180extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1181extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1182extern int nvc0_graph_create_context(struct nouveau_channel *); 1183extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1184extern int nvc0_graph_load_context(struct nouveau_channel *); 1185extern int nvc0_graph_unload_context(struct drm_device *); 1186 1187/* nv84_crypt.c */ 1188extern int nv84_crypt_init(struct drm_device *dev); 1189extern void nv84_crypt_fini(struct drm_device *dev); 1190extern int nv84_crypt_create_context(struct nouveau_channel *); 1191extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1192extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1193 1194/* nv04_instmem.c */ 1195extern int nv04_instmem_init(struct drm_device *); 1196extern void nv04_instmem_takedown(struct drm_device *); 1197extern int nv04_instmem_suspend(struct drm_device *); 1198extern void nv04_instmem_resume(struct drm_device *); 1199extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1200extern void nv04_instmem_put(struct nouveau_gpuobj *); 1201extern int nv04_instmem_map(struct nouveau_gpuobj *); 1202extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1203extern void nv04_instmem_flush(struct drm_device *); 1204 1205/* nv50_instmem.c */ 1206extern int nv50_instmem_init(struct drm_device *); 1207extern void nv50_instmem_takedown(struct drm_device *); 1208extern int nv50_instmem_suspend(struct drm_device *); 1209extern void nv50_instmem_resume(struct drm_device *); 1210extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1211extern void nv50_instmem_put(struct nouveau_gpuobj *); 1212extern int nv50_instmem_map(struct nouveau_gpuobj *); 1213extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1214extern void nv50_instmem_flush(struct drm_device *); 1215extern void nv84_instmem_flush(struct drm_device *); 1216extern void nv50_vm_flush(struct drm_device *, int engine); 1217 1218/* nvc0_instmem.c */ 1219extern int nvc0_instmem_init(struct drm_device *); 1220extern void nvc0_instmem_takedown(struct drm_device *); 1221extern int nvc0_instmem_suspend(struct drm_device *); 1222extern void nvc0_instmem_resume(struct drm_device *); 1223extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1224extern void nvc0_instmem_put(struct nouveau_gpuobj *); 1225extern int nvc0_instmem_map(struct nouveau_gpuobj *); 1226extern void nvc0_instmem_unmap(struct nouveau_gpuobj *); 1227extern void nvc0_instmem_flush(struct drm_device *); 1228 1229/* nv04_mc.c */ 1230extern int nv04_mc_init(struct drm_device *); 1231extern void nv04_mc_takedown(struct drm_device *); 1232 1233/* nv40_mc.c */ 1234extern int nv40_mc_init(struct drm_device *); 1235extern void nv40_mc_takedown(struct drm_device *); 1236 1237/* nv50_mc.c */ 1238extern int nv50_mc_init(struct drm_device *); 1239extern void nv50_mc_takedown(struct drm_device *); 1240 1241/* nv04_timer.c */ 1242extern int nv04_timer_init(struct drm_device *); 1243extern uint64_t nv04_timer_read(struct drm_device *); 1244extern void nv04_timer_takedown(struct drm_device *); 1245 1246extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1247 unsigned long arg); 1248 1249/* nv04_dac.c */ 1250extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1251extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1252extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1253extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1254extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1255 1256/* nv04_dfp.c */ 1257extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1258extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1259extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1260 int head, bool dl); 1261extern void nv04_dfp_disable(struct drm_device *dev, int head); 1262extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1263 1264/* nv04_tv.c */ 1265extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1266extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1267 1268/* nv17_tv.c */ 1269extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1270 1271/* nv04_display.c */ 1272extern int nv04_display_early_init(struct drm_device *); 1273extern void nv04_display_late_takedown(struct drm_device *); 1274extern int nv04_display_create(struct drm_device *); 1275extern int nv04_display_init(struct drm_device *); 1276extern void nv04_display_destroy(struct drm_device *); 1277 1278/* nv04_crtc.c */ 1279extern int nv04_crtc_create(struct drm_device *, int index); 1280 1281/* nouveau_bo.c */ 1282extern struct ttm_bo_driver nouveau_bo_driver; 1283extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1284 int size, int align, uint32_t flags, 1285 uint32_t tile_mode, uint32_t tile_flags, 1286 bool no_vm, bool mappable, struct nouveau_bo **); 1287extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1288extern int nouveau_bo_unpin(struct nouveau_bo *); 1289extern int nouveau_bo_map(struct nouveau_bo *); 1290extern void nouveau_bo_unmap(struct nouveau_bo *); 1291extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1292 uint32_t busy); 1293extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1294extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1295extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1296extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1297extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1298extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1299 bool no_wait_reserve, bool no_wait_gpu); 1300 1301/* nouveau_fence.c */ 1302struct nouveau_fence; 1303extern int nouveau_fence_init(struct drm_device *); 1304extern void nouveau_fence_fini(struct drm_device *); 1305extern int nouveau_fence_channel_init(struct nouveau_channel *); 1306extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1307extern void nouveau_fence_update(struct nouveau_channel *); 1308extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1309 bool emit); 1310extern int nouveau_fence_emit(struct nouveau_fence *); 1311extern void nouveau_fence_work(struct nouveau_fence *fence, 1312 void (*work)(void *priv, bool signalled), 1313 void *priv); 1314struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1315 1316extern bool __nouveau_fence_signalled(void *obj, void *arg); 1317extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1318extern int __nouveau_fence_flush(void *obj, void *arg); 1319extern void __nouveau_fence_unref(void **obj); 1320extern void *__nouveau_fence_ref(void *obj); 1321 1322static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1323{ 1324 return __nouveau_fence_signalled(obj, NULL); 1325} 1326static inline int 1327nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1328{ 1329 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1330} 1331extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1332static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1333{ 1334 return __nouveau_fence_flush(obj, NULL); 1335} 1336static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1337{ 1338 __nouveau_fence_unref((void **)obj); 1339} 1340static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1341{ 1342 return __nouveau_fence_ref(obj); 1343} 1344 1345/* nouveau_gem.c */ 1346extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1347 int size, int align, uint32_t flags, 1348 uint32_t tile_mode, uint32_t tile_flags, 1349 bool no_vm, bool mappable, struct nouveau_bo **); 1350extern int nouveau_gem_object_new(struct drm_gem_object *); 1351extern void nouveau_gem_object_del(struct drm_gem_object *); 1352extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1353 struct drm_file *); 1354extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1355 struct drm_file *); 1356extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1357 struct drm_file *); 1358extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1359 struct drm_file *); 1360extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1361 struct drm_file *); 1362 1363/* nouveau_display.c */ 1364int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1365void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1366int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1367 struct drm_pending_vblank_event *event); 1368int nouveau_finish_page_flip(struct nouveau_channel *, 1369 struct nouveau_page_flip_state *); 1370 1371/* nv10_gpio.c */ 1372int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1373int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1374 1375/* nv50_gpio.c */ 1376int nv50_gpio_init(struct drm_device *dev); 1377void nv50_gpio_fini(struct drm_device *dev); 1378int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1379int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1380int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1381 void (*)(void *, int), void *); 1382void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1383 void (*)(void *, int), void *); 1384bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1385 1386/* nv50_calc. */ 1387int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1388 int *N1, int *M1, int *N2, int *M2, int *P); 1389int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1390 int clk, int *N, int *fN, int *M, int *P); 1391 1392#ifndef ioread32_native 1393#ifdef __BIG_ENDIAN 1394#define ioread16_native ioread16be 1395#define iowrite16_native iowrite16be 1396#define ioread32_native ioread32be 1397#define iowrite32_native iowrite32be 1398#else /* def __BIG_ENDIAN */ 1399#define ioread16_native ioread16 1400#define iowrite16_native iowrite16 1401#define ioread32_native ioread32 1402#define iowrite32_native iowrite32 1403#endif /* def __BIG_ENDIAN else */ 1404#endif /* !ioread32_native */ 1405 1406/* channel control reg access */ 1407static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1408{ 1409 return ioread32_native(chan->user + reg); 1410} 1411 1412static inline void nvchan_wr32(struct nouveau_channel *chan, 1413 unsigned reg, u32 val) 1414{ 1415 iowrite32_native(val, chan->user + reg); 1416} 1417 1418/* register access */ 1419static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1420{ 1421 struct drm_nouveau_private *dev_priv = dev->dev_private; 1422 return ioread32_native(dev_priv->mmio + reg); 1423} 1424 1425static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1426{ 1427 struct drm_nouveau_private *dev_priv = dev->dev_private; 1428 iowrite32_native(val, dev_priv->mmio + reg); 1429} 1430 1431static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1432{ 1433 u32 tmp = nv_rd32(dev, reg); 1434 nv_wr32(dev, reg, (tmp & ~mask) | val); 1435 return tmp; 1436} 1437 1438static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 return ioread8(dev_priv->mmio + reg); 1442} 1443 1444static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1445{ 1446 struct drm_nouveau_private *dev_priv = dev->dev_private; 1447 iowrite8(val, dev_priv->mmio + reg); 1448} 1449 1450#define nv_wait(dev, reg, mask, val) \ 1451 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1452#define nv_wait_ne(dev, reg, mask, val) \ 1453 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1454 1455/* PRAMIN access */ 1456static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1457{ 1458 struct drm_nouveau_private *dev_priv = dev->dev_private; 1459 return ioread32_native(dev_priv->ramin + offset); 1460} 1461 1462static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1463{ 1464 struct drm_nouveau_private *dev_priv = dev->dev_private; 1465 iowrite32_native(val, dev_priv->ramin + offset); 1466} 1467 1468/* object access */ 1469extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1470extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1471 1472/* 1473 * Logging 1474 * Argument d is (struct drm_device *). 1475 */ 1476#define NV_PRINTK(level, d, fmt, arg...) \ 1477 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1478 pci_name(d->pdev), ##arg) 1479#ifndef NV_DEBUG_NOTRACE 1480#define NV_DEBUG(d, fmt, arg...) do { \ 1481 if (drm_debug & DRM_UT_DRIVER) { \ 1482 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1483 __LINE__, ##arg); \ 1484 } \ 1485} while (0) 1486#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1487 if (drm_debug & DRM_UT_KMS) { \ 1488 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1489 __LINE__, ##arg); \ 1490 } \ 1491} while (0) 1492#else 1493#define NV_DEBUG(d, fmt, arg...) do { \ 1494 if (drm_debug & DRM_UT_DRIVER) \ 1495 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1496} while (0) 1497#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1498 if (drm_debug & DRM_UT_KMS) \ 1499 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1500} while (0) 1501#endif 1502#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1503#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1504#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1505#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1506#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1507 1508/* nouveau_reg_debug bitmask */ 1509enum { 1510 NOUVEAU_REG_DEBUG_MC = 0x1, 1511 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1512 NOUVEAU_REG_DEBUG_FB = 0x4, 1513 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1514 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1515 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1516 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1517 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1518 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1519 NOUVEAU_REG_DEBUG_EVO = 0x200, 1520}; 1521 1522#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1523 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1524 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1525} while (0) 1526 1527static inline bool 1528nv_two_heads(struct drm_device *dev) 1529{ 1530 struct drm_nouveau_private *dev_priv = dev->dev_private; 1531 const int impl = dev->pci_device & 0x0ff0; 1532 1533 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1534 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1535 return true; 1536 1537 return false; 1538} 1539 1540static inline bool 1541nv_gf4_disp_arch(struct drm_device *dev) 1542{ 1543 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1544} 1545 1546static inline bool 1547nv_two_reg_pll(struct drm_device *dev) 1548{ 1549 struct drm_nouveau_private *dev_priv = dev->dev_private; 1550 const int impl = dev->pci_device & 0x0ff0; 1551 1552 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1553 return true; 1554 return false; 1555} 1556 1557static inline bool 1558nv_match_device(struct drm_device *dev, unsigned device, 1559 unsigned sub_vendor, unsigned sub_device) 1560{ 1561 return dev->pdev->device == device && 1562 dev->pdev->subsystem_vendor == sub_vendor && 1563 dev->pdev->subsystem_device == sub_device; 1564} 1565 1566/* memory type/access flags, do not match hardware values */ 1567#define NV_MEM_ACCESS_RO 1 1568#define NV_MEM_ACCESS_WO 2 1569#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1570#define NV_MEM_ACCESS_VM 4 1571 1572#define NV_MEM_TARGET_VRAM 0 1573#define NV_MEM_TARGET_PCI 1 1574#define NV_MEM_TARGET_PCI_NOSNOOP 2 1575#define NV_MEM_TARGET_VM 3 1576#define NV_MEM_TARGET_GART 4 1577 1578#define NV_MEM_TYPE_VM 0x7f 1579#define NV_MEM_COMP_VM 0x03 1580 1581/* NV_SW object class */ 1582#define NV_SW 0x0000506e 1583#define NV_SW_DMA_SEMAPHORE 0x00000060 1584#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1585#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1586#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1587#define NV_SW_YIELD 0x00000080 1588#define NV_SW_DMA_VBLSEM 0x0000018c 1589#define NV_SW_VBLSEM_OFFSET 0x00000400 1590#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1591#define NV_SW_VBLSEM_RELEASE 0x00000408 1592#define NV_SW_PAGE_FLIP 0x00000500 1593 1594#endif /* __NOUVEAU_DRV_H__ */ 1595