nouveau_drv.h revision 5c6dc6575460a0afe56d8cae7666e769e08ef942
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_pull)(struct drm_device *dev, bool enable); 300 301 int (*channel_id)(struct drm_device *); 302 303 int (*create_context)(struct nouveau_channel *); 304 void (*destroy_context)(struct nouveau_channel *); 305 int (*load_context)(struct nouveau_channel *); 306 int (*unload_context)(struct drm_device *); 307}; 308 309struct nouveau_pgraph_object_method { 310 int id; 311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 312 uint32_t data); 313}; 314 315struct nouveau_pgraph_object_class { 316 int id; 317 bool software; 318 struct nouveau_pgraph_object_method *methods; 319}; 320 321struct nouveau_pgraph_engine { 322 struct nouveau_pgraph_object_class *grclass; 323 bool accel_blocked; 324 int grctx_size; 325 326 /* NV2x/NV3x context table (0x400780) */ 327 struct nouveau_gpuobj *ctx_table; 328 329 int (*init)(struct drm_device *); 330 void (*takedown)(struct drm_device *); 331 332 void (*fifo_access)(struct drm_device *, bool); 333 334 struct nouveau_channel *(*channel)(struct drm_device *); 335 int (*create_context)(struct nouveau_channel *); 336 void (*destroy_context)(struct nouveau_channel *); 337 int (*load_context)(struct nouveau_channel *); 338 int (*unload_context)(struct drm_device *); 339 340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 341 uint32_t size, uint32_t pitch); 342}; 343 344struct nouveau_display_engine { 345 int (*early_init)(struct drm_device *); 346 void (*late_takedown)(struct drm_device *); 347 int (*create)(struct drm_device *); 348 int (*init)(struct drm_device *); 349 void (*destroy)(struct drm_device *); 350}; 351 352struct nouveau_gpio_engine { 353 int (*init)(struct drm_device *); 354 void (*takedown)(struct drm_device *); 355 356 int (*get)(struct drm_device *, enum dcb_gpio_tag); 357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 358 359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 360}; 361 362struct nouveau_pm_voltage_level { 363 u8 voltage; 364 u8 vid; 365}; 366 367struct nouveau_pm_voltage { 368 bool supported; 369 u8 vid_mask; 370 371 struct nouveau_pm_voltage_level *level; 372 int nr_level; 373}; 374 375#define NOUVEAU_PM_MAX_LEVEL 8 376struct nouveau_pm_level { 377 struct device_attribute dev_attr; 378 char name[32]; 379 int id; 380 381 u32 core; 382 u32 memory; 383 u32 shader; 384 u32 unk05; 385 386 u8 voltage; 387 u8 fanspeed; 388}; 389 390struct nouveau_pm_temp_sensor_constants { 391 u16 offset_constant; 392 s16 offset_mult; 393 u16 offset_div; 394 u16 slope_mult; 395 u16 slope_div; 396}; 397 398struct nouveau_pm_threshold_temp { 399 s16 critical; 400 s16 down_clock; 401 s16 fan_boost; 402}; 403 404struct nouveau_pm_memtiming { 405 u32 reg_100220; 406 u32 reg_100224; 407 u32 reg_100228; 408 u32 reg_10022c; 409 u32 reg_100230; 410 u32 reg_100234; 411 u32 reg_100238; 412 u32 reg_10023c; 413}; 414 415struct nouveau_pm_memtimings { 416 bool supported; 417 struct nouveau_pm_memtiming *timing; 418 int nr_timing; 419}; 420 421struct nouveau_pm_engine { 422 struct nouveau_pm_voltage voltage; 423 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 424 int nr_perflvl; 425 struct nouveau_pm_memtimings memtimings; 426 struct nouveau_pm_temp_sensor_constants sensor_constants; 427 struct nouveau_pm_threshold_temp threshold_temp; 428 429 struct nouveau_pm_level boot; 430 struct nouveau_pm_level *cur; 431 432 struct device *hwmon; 433 434 int (*clock_get)(struct drm_device *, u32 id); 435 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 436 u32 id, int khz); 437 void (*clock_set)(struct drm_device *, void *); 438 int (*voltage_get)(struct drm_device *); 439 int (*voltage_set)(struct drm_device *, int voltage); 440 int (*fanspeed_get)(struct drm_device *); 441 int (*fanspeed_set)(struct drm_device *, int fanspeed); 442 int (*temp_get)(struct drm_device *); 443}; 444 445struct nouveau_engine { 446 struct nouveau_instmem_engine instmem; 447 struct nouveau_mc_engine mc; 448 struct nouveau_timer_engine timer; 449 struct nouveau_fb_engine fb; 450 struct nouveau_pgraph_engine graph; 451 struct nouveau_fifo_engine fifo; 452 struct nouveau_display_engine display; 453 struct nouveau_gpio_engine gpio; 454 struct nouveau_pm_engine pm; 455}; 456 457struct nouveau_pll_vals { 458 union { 459 struct { 460#ifdef __BIG_ENDIAN 461 uint8_t N1, M1, N2, M2; 462#else 463 uint8_t M1, N1, M2, N2; 464#endif 465 }; 466 struct { 467 uint16_t NM1, NM2; 468 } __attribute__((packed)); 469 }; 470 int log2P; 471 472 int refclk; 473}; 474 475enum nv04_fp_display_regs { 476 FP_DISPLAY_END, 477 FP_TOTAL, 478 FP_CRTC, 479 FP_SYNC_START, 480 FP_SYNC_END, 481 FP_VALID_START, 482 FP_VALID_END 483}; 484 485struct nv04_crtc_reg { 486 unsigned char MiscOutReg; /* */ 487 uint8_t CRTC[0xa0]; 488 uint8_t CR58[0x10]; 489 uint8_t Sequencer[5]; 490 uint8_t Graphics[9]; 491 uint8_t Attribute[21]; 492 unsigned char DAC[768]; /* Internal Colorlookuptable */ 493 494 /* PCRTC regs */ 495 uint32_t fb_start; 496 uint32_t crtc_cfg; 497 uint32_t cursor_cfg; 498 uint32_t gpio_ext; 499 uint32_t crtc_830; 500 uint32_t crtc_834; 501 uint32_t crtc_850; 502 uint32_t crtc_eng_ctrl; 503 504 /* PRAMDAC regs */ 505 uint32_t nv10_cursync; 506 struct nouveau_pll_vals pllvals; 507 uint32_t ramdac_gen_ctrl; 508 uint32_t ramdac_630; 509 uint32_t ramdac_634; 510 uint32_t tv_setup; 511 uint32_t tv_vtotal; 512 uint32_t tv_vskew; 513 uint32_t tv_vsync_delay; 514 uint32_t tv_htotal; 515 uint32_t tv_hskew; 516 uint32_t tv_hsync_delay; 517 uint32_t tv_hsync_delay2; 518 uint32_t fp_horiz_regs[7]; 519 uint32_t fp_vert_regs[7]; 520 uint32_t dither; 521 uint32_t fp_control; 522 uint32_t dither_regs[6]; 523 uint32_t fp_debug_0; 524 uint32_t fp_debug_1; 525 uint32_t fp_debug_2; 526 uint32_t fp_margin_color; 527 uint32_t ramdac_8c0; 528 uint32_t ramdac_a20; 529 uint32_t ramdac_a24; 530 uint32_t ramdac_a34; 531 uint32_t ctv_regs[38]; 532}; 533 534struct nv04_output_reg { 535 uint32_t output; 536 int head; 537}; 538 539struct nv04_mode_state { 540 uint32_t bpp; 541 uint32_t width; 542 uint32_t height; 543 uint32_t interlace; 544 uint32_t repaint0; 545 uint32_t repaint1; 546 uint32_t screen; 547 uint32_t scale; 548 uint32_t dither; 549 uint32_t extra; 550 uint32_t fifo; 551 uint32_t pixel; 552 uint32_t horiz; 553 int arbitration0; 554 int arbitration1; 555 uint32_t pll; 556 uint32_t pllB; 557 uint32_t vpll; 558 uint32_t vpll2; 559 uint32_t vpllB; 560 uint32_t vpll2B; 561 uint32_t pllsel; 562 uint32_t sel_clk; 563 uint32_t general; 564 uint32_t crtcOwner; 565 uint32_t head; 566 uint32_t head2; 567 uint32_t cursorConfig; 568 uint32_t cursor0; 569 uint32_t cursor1; 570 uint32_t cursor2; 571 uint32_t timingH; 572 uint32_t timingV; 573 uint32_t displayV; 574 uint32_t crtcSync; 575 576 struct nv04_crtc_reg crtc_reg[2]; 577}; 578 579enum nouveau_card_type { 580 NV_04 = 0x00, 581 NV_10 = 0x10, 582 NV_20 = 0x20, 583 NV_30 = 0x30, 584 NV_40 = 0x40, 585 NV_50 = 0x50, 586 NV_C0 = 0xc0, 587}; 588 589struct drm_nouveau_private { 590 struct drm_device *dev; 591 592 /* the card type, takes NV_* as values */ 593 enum nouveau_card_type card_type; 594 /* exact chipset, derived from NV_PMC_BOOT_0 */ 595 int chipset; 596 int flags; 597 598 void __iomem *mmio; 599 600 spinlock_t ramin_lock; 601 void __iomem *ramin; 602 u32 ramin_size; 603 u32 ramin_base; 604 bool ramin_available; 605 struct drm_mm ramin_heap; 606 struct list_head gpuobj_list; 607 608 struct nouveau_bo *vga_ram; 609 610 struct workqueue_struct *wq; 611 struct work_struct irq_work; 612 struct work_struct hpd_work; 613 614 struct list_head vbl_waiting; 615 616 struct { 617 struct drm_global_reference mem_global_ref; 618 struct ttm_bo_global_ref bo_global_ref; 619 struct ttm_bo_device bdev; 620 atomic_t validate_sequence; 621 } ttm; 622 623 int fifo_alloc_count; 624 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 625 626 struct nouveau_engine engine; 627 struct nouveau_channel *channel; 628 629 /* For PFIFO and PGRAPH. */ 630 spinlock_t context_switch_lock; 631 632 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 633 struct nouveau_ramht *ramht; 634 struct nouveau_gpuobj *ramfc; 635 struct nouveau_gpuobj *ramro; 636 637 uint32_t ramin_rsvd_vram; 638 639 struct { 640 enum { 641 NOUVEAU_GART_NONE = 0, 642 NOUVEAU_GART_AGP, 643 NOUVEAU_GART_SGDMA 644 } type; 645 uint64_t aper_base; 646 uint64_t aper_size; 647 uint64_t aper_free; 648 649 struct nouveau_gpuobj *sg_ctxdma; 650 struct page *sg_dummy_page; 651 dma_addr_t sg_dummy_bus; 652 } gart_info; 653 654 /* nv10-nv40 tiling regions */ 655 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 656 657 /* VRAM/fb configuration */ 658 uint64_t vram_size; 659 uint64_t vram_sys_base; 660 u32 vram_rblock_size; 661 662 uint64_t fb_phys; 663 uint64_t fb_available_size; 664 uint64_t fb_mappable_pages; 665 uint64_t fb_aper_free; 666 int fb_mtrr; 667 668 /* G8x/G9x virtual address space */ 669 uint64_t vm_gart_base; 670 uint64_t vm_gart_size; 671 uint64_t vm_vram_base; 672 uint64_t vm_vram_size; 673 uint64_t vm_end; 674 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 675 int vm_vram_pt_nr; 676 677 struct nvbios vbios; 678 679 struct nv04_mode_state mode_reg; 680 struct nv04_mode_state saved_reg; 681 uint32_t saved_vga_font[4][16384]; 682 uint32_t crtc_owner; 683 uint32_t dac_users[4]; 684 685 struct nouveau_suspend_resume { 686 uint32_t *ramin_copy; 687 } susres; 688 689 struct backlight_device *backlight; 690 691 struct nouveau_channel *evo; 692 struct { 693 struct dcb_entry *dcb; 694 u16 script; 695 u32 pclk; 696 } evo_irq; 697 698 struct { 699 struct dentry *channel_root; 700 } debugfs; 701 702 struct nouveau_fbdev *nfbdev; 703 struct apertures_struct *apertures; 704}; 705 706static inline struct drm_nouveau_private * 707nouveau_bdev(struct ttm_bo_device *bd) 708{ 709 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 710} 711 712static inline int 713nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 714{ 715 struct nouveau_bo *prev; 716 717 if (!pnvbo) 718 return -EINVAL; 719 prev = *pnvbo; 720 721 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 722 if (prev) { 723 struct ttm_buffer_object *bo = &prev->bo; 724 725 ttm_bo_unref(&bo); 726 } 727 728 return 0; 729} 730 731#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 732 struct drm_nouveau_private *nv = dev->dev_private; \ 733 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 734 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 735 DRM_CURRENTPID, (id)); \ 736 return -EPERM; \ 737 } \ 738 (ch) = nv->fifos[(id)]; \ 739} while (0) 740 741/* nouveau_drv.c */ 742extern int nouveau_agpmode; 743extern int nouveau_duallink; 744extern int nouveau_uscript_lvds; 745extern int nouveau_uscript_tmds; 746extern int nouveau_vram_pushbuf; 747extern int nouveau_vram_notify; 748extern int nouveau_fbpercrtc; 749extern int nouveau_tv_disable; 750extern char *nouveau_tv_norm; 751extern int nouveau_reg_debug; 752extern char *nouveau_vbios; 753extern int nouveau_ignorelid; 754extern int nouveau_nofbaccel; 755extern int nouveau_noaccel; 756extern int nouveau_override_conntype; 757extern char *nouveau_perflvl; 758extern int nouveau_perflvl_wr; 759 760extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 761extern int nouveau_pci_resume(struct pci_dev *pdev); 762 763/* nouveau_state.c */ 764extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 765extern int nouveau_load(struct drm_device *, unsigned long flags); 766extern int nouveau_firstopen(struct drm_device *); 767extern void nouveau_lastclose(struct drm_device *); 768extern int nouveau_unload(struct drm_device *); 769extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 770 struct drm_file *); 771extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 772 struct drm_file *); 773extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 774 uint32_t reg, uint32_t mask, uint32_t val); 775extern bool nouveau_wait_for_idle(struct drm_device *); 776extern int nouveau_card_init(struct drm_device *); 777 778/* nouveau_mem.c */ 779extern int nouveau_mem_vram_init(struct drm_device *); 780extern void nouveau_mem_vram_fini(struct drm_device *); 781extern int nouveau_mem_gart_init(struct drm_device *); 782extern void nouveau_mem_gart_fini(struct drm_device *); 783extern int nouveau_mem_init_agp(struct drm_device *); 784extern int nouveau_mem_reset_agp(struct drm_device *); 785extern void nouveau_mem_close(struct drm_device *); 786extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 787 uint32_t addr, 788 uint32_t size, 789 uint32_t pitch); 790extern void nv10_mem_expire_tiling(struct drm_device *dev, 791 struct nouveau_tile_reg *tile, 792 struct nouveau_fence *fence); 793extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 794 uint32_t size, uint32_t flags, 795 uint64_t phys); 796extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 797 uint32_t size); 798 799/* nouveau_notifier.c */ 800extern int nouveau_notifier_init_channel(struct nouveau_channel *); 801extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 802extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 803 int cout, uint32_t *offset); 804extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 805extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 806 struct drm_file *); 807extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 808 struct drm_file *); 809 810/* nouveau_channel.c */ 811extern struct drm_ioctl_desc nouveau_ioctls[]; 812extern int nouveau_max_ioctl; 813extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 814extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 815 int channel); 816extern int nouveau_channel_alloc(struct drm_device *dev, 817 struct nouveau_channel **chan, 818 struct drm_file *file_priv, 819 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 820extern void nouveau_channel_free(struct nouveau_channel *); 821 822/* nouveau_object.c */ 823extern int nouveau_gpuobj_early_init(struct drm_device *); 824extern int nouveau_gpuobj_init(struct drm_device *); 825extern void nouveau_gpuobj_takedown(struct drm_device *); 826extern int nouveau_gpuobj_suspend(struct drm_device *dev); 827extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 828extern void nouveau_gpuobj_resume(struct drm_device *dev); 829extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 830 uint32_t vram_h, uint32_t tt_h); 831extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 832extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 833 uint32_t size, int align, uint32_t flags, 834 struct nouveau_gpuobj **); 835extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 836 struct nouveau_gpuobj **); 837extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 838 u32 size, u32 flags, 839 struct nouveau_gpuobj **); 840extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 841 uint64_t offset, uint64_t size, int access, 842 int target, struct nouveau_gpuobj **); 843extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 844 uint64_t offset, uint64_t size, 845 int access, struct nouveau_gpuobj **, 846 uint32_t *o_ret); 847extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 848 struct nouveau_gpuobj **); 849extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 850 struct nouveau_gpuobj **); 851extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 852 struct drm_file *); 853extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 854 struct drm_file *); 855 856/* nouveau_irq.c */ 857extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 858extern void nouveau_irq_preinstall(struct drm_device *); 859extern int nouveau_irq_postinstall(struct drm_device *); 860extern void nouveau_irq_uninstall(struct drm_device *); 861 862/* nouveau_sgdma.c */ 863extern int nouveau_sgdma_init(struct drm_device *); 864extern void nouveau_sgdma_takedown(struct drm_device *); 865extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 866 uint32_t *page); 867extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 868 869/* nouveau_debugfs.c */ 870#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 871extern int nouveau_debugfs_init(struct drm_minor *); 872extern void nouveau_debugfs_takedown(struct drm_minor *); 873extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 874extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 875#else 876static inline int 877nouveau_debugfs_init(struct drm_minor *minor) 878{ 879 return 0; 880} 881 882static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 883{ 884} 885 886static inline int 887nouveau_debugfs_channel_init(struct nouveau_channel *chan) 888{ 889 return 0; 890} 891 892static inline void 893nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 894{ 895} 896#endif 897 898/* nouveau_dma.c */ 899extern void nouveau_dma_pre_init(struct nouveau_channel *); 900extern int nouveau_dma_init(struct nouveau_channel *); 901extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 902 903/* nouveau_acpi.c */ 904#define ROM_BIOS_PAGE 4096 905#if defined(CONFIG_ACPI) 906void nouveau_register_dsm_handler(void); 907void nouveau_unregister_dsm_handler(void); 908int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 909bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 910int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 911#else 912static inline void nouveau_register_dsm_handler(void) {} 913static inline void nouveau_unregister_dsm_handler(void) {} 914static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 915static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 916static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 917#endif 918 919/* nouveau_backlight.c */ 920#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 921extern int nouveau_backlight_init(struct drm_device *); 922extern void nouveau_backlight_exit(struct drm_device *); 923#else 924static inline int nouveau_backlight_init(struct drm_device *dev) 925{ 926 return 0; 927} 928 929static inline void nouveau_backlight_exit(struct drm_device *dev) { } 930#endif 931 932/* nouveau_bios.c */ 933extern int nouveau_bios_init(struct drm_device *); 934extern void nouveau_bios_takedown(struct drm_device *dev); 935extern int nouveau_run_vbios_init(struct drm_device *); 936extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 937 struct dcb_entry *); 938extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 939 enum dcb_gpio_tag); 940extern struct dcb_connector_table_entry * 941nouveau_bios_connector_entry(struct drm_device *, int index); 942extern u32 get_pll_register(struct drm_device *, enum pll_types); 943extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 944 struct pll_lims *); 945extern int nouveau_bios_run_display_table(struct drm_device *, 946 struct dcb_entry *, 947 uint32_t script, int pxclk); 948extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 949 int *length); 950extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 951extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 952extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 953 bool *dl, bool *if_is_24bit); 954extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 955 int head, int pxclk); 956extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 957 enum LVDS_script, int pxclk); 958 959/* nouveau_ttm.c */ 960int nouveau_ttm_global_init(struct drm_nouveau_private *); 961void nouveau_ttm_global_release(struct drm_nouveau_private *); 962int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 963 964/* nouveau_dp.c */ 965int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 966 uint8_t *data, int data_nr); 967bool nouveau_dp_detect(struct drm_encoder *); 968bool nouveau_dp_link_train(struct drm_encoder *); 969 970/* nv04_fb.c */ 971extern int nv04_fb_init(struct drm_device *); 972extern void nv04_fb_takedown(struct drm_device *); 973 974/* nv10_fb.c */ 975extern int nv10_fb_init(struct drm_device *); 976extern void nv10_fb_takedown(struct drm_device *); 977extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 978 uint32_t, uint32_t); 979 980/* nv30_fb.c */ 981extern int nv30_fb_init(struct drm_device *); 982extern void nv30_fb_takedown(struct drm_device *); 983 984/* nv40_fb.c */ 985extern int nv40_fb_init(struct drm_device *); 986extern void nv40_fb_takedown(struct drm_device *); 987extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 988 uint32_t, uint32_t); 989/* nv50_fb.c */ 990extern int nv50_fb_init(struct drm_device *); 991extern void nv50_fb_takedown(struct drm_device *); 992extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 993 994/* nvc0_fb.c */ 995extern int nvc0_fb_init(struct drm_device *); 996extern void nvc0_fb_takedown(struct drm_device *); 997 998/* nv04_fifo.c */ 999extern int nv04_fifo_init(struct drm_device *); 1000extern void nv04_fifo_disable(struct drm_device *); 1001extern void nv04_fifo_enable(struct drm_device *); 1002extern bool nv04_fifo_reassign(struct drm_device *, bool); 1003extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1004extern int nv04_fifo_channel_id(struct drm_device *); 1005extern int nv04_fifo_create_context(struct nouveau_channel *); 1006extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1007extern int nv04_fifo_load_context(struct nouveau_channel *); 1008extern int nv04_fifo_unload_context(struct drm_device *); 1009 1010/* nv10_fifo.c */ 1011extern int nv10_fifo_init(struct drm_device *); 1012extern int nv10_fifo_channel_id(struct drm_device *); 1013extern int nv10_fifo_create_context(struct nouveau_channel *); 1014extern void nv10_fifo_destroy_context(struct nouveau_channel *); 1015extern int nv10_fifo_load_context(struct nouveau_channel *); 1016extern int nv10_fifo_unload_context(struct drm_device *); 1017 1018/* nv40_fifo.c */ 1019extern int nv40_fifo_init(struct drm_device *); 1020extern int nv40_fifo_create_context(struct nouveau_channel *); 1021extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1022extern int nv40_fifo_load_context(struct nouveau_channel *); 1023extern int nv40_fifo_unload_context(struct drm_device *); 1024 1025/* nv50_fifo.c */ 1026extern int nv50_fifo_init(struct drm_device *); 1027extern void nv50_fifo_takedown(struct drm_device *); 1028extern int nv50_fifo_channel_id(struct drm_device *); 1029extern int nv50_fifo_create_context(struct nouveau_channel *); 1030extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1031extern int nv50_fifo_load_context(struct nouveau_channel *); 1032extern int nv50_fifo_unload_context(struct drm_device *); 1033 1034/* nvc0_fifo.c */ 1035extern int nvc0_fifo_init(struct drm_device *); 1036extern void nvc0_fifo_takedown(struct drm_device *); 1037extern void nvc0_fifo_disable(struct drm_device *); 1038extern void nvc0_fifo_enable(struct drm_device *); 1039extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1040extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1041extern int nvc0_fifo_channel_id(struct drm_device *); 1042extern int nvc0_fifo_create_context(struct nouveau_channel *); 1043extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1044extern int nvc0_fifo_load_context(struct nouveau_channel *); 1045extern int nvc0_fifo_unload_context(struct drm_device *); 1046 1047/* nv04_graph.c */ 1048extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1049extern int nv04_graph_init(struct drm_device *); 1050extern void nv04_graph_takedown(struct drm_device *); 1051extern void nv04_graph_fifo_access(struct drm_device *, bool); 1052extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1053extern int nv04_graph_create_context(struct nouveau_channel *); 1054extern void nv04_graph_destroy_context(struct nouveau_channel *); 1055extern int nv04_graph_load_context(struct nouveau_channel *); 1056extern int nv04_graph_unload_context(struct drm_device *); 1057extern void nv04_graph_context_switch(struct drm_device *); 1058 1059/* nv10_graph.c */ 1060extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1061extern int nv10_graph_init(struct drm_device *); 1062extern void nv10_graph_takedown(struct drm_device *); 1063extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1064extern int nv10_graph_create_context(struct nouveau_channel *); 1065extern void nv10_graph_destroy_context(struct nouveau_channel *); 1066extern int nv10_graph_load_context(struct nouveau_channel *); 1067extern int nv10_graph_unload_context(struct drm_device *); 1068extern void nv10_graph_context_switch(struct drm_device *); 1069extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1070 uint32_t, uint32_t); 1071 1072/* nv20_graph.c */ 1073extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1074extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1075extern int nv20_graph_create_context(struct nouveau_channel *); 1076extern void nv20_graph_destroy_context(struct nouveau_channel *); 1077extern int nv20_graph_load_context(struct nouveau_channel *); 1078extern int nv20_graph_unload_context(struct drm_device *); 1079extern int nv20_graph_init(struct drm_device *); 1080extern void nv20_graph_takedown(struct drm_device *); 1081extern int nv30_graph_init(struct drm_device *); 1082extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1083 uint32_t, uint32_t); 1084 1085/* nv40_graph.c */ 1086extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1087extern int nv40_graph_init(struct drm_device *); 1088extern void nv40_graph_takedown(struct drm_device *); 1089extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1090extern int nv40_graph_create_context(struct nouveau_channel *); 1091extern void nv40_graph_destroy_context(struct nouveau_channel *); 1092extern int nv40_graph_load_context(struct nouveau_channel *); 1093extern int nv40_graph_unload_context(struct drm_device *); 1094extern void nv40_grctx_init(struct nouveau_grctx *); 1095extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1096 uint32_t, uint32_t); 1097 1098/* nv50_graph.c */ 1099extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1100extern int nv50_graph_init(struct drm_device *); 1101extern void nv50_graph_takedown(struct drm_device *); 1102extern void nv50_graph_fifo_access(struct drm_device *, bool); 1103extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1104extern int nv50_graph_create_context(struct nouveau_channel *); 1105extern void nv50_graph_destroy_context(struct nouveau_channel *); 1106extern int nv50_graph_load_context(struct nouveau_channel *); 1107extern int nv50_graph_unload_context(struct drm_device *); 1108extern void nv50_graph_context_switch(struct drm_device *); 1109extern int nv50_grctx_init(struct nouveau_grctx *); 1110 1111/* nvc0_graph.c */ 1112extern int nvc0_graph_init(struct drm_device *); 1113extern void nvc0_graph_takedown(struct drm_device *); 1114extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1115extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1116extern int nvc0_graph_create_context(struct nouveau_channel *); 1117extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1118extern int nvc0_graph_load_context(struct nouveau_channel *); 1119extern int nvc0_graph_unload_context(struct drm_device *); 1120 1121/* nv04_instmem.c */ 1122extern int nv04_instmem_init(struct drm_device *); 1123extern void nv04_instmem_takedown(struct drm_device *); 1124extern int nv04_instmem_suspend(struct drm_device *); 1125extern void nv04_instmem_resume(struct drm_device *); 1126extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1127 uint32_t *size); 1128extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1129extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1130extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1131extern void nv04_instmem_flush(struct drm_device *); 1132 1133/* nv50_instmem.c */ 1134extern int nv50_instmem_init(struct drm_device *); 1135extern void nv50_instmem_takedown(struct drm_device *); 1136extern int nv50_instmem_suspend(struct drm_device *); 1137extern void nv50_instmem_resume(struct drm_device *); 1138extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1139 uint32_t *size); 1140extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1141extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1142extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1143extern void nv50_instmem_flush(struct drm_device *); 1144extern void nv84_instmem_flush(struct drm_device *); 1145extern void nv50_vm_flush(struct drm_device *, int engine); 1146 1147/* nvc0_instmem.c */ 1148extern int nvc0_instmem_init(struct drm_device *); 1149extern void nvc0_instmem_takedown(struct drm_device *); 1150extern int nvc0_instmem_suspend(struct drm_device *); 1151extern void nvc0_instmem_resume(struct drm_device *); 1152extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1153 uint32_t *size); 1154extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1155extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1156extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1157extern void nvc0_instmem_flush(struct drm_device *); 1158 1159/* nv04_mc.c */ 1160extern int nv04_mc_init(struct drm_device *); 1161extern void nv04_mc_takedown(struct drm_device *); 1162 1163/* nv40_mc.c */ 1164extern int nv40_mc_init(struct drm_device *); 1165extern void nv40_mc_takedown(struct drm_device *); 1166 1167/* nv50_mc.c */ 1168extern int nv50_mc_init(struct drm_device *); 1169extern void nv50_mc_takedown(struct drm_device *); 1170 1171/* nv04_timer.c */ 1172extern int nv04_timer_init(struct drm_device *); 1173extern uint64_t nv04_timer_read(struct drm_device *); 1174extern void nv04_timer_takedown(struct drm_device *); 1175 1176extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1177 unsigned long arg); 1178 1179/* nv04_dac.c */ 1180extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1181extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1182extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1183extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1184extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1185 1186/* nv04_dfp.c */ 1187extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1188extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1189extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1190 int head, bool dl); 1191extern void nv04_dfp_disable(struct drm_device *dev, int head); 1192extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1193 1194/* nv04_tv.c */ 1195extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1196extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1197 1198/* nv17_tv.c */ 1199extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1200 1201/* nv04_display.c */ 1202extern int nv04_display_early_init(struct drm_device *); 1203extern void nv04_display_late_takedown(struct drm_device *); 1204extern int nv04_display_create(struct drm_device *); 1205extern int nv04_display_init(struct drm_device *); 1206extern void nv04_display_destroy(struct drm_device *); 1207 1208/* nv04_crtc.c */ 1209extern int nv04_crtc_create(struct drm_device *, int index); 1210 1211/* nouveau_bo.c */ 1212extern struct ttm_bo_driver nouveau_bo_driver; 1213extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1214 int size, int align, uint32_t flags, 1215 uint32_t tile_mode, uint32_t tile_flags, 1216 bool no_vm, bool mappable, struct nouveau_bo **); 1217extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1218extern int nouveau_bo_unpin(struct nouveau_bo *); 1219extern int nouveau_bo_map(struct nouveau_bo *); 1220extern void nouveau_bo_unmap(struct nouveau_bo *); 1221extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1222 uint32_t busy); 1223extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1224extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1225extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1226extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1227extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1228 1229/* nouveau_fence.c */ 1230struct nouveau_fence; 1231extern int nouveau_fence_init(struct nouveau_channel *); 1232extern void nouveau_fence_fini(struct nouveau_channel *); 1233extern void nouveau_fence_update(struct nouveau_channel *); 1234extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1235 bool emit); 1236extern int nouveau_fence_emit(struct nouveau_fence *); 1237struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1238extern bool nouveau_fence_signalled(void *obj, void *arg); 1239extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1240extern int nouveau_fence_flush(void *obj, void *arg); 1241extern void nouveau_fence_unref(void **obj); 1242extern void *nouveau_fence_ref(void *obj); 1243 1244/* nouveau_gem.c */ 1245extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1246 int size, int align, uint32_t flags, 1247 uint32_t tile_mode, uint32_t tile_flags, 1248 bool no_vm, bool mappable, struct nouveau_bo **); 1249extern int nouveau_gem_object_new(struct drm_gem_object *); 1250extern void nouveau_gem_object_del(struct drm_gem_object *); 1251extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1252 struct drm_file *); 1253extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1254 struct drm_file *); 1255extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1256 struct drm_file *); 1257extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1258 struct drm_file *); 1259extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1260 struct drm_file *); 1261 1262/* nv10_gpio.c */ 1263int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1264int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1265 1266/* nv50_gpio.c */ 1267int nv50_gpio_init(struct drm_device *dev); 1268int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1269int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1270void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1271 1272/* nv50_calc. */ 1273int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1274 int *N1, int *M1, int *N2, int *M2, int *P); 1275int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1276 int clk, int *N, int *fN, int *M, int *P); 1277 1278#ifndef ioread32_native 1279#ifdef __BIG_ENDIAN 1280#define ioread16_native ioread16be 1281#define iowrite16_native iowrite16be 1282#define ioread32_native ioread32be 1283#define iowrite32_native iowrite32be 1284#else /* def __BIG_ENDIAN */ 1285#define ioread16_native ioread16 1286#define iowrite16_native iowrite16 1287#define ioread32_native ioread32 1288#define iowrite32_native iowrite32 1289#endif /* def __BIG_ENDIAN else */ 1290#endif /* !ioread32_native */ 1291 1292/* channel control reg access */ 1293static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1294{ 1295 return ioread32_native(chan->user + reg); 1296} 1297 1298static inline void nvchan_wr32(struct nouveau_channel *chan, 1299 unsigned reg, u32 val) 1300{ 1301 iowrite32_native(val, chan->user + reg); 1302} 1303 1304/* register access */ 1305static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1306{ 1307 struct drm_nouveau_private *dev_priv = dev->dev_private; 1308 return ioread32_native(dev_priv->mmio + reg); 1309} 1310 1311static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1312{ 1313 struct drm_nouveau_private *dev_priv = dev->dev_private; 1314 iowrite32_native(val, dev_priv->mmio + reg); 1315} 1316 1317static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1318{ 1319 u32 tmp = nv_rd32(dev, reg); 1320 nv_wr32(dev, reg, (tmp & ~mask) | val); 1321 return tmp; 1322} 1323 1324static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1325{ 1326 struct drm_nouveau_private *dev_priv = dev->dev_private; 1327 return ioread8(dev_priv->mmio + reg); 1328} 1329 1330static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1331{ 1332 struct drm_nouveau_private *dev_priv = dev->dev_private; 1333 iowrite8(val, dev_priv->mmio + reg); 1334} 1335 1336#define nv_wait(dev, reg, mask, val) \ 1337 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1338 1339/* PRAMIN access */ 1340static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1341{ 1342 struct drm_nouveau_private *dev_priv = dev->dev_private; 1343 return ioread32_native(dev_priv->ramin + offset); 1344} 1345 1346static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1347{ 1348 struct drm_nouveau_private *dev_priv = dev->dev_private; 1349 iowrite32_native(val, dev_priv->ramin + offset); 1350} 1351 1352/* object access */ 1353extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1354extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1355 1356/* 1357 * Logging 1358 * Argument d is (struct drm_device *). 1359 */ 1360#define NV_PRINTK(level, d, fmt, arg...) \ 1361 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1362 pci_name(d->pdev), ##arg) 1363#ifndef NV_DEBUG_NOTRACE 1364#define NV_DEBUG(d, fmt, arg...) do { \ 1365 if (drm_debug & DRM_UT_DRIVER) { \ 1366 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1367 __LINE__, ##arg); \ 1368 } \ 1369} while (0) 1370#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1371 if (drm_debug & DRM_UT_KMS) { \ 1372 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1373 __LINE__, ##arg); \ 1374 } \ 1375} while (0) 1376#else 1377#define NV_DEBUG(d, fmt, arg...) do { \ 1378 if (drm_debug & DRM_UT_DRIVER) \ 1379 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1380} while (0) 1381#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1382 if (drm_debug & DRM_UT_KMS) \ 1383 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1384} while (0) 1385#endif 1386#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1387#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1388#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1389#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1390#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1391 1392/* nouveau_reg_debug bitmask */ 1393enum { 1394 NOUVEAU_REG_DEBUG_MC = 0x1, 1395 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1396 NOUVEAU_REG_DEBUG_FB = 0x4, 1397 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1398 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1399 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1400 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1401 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1402 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1403 NOUVEAU_REG_DEBUG_EVO = 0x200, 1404}; 1405 1406#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1407 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1408 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1409} while (0) 1410 1411static inline bool 1412nv_two_heads(struct drm_device *dev) 1413{ 1414 struct drm_nouveau_private *dev_priv = dev->dev_private; 1415 const int impl = dev->pci_device & 0x0ff0; 1416 1417 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1418 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1419 return true; 1420 1421 return false; 1422} 1423 1424static inline bool 1425nv_gf4_disp_arch(struct drm_device *dev) 1426{ 1427 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1428} 1429 1430static inline bool 1431nv_two_reg_pll(struct drm_device *dev) 1432{ 1433 struct drm_nouveau_private *dev_priv = dev->dev_private; 1434 const int impl = dev->pci_device & 0x0ff0; 1435 1436 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1437 return true; 1438 return false; 1439} 1440 1441static inline bool 1442nv_match_device(struct drm_device *dev, unsigned device, 1443 unsigned sub_vendor, unsigned sub_device) 1444{ 1445 return dev->pdev->device == device && 1446 dev->pdev->subsystem_vendor == sub_vendor && 1447 dev->pdev->subsystem_device == sub_device; 1448} 1449 1450#define NV_SW 0x0000506e 1451#define NV_SW_DMA_SEMAPHORE 0x00000060 1452#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1453#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1454#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1455#define NV_SW_DMA_VBLSEM 0x0000018c 1456#define NV_SW_VBLSEM_OFFSET 0x00000400 1457#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1458#define NV_SW_VBLSEM_RELEASE 0x00000408 1459 1460#endif /* __NOUVEAU_DRV_H__ */ 1461