nouveau_drv.h revision 6032649df9f456f379be8d51f64488cacbfa8317
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 int pin_refcnt; 100}; 101 102#define nouveau_bo_tile_layout(nvbo) \ 103 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 104 105static inline struct nouveau_bo * 106nouveau_bo(struct ttm_buffer_object *bo) 107{ 108 return container_of(bo, struct nouveau_bo, bo); 109} 110 111static inline struct nouveau_bo * 112nouveau_gem_object(struct drm_gem_object *gem) 113{ 114 return gem ? gem->driver_private : NULL; 115} 116 117/* TODO: submit equivalent to TTM generic API upstream? */ 118static inline void __iomem * 119nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 120{ 121 bool is_iomem; 122 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 123 &nvbo->kmap, &is_iomem); 124 WARN_ON_ONCE(ioptr && !is_iomem); 125 return ioptr; 126} 127 128enum nouveau_flags { 129 NV_NFORCE = 0x10000000, 130 NV_NFORCE2 = 0x20000000 131}; 132 133#define NVOBJ_ENGINE_SW 0 134#define NVOBJ_ENGINE_GR 1 135#define NVOBJ_ENGINE_DISPLAY 2 136#define NVOBJ_ENGINE_INT 0xdeadbeef 137 138#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 139#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 140struct nouveau_gpuobj { 141 struct drm_device *dev; 142 struct kref refcount; 143 struct list_head list; 144 145 struct drm_mm_node *im_pramin; 146 struct nouveau_bo *im_backing; 147 uint32_t *im_backing_suspend; 148 int im_bound; 149 150 uint32_t flags; 151 152 u32 size; 153 u32 pinst; 154 u32 cinst; 155 u64 vinst; 156 157 uint32_t engine; 158 uint32_t class; 159 160 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 161 void *priv; 162}; 163 164struct nouveau_channel { 165 struct drm_device *dev; 166 int id; 167 168 atomic_t refcount; 169 struct mutex mutex; 170 171 /* owner of this fifo */ 172 struct drm_file *file_priv; 173 /* mapping of the fifo itself */ 174 struct drm_local_map *map; 175 176 /* mapping of the regs controling the fifo */ 177 void __iomem *user; 178 uint32_t user_get; 179 uint32_t user_put; 180 181 /* Fencing */ 182 struct { 183 /* lock protects the pending list only */ 184 spinlock_t lock; 185 struct list_head pending; 186 uint32_t sequence; 187 uint32_t sequence_ack; 188 atomic_t last_sequence_irq; 189 } fence; 190 191 /* DMA push buffer */ 192 struct nouveau_gpuobj *pushbuf; 193 struct nouveau_bo *pushbuf_bo; 194 uint32_t pushbuf_base; 195 196 /* Notifier memory */ 197 struct nouveau_bo *notifier_bo; 198 struct drm_mm notifier_heap; 199 200 /* PFIFO context */ 201 struct nouveau_gpuobj *ramfc; 202 struct nouveau_gpuobj *cache; 203 204 /* PGRAPH context */ 205 /* XXX may be merge 2 pointers as private data ??? */ 206 struct nouveau_gpuobj *ramin_grctx; 207 void *pgraph_ctx; 208 209 /* NV50 VM */ 210 struct nouveau_gpuobj *vm_pd; 211 struct nouveau_gpuobj *vm_gart_pt; 212 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 213 214 /* Objects */ 215 struct nouveau_gpuobj *ramin; /* Private instmem */ 216 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 217 struct nouveau_ramht *ramht; /* Hash table */ 218 219 /* GPU object info for stuff used in-kernel (mm_enabled) */ 220 uint32_t m2mf_ntfy; 221 uint32_t vram_handle; 222 uint32_t gart_handle; 223 bool accel_done; 224 225 /* Push buffer state (only for drm's channel on !mm_enabled) */ 226 struct { 227 int max; 228 int free; 229 int cur; 230 int put; 231 /* access via pushbuf_bo */ 232 233 int ib_base; 234 int ib_max; 235 int ib_free; 236 int ib_put; 237 } dma; 238 239 uint32_t sw_subchannel[8]; 240 241 struct { 242 struct nouveau_gpuobj *vblsem; 243 uint32_t vblsem_offset; 244 uint32_t vblsem_rval; 245 struct list_head vbl_wait; 246 } nvsw; 247 248 struct { 249 bool active; 250 char name[32]; 251 struct drm_info_list info; 252 } debugfs; 253}; 254 255struct nouveau_instmem_engine { 256 void *priv; 257 258 int (*init)(struct drm_device *dev); 259 void (*takedown)(struct drm_device *dev); 260 int (*suspend)(struct drm_device *dev); 261 void (*resume)(struct drm_device *dev); 262 263 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 264 uint32_t *size); 265 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 266 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 267 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 268 void (*flush)(struct drm_device *); 269}; 270 271struct nouveau_mc_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274}; 275 276struct nouveau_timer_engine { 277 int (*init)(struct drm_device *dev); 278 void (*takedown)(struct drm_device *dev); 279 uint64_t (*read)(struct drm_device *dev); 280}; 281 282struct nouveau_fb_engine { 283 int num_tiles; 284 285 int (*init)(struct drm_device *dev); 286 void (*takedown)(struct drm_device *dev); 287 288 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 289 uint32_t size, uint32_t pitch); 290}; 291 292struct nouveau_fifo_engine { 293 int channels; 294 295 struct nouveau_gpuobj *playlist[2]; 296 int cur_playlist; 297 298 int (*init)(struct drm_device *); 299 void (*takedown)(struct drm_device *); 300 301 void (*disable)(struct drm_device *); 302 void (*enable)(struct drm_device *); 303 bool (*reassign)(struct drm_device *, bool enable); 304 bool (*cache_pull)(struct drm_device *dev, bool enable); 305 306 int (*channel_id)(struct drm_device *); 307 308 int (*create_context)(struct nouveau_channel *); 309 void (*destroy_context)(struct nouveau_channel *); 310 int (*load_context)(struct nouveau_channel *); 311 int (*unload_context)(struct drm_device *); 312 void (*tlb_flush)(struct drm_device *dev); 313}; 314 315struct nouveau_pgraph_object_method { 316 int id; 317 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 318 uint32_t data); 319}; 320 321struct nouveau_pgraph_object_class { 322 int id; 323 bool software; 324 struct nouveau_pgraph_object_method *methods; 325}; 326 327struct nouveau_pgraph_engine { 328 struct nouveau_pgraph_object_class *grclass; 329 bool accel_blocked; 330 int grctx_size; 331 332 /* NV2x/NV3x context table (0x400780) */ 333 struct nouveau_gpuobj *ctx_table; 334 335 int (*init)(struct drm_device *); 336 void (*takedown)(struct drm_device *); 337 338 void (*fifo_access)(struct drm_device *, bool); 339 340 struct nouveau_channel *(*channel)(struct drm_device *); 341 int (*create_context)(struct nouveau_channel *); 342 void (*destroy_context)(struct nouveau_channel *); 343 int (*load_context)(struct nouveau_channel *); 344 int (*unload_context)(struct drm_device *); 345 void (*tlb_flush)(struct drm_device *dev); 346 347 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 348 uint32_t size, uint32_t pitch); 349}; 350 351struct nouveau_display_engine { 352 int (*early_init)(struct drm_device *); 353 void (*late_takedown)(struct drm_device *); 354 int (*create)(struct drm_device *); 355 int (*init)(struct drm_device *); 356 void (*destroy)(struct drm_device *); 357}; 358 359struct nouveau_gpio_engine { 360 int (*init)(struct drm_device *); 361 void (*takedown)(struct drm_device *); 362 363 int (*get)(struct drm_device *, enum dcb_gpio_tag); 364 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 365 366 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 367}; 368 369struct nouveau_pm_voltage_level { 370 u8 voltage; 371 u8 vid; 372}; 373 374struct nouveau_pm_voltage { 375 bool supported; 376 u8 vid_mask; 377 378 struct nouveau_pm_voltage_level *level; 379 int nr_level; 380}; 381 382#define NOUVEAU_PM_MAX_LEVEL 8 383struct nouveau_pm_level { 384 struct device_attribute dev_attr; 385 char name[32]; 386 int id; 387 388 u32 core; 389 u32 memory; 390 u32 shader; 391 u32 unk05; 392 393 u8 voltage; 394 u8 fanspeed; 395 396 u16 memscript; 397}; 398 399struct nouveau_pm_temp_sensor_constants { 400 u16 offset_constant; 401 s16 offset_mult; 402 u16 offset_div; 403 u16 slope_mult; 404 u16 slope_div; 405}; 406 407struct nouveau_pm_threshold_temp { 408 s16 critical; 409 s16 down_clock; 410 s16 fan_boost; 411}; 412 413struct nouveau_pm_memtiming { 414 u32 reg_100220; 415 u32 reg_100224; 416 u32 reg_100228; 417 u32 reg_10022c; 418 u32 reg_100230; 419 u32 reg_100234; 420 u32 reg_100238; 421 u32 reg_10023c; 422}; 423 424struct nouveau_pm_memtimings { 425 bool supported; 426 struct nouveau_pm_memtiming *timing; 427 int nr_timing; 428}; 429 430struct nouveau_pm_engine { 431 struct nouveau_pm_voltage voltage; 432 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 433 int nr_perflvl; 434 struct nouveau_pm_memtimings memtimings; 435 struct nouveau_pm_temp_sensor_constants sensor_constants; 436 struct nouveau_pm_threshold_temp threshold_temp; 437 438 struct nouveau_pm_level boot; 439 struct nouveau_pm_level *cur; 440 441 struct device *hwmon; 442 struct notifier_block acpi_nb; 443 444 int (*clock_get)(struct drm_device *, u32 id); 445 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 446 u32 id, int khz); 447 void (*clock_set)(struct drm_device *, void *); 448 int (*voltage_get)(struct drm_device *); 449 int (*voltage_set)(struct drm_device *, int voltage); 450 int (*fanspeed_get)(struct drm_device *); 451 int (*fanspeed_set)(struct drm_device *, int fanspeed); 452 int (*temp_get)(struct drm_device *); 453}; 454 455struct nouveau_engine { 456 struct nouveau_instmem_engine instmem; 457 struct nouveau_mc_engine mc; 458 struct nouveau_timer_engine timer; 459 struct nouveau_fb_engine fb; 460 struct nouveau_pgraph_engine graph; 461 struct nouveau_fifo_engine fifo; 462 struct nouveau_display_engine display; 463 struct nouveau_gpio_engine gpio; 464 struct nouveau_pm_engine pm; 465}; 466 467struct nouveau_pll_vals { 468 union { 469 struct { 470#ifdef __BIG_ENDIAN 471 uint8_t N1, M1, N2, M2; 472#else 473 uint8_t M1, N1, M2, N2; 474#endif 475 }; 476 struct { 477 uint16_t NM1, NM2; 478 } __attribute__((packed)); 479 }; 480 int log2P; 481 482 int refclk; 483}; 484 485enum nv04_fp_display_regs { 486 FP_DISPLAY_END, 487 FP_TOTAL, 488 FP_CRTC, 489 FP_SYNC_START, 490 FP_SYNC_END, 491 FP_VALID_START, 492 FP_VALID_END 493}; 494 495struct nv04_crtc_reg { 496 unsigned char MiscOutReg; 497 uint8_t CRTC[0xa0]; 498 uint8_t CR58[0x10]; 499 uint8_t Sequencer[5]; 500 uint8_t Graphics[9]; 501 uint8_t Attribute[21]; 502 unsigned char DAC[768]; 503 504 /* PCRTC regs */ 505 uint32_t fb_start; 506 uint32_t crtc_cfg; 507 uint32_t cursor_cfg; 508 uint32_t gpio_ext; 509 uint32_t crtc_830; 510 uint32_t crtc_834; 511 uint32_t crtc_850; 512 uint32_t crtc_eng_ctrl; 513 514 /* PRAMDAC regs */ 515 uint32_t nv10_cursync; 516 struct nouveau_pll_vals pllvals; 517 uint32_t ramdac_gen_ctrl; 518 uint32_t ramdac_630; 519 uint32_t ramdac_634; 520 uint32_t tv_setup; 521 uint32_t tv_vtotal; 522 uint32_t tv_vskew; 523 uint32_t tv_vsync_delay; 524 uint32_t tv_htotal; 525 uint32_t tv_hskew; 526 uint32_t tv_hsync_delay; 527 uint32_t tv_hsync_delay2; 528 uint32_t fp_horiz_regs[7]; 529 uint32_t fp_vert_regs[7]; 530 uint32_t dither; 531 uint32_t fp_control; 532 uint32_t dither_regs[6]; 533 uint32_t fp_debug_0; 534 uint32_t fp_debug_1; 535 uint32_t fp_debug_2; 536 uint32_t fp_margin_color; 537 uint32_t ramdac_8c0; 538 uint32_t ramdac_a20; 539 uint32_t ramdac_a24; 540 uint32_t ramdac_a34; 541 uint32_t ctv_regs[38]; 542}; 543 544struct nv04_output_reg { 545 uint32_t output; 546 int head; 547}; 548 549struct nv04_mode_state { 550 struct nv04_crtc_reg crtc_reg[2]; 551 uint32_t pllsel; 552 uint32_t sel_clk; 553}; 554 555enum nouveau_card_type { 556 NV_04 = 0x00, 557 NV_10 = 0x10, 558 NV_20 = 0x20, 559 NV_30 = 0x30, 560 NV_40 = 0x40, 561 NV_50 = 0x50, 562 NV_C0 = 0xc0, 563}; 564 565struct drm_nouveau_private { 566 struct drm_device *dev; 567 568 /* the card type, takes NV_* as values */ 569 enum nouveau_card_type card_type; 570 /* exact chipset, derived from NV_PMC_BOOT_0 */ 571 int chipset; 572 int flags; 573 574 void __iomem *mmio; 575 576 spinlock_t ramin_lock; 577 void __iomem *ramin; 578 u32 ramin_size; 579 u32 ramin_base; 580 bool ramin_available; 581 struct drm_mm ramin_heap; 582 struct list_head gpuobj_list; 583 584 struct nouveau_bo *vga_ram; 585 586 struct workqueue_struct *wq; 587 struct work_struct irq_work; 588 struct work_struct hpd_work; 589 590 struct { 591 spinlock_t lock; 592 uint32_t hpd0_bits; 593 uint32_t hpd1_bits; 594 } hpd_state; 595 596 struct list_head vbl_waiting; 597 598 struct { 599 struct drm_global_reference mem_global_ref; 600 struct ttm_bo_global_ref bo_global_ref; 601 struct ttm_bo_device bdev; 602 atomic_t validate_sequence; 603 } ttm; 604 605 struct { 606 spinlock_t lock; 607 struct drm_mm heap; 608 struct nouveau_bo *bo; 609 } fence; 610 611 struct { 612 spinlock_t lock; 613 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 614 } channels; 615 616 struct nouveau_engine engine; 617 struct nouveau_channel *channel; 618 619 /* For PFIFO and PGRAPH. */ 620 spinlock_t context_switch_lock; 621 622 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 623 struct nouveau_ramht *ramht; 624 struct nouveau_gpuobj *ramfc; 625 struct nouveau_gpuobj *ramro; 626 627 uint32_t ramin_rsvd_vram; 628 629 struct { 630 enum { 631 NOUVEAU_GART_NONE = 0, 632 NOUVEAU_GART_AGP, 633 NOUVEAU_GART_SGDMA 634 } type; 635 uint64_t aper_base; 636 uint64_t aper_size; 637 uint64_t aper_free; 638 639 struct nouveau_gpuobj *sg_ctxdma; 640 struct page *sg_dummy_page; 641 dma_addr_t sg_dummy_bus; 642 } gart_info; 643 644 /* nv10-nv40 tiling regions */ 645 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 646 647 /* VRAM/fb configuration */ 648 uint64_t vram_size; 649 uint64_t vram_sys_base; 650 u32 vram_rblock_size; 651 652 uint64_t fb_phys; 653 uint64_t fb_available_size; 654 uint64_t fb_mappable_pages; 655 uint64_t fb_aper_free; 656 int fb_mtrr; 657 658 /* G8x/G9x virtual address space */ 659 uint64_t vm_gart_base; 660 uint64_t vm_gart_size; 661 uint64_t vm_vram_base; 662 uint64_t vm_vram_size; 663 uint64_t vm_end; 664 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 665 int vm_vram_pt_nr; 666 667 struct nvbios vbios; 668 669 struct nv04_mode_state mode_reg; 670 struct nv04_mode_state saved_reg; 671 uint32_t saved_vga_font[4][16384]; 672 uint32_t crtc_owner; 673 uint32_t dac_users[4]; 674 675 struct nouveau_suspend_resume { 676 uint32_t *ramin_copy; 677 } susres; 678 679 struct backlight_device *backlight; 680 681 struct nouveau_channel *evo; 682 struct { 683 struct dcb_entry *dcb; 684 u16 script; 685 u32 pclk; 686 } evo_irq; 687 688 struct { 689 struct dentry *channel_root; 690 } debugfs; 691 692 struct nouveau_fbdev *nfbdev; 693 struct apertures_struct *apertures; 694}; 695 696static inline struct drm_nouveau_private * 697nouveau_private(struct drm_device *dev) 698{ 699 return dev->dev_private; 700} 701 702static inline struct drm_nouveau_private * 703nouveau_bdev(struct ttm_bo_device *bd) 704{ 705 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 706} 707 708static inline int 709nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 710{ 711 struct nouveau_bo *prev; 712 713 if (!pnvbo) 714 return -EINVAL; 715 prev = *pnvbo; 716 717 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 718 if (prev) { 719 struct ttm_buffer_object *bo = &prev->bo; 720 721 ttm_bo_unref(&bo); 722 } 723 724 return 0; 725} 726 727/* nouveau_drv.c */ 728extern int nouveau_agpmode; 729extern int nouveau_duallink; 730extern int nouveau_uscript_lvds; 731extern int nouveau_uscript_tmds; 732extern int nouveau_vram_pushbuf; 733extern int nouveau_vram_notify; 734extern int nouveau_fbpercrtc; 735extern int nouveau_tv_disable; 736extern char *nouveau_tv_norm; 737extern int nouveau_reg_debug; 738extern char *nouveau_vbios; 739extern int nouveau_ignorelid; 740extern int nouveau_nofbaccel; 741extern int nouveau_noaccel; 742extern int nouveau_force_post; 743extern int nouveau_override_conntype; 744extern char *nouveau_perflvl; 745extern int nouveau_perflvl_wr; 746 747extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 748extern int nouveau_pci_resume(struct pci_dev *pdev); 749 750/* nouveau_state.c */ 751extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 752extern int nouveau_load(struct drm_device *, unsigned long flags); 753extern int nouveau_firstopen(struct drm_device *); 754extern void nouveau_lastclose(struct drm_device *); 755extern int nouveau_unload(struct drm_device *); 756extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 757 struct drm_file *); 758extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 759 struct drm_file *); 760extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 761 uint32_t reg, uint32_t mask, uint32_t val); 762extern bool nouveau_wait_for_idle(struct drm_device *); 763extern int nouveau_card_init(struct drm_device *); 764 765/* nouveau_mem.c */ 766extern int nouveau_mem_vram_init(struct drm_device *); 767extern void nouveau_mem_vram_fini(struct drm_device *); 768extern int nouveau_mem_gart_init(struct drm_device *); 769extern void nouveau_mem_gart_fini(struct drm_device *); 770extern int nouveau_mem_init_agp(struct drm_device *); 771extern int nouveau_mem_reset_agp(struct drm_device *); 772extern void nouveau_mem_close(struct drm_device *); 773extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 774 uint32_t addr, 775 uint32_t size, 776 uint32_t pitch); 777extern void nv10_mem_expire_tiling(struct drm_device *dev, 778 struct nouveau_tile_reg *tile, 779 struct nouveau_fence *fence); 780extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 781 uint32_t size, uint32_t flags, 782 uint64_t phys); 783extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 784 uint32_t size); 785 786/* nouveau_notifier.c */ 787extern int nouveau_notifier_init_channel(struct nouveau_channel *); 788extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 789extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 790 int cout, uint32_t *offset); 791extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 792extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 793 struct drm_file *); 794extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 795 struct drm_file *); 796 797/* nouveau_channel.c */ 798extern struct drm_ioctl_desc nouveau_ioctls[]; 799extern int nouveau_max_ioctl; 800extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 801extern int nouveau_channel_alloc(struct drm_device *dev, 802 struct nouveau_channel **chan, 803 struct drm_file *file_priv, 804 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 805extern struct nouveau_channel * 806nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 807extern void nouveau_channel_put(struct nouveau_channel **); 808 809/* nouveau_object.c */ 810extern int nouveau_gpuobj_early_init(struct drm_device *); 811extern int nouveau_gpuobj_init(struct drm_device *); 812extern void nouveau_gpuobj_takedown(struct drm_device *); 813extern int nouveau_gpuobj_suspend(struct drm_device *dev); 814extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 815extern void nouveau_gpuobj_resume(struct drm_device *dev); 816extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 817 uint32_t vram_h, uint32_t tt_h); 818extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 819extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 820 uint32_t size, int align, uint32_t flags, 821 struct nouveau_gpuobj **); 822extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 823 struct nouveau_gpuobj **); 824extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 825 u32 size, u32 flags, 826 struct nouveau_gpuobj **); 827extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 828 uint64_t offset, uint64_t size, int access, 829 int target, struct nouveau_gpuobj **); 830extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 831 uint64_t offset, uint64_t size, 832 int access, struct nouveau_gpuobj **, 833 uint32_t *o_ret); 834extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 835 struct nouveau_gpuobj **); 836extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 837 struct nouveau_gpuobj **); 838extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 839 struct drm_file *); 840extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 841 struct drm_file *); 842 843/* nouveau_irq.c */ 844extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 845extern void nouveau_irq_preinstall(struct drm_device *); 846extern int nouveau_irq_postinstall(struct drm_device *); 847extern void nouveau_irq_uninstall(struct drm_device *); 848 849/* nouveau_sgdma.c */ 850extern int nouveau_sgdma_init(struct drm_device *); 851extern void nouveau_sgdma_takedown(struct drm_device *); 852extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 853 uint32_t *page); 854extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 855 856/* nouveau_debugfs.c */ 857#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 858extern int nouveau_debugfs_init(struct drm_minor *); 859extern void nouveau_debugfs_takedown(struct drm_minor *); 860extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 861extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 862#else 863static inline int 864nouveau_debugfs_init(struct drm_minor *minor) 865{ 866 return 0; 867} 868 869static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 870{ 871} 872 873static inline int 874nouveau_debugfs_channel_init(struct nouveau_channel *chan) 875{ 876 return 0; 877} 878 879static inline void 880nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 881{ 882} 883#endif 884 885/* nouveau_dma.c */ 886extern void nouveau_dma_pre_init(struct nouveau_channel *); 887extern int nouveau_dma_init(struct nouveau_channel *); 888extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 889 890/* nouveau_acpi.c */ 891#define ROM_BIOS_PAGE 4096 892#if defined(CONFIG_ACPI) 893void nouveau_register_dsm_handler(void); 894void nouveau_unregister_dsm_handler(void); 895int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 896bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 897int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 898#else 899static inline void nouveau_register_dsm_handler(void) {} 900static inline void nouveau_unregister_dsm_handler(void) {} 901static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 902static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 903static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 904#endif 905 906/* nouveau_backlight.c */ 907#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 908extern int nouveau_backlight_init(struct drm_device *); 909extern void nouveau_backlight_exit(struct drm_device *); 910#else 911static inline int nouveau_backlight_init(struct drm_device *dev) 912{ 913 return 0; 914} 915 916static inline void nouveau_backlight_exit(struct drm_device *dev) { } 917#endif 918 919/* nouveau_bios.c */ 920extern int nouveau_bios_init(struct drm_device *); 921extern void nouveau_bios_takedown(struct drm_device *dev); 922extern int nouveau_run_vbios_init(struct drm_device *); 923extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 924 struct dcb_entry *); 925extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 926 enum dcb_gpio_tag); 927extern struct dcb_connector_table_entry * 928nouveau_bios_connector_entry(struct drm_device *, int index); 929extern u32 get_pll_register(struct drm_device *, enum pll_types); 930extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 931 struct pll_lims *); 932extern int nouveau_bios_run_display_table(struct drm_device *, 933 struct dcb_entry *, 934 uint32_t script, int pxclk); 935extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 936 int *length); 937extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 938extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 939extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 940 bool *dl, bool *if_is_24bit); 941extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 942 int head, int pxclk); 943extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 944 enum LVDS_script, int pxclk); 945 946/* nouveau_ttm.c */ 947int nouveau_ttm_global_init(struct drm_nouveau_private *); 948void nouveau_ttm_global_release(struct drm_nouveau_private *); 949int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 950 951/* nouveau_dp.c */ 952int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 953 uint8_t *data, int data_nr); 954bool nouveau_dp_detect(struct drm_encoder *); 955bool nouveau_dp_link_train(struct drm_encoder *); 956 957/* nv04_fb.c */ 958extern int nv04_fb_init(struct drm_device *); 959extern void nv04_fb_takedown(struct drm_device *); 960 961/* nv10_fb.c */ 962extern int nv10_fb_init(struct drm_device *); 963extern void nv10_fb_takedown(struct drm_device *); 964extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 965 uint32_t, uint32_t); 966 967/* nv30_fb.c */ 968extern int nv30_fb_init(struct drm_device *); 969extern void nv30_fb_takedown(struct drm_device *); 970 971/* nv40_fb.c */ 972extern int nv40_fb_init(struct drm_device *); 973extern void nv40_fb_takedown(struct drm_device *); 974extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 975 uint32_t, uint32_t); 976/* nv50_fb.c */ 977extern int nv50_fb_init(struct drm_device *); 978extern void nv50_fb_takedown(struct drm_device *); 979extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 980 981/* nvc0_fb.c */ 982extern int nvc0_fb_init(struct drm_device *); 983extern void nvc0_fb_takedown(struct drm_device *); 984 985/* nv04_fifo.c */ 986extern int nv04_fifo_init(struct drm_device *); 987extern void nv04_fifo_disable(struct drm_device *); 988extern void nv04_fifo_enable(struct drm_device *); 989extern bool nv04_fifo_reassign(struct drm_device *, bool); 990extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 991extern int nv04_fifo_channel_id(struct drm_device *); 992extern int nv04_fifo_create_context(struct nouveau_channel *); 993extern void nv04_fifo_destroy_context(struct nouveau_channel *); 994extern int nv04_fifo_load_context(struct nouveau_channel *); 995extern int nv04_fifo_unload_context(struct drm_device *); 996 997/* nv10_fifo.c */ 998extern int nv10_fifo_init(struct drm_device *); 999extern int nv10_fifo_channel_id(struct drm_device *); 1000extern int nv10_fifo_create_context(struct nouveau_channel *); 1001extern void nv10_fifo_destroy_context(struct nouveau_channel *); 1002extern int nv10_fifo_load_context(struct nouveau_channel *); 1003extern int nv10_fifo_unload_context(struct drm_device *); 1004 1005/* nv40_fifo.c */ 1006extern int nv40_fifo_init(struct drm_device *); 1007extern int nv40_fifo_create_context(struct nouveau_channel *); 1008extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1009extern int nv40_fifo_load_context(struct nouveau_channel *); 1010extern int nv40_fifo_unload_context(struct drm_device *); 1011 1012/* nv50_fifo.c */ 1013extern int nv50_fifo_init(struct drm_device *); 1014extern void nv50_fifo_takedown(struct drm_device *); 1015extern int nv50_fifo_channel_id(struct drm_device *); 1016extern int nv50_fifo_create_context(struct nouveau_channel *); 1017extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1018extern int nv50_fifo_load_context(struct nouveau_channel *); 1019extern int nv50_fifo_unload_context(struct drm_device *); 1020extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1021 1022/* nvc0_fifo.c */ 1023extern int nvc0_fifo_init(struct drm_device *); 1024extern void nvc0_fifo_takedown(struct drm_device *); 1025extern void nvc0_fifo_disable(struct drm_device *); 1026extern void nvc0_fifo_enable(struct drm_device *); 1027extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1028extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1029extern int nvc0_fifo_channel_id(struct drm_device *); 1030extern int nvc0_fifo_create_context(struct nouveau_channel *); 1031extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1032extern int nvc0_fifo_load_context(struct nouveau_channel *); 1033extern int nvc0_fifo_unload_context(struct drm_device *); 1034 1035/* nv04_graph.c */ 1036extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1037extern int nv04_graph_init(struct drm_device *); 1038extern void nv04_graph_takedown(struct drm_device *); 1039extern void nv04_graph_fifo_access(struct drm_device *, bool); 1040extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1041extern int nv04_graph_create_context(struct nouveau_channel *); 1042extern void nv04_graph_destroy_context(struct nouveau_channel *); 1043extern int nv04_graph_load_context(struct nouveau_channel *); 1044extern int nv04_graph_unload_context(struct drm_device *); 1045extern void nv04_graph_context_switch(struct drm_device *); 1046 1047/* nv10_graph.c */ 1048extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1049extern int nv10_graph_init(struct drm_device *); 1050extern void nv10_graph_takedown(struct drm_device *); 1051extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1052extern int nv10_graph_create_context(struct nouveau_channel *); 1053extern void nv10_graph_destroy_context(struct nouveau_channel *); 1054extern int nv10_graph_load_context(struct nouveau_channel *); 1055extern int nv10_graph_unload_context(struct drm_device *); 1056extern void nv10_graph_context_switch(struct drm_device *); 1057extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1058 uint32_t, uint32_t); 1059 1060/* nv20_graph.c */ 1061extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1062extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1063extern int nv20_graph_create_context(struct nouveau_channel *); 1064extern void nv20_graph_destroy_context(struct nouveau_channel *); 1065extern int nv20_graph_load_context(struct nouveau_channel *); 1066extern int nv20_graph_unload_context(struct drm_device *); 1067extern int nv20_graph_init(struct drm_device *); 1068extern void nv20_graph_takedown(struct drm_device *); 1069extern int nv30_graph_init(struct drm_device *); 1070extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1071 uint32_t, uint32_t); 1072 1073/* nv40_graph.c */ 1074extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1075extern int nv40_graph_init(struct drm_device *); 1076extern void nv40_graph_takedown(struct drm_device *); 1077extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1078extern int nv40_graph_create_context(struct nouveau_channel *); 1079extern void nv40_graph_destroy_context(struct nouveau_channel *); 1080extern int nv40_graph_load_context(struct nouveau_channel *); 1081extern int nv40_graph_unload_context(struct drm_device *); 1082extern void nv40_grctx_init(struct nouveau_grctx *); 1083extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1084 uint32_t, uint32_t); 1085 1086/* nv50_graph.c */ 1087extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1088extern int nv50_graph_init(struct drm_device *); 1089extern void nv50_graph_takedown(struct drm_device *); 1090extern void nv50_graph_fifo_access(struct drm_device *, bool); 1091extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1092extern int nv50_graph_create_context(struct nouveau_channel *); 1093extern void nv50_graph_destroy_context(struct nouveau_channel *); 1094extern int nv50_graph_load_context(struct nouveau_channel *); 1095extern int nv50_graph_unload_context(struct drm_device *); 1096extern void nv50_graph_context_switch(struct drm_device *); 1097extern int nv50_grctx_init(struct nouveau_grctx *); 1098extern void nv50_graph_tlb_flush(struct drm_device *dev); 1099extern void nv86_graph_tlb_flush(struct drm_device *dev); 1100 1101/* nvc0_graph.c */ 1102extern int nvc0_graph_init(struct drm_device *); 1103extern void nvc0_graph_takedown(struct drm_device *); 1104extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1105extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1106extern int nvc0_graph_create_context(struct nouveau_channel *); 1107extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1108extern int nvc0_graph_load_context(struct nouveau_channel *); 1109extern int nvc0_graph_unload_context(struct drm_device *); 1110 1111/* nv04_instmem.c */ 1112extern int nv04_instmem_init(struct drm_device *); 1113extern void nv04_instmem_takedown(struct drm_device *); 1114extern int nv04_instmem_suspend(struct drm_device *); 1115extern void nv04_instmem_resume(struct drm_device *); 1116extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1117 uint32_t *size); 1118extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1119extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1120extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1121extern void nv04_instmem_flush(struct drm_device *); 1122 1123/* nv50_instmem.c */ 1124extern int nv50_instmem_init(struct drm_device *); 1125extern void nv50_instmem_takedown(struct drm_device *); 1126extern int nv50_instmem_suspend(struct drm_device *); 1127extern void nv50_instmem_resume(struct drm_device *); 1128extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1129 uint32_t *size); 1130extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1131extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1132extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1133extern void nv50_instmem_flush(struct drm_device *); 1134extern void nv84_instmem_flush(struct drm_device *); 1135extern void nv50_vm_flush(struct drm_device *, int engine); 1136 1137/* nvc0_instmem.c */ 1138extern int nvc0_instmem_init(struct drm_device *); 1139extern void nvc0_instmem_takedown(struct drm_device *); 1140extern int nvc0_instmem_suspend(struct drm_device *); 1141extern void nvc0_instmem_resume(struct drm_device *); 1142extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1143 uint32_t *size); 1144extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1145extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1146extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1147extern void nvc0_instmem_flush(struct drm_device *); 1148 1149/* nv04_mc.c */ 1150extern int nv04_mc_init(struct drm_device *); 1151extern void nv04_mc_takedown(struct drm_device *); 1152 1153/* nv40_mc.c */ 1154extern int nv40_mc_init(struct drm_device *); 1155extern void nv40_mc_takedown(struct drm_device *); 1156 1157/* nv50_mc.c */ 1158extern int nv50_mc_init(struct drm_device *); 1159extern void nv50_mc_takedown(struct drm_device *); 1160 1161/* nv04_timer.c */ 1162extern int nv04_timer_init(struct drm_device *); 1163extern uint64_t nv04_timer_read(struct drm_device *); 1164extern void nv04_timer_takedown(struct drm_device *); 1165 1166extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1167 unsigned long arg); 1168 1169/* nv04_dac.c */ 1170extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1171extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1172extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1173extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1174extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1175 1176/* nv04_dfp.c */ 1177extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1178extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1179extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1180 int head, bool dl); 1181extern void nv04_dfp_disable(struct drm_device *dev, int head); 1182extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1183 1184/* nv04_tv.c */ 1185extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1186extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1187 1188/* nv17_tv.c */ 1189extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1190 1191/* nv04_display.c */ 1192extern int nv04_display_early_init(struct drm_device *); 1193extern void nv04_display_late_takedown(struct drm_device *); 1194extern int nv04_display_create(struct drm_device *); 1195extern int nv04_display_init(struct drm_device *); 1196extern void nv04_display_destroy(struct drm_device *); 1197 1198/* nv04_crtc.c */ 1199extern int nv04_crtc_create(struct drm_device *, int index); 1200 1201/* nouveau_bo.c */ 1202extern struct ttm_bo_driver nouveau_bo_driver; 1203extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1204 int size, int align, uint32_t flags, 1205 uint32_t tile_mode, uint32_t tile_flags, 1206 bool no_vm, bool mappable, struct nouveau_bo **); 1207extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1208extern int nouveau_bo_unpin(struct nouveau_bo *); 1209extern int nouveau_bo_map(struct nouveau_bo *); 1210extern void nouveau_bo_unmap(struct nouveau_bo *); 1211extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1212 uint32_t busy); 1213extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1214extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1215extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1216extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1217 1218/* nouveau_fence.c */ 1219struct nouveau_fence; 1220extern int nouveau_fence_init(struct drm_device *); 1221extern void nouveau_fence_fini(struct drm_device *); 1222extern int nouveau_fence_channel_init(struct nouveau_channel *); 1223extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1224extern void nouveau_fence_update(struct nouveau_channel *); 1225extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1226 bool emit); 1227extern int nouveau_fence_emit(struct nouveau_fence *); 1228extern void nouveau_fence_work(struct nouveau_fence *fence, 1229 void (*work)(void *priv, bool signalled), 1230 void *priv); 1231struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1232extern bool nouveau_fence_signalled(void *obj, void *arg); 1233extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1234extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1235extern int nouveau_fence_flush(void *obj, void *arg); 1236extern void nouveau_fence_unref(void **obj); 1237extern void *nouveau_fence_ref(void *obj); 1238 1239/* nouveau_gem.c */ 1240extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1241 int size, int align, uint32_t flags, 1242 uint32_t tile_mode, uint32_t tile_flags, 1243 bool no_vm, bool mappable, struct nouveau_bo **); 1244extern int nouveau_gem_object_new(struct drm_gem_object *); 1245extern void nouveau_gem_object_del(struct drm_gem_object *); 1246extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1247 struct drm_file *); 1248extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1249 struct drm_file *); 1250extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1251 struct drm_file *); 1252extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1253 struct drm_file *); 1254extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1255 struct drm_file *); 1256 1257/* nv10_gpio.c */ 1258int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1259int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1260 1261/* nv50_gpio.c */ 1262int nv50_gpio_init(struct drm_device *dev); 1263int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1264int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1265void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1266 1267/* nv50_calc. */ 1268int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1269 int *N1, int *M1, int *N2, int *M2, int *P); 1270int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1271 int clk, int *N, int *fN, int *M, int *P); 1272 1273#ifndef ioread32_native 1274#ifdef __BIG_ENDIAN 1275#define ioread16_native ioread16be 1276#define iowrite16_native iowrite16be 1277#define ioread32_native ioread32be 1278#define iowrite32_native iowrite32be 1279#else /* def __BIG_ENDIAN */ 1280#define ioread16_native ioread16 1281#define iowrite16_native iowrite16 1282#define ioread32_native ioread32 1283#define iowrite32_native iowrite32 1284#endif /* def __BIG_ENDIAN else */ 1285#endif /* !ioread32_native */ 1286 1287/* channel control reg access */ 1288static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1289{ 1290 return ioread32_native(chan->user + reg); 1291} 1292 1293static inline void nvchan_wr32(struct nouveau_channel *chan, 1294 unsigned reg, u32 val) 1295{ 1296 iowrite32_native(val, chan->user + reg); 1297} 1298 1299/* register access */ 1300static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1301{ 1302 struct drm_nouveau_private *dev_priv = dev->dev_private; 1303 return ioread32_native(dev_priv->mmio + reg); 1304} 1305 1306static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1307{ 1308 struct drm_nouveau_private *dev_priv = dev->dev_private; 1309 iowrite32_native(val, dev_priv->mmio + reg); 1310} 1311 1312static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1313{ 1314 u32 tmp = nv_rd32(dev, reg); 1315 nv_wr32(dev, reg, (tmp & ~mask) | val); 1316 return tmp; 1317} 1318 1319static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1320{ 1321 struct drm_nouveau_private *dev_priv = dev->dev_private; 1322 return ioread8(dev_priv->mmio + reg); 1323} 1324 1325static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1326{ 1327 struct drm_nouveau_private *dev_priv = dev->dev_private; 1328 iowrite8(val, dev_priv->mmio + reg); 1329} 1330 1331#define nv_wait(dev, reg, mask, val) \ 1332 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1333 1334/* PRAMIN access */ 1335static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1336{ 1337 struct drm_nouveau_private *dev_priv = dev->dev_private; 1338 return ioread32_native(dev_priv->ramin + offset); 1339} 1340 1341static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1342{ 1343 struct drm_nouveau_private *dev_priv = dev->dev_private; 1344 iowrite32_native(val, dev_priv->ramin + offset); 1345} 1346 1347/* object access */ 1348extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1349extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1350 1351/* 1352 * Logging 1353 * Argument d is (struct drm_device *). 1354 */ 1355#define NV_PRINTK(level, d, fmt, arg...) \ 1356 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1357 pci_name(d->pdev), ##arg) 1358#ifndef NV_DEBUG_NOTRACE 1359#define NV_DEBUG(d, fmt, arg...) do { \ 1360 if (drm_debug & DRM_UT_DRIVER) { \ 1361 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1362 __LINE__, ##arg); \ 1363 } \ 1364} while (0) 1365#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1366 if (drm_debug & DRM_UT_KMS) { \ 1367 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1368 __LINE__, ##arg); \ 1369 } \ 1370} while (0) 1371#else 1372#define NV_DEBUG(d, fmt, arg...) do { \ 1373 if (drm_debug & DRM_UT_DRIVER) \ 1374 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1375} while (0) 1376#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1377 if (drm_debug & DRM_UT_KMS) \ 1378 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1379} while (0) 1380#endif 1381#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1382#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1383#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1384#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1385#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1386 1387/* nouveau_reg_debug bitmask */ 1388enum { 1389 NOUVEAU_REG_DEBUG_MC = 0x1, 1390 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1391 NOUVEAU_REG_DEBUG_FB = 0x4, 1392 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1393 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1394 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1395 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1396 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1397 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1398 NOUVEAU_REG_DEBUG_EVO = 0x200, 1399}; 1400 1401#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1402 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1403 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1404} while (0) 1405 1406static inline bool 1407nv_two_heads(struct drm_device *dev) 1408{ 1409 struct drm_nouveau_private *dev_priv = dev->dev_private; 1410 const int impl = dev->pci_device & 0x0ff0; 1411 1412 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1413 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1414 return true; 1415 1416 return false; 1417} 1418 1419static inline bool 1420nv_gf4_disp_arch(struct drm_device *dev) 1421{ 1422 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1423} 1424 1425static inline bool 1426nv_two_reg_pll(struct drm_device *dev) 1427{ 1428 struct drm_nouveau_private *dev_priv = dev->dev_private; 1429 const int impl = dev->pci_device & 0x0ff0; 1430 1431 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1432 return true; 1433 return false; 1434} 1435 1436static inline bool 1437nv_match_device(struct drm_device *dev, unsigned device, 1438 unsigned sub_vendor, unsigned sub_device) 1439{ 1440 return dev->pdev->device == device && 1441 dev->pdev->subsystem_vendor == sub_vendor && 1442 dev->pdev->subsystem_device == sub_device; 1443} 1444 1445#define NV_SW 0x0000506e 1446#define NV_SW_DMA_SEMAPHORE 0x00000060 1447#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1448#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1449#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1450#define NV_SW_YIELD 0x00000080 1451#define NV_SW_DMA_VBLSEM 0x0000018c 1452#define NV_SW_VBLSEM_OFFSET 0x00000400 1453#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1454#define NV_SW_VBLSEM_RELEASE 0x00000408 1455 1456#endif /* __NOUVEAU_DRV_H__ */ 1457