nouveau_drv.h revision 639212d01157266d9ee0b904fbc9f4a556e1c711
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma tmp_vma; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 120 uint32_t tile_mode; 121 uint32_t tile_flags; 122 struct nouveau_tile_reg *tile; 123 124 struct drm_gem_object *gem; 125 int pin_refcnt; 126}; 127 128#define nouveau_bo_tile_layout(nvbo) \ 129 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 130 131static inline struct nouveau_bo * 132nouveau_bo(struct ttm_buffer_object *bo) 133{ 134 return container_of(bo, struct nouveau_bo, bo); 135} 136 137static inline struct nouveau_bo * 138nouveau_gem_object(struct drm_gem_object *gem) 139{ 140 return gem ? gem->driver_private : NULL; 141} 142 143/* TODO: submit equivalent to TTM generic API upstream? */ 144static inline void __iomem * 145nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 146{ 147 bool is_iomem; 148 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 149 &nvbo->kmap, &is_iomem); 150 WARN_ON_ONCE(ioptr && !is_iomem); 151 return ioptr; 152} 153 154enum nouveau_flags { 155 NV_NFORCE = 0x10000000, 156 NV_NFORCE2 = 0x20000000 157}; 158 159#define NVOBJ_ENGINE_SW 0 160#define NVOBJ_ENGINE_GR 1 161#define NVOBJ_ENGINE_CRYPT 2 162#define NVOBJ_ENGINE_COPY0 3 163#define NVOBJ_ENGINE_COPY1 4 164#define NVOBJ_ENGINE_MPEG 5 165#define NVOBJ_ENGINE_DISPLAY 15 166#define NVOBJ_ENGINE_NR 16 167 168#define NVOBJ_FLAG_DONT_MAP (1 << 0) 169#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 170#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 171#define NVOBJ_FLAG_VM (1 << 3) 172#define NVOBJ_FLAG_VM_USER (1 << 4) 173 174#define NVOBJ_CINST_GLOBAL 0xdeadbeef 175 176struct nouveau_gpuobj { 177 struct drm_device *dev; 178 struct kref refcount; 179 struct list_head list; 180 181 void *node; 182 u32 *suspend; 183 184 uint32_t flags; 185 186 u32 size; 187 u32 pinst; /* PRAMIN BAR offset */ 188 u32 cinst; /* Channel offset */ 189 u64 vinst; /* VRAM address */ 190 u64 linst; /* VM address */ 191 192 uint32_t engine; 193 uint32_t class; 194 195 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 196 void *priv; 197}; 198 199struct nouveau_page_flip_state { 200 struct list_head head; 201 struct drm_pending_vblank_event *event; 202 int crtc, bpp, pitch, x, y; 203 uint64_t offset; 204}; 205 206enum nouveau_channel_mutex_class { 207 NOUVEAU_UCHANNEL_MUTEX, 208 NOUVEAU_KCHANNEL_MUTEX 209}; 210 211struct nouveau_channel { 212 struct drm_device *dev; 213 struct list_head list; 214 int id; 215 216 /* references to the channel data structure */ 217 struct kref ref; 218 /* users of the hardware channel resources, the hardware 219 * context will be kicked off when it reaches zero. */ 220 atomic_t users; 221 struct mutex mutex; 222 223 /* owner of this fifo */ 224 struct drm_file *file_priv; 225 /* mapping of the fifo itself */ 226 struct drm_local_map *map; 227 228 /* mapping of the regs controlling the fifo */ 229 void __iomem *user; 230 uint32_t user_get; 231 uint32_t user_put; 232 233 /* Fencing */ 234 struct { 235 /* lock protects the pending list only */ 236 spinlock_t lock; 237 struct list_head pending; 238 uint32_t sequence; 239 uint32_t sequence_ack; 240 atomic_t last_sequence_irq; 241 } fence; 242 243 /* DMA push buffer */ 244 struct nouveau_gpuobj *pushbuf; 245 struct nouveau_bo *pushbuf_bo; 246 uint32_t pushbuf_base; 247 248 /* Notifier memory */ 249 struct nouveau_bo *notifier_bo; 250 struct drm_mm notifier_heap; 251 252 /* PFIFO context */ 253 struct nouveau_gpuobj *ramfc; 254 struct nouveau_gpuobj *cache; 255 void *fifo_priv; 256 257 /* Execution engine contexts */ 258 void *engctx[NVOBJ_ENGINE_NR]; 259 260 /* NV50 VM */ 261 struct nouveau_vm *vm; 262 struct nouveau_gpuobj *vm_pd; 263 264 /* Objects */ 265 struct nouveau_gpuobj *ramin; /* Private instmem */ 266 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 267 struct nouveau_ramht *ramht; /* Hash table */ 268 269 /* GPU object info for stuff used in-kernel (mm_enabled) */ 270 uint32_t m2mf_ntfy; 271 uint32_t vram_handle; 272 uint32_t gart_handle; 273 bool accel_done; 274 275 /* Push buffer state (only for drm's channel on !mm_enabled) */ 276 struct { 277 int max; 278 int free; 279 int cur; 280 int put; 281 /* access via pushbuf_bo */ 282 283 int ib_base; 284 int ib_max; 285 int ib_free; 286 int ib_put; 287 } dma; 288 289 uint32_t sw_subchannel[8]; 290 291 struct { 292 struct nouveau_gpuobj *vblsem; 293 uint32_t vblsem_head; 294 uint32_t vblsem_offset; 295 uint32_t vblsem_rval; 296 struct list_head vbl_wait; 297 struct list_head flip; 298 } nvsw; 299 300 struct { 301 bool active; 302 char name[32]; 303 struct drm_info_list info; 304 } debugfs; 305}; 306 307struct nouveau_exec_engine { 308 void (*destroy)(struct drm_device *, int engine); 309 int (*init)(struct drm_device *, int engine); 310 int (*fini)(struct drm_device *, int engine); 311 int (*context_new)(struct nouveau_channel *, int engine); 312 void (*context_del)(struct nouveau_channel *, int engine); 313 int (*object_new)(struct nouveau_channel *, int engine, 314 u32 handle, u16 class); 315 void (*set_tile_region)(struct drm_device *dev, int i); 316 void (*tlb_flush)(struct drm_device *, int engine); 317}; 318 319struct nouveau_instmem_engine { 320 void *priv; 321 322 int (*init)(struct drm_device *dev); 323 void (*takedown)(struct drm_device *dev); 324 int (*suspend)(struct drm_device *dev); 325 void (*resume)(struct drm_device *dev); 326 327 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 328 void (*put)(struct nouveau_gpuobj *); 329 int (*map)(struct nouveau_gpuobj *); 330 void (*unmap)(struct nouveau_gpuobj *); 331 332 void (*flush)(struct drm_device *); 333}; 334 335struct nouveau_mc_engine { 336 int (*init)(struct drm_device *dev); 337 void (*takedown)(struct drm_device *dev); 338}; 339 340struct nouveau_timer_engine { 341 int (*init)(struct drm_device *dev); 342 void (*takedown)(struct drm_device *dev); 343 uint64_t (*read)(struct drm_device *dev); 344}; 345 346struct nouveau_fb_engine { 347 int num_tiles; 348 struct drm_mm tag_heap; 349 void *priv; 350 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 354 void (*init_tile_region)(struct drm_device *dev, int i, 355 uint32_t addr, uint32_t size, 356 uint32_t pitch, uint32_t flags); 357 void (*set_tile_region)(struct drm_device *dev, int i); 358 void (*free_tile_region)(struct drm_device *dev, int i); 359}; 360 361struct nouveau_fifo_engine { 362 void *priv; 363 int channels; 364 365 struct nouveau_gpuobj *playlist[2]; 366 int cur_playlist; 367 368 int (*init)(struct drm_device *); 369 void (*takedown)(struct drm_device *); 370 371 void (*disable)(struct drm_device *); 372 void (*enable)(struct drm_device *); 373 bool (*reassign)(struct drm_device *, bool enable); 374 bool (*cache_pull)(struct drm_device *dev, bool enable); 375 376 int (*channel_id)(struct drm_device *); 377 378 int (*create_context)(struct nouveau_channel *); 379 void (*destroy_context)(struct nouveau_channel *); 380 int (*load_context)(struct nouveau_channel *); 381 int (*unload_context)(struct drm_device *); 382 void (*tlb_flush)(struct drm_device *dev); 383}; 384 385struct nouveau_display_engine { 386 void *priv; 387 int (*early_init)(struct drm_device *); 388 void (*late_takedown)(struct drm_device *); 389 int (*create)(struct drm_device *); 390 int (*init)(struct drm_device *); 391 void (*destroy)(struct drm_device *); 392}; 393 394struct nouveau_gpio_engine { 395 void *priv; 396 397 int (*init)(struct drm_device *); 398 void (*takedown)(struct drm_device *); 399 400 int (*get)(struct drm_device *, enum dcb_gpio_tag); 401 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 402 403 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 404 void (*)(void *, int), void *); 405 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 406 void (*)(void *, int), void *); 407 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 408}; 409 410struct nouveau_pm_voltage_level { 411 u8 voltage; 412 u8 vid; 413}; 414 415struct nouveau_pm_voltage { 416 bool supported; 417 u8 vid_mask; 418 419 struct nouveau_pm_voltage_level *level; 420 int nr_level; 421}; 422 423struct nouveau_pm_memtiming { 424 int id; 425 u32 reg_100220; 426 u32 reg_100224; 427 u32 reg_100228; 428 u32 reg_10022c; 429 u32 reg_100230; 430 u32 reg_100234; 431 u32 reg_100238; 432 u32 reg_10023c; 433 u32 reg_100240; 434}; 435 436#define NOUVEAU_PM_MAX_LEVEL 8 437struct nouveau_pm_level { 438 struct device_attribute dev_attr; 439 char name[32]; 440 int id; 441 442 u32 core; 443 u32 memory; 444 u32 shader; 445 u32 unk05; 446 u32 unk0a; 447 448 u8 voltage; 449 u8 fanspeed; 450 451 u16 memscript; 452 struct nouveau_pm_memtiming *timing; 453}; 454 455struct nouveau_pm_temp_sensor_constants { 456 u16 offset_constant; 457 s16 offset_mult; 458 u16 offset_div; 459 u16 slope_mult; 460 u16 slope_div; 461}; 462 463struct nouveau_pm_threshold_temp { 464 s16 critical; 465 s16 down_clock; 466 s16 fan_boost; 467}; 468 469struct nouveau_pm_memtimings { 470 bool supported; 471 struct nouveau_pm_memtiming *timing; 472 int nr_timing; 473}; 474 475struct nouveau_pm_engine { 476 struct nouveau_pm_voltage voltage; 477 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 478 int nr_perflvl; 479 struct nouveau_pm_memtimings memtimings; 480 struct nouveau_pm_temp_sensor_constants sensor_constants; 481 struct nouveau_pm_threshold_temp threshold_temp; 482 483 struct nouveau_pm_level boot; 484 struct nouveau_pm_level *cur; 485 486 struct device *hwmon; 487 struct notifier_block acpi_nb; 488 489 int (*clock_get)(struct drm_device *, u32 id); 490 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 491 u32 id, int khz); 492 void (*clock_set)(struct drm_device *, void *); 493 int (*voltage_get)(struct drm_device *); 494 int (*voltage_set)(struct drm_device *, int voltage); 495 int (*fanspeed_get)(struct drm_device *); 496 int (*fanspeed_set)(struct drm_device *, int fanspeed); 497 int (*temp_get)(struct drm_device *); 498}; 499 500struct nouveau_vram_engine { 501 int (*init)(struct drm_device *); 502 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 503 u32 type, struct nouveau_mem **); 504 void (*put)(struct drm_device *, struct nouveau_mem **); 505 506 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 507}; 508 509struct nouveau_engine { 510 struct nouveau_instmem_engine instmem; 511 struct nouveau_mc_engine mc; 512 struct nouveau_timer_engine timer; 513 struct nouveau_fb_engine fb; 514 struct nouveau_fifo_engine fifo; 515 struct nouveau_display_engine display; 516 struct nouveau_gpio_engine gpio; 517 struct nouveau_pm_engine pm; 518 struct nouveau_vram_engine vram; 519}; 520 521struct nouveau_pll_vals { 522 union { 523 struct { 524#ifdef __BIG_ENDIAN 525 uint8_t N1, M1, N2, M2; 526#else 527 uint8_t M1, N1, M2, N2; 528#endif 529 }; 530 struct { 531 uint16_t NM1, NM2; 532 } __attribute__((packed)); 533 }; 534 int log2P; 535 536 int refclk; 537}; 538 539enum nv04_fp_display_regs { 540 FP_DISPLAY_END, 541 FP_TOTAL, 542 FP_CRTC, 543 FP_SYNC_START, 544 FP_SYNC_END, 545 FP_VALID_START, 546 FP_VALID_END 547}; 548 549struct nv04_crtc_reg { 550 unsigned char MiscOutReg; 551 uint8_t CRTC[0xa0]; 552 uint8_t CR58[0x10]; 553 uint8_t Sequencer[5]; 554 uint8_t Graphics[9]; 555 uint8_t Attribute[21]; 556 unsigned char DAC[768]; 557 558 /* PCRTC regs */ 559 uint32_t fb_start; 560 uint32_t crtc_cfg; 561 uint32_t cursor_cfg; 562 uint32_t gpio_ext; 563 uint32_t crtc_830; 564 uint32_t crtc_834; 565 uint32_t crtc_850; 566 uint32_t crtc_eng_ctrl; 567 568 /* PRAMDAC regs */ 569 uint32_t nv10_cursync; 570 struct nouveau_pll_vals pllvals; 571 uint32_t ramdac_gen_ctrl; 572 uint32_t ramdac_630; 573 uint32_t ramdac_634; 574 uint32_t tv_setup; 575 uint32_t tv_vtotal; 576 uint32_t tv_vskew; 577 uint32_t tv_vsync_delay; 578 uint32_t tv_htotal; 579 uint32_t tv_hskew; 580 uint32_t tv_hsync_delay; 581 uint32_t tv_hsync_delay2; 582 uint32_t fp_horiz_regs[7]; 583 uint32_t fp_vert_regs[7]; 584 uint32_t dither; 585 uint32_t fp_control; 586 uint32_t dither_regs[6]; 587 uint32_t fp_debug_0; 588 uint32_t fp_debug_1; 589 uint32_t fp_debug_2; 590 uint32_t fp_margin_color; 591 uint32_t ramdac_8c0; 592 uint32_t ramdac_a20; 593 uint32_t ramdac_a24; 594 uint32_t ramdac_a34; 595 uint32_t ctv_regs[38]; 596}; 597 598struct nv04_output_reg { 599 uint32_t output; 600 int head; 601}; 602 603struct nv04_mode_state { 604 struct nv04_crtc_reg crtc_reg[2]; 605 uint32_t pllsel; 606 uint32_t sel_clk; 607}; 608 609enum nouveau_card_type { 610 NV_04 = 0x00, 611 NV_10 = 0x10, 612 NV_20 = 0x20, 613 NV_30 = 0x30, 614 NV_40 = 0x40, 615 NV_50 = 0x50, 616 NV_C0 = 0xc0, 617}; 618 619struct drm_nouveau_private { 620 struct drm_device *dev; 621 bool noaccel; 622 623 /* the card type, takes NV_* as values */ 624 enum nouveau_card_type card_type; 625 /* exact chipset, derived from NV_PMC_BOOT_0 */ 626 int chipset; 627 int stepping; 628 int flags; 629 630 void __iomem *mmio; 631 632 spinlock_t ramin_lock; 633 void __iomem *ramin; 634 u32 ramin_size; 635 u32 ramin_base; 636 bool ramin_available; 637 struct drm_mm ramin_heap; 638 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 639 struct list_head gpuobj_list; 640 struct list_head classes; 641 642 struct nouveau_bo *vga_ram; 643 644 /* interrupt handling */ 645 void (*irq_handler[32])(struct drm_device *); 646 bool msi_enabled; 647 648 struct list_head vbl_waiting; 649 650 struct { 651 struct drm_global_reference mem_global_ref; 652 struct ttm_bo_global_ref bo_global_ref; 653 struct ttm_bo_device bdev; 654 atomic_t validate_sequence; 655 } ttm; 656 657 struct { 658 spinlock_t lock; 659 struct drm_mm heap; 660 struct nouveau_bo *bo; 661 } fence; 662 663 struct { 664 spinlock_t lock; 665 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 666 } channels; 667 668 struct nouveau_engine engine; 669 struct nouveau_channel *channel; 670 671 /* For PFIFO and PGRAPH. */ 672 spinlock_t context_switch_lock; 673 674 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 675 spinlock_t vm_lock; 676 677 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 678 struct nouveau_ramht *ramht; 679 struct nouveau_gpuobj *ramfc; 680 struct nouveau_gpuobj *ramro; 681 682 uint32_t ramin_rsvd_vram; 683 684 struct { 685 enum { 686 NOUVEAU_GART_NONE = 0, 687 NOUVEAU_GART_AGP, /* AGP */ 688 NOUVEAU_GART_PDMA, /* paged dma object */ 689 NOUVEAU_GART_HW /* on-chip gart/vm */ 690 } type; 691 uint64_t aper_base; 692 uint64_t aper_size; 693 uint64_t aper_free; 694 695 struct ttm_backend_func *func; 696 697 struct { 698 struct page *page; 699 dma_addr_t addr; 700 } dummy; 701 702 struct nouveau_gpuobj *sg_ctxdma; 703 } gart_info; 704 705 /* nv10-nv40 tiling regions */ 706 struct { 707 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 708 spinlock_t lock; 709 } tile; 710 711 /* VRAM/fb configuration */ 712 uint64_t vram_size; 713 uint64_t vram_sys_base; 714 u32 vram_rblock_size; 715 716 uint64_t fb_phys; 717 uint64_t fb_available_size; 718 uint64_t fb_mappable_pages; 719 uint64_t fb_aper_free; 720 int fb_mtrr; 721 722 /* BAR control (NV50-) */ 723 struct nouveau_vm *bar1_vm; 724 struct nouveau_vm *bar3_vm; 725 726 /* G8x/G9x virtual address space */ 727 struct nouveau_vm *chan_vm; 728 729 struct nvbios vbios; 730 731 struct nv04_mode_state mode_reg; 732 struct nv04_mode_state saved_reg; 733 uint32_t saved_vga_font[4][16384]; 734 uint32_t crtc_owner; 735 uint32_t dac_users[4]; 736 737 struct backlight_device *backlight; 738 739 struct { 740 struct dentry *channel_root; 741 } debugfs; 742 743 struct nouveau_fbdev *nfbdev; 744 struct apertures_struct *apertures; 745}; 746 747static inline struct drm_nouveau_private * 748nouveau_private(struct drm_device *dev) 749{ 750 return dev->dev_private; 751} 752 753static inline struct drm_nouveau_private * 754nouveau_bdev(struct ttm_bo_device *bd) 755{ 756 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 757} 758 759static inline int 760nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 761{ 762 struct nouveau_bo *prev; 763 764 if (!pnvbo) 765 return -EINVAL; 766 prev = *pnvbo; 767 768 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 769 if (prev) { 770 struct ttm_buffer_object *bo = &prev->bo; 771 772 ttm_bo_unref(&bo); 773 } 774 775 return 0; 776} 777 778/* nouveau_drv.c */ 779extern int nouveau_agpmode; 780extern int nouveau_duallink; 781extern int nouveau_uscript_lvds; 782extern int nouveau_uscript_tmds; 783extern int nouveau_vram_pushbuf; 784extern int nouveau_vram_notify; 785extern int nouveau_fbpercrtc; 786extern int nouveau_tv_disable; 787extern char *nouveau_tv_norm; 788extern int nouveau_reg_debug; 789extern char *nouveau_vbios; 790extern int nouveau_ignorelid; 791extern int nouveau_nofbaccel; 792extern int nouveau_noaccel; 793extern int nouveau_force_post; 794extern int nouveau_override_conntype; 795extern char *nouveau_perflvl; 796extern int nouveau_perflvl_wr; 797extern int nouveau_msi; 798extern int nouveau_ctxfw; 799 800extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 801extern int nouveau_pci_resume(struct pci_dev *pdev); 802 803/* nouveau_state.c */ 804extern int nouveau_open(struct drm_device *, struct drm_file *); 805extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 806extern void nouveau_postclose(struct drm_device *, struct drm_file *); 807extern int nouveau_load(struct drm_device *, unsigned long flags); 808extern int nouveau_firstopen(struct drm_device *); 809extern void nouveau_lastclose(struct drm_device *); 810extern int nouveau_unload(struct drm_device *); 811extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 812 struct drm_file *); 813extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 814 struct drm_file *); 815extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 816 uint32_t reg, uint32_t mask, uint32_t val); 817extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 818 uint32_t reg, uint32_t mask, uint32_t val); 819extern bool nouveau_wait_for_idle(struct drm_device *); 820extern int nouveau_card_init(struct drm_device *); 821 822/* nouveau_mem.c */ 823extern int nouveau_mem_vram_init(struct drm_device *); 824extern void nouveau_mem_vram_fini(struct drm_device *); 825extern int nouveau_mem_gart_init(struct drm_device *); 826extern void nouveau_mem_gart_fini(struct drm_device *); 827extern int nouveau_mem_init_agp(struct drm_device *); 828extern int nouveau_mem_reset_agp(struct drm_device *); 829extern void nouveau_mem_close(struct drm_device *); 830extern int nouveau_mem_detect(struct drm_device *); 831extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 832extern struct nouveau_tile_reg *nv10_mem_set_tiling( 833 struct drm_device *dev, uint32_t addr, uint32_t size, 834 uint32_t pitch, uint32_t flags); 835extern void nv10_mem_put_tile_region(struct drm_device *dev, 836 struct nouveau_tile_reg *tile, 837 struct nouveau_fence *fence); 838extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 839extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 840 841/* nouveau_notifier.c */ 842extern int nouveau_notifier_init_channel(struct nouveau_channel *); 843extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 844extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 845 int cout, uint32_t start, uint32_t end, 846 uint32_t *offset); 847extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 848extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 849 struct drm_file *); 850extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 851 struct drm_file *); 852 853/* nouveau_channel.c */ 854extern struct drm_ioctl_desc nouveau_ioctls[]; 855extern int nouveau_max_ioctl; 856extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 857extern int nouveau_channel_alloc(struct drm_device *dev, 858 struct nouveau_channel **chan, 859 struct drm_file *file_priv, 860 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 861extern struct nouveau_channel * 862nouveau_channel_get_unlocked(struct nouveau_channel *); 863extern struct nouveau_channel * 864nouveau_channel_get(struct drm_file *, int id); 865extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 866extern void nouveau_channel_put(struct nouveau_channel **); 867extern void nouveau_channel_ref(struct nouveau_channel *chan, 868 struct nouveau_channel **pchan); 869extern void nouveau_channel_idle(struct nouveau_channel *chan); 870 871/* nouveau_object.c */ 872#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 873 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 874 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 875} while (0) 876 877#define NVOBJ_ENGINE_DEL(d, e) do { \ 878 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 879 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 880} while (0) 881 882#define NVOBJ_CLASS(d, c, e) do { \ 883 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 884 if (ret) \ 885 return ret; \ 886} while (0) 887 888#define NVOBJ_MTHD(d, c, m, e) do { \ 889 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 890 if (ret) \ 891 return ret; \ 892} while (0) 893 894extern int nouveau_gpuobj_early_init(struct drm_device *); 895extern int nouveau_gpuobj_init(struct drm_device *); 896extern void nouveau_gpuobj_takedown(struct drm_device *); 897extern int nouveau_gpuobj_suspend(struct drm_device *dev); 898extern void nouveau_gpuobj_resume(struct drm_device *dev); 899extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 900extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 901 int (*exec)(struct nouveau_channel *, 902 u32 class, u32 mthd, u32 data)); 903extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 904extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 905extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 906 uint32_t vram_h, uint32_t tt_h); 907extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 908extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 909 uint32_t size, int align, uint32_t flags, 910 struct nouveau_gpuobj **); 911extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 912 struct nouveau_gpuobj **); 913extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 914 u32 size, u32 flags, 915 struct nouveau_gpuobj **); 916extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 917 uint64_t offset, uint64_t size, int access, 918 int target, struct nouveau_gpuobj **); 919extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 920extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 921 u64 size, int target, int access, u32 type, 922 u32 comp, struct nouveau_gpuobj **pobj); 923extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 924 int class, u64 base, u64 size, int target, 925 int access, u32 type, u32 comp); 926extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 927 struct drm_file *); 928extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 929 struct drm_file *); 930 931/* nouveau_irq.c */ 932extern int nouveau_irq_init(struct drm_device *); 933extern void nouveau_irq_fini(struct drm_device *); 934extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 935extern void nouveau_irq_register(struct drm_device *, int status_bit, 936 void (*)(struct drm_device *)); 937extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 938extern void nouveau_irq_preinstall(struct drm_device *); 939extern int nouveau_irq_postinstall(struct drm_device *); 940extern void nouveau_irq_uninstall(struct drm_device *); 941 942/* nouveau_sgdma.c */ 943extern int nouveau_sgdma_init(struct drm_device *); 944extern void nouveau_sgdma_takedown(struct drm_device *); 945extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 946 uint32_t offset); 947extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 948 949/* nouveau_debugfs.c */ 950#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 951extern int nouveau_debugfs_init(struct drm_minor *); 952extern void nouveau_debugfs_takedown(struct drm_minor *); 953extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 954extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 955#else 956static inline int 957nouveau_debugfs_init(struct drm_minor *minor) 958{ 959 return 0; 960} 961 962static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 963{ 964} 965 966static inline int 967nouveau_debugfs_channel_init(struct nouveau_channel *chan) 968{ 969 return 0; 970} 971 972static inline void 973nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 974{ 975} 976#endif 977 978/* nouveau_dma.c */ 979extern void nouveau_dma_pre_init(struct nouveau_channel *); 980extern int nouveau_dma_init(struct nouveau_channel *); 981extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 982 983/* nouveau_acpi.c */ 984#define ROM_BIOS_PAGE 4096 985#if defined(CONFIG_ACPI) 986void nouveau_register_dsm_handler(void); 987void nouveau_unregister_dsm_handler(void); 988int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 989bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 990int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 991#else 992static inline void nouveau_register_dsm_handler(void) {} 993static inline void nouveau_unregister_dsm_handler(void) {} 994static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 995static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 996static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 997#endif 998 999/* nouveau_backlight.c */ 1000#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1001extern int nouveau_backlight_init(struct drm_connector *); 1002extern void nouveau_backlight_exit(struct drm_connector *); 1003#else 1004static inline int nouveau_backlight_init(struct drm_connector *dev) 1005{ 1006 return 0; 1007} 1008 1009static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1010#endif 1011 1012/* nouveau_bios.c */ 1013extern int nouveau_bios_init(struct drm_device *); 1014extern void nouveau_bios_takedown(struct drm_device *dev); 1015extern int nouveau_run_vbios_init(struct drm_device *); 1016extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1017 struct dcb_entry *); 1018extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1019 enum dcb_gpio_tag); 1020extern struct dcb_connector_table_entry * 1021nouveau_bios_connector_entry(struct drm_device *, int index); 1022extern u32 get_pll_register(struct drm_device *, enum pll_types); 1023extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1024 struct pll_lims *); 1025extern int nouveau_bios_run_display_table(struct drm_device *, 1026 struct dcb_entry *, 1027 uint32_t script, int pxclk); 1028extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1029 int *length); 1030extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1031extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1032extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1033 bool *dl, bool *if_is_24bit); 1034extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1035 int head, int pxclk); 1036extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1037 enum LVDS_script, int pxclk); 1038 1039/* nouveau_ttm.c */ 1040int nouveau_ttm_global_init(struct drm_nouveau_private *); 1041void nouveau_ttm_global_release(struct drm_nouveau_private *); 1042int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1043 1044/* nouveau_dp.c */ 1045int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1046 uint8_t *data, int data_nr); 1047bool nouveau_dp_detect(struct drm_encoder *); 1048bool nouveau_dp_link_train(struct drm_encoder *); 1049 1050/* nv04_fb.c */ 1051extern int nv04_fb_init(struct drm_device *); 1052extern void nv04_fb_takedown(struct drm_device *); 1053 1054/* nv10_fb.c */ 1055extern int nv10_fb_init(struct drm_device *); 1056extern void nv10_fb_takedown(struct drm_device *); 1057extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1058 uint32_t addr, uint32_t size, 1059 uint32_t pitch, uint32_t flags); 1060extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1061extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1062 1063/* nv30_fb.c */ 1064extern int nv30_fb_init(struct drm_device *); 1065extern void nv30_fb_takedown(struct drm_device *); 1066extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1067 uint32_t addr, uint32_t size, 1068 uint32_t pitch, uint32_t flags); 1069extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1070 1071/* nv40_fb.c */ 1072extern int nv40_fb_init(struct drm_device *); 1073extern void nv40_fb_takedown(struct drm_device *); 1074extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1075 1076/* nv50_fb.c */ 1077extern int nv50_fb_init(struct drm_device *); 1078extern void nv50_fb_takedown(struct drm_device *); 1079extern void nv50_fb_vm_trap(struct drm_device *, int display); 1080 1081/* nvc0_fb.c */ 1082extern int nvc0_fb_init(struct drm_device *); 1083extern void nvc0_fb_takedown(struct drm_device *); 1084 1085/* nv04_fifo.c */ 1086extern int nv04_fifo_init(struct drm_device *); 1087extern void nv04_fifo_fini(struct drm_device *); 1088extern void nv04_fifo_disable(struct drm_device *); 1089extern void nv04_fifo_enable(struct drm_device *); 1090extern bool nv04_fifo_reassign(struct drm_device *, bool); 1091extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1092extern int nv04_fifo_channel_id(struct drm_device *); 1093extern int nv04_fifo_create_context(struct nouveau_channel *); 1094extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1095extern int nv04_fifo_load_context(struct nouveau_channel *); 1096extern int nv04_fifo_unload_context(struct drm_device *); 1097extern void nv04_fifo_isr(struct drm_device *); 1098 1099/* nv10_fifo.c */ 1100extern int nv10_fifo_init(struct drm_device *); 1101extern int nv10_fifo_channel_id(struct drm_device *); 1102extern int nv10_fifo_create_context(struct nouveau_channel *); 1103extern int nv10_fifo_load_context(struct nouveau_channel *); 1104extern int nv10_fifo_unload_context(struct drm_device *); 1105 1106/* nv40_fifo.c */ 1107extern int nv40_fifo_init(struct drm_device *); 1108extern int nv40_fifo_create_context(struct nouveau_channel *); 1109extern int nv40_fifo_load_context(struct nouveau_channel *); 1110extern int nv40_fifo_unload_context(struct drm_device *); 1111 1112/* nv50_fifo.c */ 1113extern int nv50_fifo_init(struct drm_device *); 1114extern void nv50_fifo_takedown(struct drm_device *); 1115extern int nv50_fifo_channel_id(struct drm_device *); 1116extern int nv50_fifo_create_context(struct nouveau_channel *); 1117extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1118extern int nv50_fifo_load_context(struct nouveau_channel *); 1119extern int nv50_fifo_unload_context(struct drm_device *); 1120extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1121 1122/* nvc0_fifo.c */ 1123extern int nvc0_fifo_init(struct drm_device *); 1124extern void nvc0_fifo_takedown(struct drm_device *); 1125extern void nvc0_fifo_disable(struct drm_device *); 1126extern void nvc0_fifo_enable(struct drm_device *); 1127extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1128extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1129extern int nvc0_fifo_channel_id(struct drm_device *); 1130extern int nvc0_fifo_create_context(struct nouveau_channel *); 1131extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1132extern int nvc0_fifo_load_context(struct nouveau_channel *); 1133extern int nvc0_fifo_unload_context(struct drm_device *); 1134 1135/* nv04_graph.c */ 1136extern int nv04_graph_create(struct drm_device *); 1137extern void nv04_graph_fifo_access(struct drm_device *, bool); 1138extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1139extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1140 u32 class, u32 mthd, u32 data); 1141extern struct nouveau_bitfield nv04_graph_nsource[]; 1142 1143/* nv10_graph.c */ 1144extern int nv10_graph_create(struct drm_device *); 1145extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1146extern struct nouveau_bitfield nv10_graph_intr[]; 1147extern struct nouveau_bitfield nv10_graph_nstatus[]; 1148 1149/* nv20_graph.c */ 1150extern int nv20_graph_create(struct drm_device *); 1151 1152/* nv40_graph.c */ 1153extern int nv40_graph_create(struct drm_device *); 1154extern void nv40_grctx_init(struct nouveau_grctx *); 1155 1156/* nv50_graph.c */ 1157extern int nv50_graph_create(struct drm_device *); 1158extern int nv50_grctx_init(struct nouveau_grctx *); 1159extern struct nouveau_enum nv50_data_error_names[]; 1160extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1161 1162/* nvc0_graph.c */ 1163extern int nvc0_graph_create(struct drm_device *); 1164extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1165 1166/* nv84_crypt.c */ 1167extern int nv84_crypt_create(struct drm_device *); 1168 1169/* nva3_copy.c */ 1170extern int nva3_copy_create(struct drm_device *dev); 1171 1172/* nvc0_copy.c */ 1173extern int nvc0_copy_create(struct drm_device *dev, int engine); 1174 1175/* nv40_mpeg.c */ 1176extern int nv40_mpeg_create(struct drm_device *dev); 1177 1178/* nv50_mpeg.c */ 1179extern int nv50_mpeg_create(struct drm_device *dev); 1180 1181/* nv04_instmem.c */ 1182extern int nv04_instmem_init(struct drm_device *); 1183extern void nv04_instmem_takedown(struct drm_device *); 1184extern int nv04_instmem_suspend(struct drm_device *); 1185extern void nv04_instmem_resume(struct drm_device *); 1186extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1187extern void nv04_instmem_put(struct nouveau_gpuobj *); 1188extern int nv04_instmem_map(struct nouveau_gpuobj *); 1189extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1190extern void nv04_instmem_flush(struct drm_device *); 1191 1192/* nv50_instmem.c */ 1193extern int nv50_instmem_init(struct drm_device *); 1194extern void nv50_instmem_takedown(struct drm_device *); 1195extern int nv50_instmem_suspend(struct drm_device *); 1196extern void nv50_instmem_resume(struct drm_device *); 1197extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1198extern void nv50_instmem_put(struct nouveau_gpuobj *); 1199extern int nv50_instmem_map(struct nouveau_gpuobj *); 1200extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1201extern void nv50_instmem_flush(struct drm_device *); 1202extern void nv84_instmem_flush(struct drm_device *); 1203 1204/* nvc0_instmem.c */ 1205extern int nvc0_instmem_init(struct drm_device *); 1206extern void nvc0_instmem_takedown(struct drm_device *); 1207extern int nvc0_instmem_suspend(struct drm_device *); 1208extern void nvc0_instmem_resume(struct drm_device *); 1209 1210/* nv04_mc.c */ 1211extern int nv04_mc_init(struct drm_device *); 1212extern void nv04_mc_takedown(struct drm_device *); 1213 1214/* nv40_mc.c */ 1215extern int nv40_mc_init(struct drm_device *); 1216extern void nv40_mc_takedown(struct drm_device *); 1217 1218/* nv50_mc.c */ 1219extern int nv50_mc_init(struct drm_device *); 1220extern void nv50_mc_takedown(struct drm_device *); 1221 1222/* nv04_timer.c */ 1223extern int nv04_timer_init(struct drm_device *); 1224extern uint64_t nv04_timer_read(struct drm_device *); 1225extern void nv04_timer_takedown(struct drm_device *); 1226 1227extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1228 unsigned long arg); 1229 1230/* nv04_dac.c */ 1231extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1232extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1233extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1234extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1235extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1236 1237/* nv04_dfp.c */ 1238extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1239extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1240extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1241 int head, bool dl); 1242extern void nv04_dfp_disable(struct drm_device *dev, int head); 1243extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1244 1245/* nv04_tv.c */ 1246extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1247extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1248 1249/* nv17_tv.c */ 1250extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1251 1252/* nv04_display.c */ 1253extern int nv04_display_early_init(struct drm_device *); 1254extern void nv04_display_late_takedown(struct drm_device *); 1255extern int nv04_display_create(struct drm_device *); 1256extern int nv04_display_init(struct drm_device *); 1257extern void nv04_display_destroy(struct drm_device *); 1258 1259/* nv04_crtc.c */ 1260extern int nv04_crtc_create(struct drm_device *, int index); 1261 1262/* nouveau_bo.c */ 1263extern struct ttm_bo_driver nouveau_bo_driver; 1264extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1265 int size, int align, uint32_t flags, 1266 uint32_t tile_mode, uint32_t tile_flags, 1267 struct nouveau_bo **); 1268extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1269extern int nouveau_bo_unpin(struct nouveau_bo *); 1270extern int nouveau_bo_map(struct nouveau_bo *); 1271extern void nouveau_bo_unmap(struct nouveau_bo *); 1272extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1273 uint32_t busy); 1274extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1275extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1276extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1277extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1278extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1279extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1280 bool no_wait_reserve, bool no_wait_gpu); 1281 1282/* nouveau_fence.c */ 1283struct nouveau_fence; 1284extern int nouveau_fence_init(struct drm_device *); 1285extern void nouveau_fence_fini(struct drm_device *); 1286extern int nouveau_fence_channel_init(struct nouveau_channel *); 1287extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1288extern void nouveau_fence_update(struct nouveau_channel *); 1289extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1290 bool emit); 1291extern int nouveau_fence_emit(struct nouveau_fence *); 1292extern void nouveau_fence_work(struct nouveau_fence *fence, 1293 void (*work)(void *priv, bool signalled), 1294 void *priv); 1295struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1296 1297extern bool __nouveau_fence_signalled(void *obj, void *arg); 1298extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1299extern int __nouveau_fence_flush(void *obj, void *arg); 1300extern void __nouveau_fence_unref(void **obj); 1301extern void *__nouveau_fence_ref(void *obj); 1302 1303static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1304{ 1305 return __nouveau_fence_signalled(obj, NULL); 1306} 1307static inline int 1308nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1309{ 1310 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1311} 1312extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1313static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1314{ 1315 return __nouveau_fence_flush(obj, NULL); 1316} 1317static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1318{ 1319 __nouveau_fence_unref((void **)obj); 1320} 1321static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1322{ 1323 return __nouveau_fence_ref(obj); 1324} 1325 1326/* nouveau_gem.c */ 1327extern int nouveau_gem_new(struct drm_device *, int size, int align, 1328 uint32_t domain, uint32_t tile_mode, 1329 uint32_t tile_flags, struct nouveau_bo **); 1330extern int nouveau_gem_object_new(struct drm_gem_object *); 1331extern void nouveau_gem_object_del(struct drm_gem_object *); 1332extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1333extern void nouveau_gem_object_close(struct drm_gem_object *, 1334 struct drm_file *); 1335extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1336 struct drm_file *); 1337extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1338 struct drm_file *); 1339extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1340 struct drm_file *); 1341extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1342 struct drm_file *); 1343extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1344 struct drm_file *); 1345 1346/* nouveau_display.c */ 1347int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1348void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1349int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1350 struct drm_pending_vblank_event *event); 1351int nouveau_finish_page_flip(struct nouveau_channel *, 1352 struct nouveau_page_flip_state *); 1353 1354/* nv10_gpio.c */ 1355int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1356int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1357 1358/* nv50_gpio.c */ 1359int nv50_gpio_init(struct drm_device *dev); 1360void nv50_gpio_fini(struct drm_device *dev); 1361int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1362int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1363int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1364 void (*)(void *, int), void *); 1365void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1366 void (*)(void *, int), void *); 1367bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1368 1369/* nv50_calc. */ 1370int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1371 int *N1, int *M1, int *N2, int *M2, int *P); 1372int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1373 int clk, int *N, int *fN, int *M, int *P); 1374 1375#ifndef ioread32_native 1376#ifdef __BIG_ENDIAN 1377#define ioread16_native ioread16be 1378#define iowrite16_native iowrite16be 1379#define ioread32_native ioread32be 1380#define iowrite32_native iowrite32be 1381#else /* def __BIG_ENDIAN */ 1382#define ioread16_native ioread16 1383#define iowrite16_native iowrite16 1384#define ioread32_native ioread32 1385#define iowrite32_native iowrite32 1386#endif /* def __BIG_ENDIAN else */ 1387#endif /* !ioread32_native */ 1388 1389/* channel control reg access */ 1390static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1391{ 1392 return ioread32_native(chan->user + reg); 1393} 1394 1395static inline void nvchan_wr32(struct nouveau_channel *chan, 1396 unsigned reg, u32 val) 1397{ 1398 iowrite32_native(val, chan->user + reg); 1399} 1400 1401/* register access */ 1402static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1403{ 1404 struct drm_nouveau_private *dev_priv = dev->dev_private; 1405 return ioread32_native(dev_priv->mmio + reg); 1406} 1407 1408static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1409{ 1410 struct drm_nouveau_private *dev_priv = dev->dev_private; 1411 iowrite32_native(val, dev_priv->mmio + reg); 1412} 1413 1414static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1415{ 1416 u32 tmp = nv_rd32(dev, reg); 1417 nv_wr32(dev, reg, (tmp & ~mask) | val); 1418 return tmp; 1419} 1420 1421static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1422{ 1423 struct drm_nouveau_private *dev_priv = dev->dev_private; 1424 return ioread8(dev_priv->mmio + reg); 1425} 1426 1427static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1428{ 1429 struct drm_nouveau_private *dev_priv = dev->dev_private; 1430 iowrite8(val, dev_priv->mmio + reg); 1431} 1432 1433#define nv_wait(dev, reg, mask, val) \ 1434 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1435#define nv_wait_ne(dev, reg, mask, val) \ 1436 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1437 1438/* PRAMIN access */ 1439static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1440{ 1441 struct drm_nouveau_private *dev_priv = dev->dev_private; 1442 return ioread32_native(dev_priv->ramin + offset); 1443} 1444 1445static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1446{ 1447 struct drm_nouveau_private *dev_priv = dev->dev_private; 1448 iowrite32_native(val, dev_priv->ramin + offset); 1449} 1450 1451/* object access */ 1452extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1453extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1454 1455/* 1456 * Logging 1457 * Argument d is (struct drm_device *). 1458 */ 1459#define NV_PRINTK(level, d, fmt, arg...) \ 1460 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1461 pci_name(d->pdev), ##arg) 1462#ifndef NV_DEBUG_NOTRACE 1463#define NV_DEBUG(d, fmt, arg...) do { \ 1464 if (drm_debug & DRM_UT_DRIVER) { \ 1465 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1466 __LINE__, ##arg); \ 1467 } \ 1468} while (0) 1469#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1470 if (drm_debug & DRM_UT_KMS) { \ 1471 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1472 __LINE__, ##arg); \ 1473 } \ 1474} while (0) 1475#else 1476#define NV_DEBUG(d, fmt, arg...) do { \ 1477 if (drm_debug & DRM_UT_DRIVER) \ 1478 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1479} while (0) 1480#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1481 if (drm_debug & DRM_UT_KMS) \ 1482 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1483} while (0) 1484#endif 1485#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1486#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1487#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1488#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1489#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1490 1491/* nouveau_reg_debug bitmask */ 1492enum { 1493 NOUVEAU_REG_DEBUG_MC = 0x1, 1494 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1495 NOUVEAU_REG_DEBUG_FB = 0x4, 1496 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1497 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1498 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1499 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1500 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1501 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1502 NOUVEAU_REG_DEBUG_EVO = 0x200, 1503}; 1504 1505#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1506 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1507 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1508} while (0) 1509 1510static inline bool 1511nv_two_heads(struct drm_device *dev) 1512{ 1513 struct drm_nouveau_private *dev_priv = dev->dev_private; 1514 const int impl = dev->pci_device & 0x0ff0; 1515 1516 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1517 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1518 return true; 1519 1520 return false; 1521} 1522 1523static inline bool 1524nv_gf4_disp_arch(struct drm_device *dev) 1525{ 1526 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1527} 1528 1529static inline bool 1530nv_two_reg_pll(struct drm_device *dev) 1531{ 1532 struct drm_nouveau_private *dev_priv = dev->dev_private; 1533 const int impl = dev->pci_device & 0x0ff0; 1534 1535 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1536 return true; 1537 return false; 1538} 1539 1540static inline bool 1541nv_match_device(struct drm_device *dev, unsigned device, 1542 unsigned sub_vendor, unsigned sub_device) 1543{ 1544 return dev->pdev->device == device && 1545 dev->pdev->subsystem_vendor == sub_vendor && 1546 dev->pdev->subsystem_device == sub_device; 1547} 1548 1549static inline void * 1550nv_engine(struct drm_device *dev, int engine) 1551{ 1552 struct drm_nouveau_private *dev_priv = dev->dev_private; 1553 return (void *)dev_priv->eng[engine]; 1554} 1555 1556/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1557 * helpful to determine a number of other hardware features 1558 */ 1559static inline int 1560nv44_graph_class(struct drm_device *dev) 1561{ 1562 struct drm_nouveau_private *dev_priv = dev->dev_private; 1563 1564 if ((dev_priv->chipset & 0xf0) == 0x60) 1565 return 1; 1566 1567 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1568} 1569 1570/* memory type/access flags, do not match hardware values */ 1571#define NV_MEM_ACCESS_RO 1 1572#define NV_MEM_ACCESS_WO 2 1573#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1574#define NV_MEM_ACCESS_SYS 4 1575#define NV_MEM_ACCESS_VM 8 1576 1577#define NV_MEM_TARGET_VRAM 0 1578#define NV_MEM_TARGET_PCI 1 1579#define NV_MEM_TARGET_PCI_NOSNOOP 2 1580#define NV_MEM_TARGET_VM 3 1581#define NV_MEM_TARGET_GART 4 1582 1583#define NV_MEM_TYPE_VM 0x7f 1584#define NV_MEM_COMP_VM 0x03 1585 1586/* NV_SW object class */ 1587#define NV_SW 0x0000506e 1588#define NV_SW_DMA_SEMAPHORE 0x00000060 1589#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1590#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1591#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1592#define NV_SW_YIELD 0x00000080 1593#define NV_SW_DMA_VBLSEM 0x0000018c 1594#define NV_SW_VBLSEM_OFFSET 0x00000400 1595#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1596#define NV_SW_VBLSEM_RELEASE 0x00000408 1597#define NV_SW_PAGE_FLIP 0x00000500 1598 1599#endif /* __NOUVEAU_DRV_H__ */ 1600