nouveau_drv.h revision 6a6b73f254123851f7f73ab5e57344a569d6a0ab
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103#define nouveau_bo_tile_layout(nvbo) \ 104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 105 106static inline struct nouveau_bo * 107nouveau_bo(struct ttm_buffer_object *bo) 108{ 109 return container_of(bo, struct nouveau_bo, bo); 110} 111 112static inline struct nouveau_bo * 113nouveau_gem_object(struct drm_gem_object *gem) 114{ 115 return gem ? gem->driver_private : NULL; 116} 117 118/* TODO: submit equivalent to TTM generic API upstream? */ 119static inline void __iomem * 120nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 121{ 122 bool is_iomem; 123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 124 &nvbo->kmap, &is_iomem); 125 WARN_ON_ONCE(ioptr && !is_iomem); 126 return ioptr; 127} 128 129enum nouveau_flags { 130 NV_NFORCE = 0x10000000, 131 NV_NFORCE2 = 0x20000000 132}; 133 134#define NVOBJ_ENGINE_SW 0 135#define NVOBJ_ENGINE_GR 1 136#define NVOBJ_ENGINE_DISPLAY 2 137#define NVOBJ_ENGINE_INT 0xdeadbeef 138 139#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 140#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 141struct nouveau_gpuobj { 142 struct drm_device *dev; 143 struct kref refcount; 144 struct list_head list; 145 146 struct drm_mm_node *im_pramin; 147 struct nouveau_bo *im_backing; 148 uint32_t *im_backing_suspend; 149 int im_bound; 150 151 uint32_t flags; 152 153 u32 size; 154 u32 pinst; 155 u32 cinst; 156 u64 vinst; 157 158 uint32_t engine; 159 uint32_t class; 160 161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 162 void *priv; 163}; 164 165struct nouveau_channel { 166 struct drm_device *dev; 167 int id; 168 169 struct mutex mutex; 170 171 /* owner of this fifo */ 172 struct drm_file *file_priv; 173 /* mapping of the fifo itself */ 174 struct drm_local_map *map; 175 176 /* mapping of the regs controling the fifo */ 177 void __iomem *user; 178 uint32_t user_get; 179 uint32_t user_put; 180 181 /* Fencing */ 182 struct { 183 /* lock protects the pending list only */ 184 spinlock_t lock; 185 struct list_head pending; 186 uint32_t sequence; 187 uint32_t sequence_ack; 188 atomic_t last_sequence_irq; 189 } fence; 190 191 /* DMA push buffer */ 192 struct nouveau_gpuobj *pushbuf; 193 struct nouveau_bo *pushbuf_bo; 194 uint32_t pushbuf_base; 195 196 /* Notifier memory */ 197 struct nouveau_bo *notifier_bo; 198 struct drm_mm notifier_heap; 199 200 /* PFIFO context */ 201 struct nouveau_gpuobj *ramfc; 202 struct nouveau_gpuobj *cache; 203 204 /* PGRAPH context */ 205 /* XXX may be merge 2 pointers as private data ??? */ 206 struct nouveau_gpuobj *ramin_grctx; 207 void *pgraph_ctx; 208 209 /* NV50 VM */ 210 struct nouveau_gpuobj *vm_pd; 211 struct nouveau_gpuobj *vm_gart_pt; 212 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 213 214 /* Objects */ 215 struct nouveau_gpuobj *ramin; /* Private instmem */ 216 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 217 struct nouveau_ramht *ramht; /* Hash table */ 218 219 /* GPU object info for stuff used in-kernel (mm_enabled) */ 220 uint32_t m2mf_ntfy; 221 uint32_t vram_handle; 222 uint32_t gart_handle; 223 bool accel_done; 224 225 /* Push buffer state (only for drm's channel on !mm_enabled) */ 226 struct { 227 int max; 228 int free; 229 int cur; 230 int put; 231 /* access via pushbuf_bo */ 232 233 int ib_base; 234 int ib_max; 235 int ib_free; 236 int ib_put; 237 } dma; 238 239 uint32_t sw_subchannel[8]; 240 241 struct { 242 struct nouveau_gpuobj *vblsem; 243 uint32_t vblsem_offset; 244 uint32_t vblsem_rval; 245 struct list_head vbl_wait; 246 } nvsw; 247 248 struct { 249 bool active; 250 char name[32]; 251 struct drm_info_list info; 252 } debugfs; 253}; 254 255struct nouveau_instmem_engine { 256 void *priv; 257 258 int (*init)(struct drm_device *dev); 259 void (*takedown)(struct drm_device *dev); 260 int (*suspend)(struct drm_device *dev); 261 void (*resume)(struct drm_device *dev); 262 263 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 264 uint32_t *size); 265 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 266 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 267 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 268 void (*flush)(struct drm_device *); 269}; 270 271struct nouveau_mc_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274}; 275 276struct nouveau_timer_engine { 277 int (*init)(struct drm_device *dev); 278 void (*takedown)(struct drm_device *dev); 279 uint64_t (*read)(struct drm_device *dev); 280}; 281 282struct nouveau_fb_engine { 283 int num_tiles; 284 285 int (*init)(struct drm_device *dev); 286 void (*takedown)(struct drm_device *dev); 287 288 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 289 uint32_t size, uint32_t pitch); 290}; 291 292struct nouveau_fifo_engine { 293 int channels; 294 295 struct nouveau_gpuobj *playlist[2]; 296 int cur_playlist; 297 298 int (*init)(struct drm_device *); 299 void (*takedown)(struct drm_device *); 300 301 void (*disable)(struct drm_device *); 302 void (*enable)(struct drm_device *); 303 bool (*reassign)(struct drm_device *, bool enable); 304 bool (*cache_pull)(struct drm_device *dev, bool enable); 305 306 int (*channel_id)(struct drm_device *); 307 308 int (*create_context)(struct nouveau_channel *); 309 void (*destroy_context)(struct nouveau_channel *); 310 int (*load_context)(struct nouveau_channel *); 311 int (*unload_context)(struct drm_device *); 312 void (*tlb_flush)(struct drm_device *dev); 313}; 314 315struct nouveau_pgraph_object_method { 316 int id; 317 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 318 uint32_t data); 319}; 320 321struct nouveau_pgraph_object_class { 322 int id; 323 bool software; 324 struct nouveau_pgraph_object_method *methods; 325}; 326 327struct nouveau_pgraph_engine { 328 struct nouveau_pgraph_object_class *grclass; 329 bool accel_blocked; 330 int grctx_size; 331 332 /* NV2x/NV3x context table (0x400780) */ 333 struct nouveau_gpuobj *ctx_table; 334 335 int (*init)(struct drm_device *); 336 void (*takedown)(struct drm_device *); 337 338 void (*fifo_access)(struct drm_device *, bool); 339 340 struct nouveau_channel *(*channel)(struct drm_device *); 341 int (*create_context)(struct nouveau_channel *); 342 void (*destroy_context)(struct nouveau_channel *); 343 int (*load_context)(struct nouveau_channel *); 344 int (*unload_context)(struct drm_device *); 345 void (*tlb_flush)(struct drm_device *dev); 346 347 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 348 uint32_t size, uint32_t pitch); 349}; 350 351struct nouveau_display_engine { 352 int (*early_init)(struct drm_device *); 353 void (*late_takedown)(struct drm_device *); 354 int (*create)(struct drm_device *); 355 int (*init)(struct drm_device *); 356 void (*destroy)(struct drm_device *); 357}; 358 359struct nouveau_gpio_engine { 360 int (*init)(struct drm_device *); 361 void (*takedown)(struct drm_device *); 362 363 int (*get)(struct drm_device *, enum dcb_gpio_tag); 364 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 365 366 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 367}; 368 369struct nouveau_pm_voltage_level { 370 u8 voltage; 371 u8 vid; 372}; 373 374struct nouveau_pm_voltage { 375 bool supported; 376 u8 vid_mask; 377 378 struct nouveau_pm_voltage_level *level; 379 int nr_level; 380}; 381 382#define NOUVEAU_PM_MAX_LEVEL 8 383struct nouveau_pm_level { 384 struct device_attribute dev_attr; 385 char name[32]; 386 int id; 387 388 u32 core; 389 u32 memory; 390 u32 shader; 391 u32 unk05; 392 393 u8 voltage; 394 u8 fanspeed; 395 396 u16 memscript; 397}; 398 399struct nouveau_pm_temp_sensor_constants { 400 u16 offset_constant; 401 s16 offset_mult; 402 u16 offset_div; 403 u16 slope_mult; 404 u16 slope_div; 405}; 406 407struct nouveau_pm_threshold_temp { 408 s16 critical; 409 s16 down_clock; 410 s16 fan_boost; 411}; 412 413struct nouveau_pm_memtiming { 414 u32 reg_100220; 415 u32 reg_100224; 416 u32 reg_100228; 417 u32 reg_10022c; 418 u32 reg_100230; 419 u32 reg_100234; 420 u32 reg_100238; 421 u32 reg_10023c; 422}; 423 424struct nouveau_pm_memtimings { 425 bool supported; 426 struct nouveau_pm_memtiming *timing; 427 int nr_timing; 428}; 429 430struct nouveau_pm_engine { 431 struct nouveau_pm_voltage voltage; 432 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 433 int nr_perflvl; 434 struct nouveau_pm_memtimings memtimings; 435 struct nouveau_pm_temp_sensor_constants sensor_constants; 436 struct nouveau_pm_threshold_temp threshold_temp; 437 438 struct nouveau_pm_level boot; 439 struct nouveau_pm_level *cur; 440 441 struct device *hwmon; 442 443 int (*clock_get)(struct drm_device *, u32 id); 444 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 445 u32 id, int khz); 446 void (*clock_set)(struct drm_device *, void *); 447 int (*voltage_get)(struct drm_device *); 448 int (*voltage_set)(struct drm_device *, int voltage); 449 int (*fanspeed_get)(struct drm_device *); 450 int (*fanspeed_set)(struct drm_device *, int fanspeed); 451 int (*temp_get)(struct drm_device *); 452}; 453 454struct nouveau_engine { 455 struct nouveau_instmem_engine instmem; 456 struct nouveau_mc_engine mc; 457 struct nouveau_timer_engine timer; 458 struct nouveau_fb_engine fb; 459 struct nouveau_pgraph_engine graph; 460 struct nouveau_fifo_engine fifo; 461 struct nouveau_display_engine display; 462 struct nouveau_gpio_engine gpio; 463 struct nouveau_pm_engine pm; 464}; 465 466struct nouveau_pll_vals { 467 union { 468 struct { 469#ifdef __BIG_ENDIAN 470 uint8_t N1, M1, N2, M2; 471#else 472 uint8_t M1, N1, M2, N2; 473#endif 474 }; 475 struct { 476 uint16_t NM1, NM2; 477 } __attribute__((packed)); 478 }; 479 int log2P; 480 481 int refclk; 482}; 483 484enum nv04_fp_display_regs { 485 FP_DISPLAY_END, 486 FP_TOTAL, 487 FP_CRTC, 488 FP_SYNC_START, 489 FP_SYNC_END, 490 FP_VALID_START, 491 FP_VALID_END 492}; 493 494struct nv04_crtc_reg { 495 unsigned char MiscOutReg; 496 uint8_t CRTC[0xa0]; 497 uint8_t CR58[0x10]; 498 uint8_t Sequencer[5]; 499 uint8_t Graphics[9]; 500 uint8_t Attribute[21]; 501 unsigned char DAC[768]; 502 503 /* PCRTC regs */ 504 uint32_t fb_start; 505 uint32_t crtc_cfg; 506 uint32_t cursor_cfg; 507 uint32_t gpio_ext; 508 uint32_t crtc_830; 509 uint32_t crtc_834; 510 uint32_t crtc_850; 511 uint32_t crtc_eng_ctrl; 512 513 /* PRAMDAC regs */ 514 uint32_t nv10_cursync; 515 struct nouveau_pll_vals pllvals; 516 uint32_t ramdac_gen_ctrl; 517 uint32_t ramdac_630; 518 uint32_t ramdac_634; 519 uint32_t tv_setup; 520 uint32_t tv_vtotal; 521 uint32_t tv_vskew; 522 uint32_t tv_vsync_delay; 523 uint32_t tv_htotal; 524 uint32_t tv_hskew; 525 uint32_t tv_hsync_delay; 526 uint32_t tv_hsync_delay2; 527 uint32_t fp_horiz_regs[7]; 528 uint32_t fp_vert_regs[7]; 529 uint32_t dither; 530 uint32_t fp_control; 531 uint32_t dither_regs[6]; 532 uint32_t fp_debug_0; 533 uint32_t fp_debug_1; 534 uint32_t fp_debug_2; 535 uint32_t fp_margin_color; 536 uint32_t ramdac_8c0; 537 uint32_t ramdac_a20; 538 uint32_t ramdac_a24; 539 uint32_t ramdac_a34; 540 uint32_t ctv_regs[38]; 541}; 542 543struct nv04_output_reg { 544 uint32_t output; 545 int head; 546}; 547 548struct nv04_mode_state { 549 struct nv04_crtc_reg crtc_reg[2]; 550 uint32_t pllsel; 551 uint32_t sel_clk; 552}; 553 554enum nouveau_card_type { 555 NV_04 = 0x00, 556 NV_10 = 0x10, 557 NV_20 = 0x20, 558 NV_30 = 0x30, 559 NV_40 = 0x40, 560 NV_50 = 0x50, 561 NV_C0 = 0xc0, 562}; 563 564struct drm_nouveau_private { 565 struct drm_device *dev; 566 567 /* the card type, takes NV_* as values */ 568 enum nouveau_card_type card_type; 569 /* exact chipset, derived from NV_PMC_BOOT_0 */ 570 int chipset; 571 int flags; 572 573 void __iomem *mmio; 574 575 spinlock_t ramin_lock; 576 void __iomem *ramin; 577 u32 ramin_size; 578 u32 ramin_base; 579 bool ramin_available; 580 struct drm_mm ramin_heap; 581 struct list_head gpuobj_list; 582 583 struct nouveau_bo *vga_ram; 584 585 struct workqueue_struct *wq; 586 struct work_struct irq_work; 587 struct work_struct hpd_work; 588 589 struct { 590 spinlock_t lock; 591 uint32_t hpd0_bits; 592 uint32_t hpd1_bits; 593 } hpd_state; 594 595 struct list_head vbl_waiting; 596 597 struct { 598 struct drm_global_reference mem_global_ref; 599 struct ttm_bo_global_ref bo_global_ref; 600 struct ttm_bo_device bdev; 601 atomic_t validate_sequence; 602 } ttm; 603 604 struct { 605 spinlock_t lock; 606 struct drm_mm heap; 607 struct nouveau_bo *bo; 608 } fence; 609 610 int fifo_alloc_count; 611 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 612 613 struct nouveau_engine engine; 614 struct nouveau_channel *channel; 615 616 /* For PFIFO and PGRAPH. */ 617 spinlock_t context_switch_lock; 618 619 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 620 struct nouveau_ramht *ramht; 621 struct nouveau_gpuobj *ramfc; 622 struct nouveau_gpuobj *ramro; 623 624 uint32_t ramin_rsvd_vram; 625 626 struct { 627 enum { 628 NOUVEAU_GART_NONE = 0, 629 NOUVEAU_GART_AGP, 630 NOUVEAU_GART_SGDMA 631 } type; 632 uint64_t aper_base; 633 uint64_t aper_size; 634 uint64_t aper_free; 635 636 struct nouveau_gpuobj *sg_ctxdma; 637 struct page *sg_dummy_page; 638 dma_addr_t sg_dummy_bus; 639 } gart_info; 640 641 /* nv10-nv40 tiling regions */ 642 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 643 644 /* VRAM/fb configuration */ 645 uint64_t vram_size; 646 uint64_t vram_sys_base; 647 u32 vram_rblock_size; 648 649 uint64_t fb_phys; 650 uint64_t fb_available_size; 651 uint64_t fb_mappable_pages; 652 uint64_t fb_aper_free; 653 int fb_mtrr; 654 655 /* G8x/G9x virtual address space */ 656 uint64_t vm_gart_base; 657 uint64_t vm_gart_size; 658 uint64_t vm_vram_base; 659 uint64_t vm_vram_size; 660 uint64_t vm_end; 661 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 662 int vm_vram_pt_nr; 663 664 struct nvbios vbios; 665 666 struct nv04_mode_state mode_reg; 667 struct nv04_mode_state saved_reg; 668 uint32_t saved_vga_font[4][16384]; 669 uint32_t crtc_owner; 670 uint32_t dac_users[4]; 671 672 struct nouveau_suspend_resume { 673 uint32_t *ramin_copy; 674 } susres; 675 676 struct backlight_device *backlight; 677 678 struct nouveau_channel *evo; 679 struct { 680 struct dcb_entry *dcb; 681 u16 script; 682 u32 pclk; 683 } evo_irq; 684 685 struct { 686 struct dentry *channel_root; 687 } debugfs; 688 689 struct nouveau_fbdev *nfbdev; 690 struct apertures_struct *apertures; 691}; 692 693static inline struct drm_nouveau_private * 694nouveau_private(struct drm_device *dev) 695{ 696 return dev->dev_private; 697} 698 699static inline struct drm_nouveau_private * 700nouveau_bdev(struct ttm_bo_device *bd) 701{ 702 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 703} 704 705static inline int 706nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 707{ 708 struct nouveau_bo *prev; 709 710 if (!pnvbo) 711 return -EINVAL; 712 prev = *pnvbo; 713 714 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 715 if (prev) { 716 struct ttm_buffer_object *bo = &prev->bo; 717 718 ttm_bo_unref(&bo); 719 } 720 721 return 0; 722} 723 724#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 725 struct drm_nouveau_private *nv = dev->dev_private; \ 726 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 727 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 728 DRM_CURRENTPID, (id)); \ 729 return -EPERM; \ 730 } \ 731 (ch) = nv->fifos[(id)]; \ 732} while (0) 733 734/* nouveau_drv.c */ 735extern int nouveau_agpmode; 736extern int nouveau_duallink; 737extern int nouveau_uscript_lvds; 738extern int nouveau_uscript_tmds; 739extern int nouveau_vram_pushbuf; 740extern int nouveau_vram_notify; 741extern int nouveau_fbpercrtc; 742extern int nouveau_tv_disable; 743extern char *nouveau_tv_norm; 744extern int nouveau_reg_debug; 745extern char *nouveau_vbios; 746extern int nouveau_ignorelid; 747extern int nouveau_nofbaccel; 748extern int nouveau_noaccel; 749extern int nouveau_force_post; 750extern int nouveau_override_conntype; 751extern char *nouveau_perflvl; 752extern int nouveau_perflvl_wr; 753 754extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 755extern int nouveau_pci_resume(struct pci_dev *pdev); 756 757/* nouveau_state.c */ 758extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 759extern int nouveau_load(struct drm_device *, unsigned long flags); 760extern int nouveau_firstopen(struct drm_device *); 761extern void nouveau_lastclose(struct drm_device *); 762extern int nouveau_unload(struct drm_device *); 763extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 764 struct drm_file *); 765extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 766 struct drm_file *); 767extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 768 uint32_t reg, uint32_t mask, uint32_t val); 769extern bool nouveau_wait_for_idle(struct drm_device *); 770extern int nouveau_card_init(struct drm_device *); 771 772/* nouveau_mem.c */ 773extern int nouveau_mem_vram_init(struct drm_device *); 774extern void nouveau_mem_vram_fini(struct drm_device *); 775extern int nouveau_mem_gart_init(struct drm_device *); 776extern void nouveau_mem_gart_fini(struct drm_device *); 777extern int nouveau_mem_init_agp(struct drm_device *); 778extern int nouveau_mem_reset_agp(struct drm_device *); 779extern void nouveau_mem_close(struct drm_device *); 780extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 781 uint32_t addr, 782 uint32_t size, 783 uint32_t pitch); 784extern void nv10_mem_expire_tiling(struct drm_device *dev, 785 struct nouveau_tile_reg *tile, 786 struct nouveau_fence *fence); 787extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 788 uint32_t size, uint32_t flags, 789 uint64_t phys); 790extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 791 uint32_t size); 792 793/* nouveau_notifier.c */ 794extern int nouveau_notifier_init_channel(struct nouveau_channel *); 795extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 796extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 797 int cout, uint32_t *offset); 798extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 799extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 800 struct drm_file *); 801extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 802 struct drm_file *); 803 804/* nouveau_channel.c */ 805extern struct drm_ioctl_desc nouveau_ioctls[]; 806extern int nouveau_max_ioctl; 807extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 808extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 809 int channel); 810extern int nouveau_channel_alloc(struct drm_device *dev, 811 struct nouveau_channel **chan, 812 struct drm_file *file_priv, 813 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 814extern void nouveau_channel_free(struct nouveau_channel *); 815 816/* nouveau_object.c */ 817extern int nouveau_gpuobj_early_init(struct drm_device *); 818extern int nouveau_gpuobj_init(struct drm_device *); 819extern void nouveau_gpuobj_takedown(struct drm_device *); 820extern int nouveau_gpuobj_suspend(struct drm_device *dev); 821extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 822extern void nouveau_gpuobj_resume(struct drm_device *dev); 823extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 824 uint32_t vram_h, uint32_t tt_h); 825extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 826extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 827 uint32_t size, int align, uint32_t flags, 828 struct nouveau_gpuobj **); 829extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 830 struct nouveau_gpuobj **); 831extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 832 u32 size, u32 flags, 833 struct nouveau_gpuobj **); 834extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 835 uint64_t offset, uint64_t size, int access, 836 int target, struct nouveau_gpuobj **); 837extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 838 uint64_t offset, uint64_t size, 839 int access, struct nouveau_gpuobj **, 840 uint32_t *o_ret); 841extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 842 struct nouveau_gpuobj **); 843extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 844 struct nouveau_gpuobj **); 845extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 846 struct drm_file *); 847extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 848 struct drm_file *); 849 850/* nouveau_irq.c */ 851extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 852extern void nouveau_irq_preinstall(struct drm_device *); 853extern int nouveau_irq_postinstall(struct drm_device *); 854extern void nouveau_irq_uninstall(struct drm_device *); 855 856/* nouveau_sgdma.c */ 857extern int nouveau_sgdma_init(struct drm_device *); 858extern void nouveau_sgdma_takedown(struct drm_device *); 859extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 860 uint32_t *page); 861extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 862 863/* nouveau_debugfs.c */ 864#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 865extern int nouveau_debugfs_init(struct drm_minor *); 866extern void nouveau_debugfs_takedown(struct drm_minor *); 867extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 868extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 869#else 870static inline int 871nouveau_debugfs_init(struct drm_minor *minor) 872{ 873 return 0; 874} 875 876static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 877{ 878} 879 880static inline int 881nouveau_debugfs_channel_init(struct nouveau_channel *chan) 882{ 883 return 0; 884} 885 886static inline void 887nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 888{ 889} 890#endif 891 892/* nouveau_dma.c */ 893extern void nouveau_dma_pre_init(struct nouveau_channel *); 894extern int nouveau_dma_init(struct nouveau_channel *); 895extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 896 897/* nouveau_acpi.c */ 898#define ROM_BIOS_PAGE 4096 899#if defined(CONFIG_ACPI) 900void nouveau_register_dsm_handler(void); 901void nouveau_unregister_dsm_handler(void); 902int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 903bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 904int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 905#else 906static inline void nouveau_register_dsm_handler(void) {} 907static inline void nouveau_unregister_dsm_handler(void) {} 908static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 909static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 910static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 911#endif 912 913/* nouveau_backlight.c */ 914#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 915extern int nouveau_backlight_init(struct drm_device *); 916extern void nouveau_backlight_exit(struct drm_device *); 917#else 918static inline int nouveau_backlight_init(struct drm_device *dev) 919{ 920 return 0; 921} 922 923static inline void nouveau_backlight_exit(struct drm_device *dev) { } 924#endif 925 926/* nouveau_bios.c */ 927extern int nouveau_bios_init(struct drm_device *); 928extern void nouveau_bios_takedown(struct drm_device *dev); 929extern int nouveau_run_vbios_init(struct drm_device *); 930extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 931 struct dcb_entry *); 932extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 933 enum dcb_gpio_tag); 934extern struct dcb_connector_table_entry * 935nouveau_bios_connector_entry(struct drm_device *, int index); 936extern u32 get_pll_register(struct drm_device *, enum pll_types); 937extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 938 struct pll_lims *); 939extern int nouveau_bios_run_display_table(struct drm_device *, 940 struct dcb_entry *, 941 uint32_t script, int pxclk); 942extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 943 int *length); 944extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 945extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 946extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 947 bool *dl, bool *if_is_24bit); 948extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 949 int head, int pxclk); 950extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 951 enum LVDS_script, int pxclk); 952 953/* nouveau_ttm.c */ 954int nouveau_ttm_global_init(struct drm_nouveau_private *); 955void nouveau_ttm_global_release(struct drm_nouveau_private *); 956int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 957 958/* nouveau_dp.c */ 959int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 960 uint8_t *data, int data_nr); 961bool nouveau_dp_detect(struct drm_encoder *); 962bool nouveau_dp_link_train(struct drm_encoder *); 963 964/* nv04_fb.c */ 965extern int nv04_fb_init(struct drm_device *); 966extern void nv04_fb_takedown(struct drm_device *); 967 968/* nv10_fb.c */ 969extern int nv10_fb_init(struct drm_device *); 970extern void nv10_fb_takedown(struct drm_device *); 971extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 972 uint32_t, uint32_t); 973 974/* nv30_fb.c */ 975extern int nv30_fb_init(struct drm_device *); 976extern void nv30_fb_takedown(struct drm_device *); 977 978/* nv40_fb.c */ 979extern int nv40_fb_init(struct drm_device *); 980extern void nv40_fb_takedown(struct drm_device *); 981extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 982 uint32_t, uint32_t); 983/* nv50_fb.c */ 984extern int nv50_fb_init(struct drm_device *); 985extern void nv50_fb_takedown(struct drm_device *); 986extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 987 988/* nvc0_fb.c */ 989extern int nvc0_fb_init(struct drm_device *); 990extern void nvc0_fb_takedown(struct drm_device *); 991 992/* nv04_fifo.c */ 993extern int nv04_fifo_init(struct drm_device *); 994extern void nv04_fifo_disable(struct drm_device *); 995extern void nv04_fifo_enable(struct drm_device *); 996extern bool nv04_fifo_reassign(struct drm_device *, bool); 997extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 998extern int nv04_fifo_channel_id(struct drm_device *); 999extern int nv04_fifo_create_context(struct nouveau_channel *); 1000extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1001extern int nv04_fifo_load_context(struct nouveau_channel *); 1002extern int nv04_fifo_unload_context(struct drm_device *); 1003 1004/* nv10_fifo.c */ 1005extern int nv10_fifo_init(struct drm_device *); 1006extern int nv10_fifo_channel_id(struct drm_device *); 1007extern int nv10_fifo_create_context(struct nouveau_channel *); 1008extern void nv10_fifo_destroy_context(struct nouveau_channel *); 1009extern int nv10_fifo_load_context(struct nouveau_channel *); 1010extern int nv10_fifo_unload_context(struct drm_device *); 1011 1012/* nv40_fifo.c */ 1013extern int nv40_fifo_init(struct drm_device *); 1014extern int nv40_fifo_create_context(struct nouveau_channel *); 1015extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1016extern int nv40_fifo_load_context(struct nouveau_channel *); 1017extern int nv40_fifo_unload_context(struct drm_device *); 1018 1019/* nv50_fifo.c */ 1020extern int nv50_fifo_init(struct drm_device *); 1021extern void nv50_fifo_takedown(struct drm_device *); 1022extern int nv50_fifo_channel_id(struct drm_device *); 1023extern int nv50_fifo_create_context(struct nouveau_channel *); 1024extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1025extern int nv50_fifo_load_context(struct nouveau_channel *); 1026extern int nv50_fifo_unload_context(struct drm_device *); 1027extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1028 1029/* nvc0_fifo.c */ 1030extern int nvc0_fifo_init(struct drm_device *); 1031extern void nvc0_fifo_takedown(struct drm_device *); 1032extern void nvc0_fifo_disable(struct drm_device *); 1033extern void nvc0_fifo_enable(struct drm_device *); 1034extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1035extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1036extern int nvc0_fifo_channel_id(struct drm_device *); 1037extern int nvc0_fifo_create_context(struct nouveau_channel *); 1038extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1039extern int nvc0_fifo_load_context(struct nouveau_channel *); 1040extern int nvc0_fifo_unload_context(struct drm_device *); 1041 1042/* nv04_graph.c */ 1043extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1044extern int nv04_graph_init(struct drm_device *); 1045extern void nv04_graph_takedown(struct drm_device *); 1046extern void nv04_graph_fifo_access(struct drm_device *, bool); 1047extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1048extern int nv04_graph_create_context(struct nouveau_channel *); 1049extern void nv04_graph_destroy_context(struct nouveau_channel *); 1050extern int nv04_graph_load_context(struct nouveau_channel *); 1051extern int nv04_graph_unload_context(struct drm_device *); 1052extern void nv04_graph_context_switch(struct drm_device *); 1053 1054/* nv10_graph.c */ 1055extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1056extern int nv10_graph_init(struct drm_device *); 1057extern void nv10_graph_takedown(struct drm_device *); 1058extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1059extern int nv10_graph_create_context(struct nouveau_channel *); 1060extern void nv10_graph_destroy_context(struct nouveau_channel *); 1061extern int nv10_graph_load_context(struct nouveau_channel *); 1062extern int nv10_graph_unload_context(struct drm_device *); 1063extern void nv10_graph_context_switch(struct drm_device *); 1064extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1065 uint32_t, uint32_t); 1066 1067/* nv20_graph.c */ 1068extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1069extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1070extern int nv20_graph_create_context(struct nouveau_channel *); 1071extern void nv20_graph_destroy_context(struct nouveau_channel *); 1072extern int nv20_graph_load_context(struct nouveau_channel *); 1073extern int nv20_graph_unload_context(struct drm_device *); 1074extern int nv20_graph_init(struct drm_device *); 1075extern void nv20_graph_takedown(struct drm_device *); 1076extern int nv30_graph_init(struct drm_device *); 1077extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1078 uint32_t, uint32_t); 1079 1080/* nv40_graph.c */ 1081extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1082extern int nv40_graph_init(struct drm_device *); 1083extern void nv40_graph_takedown(struct drm_device *); 1084extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1085extern int nv40_graph_create_context(struct nouveau_channel *); 1086extern void nv40_graph_destroy_context(struct nouveau_channel *); 1087extern int nv40_graph_load_context(struct nouveau_channel *); 1088extern int nv40_graph_unload_context(struct drm_device *); 1089extern void nv40_grctx_init(struct nouveau_grctx *); 1090extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1091 uint32_t, uint32_t); 1092 1093/* nv50_graph.c */ 1094extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1095extern int nv50_graph_init(struct drm_device *); 1096extern void nv50_graph_takedown(struct drm_device *); 1097extern void nv50_graph_fifo_access(struct drm_device *, bool); 1098extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1099extern int nv50_graph_create_context(struct nouveau_channel *); 1100extern void nv50_graph_destroy_context(struct nouveau_channel *); 1101extern int nv50_graph_load_context(struct nouveau_channel *); 1102extern int nv50_graph_unload_context(struct drm_device *); 1103extern void nv50_graph_context_switch(struct drm_device *); 1104extern int nv50_grctx_init(struct nouveau_grctx *); 1105extern void nv50_graph_tlb_flush(struct drm_device *dev); 1106extern void nv86_graph_tlb_flush(struct drm_device *dev); 1107 1108/* nvc0_graph.c */ 1109extern int nvc0_graph_init(struct drm_device *); 1110extern void nvc0_graph_takedown(struct drm_device *); 1111extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1112extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1113extern int nvc0_graph_create_context(struct nouveau_channel *); 1114extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1115extern int nvc0_graph_load_context(struct nouveau_channel *); 1116extern int nvc0_graph_unload_context(struct drm_device *); 1117 1118/* nv04_instmem.c */ 1119extern int nv04_instmem_init(struct drm_device *); 1120extern void nv04_instmem_takedown(struct drm_device *); 1121extern int nv04_instmem_suspend(struct drm_device *); 1122extern void nv04_instmem_resume(struct drm_device *); 1123extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1124 uint32_t *size); 1125extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1126extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1127extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1128extern void nv04_instmem_flush(struct drm_device *); 1129 1130/* nv50_instmem.c */ 1131extern int nv50_instmem_init(struct drm_device *); 1132extern void nv50_instmem_takedown(struct drm_device *); 1133extern int nv50_instmem_suspend(struct drm_device *); 1134extern void nv50_instmem_resume(struct drm_device *); 1135extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1136 uint32_t *size); 1137extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1138extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1139extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1140extern void nv50_instmem_flush(struct drm_device *); 1141extern void nv84_instmem_flush(struct drm_device *); 1142extern void nv50_vm_flush(struct drm_device *, int engine); 1143 1144/* nvc0_instmem.c */ 1145extern int nvc0_instmem_init(struct drm_device *); 1146extern void nvc0_instmem_takedown(struct drm_device *); 1147extern int nvc0_instmem_suspend(struct drm_device *); 1148extern void nvc0_instmem_resume(struct drm_device *); 1149extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1150 uint32_t *size); 1151extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1152extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1153extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1154extern void nvc0_instmem_flush(struct drm_device *); 1155 1156/* nv04_mc.c */ 1157extern int nv04_mc_init(struct drm_device *); 1158extern void nv04_mc_takedown(struct drm_device *); 1159 1160/* nv40_mc.c */ 1161extern int nv40_mc_init(struct drm_device *); 1162extern void nv40_mc_takedown(struct drm_device *); 1163 1164/* nv50_mc.c */ 1165extern int nv50_mc_init(struct drm_device *); 1166extern void nv50_mc_takedown(struct drm_device *); 1167 1168/* nv04_timer.c */ 1169extern int nv04_timer_init(struct drm_device *); 1170extern uint64_t nv04_timer_read(struct drm_device *); 1171extern void nv04_timer_takedown(struct drm_device *); 1172 1173extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1174 unsigned long arg); 1175 1176/* nv04_dac.c */ 1177extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1178extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1179extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1180extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1181extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1182 1183/* nv04_dfp.c */ 1184extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1185extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1186extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1187 int head, bool dl); 1188extern void nv04_dfp_disable(struct drm_device *dev, int head); 1189extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1190 1191/* nv04_tv.c */ 1192extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1193extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1194 1195/* nv17_tv.c */ 1196extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1197 1198/* nv04_display.c */ 1199extern int nv04_display_early_init(struct drm_device *); 1200extern void nv04_display_late_takedown(struct drm_device *); 1201extern int nv04_display_create(struct drm_device *); 1202extern int nv04_display_init(struct drm_device *); 1203extern void nv04_display_destroy(struct drm_device *); 1204 1205/* nv04_crtc.c */ 1206extern int nv04_crtc_create(struct drm_device *, int index); 1207 1208/* nouveau_bo.c */ 1209extern struct ttm_bo_driver nouveau_bo_driver; 1210extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1211 int size, int align, uint32_t flags, 1212 uint32_t tile_mode, uint32_t tile_flags, 1213 bool no_vm, bool mappable, struct nouveau_bo **); 1214extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1215extern int nouveau_bo_unpin(struct nouveau_bo *); 1216extern int nouveau_bo_map(struct nouveau_bo *); 1217extern void nouveau_bo_unmap(struct nouveau_bo *); 1218extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1219 uint32_t busy); 1220extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1221extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1222extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1223extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1224 1225/* nouveau_fence.c */ 1226struct nouveau_fence; 1227extern int nouveau_fence_init(struct drm_device *); 1228extern void nouveau_fence_fini(struct drm_device *); 1229extern int nouveau_fence_channel_init(struct nouveau_channel *); 1230extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1231extern void nouveau_fence_update(struct nouveau_channel *); 1232extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1233 bool emit); 1234extern int nouveau_fence_emit(struct nouveau_fence *); 1235extern void nouveau_fence_work(struct nouveau_fence *fence, 1236 void (*work)(void *priv, bool signalled), 1237 void *priv); 1238struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1239extern bool nouveau_fence_signalled(void *obj, void *arg); 1240extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1241extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1242extern int nouveau_fence_flush(void *obj, void *arg); 1243extern void nouveau_fence_unref(void **obj); 1244extern void *nouveau_fence_ref(void *obj); 1245 1246/* nouveau_gem.c */ 1247extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1248 int size, int align, uint32_t flags, 1249 uint32_t tile_mode, uint32_t tile_flags, 1250 bool no_vm, bool mappable, struct nouveau_bo **); 1251extern int nouveau_gem_object_new(struct drm_gem_object *); 1252extern void nouveau_gem_object_del(struct drm_gem_object *); 1253extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1254 struct drm_file *); 1255extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1256 struct drm_file *); 1257extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1258 struct drm_file *); 1259extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1260 struct drm_file *); 1261extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1262 struct drm_file *); 1263 1264/* nv10_gpio.c */ 1265int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1266int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1267 1268/* nv50_gpio.c */ 1269int nv50_gpio_init(struct drm_device *dev); 1270int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1271int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1272void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1273 1274/* nv50_calc. */ 1275int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1276 int *N1, int *M1, int *N2, int *M2, int *P); 1277int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1278 int clk, int *N, int *fN, int *M, int *P); 1279 1280#ifndef ioread32_native 1281#ifdef __BIG_ENDIAN 1282#define ioread16_native ioread16be 1283#define iowrite16_native iowrite16be 1284#define ioread32_native ioread32be 1285#define iowrite32_native iowrite32be 1286#else /* def __BIG_ENDIAN */ 1287#define ioread16_native ioread16 1288#define iowrite16_native iowrite16 1289#define ioread32_native ioread32 1290#define iowrite32_native iowrite32 1291#endif /* def __BIG_ENDIAN else */ 1292#endif /* !ioread32_native */ 1293 1294/* channel control reg access */ 1295static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1296{ 1297 return ioread32_native(chan->user + reg); 1298} 1299 1300static inline void nvchan_wr32(struct nouveau_channel *chan, 1301 unsigned reg, u32 val) 1302{ 1303 iowrite32_native(val, chan->user + reg); 1304} 1305 1306/* register access */ 1307static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1308{ 1309 struct drm_nouveau_private *dev_priv = dev->dev_private; 1310 return ioread32_native(dev_priv->mmio + reg); 1311} 1312 1313static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1314{ 1315 struct drm_nouveau_private *dev_priv = dev->dev_private; 1316 iowrite32_native(val, dev_priv->mmio + reg); 1317} 1318 1319static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1320{ 1321 u32 tmp = nv_rd32(dev, reg); 1322 nv_wr32(dev, reg, (tmp & ~mask) | val); 1323 return tmp; 1324} 1325 1326static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1327{ 1328 struct drm_nouveau_private *dev_priv = dev->dev_private; 1329 return ioread8(dev_priv->mmio + reg); 1330} 1331 1332static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1333{ 1334 struct drm_nouveau_private *dev_priv = dev->dev_private; 1335 iowrite8(val, dev_priv->mmio + reg); 1336} 1337 1338#define nv_wait(dev, reg, mask, val) \ 1339 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1340 1341/* PRAMIN access */ 1342static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1343{ 1344 struct drm_nouveau_private *dev_priv = dev->dev_private; 1345 return ioread32_native(dev_priv->ramin + offset); 1346} 1347 1348static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1349{ 1350 struct drm_nouveau_private *dev_priv = dev->dev_private; 1351 iowrite32_native(val, dev_priv->ramin + offset); 1352} 1353 1354/* object access */ 1355extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1356extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1357 1358/* 1359 * Logging 1360 * Argument d is (struct drm_device *). 1361 */ 1362#define NV_PRINTK(level, d, fmt, arg...) \ 1363 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1364 pci_name(d->pdev), ##arg) 1365#ifndef NV_DEBUG_NOTRACE 1366#define NV_DEBUG(d, fmt, arg...) do { \ 1367 if (drm_debug & DRM_UT_DRIVER) { \ 1368 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1369 __LINE__, ##arg); \ 1370 } \ 1371} while (0) 1372#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1373 if (drm_debug & DRM_UT_KMS) { \ 1374 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1375 __LINE__, ##arg); \ 1376 } \ 1377} while (0) 1378#else 1379#define NV_DEBUG(d, fmt, arg...) do { \ 1380 if (drm_debug & DRM_UT_DRIVER) \ 1381 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1382} while (0) 1383#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1384 if (drm_debug & DRM_UT_KMS) \ 1385 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1386} while (0) 1387#endif 1388#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1389#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1390#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1391#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1392#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1393 1394/* nouveau_reg_debug bitmask */ 1395enum { 1396 NOUVEAU_REG_DEBUG_MC = 0x1, 1397 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1398 NOUVEAU_REG_DEBUG_FB = 0x4, 1399 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1400 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1401 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1402 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1403 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1404 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1405 NOUVEAU_REG_DEBUG_EVO = 0x200, 1406}; 1407 1408#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1409 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1410 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1411} while (0) 1412 1413static inline bool 1414nv_two_heads(struct drm_device *dev) 1415{ 1416 struct drm_nouveau_private *dev_priv = dev->dev_private; 1417 const int impl = dev->pci_device & 0x0ff0; 1418 1419 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1420 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1421 return true; 1422 1423 return false; 1424} 1425 1426static inline bool 1427nv_gf4_disp_arch(struct drm_device *dev) 1428{ 1429 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1430} 1431 1432static inline bool 1433nv_two_reg_pll(struct drm_device *dev) 1434{ 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 const int impl = dev->pci_device & 0x0ff0; 1437 1438 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1439 return true; 1440 return false; 1441} 1442 1443static inline bool 1444nv_match_device(struct drm_device *dev, unsigned device, 1445 unsigned sub_vendor, unsigned sub_device) 1446{ 1447 return dev->pdev->device == device && 1448 dev->pdev->subsystem_vendor == sub_vendor && 1449 dev->pdev->subsystem_device == sub_device; 1450} 1451 1452#define NV_SW 0x0000506e 1453#define NV_SW_DMA_SEMAPHORE 0x00000060 1454#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1455#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1456#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1457#define NV_SW_YIELD 0x00000080 1458#define NV_SW_DMA_VBLSEM 0x0000018c 1459#define NV_SW_VBLSEM_OFFSET 0x00000400 1460#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1461#define NV_SW_VBLSEM_RELEASE 0x00000408 1462 1463#endif /* __NOUVEAU_DRV_H__ */ 1464