nouveau_drv.h revision 6ba9a68317781537d6184d3fdb2d0f20c97da3a4
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78}; 79 80struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88}; 89 90struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 108 uint32_t tile_mode; 109 uint32_t tile_flags; 110 struct nouveau_tile_reg *tile; 111 112 struct drm_gem_object *gem; 113 int pin_refcnt; 114}; 115 116#define nouveau_bo_tile_layout(nvbo) \ 117 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 118 119static inline struct nouveau_bo * 120nouveau_bo(struct ttm_buffer_object *bo) 121{ 122 return container_of(bo, struct nouveau_bo, bo); 123} 124 125static inline struct nouveau_bo * 126nouveau_gem_object(struct drm_gem_object *gem) 127{ 128 return gem ? gem->driver_private : NULL; 129} 130 131/* TODO: submit equivalent to TTM generic API upstream? */ 132static inline void __iomem * 133nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 134{ 135 bool is_iomem; 136 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 137 &nvbo->kmap, &is_iomem); 138 WARN_ON_ONCE(ioptr && !is_iomem); 139 return ioptr; 140} 141 142enum nouveau_flags { 143 NV_NFORCE = 0x10000000, 144 NV_NFORCE2 = 0x20000000 145}; 146 147#define NVOBJ_ENGINE_SW 0 148#define NVOBJ_ENGINE_GR 1 149#define NVOBJ_ENGINE_PPP 2 150#define NVOBJ_ENGINE_COPY 3 151#define NVOBJ_ENGINE_VP 4 152#define NVOBJ_ENGINE_CRYPT 5 153#define NVOBJ_ENGINE_BSP 6 154#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 155#define NVOBJ_ENGINE_INT 0xdeadbeef 156 157#define NVOBJ_FLAG_DONT_MAP (1 << 0) 158#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 159#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 160#define NVOBJ_FLAG_VM (1 << 3) 161#define NVOBJ_FLAG_VM_USER (1 << 4) 162 163#define NVOBJ_CINST_GLOBAL 0xdeadbeef 164 165struct nouveau_gpuobj { 166 struct drm_device *dev; 167 struct kref refcount; 168 struct list_head list; 169 170 void *node; 171 u32 *suspend; 172 173 uint32_t flags; 174 175 u32 size; 176 u32 pinst; 177 u32 cinst; 178 u64 vinst; 179 180 uint32_t engine; 181 uint32_t class; 182 183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 184 void *priv; 185}; 186 187struct nouveau_page_flip_state { 188 struct list_head head; 189 struct drm_pending_vblank_event *event; 190 int crtc, bpp, pitch, x, y; 191 uint64_t offset; 192}; 193 194enum nouveau_channel_mutex_class { 195 NOUVEAU_UCHANNEL_MUTEX, 196 NOUVEAU_KCHANNEL_MUTEX 197}; 198 199struct nouveau_channel { 200 struct drm_device *dev; 201 int id; 202 203 /* references to the channel data structure */ 204 struct kref ref; 205 /* users of the hardware channel resources, the hardware 206 * context will be kicked off when it reaches zero. */ 207 atomic_t users; 208 struct mutex mutex; 209 210 /* owner of this fifo */ 211 struct drm_file *file_priv; 212 /* mapping of the fifo itself */ 213 struct drm_local_map *map; 214 215 /* mapping of the regs controling the fifo */ 216 void __iomem *user; 217 uint32_t user_get; 218 uint32_t user_put; 219 220 /* Fencing */ 221 struct { 222 /* lock protects the pending list only */ 223 spinlock_t lock; 224 struct list_head pending; 225 uint32_t sequence; 226 uint32_t sequence_ack; 227 atomic_t last_sequence_irq; 228 } fence; 229 230 /* DMA push buffer */ 231 struct nouveau_gpuobj *pushbuf; 232 struct nouveau_bo *pushbuf_bo; 233 uint32_t pushbuf_base; 234 235 /* Notifier memory */ 236 struct nouveau_bo *notifier_bo; 237 struct drm_mm notifier_heap; 238 239 /* PFIFO context */ 240 struct nouveau_gpuobj *ramfc; 241 struct nouveau_gpuobj *cache; 242 void *fifo_priv; 243 244 /* PGRAPH context */ 245 /* XXX may be merge 2 pointers as private data ??? */ 246 struct nouveau_gpuobj *ramin_grctx; 247 struct nouveau_gpuobj *crypt_ctx; 248 void *pgraph_ctx; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295}; 296 297struct nouveau_instmem_engine { 298 void *priv; 299 300 int (*init)(struct drm_device *dev); 301 void (*takedown)(struct drm_device *dev); 302 int (*suspend)(struct drm_device *dev); 303 void (*resume)(struct drm_device *dev); 304 305 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 306 void (*put)(struct nouveau_gpuobj *); 307 int (*map)(struct nouveau_gpuobj *); 308 void (*unmap)(struct nouveau_gpuobj *); 309 310 void (*flush)(struct drm_device *); 311}; 312 313struct nouveau_mc_engine { 314 int (*init)(struct drm_device *dev); 315 void (*takedown)(struct drm_device *dev); 316}; 317 318struct nouveau_timer_engine { 319 int (*init)(struct drm_device *dev); 320 void (*takedown)(struct drm_device *dev); 321 uint64_t (*read)(struct drm_device *dev); 322}; 323 324struct nouveau_fb_engine { 325 int num_tiles; 326 struct drm_mm tag_heap; 327 void *priv; 328 329 int (*init)(struct drm_device *dev); 330 void (*takedown)(struct drm_device *dev); 331 332 void (*init_tile_region)(struct drm_device *dev, int i, 333 uint32_t addr, uint32_t size, 334 uint32_t pitch, uint32_t flags); 335 void (*set_tile_region)(struct drm_device *dev, int i); 336 void (*free_tile_region)(struct drm_device *dev, int i); 337}; 338 339struct nouveau_fifo_engine { 340 void *priv; 341 int channels; 342 343 struct nouveau_gpuobj *playlist[2]; 344 int cur_playlist; 345 346 int (*init)(struct drm_device *); 347 void (*takedown)(struct drm_device *); 348 349 void (*disable)(struct drm_device *); 350 void (*enable)(struct drm_device *); 351 bool (*reassign)(struct drm_device *, bool enable); 352 bool (*cache_pull)(struct drm_device *dev, bool enable); 353 354 int (*channel_id)(struct drm_device *); 355 356 int (*create_context)(struct nouveau_channel *); 357 void (*destroy_context)(struct nouveau_channel *); 358 int (*load_context)(struct nouveau_channel *); 359 int (*unload_context)(struct drm_device *); 360 void (*tlb_flush)(struct drm_device *dev); 361}; 362 363struct nouveau_pgraph_engine { 364 bool accel_blocked; 365 bool registered; 366 int grctx_size; 367 void *priv; 368 369 /* NV2x/NV3x context table (0x400780) */ 370 struct nouveau_gpuobj *ctx_table; 371 372 int (*init)(struct drm_device *); 373 void (*takedown)(struct drm_device *); 374 375 void (*fifo_access)(struct drm_device *, bool); 376 377 struct nouveau_channel *(*channel)(struct drm_device *); 378 int (*create_context)(struct nouveau_channel *); 379 void (*destroy_context)(struct nouveau_channel *); 380 int (*load_context)(struct nouveau_channel *); 381 int (*unload_context)(struct drm_device *); 382 void (*tlb_flush)(struct drm_device *dev); 383 384 void (*set_tile_region)(struct drm_device *dev, int i); 385}; 386 387struct nouveau_display_engine { 388 void *priv; 389 int (*early_init)(struct drm_device *); 390 void (*late_takedown)(struct drm_device *); 391 int (*create)(struct drm_device *); 392 int (*init)(struct drm_device *); 393 void (*destroy)(struct drm_device *); 394}; 395 396struct nouveau_gpio_engine { 397 void *priv; 398 399 int (*init)(struct drm_device *); 400 void (*takedown)(struct drm_device *); 401 402 int (*get)(struct drm_device *, enum dcb_gpio_tag); 403 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 404 405 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 406 void (*)(void *, int), void *); 407 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 408 void (*)(void *, int), void *); 409 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 410}; 411 412struct nouveau_pm_voltage_level { 413 u8 voltage; 414 u8 vid; 415}; 416 417struct nouveau_pm_voltage { 418 bool supported; 419 u8 vid_mask; 420 421 struct nouveau_pm_voltage_level *level; 422 int nr_level; 423}; 424 425#define NOUVEAU_PM_MAX_LEVEL 8 426struct nouveau_pm_level { 427 struct device_attribute dev_attr; 428 char name[32]; 429 int id; 430 431 u32 core; 432 u32 memory; 433 u32 shader; 434 u32 unk05; 435 436 u8 voltage; 437 u8 fanspeed; 438 439 u16 memscript; 440}; 441 442struct nouveau_pm_temp_sensor_constants { 443 u16 offset_constant; 444 s16 offset_mult; 445 u16 offset_div; 446 u16 slope_mult; 447 u16 slope_div; 448}; 449 450struct nouveau_pm_threshold_temp { 451 s16 critical; 452 s16 down_clock; 453 s16 fan_boost; 454}; 455 456struct nouveau_pm_memtiming { 457 u32 reg_100220; 458 u32 reg_100224; 459 u32 reg_100228; 460 u32 reg_10022c; 461 u32 reg_100230; 462 u32 reg_100234; 463 u32 reg_100238; 464 u32 reg_10023c; 465}; 466 467struct nouveau_pm_memtimings { 468 bool supported; 469 struct nouveau_pm_memtiming *timing; 470 int nr_timing; 471}; 472 473struct nouveau_pm_engine { 474 struct nouveau_pm_voltage voltage; 475 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 476 int nr_perflvl; 477 struct nouveau_pm_memtimings memtimings; 478 struct nouveau_pm_temp_sensor_constants sensor_constants; 479 struct nouveau_pm_threshold_temp threshold_temp; 480 481 struct nouveau_pm_level boot; 482 struct nouveau_pm_level *cur; 483 484 struct device *hwmon; 485 struct notifier_block acpi_nb; 486 487 int (*clock_get)(struct drm_device *, u32 id); 488 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 489 u32 id, int khz); 490 void (*clock_set)(struct drm_device *, void *); 491 int (*voltage_get)(struct drm_device *); 492 int (*voltage_set)(struct drm_device *, int voltage); 493 int (*fanspeed_get)(struct drm_device *); 494 int (*fanspeed_set)(struct drm_device *, int fanspeed); 495 int (*temp_get)(struct drm_device *); 496}; 497 498struct nouveau_crypt_engine { 499 bool registered; 500 501 int (*init)(struct drm_device *); 502 void (*takedown)(struct drm_device *); 503 int (*create_context)(struct nouveau_channel *); 504 void (*destroy_context)(struct nouveau_channel *); 505 void (*tlb_flush)(struct drm_device *dev); 506}; 507 508struct nouveau_vram_engine { 509 int (*init)(struct drm_device *); 510 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 511 u32 type, struct nouveau_vram **); 512 void (*put)(struct drm_device *, struct nouveau_vram **); 513 514 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 515}; 516 517struct nouveau_engine { 518 struct nouveau_instmem_engine instmem; 519 struct nouveau_mc_engine mc; 520 struct nouveau_timer_engine timer; 521 struct nouveau_fb_engine fb; 522 struct nouveau_pgraph_engine graph; 523 struct nouveau_fifo_engine fifo; 524 struct nouveau_display_engine display; 525 struct nouveau_gpio_engine gpio; 526 struct nouveau_pm_engine pm; 527 struct nouveau_crypt_engine crypt; 528 struct nouveau_vram_engine vram; 529}; 530 531struct nouveau_pll_vals { 532 union { 533 struct { 534#ifdef __BIG_ENDIAN 535 uint8_t N1, M1, N2, M2; 536#else 537 uint8_t M1, N1, M2, N2; 538#endif 539 }; 540 struct { 541 uint16_t NM1, NM2; 542 } __attribute__((packed)); 543 }; 544 int log2P; 545 546 int refclk; 547}; 548 549enum nv04_fp_display_regs { 550 FP_DISPLAY_END, 551 FP_TOTAL, 552 FP_CRTC, 553 FP_SYNC_START, 554 FP_SYNC_END, 555 FP_VALID_START, 556 FP_VALID_END 557}; 558 559struct nv04_crtc_reg { 560 unsigned char MiscOutReg; 561 uint8_t CRTC[0xa0]; 562 uint8_t CR58[0x10]; 563 uint8_t Sequencer[5]; 564 uint8_t Graphics[9]; 565 uint8_t Attribute[21]; 566 unsigned char DAC[768]; 567 568 /* PCRTC regs */ 569 uint32_t fb_start; 570 uint32_t crtc_cfg; 571 uint32_t cursor_cfg; 572 uint32_t gpio_ext; 573 uint32_t crtc_830; 574 uint32_t crtc_834; 575 uint32_t crtc_850; 576 uint32_t crtc_eng_ctrl; 577 578 /* PRAMDAC regs */ 579 uint32_t nv10_cursync; 580 struct nouveau_pll_vals pllvals; 581 uint32_t ramdac_gen_ctrl; 582 uint32_t ramdac_630; 583 uint32_t ramdac_634; 584 uint32_t tv_setup; 585 uint32_t tv_vtotal; 586 uint32_t tv_vskew; 587 uint32_t tv_vsync_delay; 588 uint32_t tv_htotal; 589 uint32_t tv_hskew; 590 uint32_t tv_hsync_delay; 591 uint32_t tv_hsync_delay2; 592 uint32_t fp_horiz_regs[7]; 593 uint32_t fp_vert_regs[7]; 594 uint32_t dither; 595 uint32_t fp_control; 596 uint32_t dither_regs[6]; 597 uint32_t fp_debug_0; 598 uint32_t fp_debug_1; 599 uint32_t fp_debug_2; 600 uint32_t fp_margin_color; 601 uint32_t ramdac_8c0; 602 uint32_t ramdac_a20; 603 uint32_t ramdac_a24; 604 uint32_t ramdac_a34; 605 uint32_t ctv_regs[38]; 606}; 607 608struct nv04_output_reg { 609 uint32_t output; 610 int head; 611}; 612 613struct nv04_mode_state { 614 struct nv04_crtc_reg crtc_reg[2]; 615 uint32_t pllsel; 616 uint32_t sel_clk; 617}; 618 619enum nouveau_card_type { 620 NV_04 = 0x00, 621 NV_10 = 0x10, 622 NV_20 = 0x20, 623 NV_30 = 0x30, 624 NV_40 = 0x40, 625 NV_50 = 0x50, 626 NV_C0 = 0xc0, 627}; 628 629struct drm_nouveau_private { 630 struct drm_device *dev; 631 632 /* the card type, takes NV_* as values */ 633 enum nouveau_card_type card_type; 634 /* exact chipset, derived from NV_PMC_BOOT_0 */ 635 int chipset; 636 int flags; 637 638 void __iomem *mmio; 639 640 spinlock_t ramin_lock; 641 void __iomem *ramin; 642 u32 ramin_size; 643 u32 ramin_base; 644 bool ramin_available; 645 struct drm_mm ramin_heap; 646 struct list_head gpuobj_list; 647 struct list_head classes; 648 649 struct nouveau_bo *vga_ram; 650 651 /* interrupt handling */ 652 void (*irq_handler[32])(struct drm_device *); 653 bool msi_enabled; 654 655 struct list_head vbl_waiting; 656 657 struct { 658 struct drm_global_reference mem_global_ref; 659 struct ttm_bo_global_ref bo_global_ref; 660 struct ttm_bo_device bdev; 661 atomic_t validate_sequence; 662 } ttm; 663 664 struct { 665 spinlock_t lock; 666 struct drm_mm heap; 667 struct nouveau_bo *bo; 668 } fence; 669 670 struct { 671 spinlock_t lock; 672 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 673 } channels; 674 675 struct nouveau_engine engine; 676 struct nouveau_channel *channel; 677 678 /* For PFIFO and PGRAPH. */ 679 spinlock_t context_switch_lock; 680 681 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 682 struct nouveau_ramht *ramht; 683 struct nouveau_gpuobj *ramfc; 684 struct nouveau_gpuobj *ramro; 685 686 uint32_t ramin_rsvd_vram; 687 688 struct { 689 enum { 690 NOUVEAU_GART_NONE = 0, 691 NOUVEAU_GART_AGP, /* AGP */ 692 NOUVEAU_GART_PDMA, /* paged dma object */ 693 NOUVEAU_GART_HW /* on-chip gart/vm */ 694 } type; 695 uint64_t aper_base; 696 uint64_t aper_size; 697 uint64_t aper_free; 698 699 struct ttm_backend_func *func; 700 701 struct { 702 struct page *page; 703 dma_addr_t addr; 704 } dummy; 705 706 struct nouveau_gpuobj *sg_ctxdma; 707 struct nouveau_vma vma; 708 } gart_info; 709 710 /* nv10-nv40 tiling regions */ 711 struct { 712 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 713 spinlock_t lock; 714 } tile; 715 716 /* VRAM/fb configuration */ 717 uint64_t vram_size; 718 uint64_t vram_sys_base; 719 u32 vram_rblock_size; 720 721 uint64_t fb_phys; 722 uint64_t fb_available_size; 723 uint64_t fb_mappable_pages; 724 uint64_t fb_aper_free; 725 int fb_mtrr; 726 727 /* BAR control (NV50-) */ 728 struct nouveau_vm *bar1_vm; 729 struct nouveau_vm *bar3_vm; 730 731 /* G8x/G9x virtual address space */ 732 struct nouveau_vm *chan_vm; 733 734 struct nvbios vbios; 735 736 struct nv04_mode_state mode_reg; 737 struct nv04_mode_state saved_reg; 738 uint32_t saved_vga_font[4][16384]; 739 uint32_t crtc_owner; 740 uint32_t dac_users[4]; 741 742 struct nouveau_suspend_resume { 743 uint32_t *ramin_copy; 744 } susres; 745 746 struct backlight_device *backlight; 747 748 struct { 749 struct dentry *channel_root; 750 } debugfs; 751 752 struct nouveau_fbdev *nfbdev; 753 struct apertures_struct *apertures; 754 755 bool powered_down; 756}; 757 758static inline struct drm_nouveau_private * 759nouveau_private(struct drm_device *dev) 760{ 761 return dev->dev_private; 762} 763 764static inline struct drm_nouveau_private * 765nouveau_bdev(struct ttm_bo_device *bd) 766{ 767 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 768} 769 770static inline int 771nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 772{ 773 struct nouveau_bo *prev; 774 775 if (!pnvbo) 776 return -EINVAL; 777 prev = *pnvbo; 778 779 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 780 if (prev) { 781 struct ttm_buffer_object *bo = &prev->bo; 782 783 ttm_bo_unref(&bo); 784 } 785 786 return 0; 787} 788 789/* nouveau_drv.c */ 790extern int nouveau_agpmode; 791extern int nouveau_duallink; 792extern int nouveau_uscript_lvds; 793extern int nouveau_uscript_tmds; 794extern int nouveau_vram_pushbuf; 795extern int nouveau_vram_notify; 796extern int nouveau_fbpercrtc; 797extern int nouveau_tv_disable; 798extern char *nouveau_tv_norm; 799extern int nouveau_reg_debug; 800extern char *nouveau_vbios; 801extern int nouveau_ignorelid; 802extern int nouveau_nofbaccel; 803extern int nouveau_noaccel; 804extern int nouveau_force_post; 805extern int nouveau_override_conntype; 806extern char *nouveau_perflvl; 807extern int nouveau_perflvl_wr; 808extern int nouveau_msi; 809 810extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 811extern int nouveau_pci_resume(struct pci_dev *pdev); 812 813/* nouveau_state.c */ 814extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 815extern int nouveau_load(struct drm_device *, unsigned long flags); 816extern int nouveau_firstopen(struct drm_device *); 817extern void nouveau_lastclose(struct drm_device *); 818extern int nouveau_unload(struct drm_device *); 819extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 820 struct drm_file *); 821extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 822 struct drm_file *); 823extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 824 uint32_t reg, uint32_t mask, uint32_t val); 825extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 826 uint32_t reg, uint32_t mask, uint32_t val); 827extern bool nouveau_wait_for_idle(struct drm_device *); 828extern int nouveau_card_init(struct drm_device *); 829 830/* nouveau_mem.c */ 831extern int nouveau_mem_vram_init(struct drm_device *); 832extern void nouveau_mem_vram_fini(struct drm_device *); 833extern int nouveau_mem_gart_init(struct drm_device *); 834extern void nouveau_mem_gart_fini(struct drm_device *); 835extern int nouveau_mem_init_agp(struct drm_device *); 836extern int nouveau_mem_reset_agp(struct drm_device *); 837extern void nouveau_mem_close(struct drm_device *); 838extern int nouveau_mem_detect(struct drm_device *); 839extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 840extern struct nouveau_tile_reg *nv10_mem_set_tiling( 841 struct drm_device *dev, uint32_t addr, uint32_t size, 842 uint32_t pitch, uint32_t flags); 843extern void nv10_mem_put_tile_region(struct drm_device *dev, 844 struct nouveau_tile_reg *tile, 845 struct nouveau_fence *fence); 846extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 847 848/* nouveau_notifier.c */ 849extern int nouveau_notifier_init_channel(struct nouveau_channel *); 850extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 851extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 852 int cout, uint32_t *offset); 853extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 854extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 855 struct drm_file *); 856extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 857 struct drm_file *); 858 859/* nouveau_channel.c */ 860extern struct drm_ioctl_desc nouveau_ioctls[]; 861extern int nouveau_max_ioctl; 862extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 863extern int nouveau_channel_alloc(struct drm_device *dev, 864 struct nouveau_channel **chan, 865 struct drm_file *file_priv, 866 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 867extern struct nouveau_channel * 868nouveau_channel_get_unlocked(struct nouveau_channel *); 869extern struct nouveau_channel * 870nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 871extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 872extern void nouveau_channel_put(struct nouveau_channel **); 873extern void nouveau_channel_ref(struct nouveau_channel *chan, 874 struct nouveau_channel **pchan); 875extern void nouveau_channel_idle(struct nouveau_channel *chan); 876 877/* nouveau_object.c */ 878#define NVOBJ_CLASS(d,c,e) do { \ 879 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 880 if (ret) \ 881 return ret; \ 882} while(0) 883 884#define NVOBJ_MTHD(d,c,m,e) do { \ 885 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 886 if (ret) \ 887 return ret; \ 888} while(0) 889 890extern int nouveau_gpuobj_early_init(struct drm_device *); 891extern int nouveau_gpuobj_init(struct drm_device *); 892extern void nouveau_gpuobj_takedown(struct drm_device *); 893extern int nouveau_gpuobj_suspend(struct drm_device *dev); 894extern void nouveau_gpuobj_resume(struct drm_device *dev); 895extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 896extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 897 int (*exec)(struct nouveau_channel *, 898 u32 class, u32 mthd, u32 data)); 899extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 900extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 901extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 902 uint32_t vram_h, uint32_t tt_h); 903extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 904extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 905 uint32_t size, int align, uint32_t flags, 906 struct nouveau_gpuobj **); 907extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 908 struct nouveau_gpuobj **); 909extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 910 u32 size, u32 flags, 911 struct nouveau_gpuobj **); 912extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 913 uint64_t offset, uint64_t size, int access, 914 int target, struct nouveau_gpuobj **); 915extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 916extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 917 u64 size, int target, int access, u32 type, 918 u32 comp, struct nouveau_gpuobj **pobj); 919extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 920 int class, u64 base, u64 size, int target, 921 int access, u32 type, u32 comp); 922extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 923 struct drm_file *); 924extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 925 struct drm_file *); 926 927/* nouveau_irq.c */ 928extern int nouveau_irq_init(struct drm_device *); 929extern void nouveau_irq_fini(struct drm_device *); 930extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 931extern void nouveau_irq_register(struct drm_device *, int status_bit, 932 void (*)(struct drm_device *)); 933extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 934extern void nouveau_irq_preinstall(struct drm_device *); 935extern int nouveau_irq_postinstall(struct drm_device *); 936extern void nouveau_irq_uninstall(struct drm_device *); 937 938/* nouveau_sgdma.c */ 939extern int nouveau_sgdma_init(struct drm_device *); 940extern void nouveau_sgdma_takedown(struct drm_device *); 941extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 942 uint32_t offset); 943extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 944 945/* nouveau_debugfs.c */ 946#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 947extern int nouveau_debugfs_init(struct drm_minor *); 948extern void nouveau_debugfs_takedown(struct drm_minor *); 949extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 950extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 951#else 952static inline int 953nouveau_debugfs_init(struct drm_minor *minor) 954{ 955 return 0; 956} 957 958static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 959{ 960} 961 962static inline int 963nouveau_debugfs_channel_init(struct nouveau_channel *chan) 964{ 965 return 0; 966} 967 968static inline void 969nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 970{ 971} 972#endif 973 974/* nouveau_dma.c */ 975extern void nouveau_dma_pre_init(struct nouveau_channel *); 976extern int nouveau_dma_init(struct nouveau_channel *); 977extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 978 979/* nouveau_acpi.c */ 980#define ROM_BIOS_PAGE 4096 981#if defined(CONFIG_ACPI) 982void nouveau_register_dsm_handler(void); 983void nouveau_unregister_dsm_handler(void); 984int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 985bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 986int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 987#else 988static inline void nouveau_register_dsm_handler(void) {} 989static inline void nouveau_unregister_dsm_handler(void) {} 990static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 991static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 992static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 993#endif 994 995/* nouveau_backlight.c */ 996#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 997extern int nouveau_backlight_init(struct drm_device *); 998extern void nouveau_backlight_exit(struct drm_device *); 999#else 1000static inline int nouveau_backlight_init(struct drm_device *dev) 1001{ 1002 return 0; 1003} 1004 1005static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1006#endif 1007 1008/* nouveau_bios.c */ 1009extern int nouveau_bios_init(struct drm_device *); 1010extern void nouveau_bios_takedown(struct drm_device *dev); 1011extern int nouveau_run_vbios_init(struct drm_device *); 1012extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1013 struct dcb_entry *); 1014extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1015 enum dcb_gpio_tag); 1016extern struct dcb_connector_table_entry * 1017nouveau_bios_connector_entry(struct drm_device *, int index); 1018extern u32 get_pll_register(struct drm_device *, enum pll_types); 1019extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1020 struct pll_lims *); 1021extern int nouveau_bios_run_display_table(struct drm_device *, 1022 struct dcb_entry *, 1023 uint32_t script, int pxclk); 1024extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1025 int *length); 1026extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1027extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1028extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1029 bool *dl, bool *if_is_24bit); 1030extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1031 int head, int pxclk); 1032extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1033 enum LVDS_script, int pxclk); 1034 1035/* nouveau_ttm.c */ 1036int nouveau_ttm_global_init(struct drm_nouveau_private *); 1037void nouveau_ttm_global_release(struct drm_nouveau_private *); 1038int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1039 1040/* nouveau_dp.c */ 1041int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1042 uint8_t *data, int data_nr); 1043bool nouveau_dp_detect(struct drm_encoder *); 1044bool nouveau_dp_link_train(struct drm_encoder *); 1045 1046/* nv04_fb.c */ 1047extern int nv04_fb_init(struct drm_device *); 1048extern void nv04_fb_takedown(struct drm_device *); 1049 1050/* nv10_fb.c */ 1051extern int nv10_fb_init(struct drm_device *); 1052extern void nv10_fb_takedown(struct drm_device *); 1053extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1054 uint32_t addr, uint32_t size, 1055 uint32_t pitch, uint32_t flags); 1056extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1057extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1058 1059/* nv30_fb.c */ 1060extern int nv30_fb_init(struct drm_device *); 1061extern void nv30_fb_takedown(struct drm_device *); 1062extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1063 uint32_t addr, uint32_t size, 1064 uint32_t pitch, uint32_t flags); 1065extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1066 1067/* nv40_fb.c */ 1068extern int nv40_fb_init(struct drm_device *); 1069extern void nv40_fb_takedown(struct drm_device *); 1070extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1071 1072/* nv50_fb.c */ 1073extern int nv50_fb_init(struct drm_device *); 1074extern void nv50_fb_takedown(struct drm_device *); 1075extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1076 1077/* nvc0_fb.c */ 1078extern int nvc0_fb_init(struct drm_device *); 1079extern void nvc0_fb_takedown(struct drm_device *); 1080 1081/* nv04_fifo.c */ 1082extern int nv04_fifo_init(struct drm_device *); 1083extern void nv04_fifo_fini(struct drm_device *); 1084extern void nv04_fifo_disable(struct drm_device *); 1085extern void nv04_fifo_enable(struct drm_device *); 1086extern bool nv04_fifo_reassign(struct drm_device *, bool); 1087extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1088extern int nv04_fifo_channel_id(struct drm_device *); 1089extern int nv04_fifo_create_context(struct nouveau_channel *); 1090extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1091extern int nv04_fifo_load_context(struct nouveau_channel *); 1092extern int nv04_fifo_unload_context(struct drm_device *); 1093extern void nv04_fifo_isr(struct drm_device *); 1094 1095/* nv10_fifo.c */ 1096extern int nv10_fifo_init(struct drm_device *); 1097extern int nv10_fifo_channel_id(struct drm_device *); 1098extern int nv10_fifo_create_context(struct nouveau_channel *); 1099extern int nv10_fifo_load_context(struct nouveau_channel *); 1100extern int nv10_fifo_unload_context(struct drm_device *); 1101 1102/* nv40_fifo.c */ 1103extern int nv40_fifo_init(struct drm_device *); 1104extern int nv40_fifo_create_context(struct nouveau_channel *); 1105extern int nv40_fifo_load_context(struct nouveau_channel *); 1106extern int nv40_fifo_unload_context(struct drm_device *); 1107 1108/* nv50_fifo.c */ 1109extern int nv50_fifo_init(struct drm_device *); 1110extern void nv50_fifo_takedown(struct drm_device *); 1111extern int nv50_fifo_channel_id(struct drm_device *); 1112extern int nv50_fifo_create_context(struct nouveau_channel *); 1113extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1114extern int nv50_fifo_load_context(struct nouveau_channel *); 1115extern int nv50_fifo_unload_context(struct drm_device *); 1116extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1117 1118/* nvc0_fifo.c */ 1119extern int nvc0_fifo_init(struct drm_device *); 1120extern void nvc0_fifo_takedown(struct drm_device *); 1121extern void nvc0_fifo_disable(struct drm_device *); 1122extern void nvc0_fifo_enable(struct drm_device *); 1123extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1124extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1125extern int nvc0_fifo_channel_id(struct drm_device *); 1126extern int nvc0_fifo_create_context(struct nouveau_channel *); 1127extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1128extern int nvc0_fifo_load_context(struct nouveau_channel *); 1129extern int nvc0_fifo_unload_context(struct drm_device *); 1130 1131/* nv04_graph.c */ 1132extern int nv04_graph_init(struct drm_device *); 1133extern void nv04_graph_takedown(struct drm_device *); 1134extern void nv04_graph_fifo_access(struct drm_device *, bool); 1135extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1136extern int nv04_graph_create_context(struct nouveau_channel *); 1137extern void nv04_graph_destroy_context(struct nouveau_channel *); 1138extern int nv04_graph_load_context(struct nouveau_channel *); 1139extern int nv04_graph_unload_context(struct drm_device *); 1140extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1141 u32 class, u32 mthd, u32 data); 1142extern struct nouveau_bitfield nv04_graph_nsource[]; 1143 1144/* nv10_graph.c */ 1145extern int nv10_graph_init(struct drm_device *); 1146extern void nv10_graph_takedown(struct drm_device *); 1147extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1148extern int nv10_graph_create_context(struct nouveau_channel *); 1149extern void nv10_graph_destroy_context(struct nouveau_channel *); 1150extern int nv10_graph_load_context(struct nouveau_channel *); 1151extern int nv10_graph_unload_context(struct drm_device *); 1152extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1153extern struct nouveau_bitfield nv10_graph_intr[]; 1154extern struct nouveau_bitfield nv10_graph_nstatus[]; 1155 1156/* nv20_graph.c */ 1157extern int nv20_graph_create_context(struct nouveau_channel *); 1158extern void nv20_graph_destroy_context(struct nouveau_channel *); 1159extern int nv20_graph_load_context(struct nouveau_channel *); 1160extern int nv20_graph_unload_context(struct drm_device *); 1161extern int nv20_graph_init(struct drm_device *); 1162extern void nv20_graph_takedown(struct drm_device *); 1163extern int nv30_graph_init(struct drm_device *); 1164extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1165 1166/* nv40_graph.c */ 1167extern int nv40_graph_init(struct drm_device *); 1168extern void nv40_graph_takedown(struct drm_device *); 1169extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1170extern int nv40_graph_create_context(struct nouveau_channel *); 1171extern void nv40_graph_destroy_context(struct nouveau_channel *); 1172extern int nv40_graph_load_context(struct nouveau_channel *); 1173extern int nv40_graph_unload_context(struct drm_device *); 1174extern void nv40_grctx_init(struct nouveau_grctx *); 1175extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1176 1177/* nv50_graph.c */ 1178extern int nv50_graph_init(struct drm_device *); 1179extern void nv50_graph_takedown(struct drm_device *); 1180extern void nv50_graph_fifo_access(struct drm_device *, bool); 1181extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1182extern int nv50_graph_create_context(struct nouveau_channel *); 1183extern void nv50_graph_destroy_context(struct nouveau_channel *); 1184extern int nv50_graph_load_context(struct nouveau_channel *); 1185extern int nv50_graph_unload_context(struct drm_device *); 1186extern int nv50_grctx_init(struct nouveau_grctx *); 1187extern void nv50_graph_tlb_flush(struct drm_device *dev); 1188extern void nv86_graph_tlb_flush(struct drm_device *dev); 1189extern struct nouveau_enum nv50_data_error_names[]; 1190 1191/* nvc0_graph.c */ 1192extern int nvc0_graph_init(struct drm_device *); 1193extern void nvc0_graph_takedown(struct drm_device *); 1194extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1195extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1196extern int nvc0_graph_create_context(struct nouveau_channel *); 1197extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1198extern int nvc0_graph_load_context(struct nouveau_channel *); 1199extern int nvc0_graph_unload_context(struct drm_device *); 1200 1201/* nv84_crypt.c */ 1202extern int nv84_crypt_init(struct drm_device *dev); 1203extern void nv84_crypt_fini(struct drm_device *dev); 1204extern int nv84_crypt_create_context(struct nouveau_channel *); 1205extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1206extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1207 1208/* nv04_instmem.c */ 1209extern int nv04_instmem_init(struct drm_device *); 1210extern void nv04_instmem_takedown(struct drm_device *); 1211extern int nv04_instmem_suspend(struct drm_device *); 1212extern void nv04_instmem_resume(struct drm_device *); 1213extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1214extern void nv04_instmem_put(struct nouveau_gpuobj *); 1215extern int nv04_instmem_map(struct nouveau_gpuobj *); 1216extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1217extern void nv04_instmem_flush(struct drm_device *); 1218 1219/* nv50_instmem.c */ 1220extern int nv50_instmem_init(struct drm_device *); 1221extern void nv50_instmem_takedown(struct drm_device *); 1222extern int nv50_instmem_suspend(struct drm_device *); 1223extern void nv50_instmem_resume(struct drm_device *); 1224extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1225extern void nv50_instmem_put(struct nouveau_gpuobj *); 1226extern int nv50_instmem_map(struct nouveau_gpuobj *); 1227extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1228extern void nv50_instmem_flush(struct drm_device *); 1229extern void nv84_instmem_flush(struct drm_device *); 1230 1231/* nvc0_instmem.c */ 1232extern int nvc0_instmem_init(struct drm_device *); 1233extern void nvc0_instmem_takedown(struct drm_device *); 1234extern int nvc0_instmem_suspend(struct drm_device *); 1235extern void nvc0_instmem_resume(struct drm_device *); 1236 1237/* nv04_mc.c */ 1238extern int nv04_mc_init(struct drm_device *); 1239extern void nv04_mc_takedown(struct drm_device *); 1240 1241/* nv40_mc.c */ 1242extern int nv40_mc_init(struct drm_device *); 1243extern void nv40_mc_takedown(struct drm_device *); 1244 1245/* nv50_mc.c */ 1246extern int nv50_mc_init(struct drm_device *); 1247extern void nv50_mc_takedown(struct drm_device *); 1248 1249/* nv04_timer.c */ 1250extern int nv04_timer_init(struct drm_device *); 1251extern uint64_t nv04_timer_read(struct drm_device *); 1252extern void nv04_timer_takedown(struct drm_device *); 1253 1254extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1255 unsigned long arg); 1256 1257/* nv04_dac.c */ 1258extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1259extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1260extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1261extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1262extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1263 1264/* nv04_dfp.c */ 1265extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1266extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1267extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1268 int head, bool dl); 1269extern void nv04_dfp_disable(struct drm_device *dev, int head); 1270extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1271 1272/* nv04_tv.c */ 1273extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1274extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1275 1276/* nv17_tv.c */ 1277extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1278 1279/* nv04_display.c */ 1280extern int nv04_display_early_init(struct drm_device *); 1281extern void nv04_display_late_takedown(struct drm_device *); 1282extern int nv04_display_create(struct drm_device *); 1283extern int nv04_display_init(struct drm_device *); 1284extern void nv04_display_destroy(struct drm_device *); 1285 1286/* nv04_crtc.c */ 1287extern int nv04_crtc_create(struct drm_device *, int index); 1288 1289/* nouveau_bo.c */ 1290extern struct ttm_bo_driver nouveau_bo_driver; 1291extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1292 int size, int align, uint32_t flags, 1293 uint32_t tile_mode, uint32_t tile_flags, 1294 struct nouveau_bo **); 1295extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1296extern int nouveau_bo_unpin(struct nouveau_bo *); 1297extern int nouveau_bo_map(struct nouveau_bo *); 1298extern void nouveau_bo_unmap(struct nouveau_bo *); 1299extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1300 uint32_t busy); 1301extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1302extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1303extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1304extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1305extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1306extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1307 bool no_wait_reserve, bool no_wait_gpu); 1308 1309/* nouveau_fence.c */ 1310struct nouveau_fence; 1311extern int nouveau_fence_init(struct drm_device *); 1312extern void nouveau_fence_fini(struct drm_device *); 1313extern int nouveau_fence_channel_init(struct nouveau_channel *); 1314extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1315extern void nouveau_fence_update(struct nouveau_channel *); 1316extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1317 bool emit); 1318extern int nouveau_fence_emit(struct nouveau_fence *); 1319extern void nouveau_fence_work(struct nouveau_fence *fence, 1320 void (*work)(void *priv, bool signalled), 1321 void *priv); 1322struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1323 1324extern bool __nouveau_fence_signalled(void *obj, void *arg); 1325extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1326extern int __nouveau_fence_flush(void *obj, void *arg); 1327extern void __nouveau_fence_unref(void **obj); 1328extern void *__nouveau_fence_ref(void *obj); 1329 1330static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1331{ 1332 return __nouveau_fence_signalled(obj, NULL); 1333} 1334static inline int 1335nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1336{ 1337 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1338} 1339extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1340static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1341{ 1342 return __nouveau_fence_flush(obj, NULL); 1343} 1344static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1345{ 1346 __nouveau_fence_unref((void **)obj); 1347} 1348static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1349{ 1350 return __nouveau_fence_ref(obj); 1351} 1352 1353/* nouveau_gem.c */ 1354extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1355 int size, int align, uint32_t domain, 1356 uint32_t tile_mode, uint32_t tile_flags, 1357 struct nouveau_bo **); 1358extern int nouveau_gem_object_new(struct drm_gem_object *); 1359extern void nouveau_gem_object_del(struct drm_gem_object *); 1360extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1361 struct drm_file *); 1362extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1363 struct drm_file *); 1364extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1365 struct drm_file *); 1366extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1367 struct drm_file *); 1368extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1369 struct drm_file *); 1370 1371/* nouveau_display.c */ 1372int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1373void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1374int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1375 struct drm_pending_vblank_event *event); 1376int nouveau_finish_page_flip(struct nouveau_channel *, 1377 struct nouveau_page_flip_state *); 1378 1379/* nv10_gpio.c */ 1380int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1381int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1382 1383/* nv50_gpio.c */ 1384int nv50_gpio_init(struct drm_device *dev); 1385void nv50_gpio_fini(struct drm_device *dev); 1386int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1387int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1388int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1389 void (*)(void *, int), void *); 1390void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1391 void (*)(void *, int), void *); 1392bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1393 1394/* nv50_calc. */ 1395int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1396 int *N1, int *M1, int *N2, int *M2, int *P); 1397int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1398 int clk, int *N, int *fN, int *M, int *P); 1399 1400#ifndef ioread32_native 1401#ifdef __BIG_ENDIAN 1402#define ioread16_native ioread16be 1403#define iowrite16_native iowrite16be 1404#define ioread32_native ioread32be 1405#define iowrite32_native iowrite32be 1406#else /* def __BIG_ENDIAN */ 1407#define ioread16_native ioread16 1408#define iowrite16_native iowrite16 1409#define ioread32_native ioread32 1410#define iowrite32_native iowrite32 1411#endif /* def __BIG_ENDIAN else */ 1412#endif /* !ioread32_native */ 1413 1414/* channel control reg access */ 1415static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1416{ 1417 return ioread32_native(chan->user + reg); 1418} 1419 1420static inline void nvchan_wr32(struct nouveau_channel *chan, 1421 unsigned reg, u32 val) 1422{ 1423 iowrite32_native(val, chan->user + reg); 1424} 1425 1426/* register access */ 1427static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1428{ 1429 struct drm_nouveau_private *dev_priv = dev->dev_private; 1430 return ioread32_native(dev_priv->mmio + reg); 1431} 1432 1433static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1434{ 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 iowrite32_native(val, dev_priv->mmio + reg); 1437} 1438 1439static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1440{ 1441 u32 tmp = nv_rd32(dev, reg); 1442 nv_wr32(dev, reg, (tmp & ~mask) | val); 1443 return tmp; 1444} 1445 1446static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1447{ 1448 struct drm_nouveau_private *dev_priv = dev->dev_private; 1449 return ioread8(dev_priv->mmio + reg); 1450} 1451 1452static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1453{ 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 iowrite8(val, dev_priv->mmio + reg); 1456} 1457 1458#define nv_wait(dev, reg, mask, val) \ 1459 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1460#define nv_wait_ne(dev, reg, mask, val) \ 1461 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1462 1463/* PRAMIN access */ 1464static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1465{ 1466 struct drm_nouveau_private *dev_priv = dev->dev_private; 1467 return ioread32_native(dev_priv->ramin + offset); 1468} 1469 1470static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1471{ 1472 struct drm_nouveau_private *dev_priv = dev->dev_private; 1473 iowrite32_native(val, dev_priv->ramin + offset); 1474} 1475 1476/* object access */ 1477extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1478extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1479 1480/* 1481 * Logging 1482 * Argument d is (struct drm_device *). 1483 */ 1484#define NV_PRINTK(level, d, fmt, arg...) \ 1485 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1486 pci_name(d->pdev), ##arg) 1487#ifndef NV_DEBUG_NOTRACE 1488#define NV_DEBUG(d, fmt, arg...) do { \ 1489 if (drm_debug & DRM_UT_DRIVER) { \ 1490 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1491 __LINE__, ##arg); \ 1492 } \ 1493} while (0) 1494#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1495 if (drm_debug & DRM_UT_KMS) { \ 1496 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1497 __LINE__, ##arg); \ 1498 } \ 1499} while (0) 1500#else 1501#define NV_DEBUG(d, fmt, arg...) do { \ 1502 if (drm_debug & DRM_UT_DRIVER) \ 1503 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1504} while (0) 1505#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1506 if (drm_debug & DRM_UT_KMS) \ 1507 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1508} while (0) 1509#endif 1510#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1511#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1512#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1513#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1514#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1515 1516/* nouveau_reg_debug bitmask */ 1517enum { 1518 NOUVEAU_REG_DEBUG_MC = 0x1, 1519 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1520 NOUVEAU_REG_DEBUG_FB = 0x4, 1521 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1522 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1523 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1524 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1525 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1526 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1527 NOUVEAU_REG_DEBUG_EVO = 0x200, 1528}; 1529 1530#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1531 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1532 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1533} while (0) 1534 1535static inline bool 1536nv_two_heads(struct drm_device *dev) 1537{ 1538 struct drm_nouveau_private *dev_priv = dev->dev_private; 1539 const int impl = dev->pci_device & 0x0ff0; 1540 1541 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1542 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1543 return true; 1544 1545 return false; 1546} 1547 1548static inline bool 1549nv_gf4_disp_arch(struct drm_device *dev) 1550{ 1551 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1552} 1553 1554static inline bool 1555nv_two_reg_pll(struct drm_device *dev) 1556{ 1557 struct drm_nouveau_private *dev_priv = dev->dev_private; 1558 const int impl = dev->pci_device & 0x0ff0; 1559 1560 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1561 return true; 1562 return false; 1563} 1564 1565static inline bool 1566nv_match_device(struct drm_device *dev, unsigned device, 1567 unsigned sub_vendor, unsigned sub_device) 1568{ 1569 return dev->pdev->device == device && 1570 dev->pdev->subsystem_vendor == sub_vendor && 1571 dev->pdev->subsystem_device == sub_device; 1572} 1573 1574/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1575 * helpful to determine a number of other hardware features 1576 */ 1577static inline int 1578nv44_graph_class(struct drm_device *dev) 1579{ 1580 struct drm_nouveau_private *dev_priv = dev->dev_private; 1581 1582 if ((dev_priv->chipset & 0xf0) == 0x60) 1583 return 1; 1584 1585 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1586} 1587 1588/* memory type/access flags, do not match hardware values */ 1589#define NV_MEM_ACCESS_RO 1 1590#define NV_MEM_ACCESS_WO 2 1591#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1592#define NV_MEM_ACCESS_SYS 4 1593#define NV_MEM_ACCESS_VM 8 1594 1595#define NV_MEM_TARGET_VRAM 0 1596#define NV_MEM_TARGET_PCI 1 1597#define NV_MEM_TARGET_PCI_NOSNOOP 2 1598#define NV_MEM_TARGET_VM 3 1599#define NV_MEM_TARGET_GART 4 1600 1601#define NV_MEM_TYPE_VM 0x7f 1602#define NV_MEM_COMP_VM 0x03 1603 1604/* NV_SW object class */ 1605#define NV_SW 0x0000506e 1606#define NV_SW_DMA_SEMAPHORE 0x00000060 1607#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1608#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1609#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1610#define NV_SW_YIELD 0x00000080 1611#define NV_SW_DMA_VBLSEM 0x0000018c 1612#define NV_SW_VBLSEM_OFFSET 0x00000400 1613#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1614#define NV_SW_VBLSEM_RELEASE 0x00000408 1615#define NV_SW_PAGE_FLIP 0x00000500 1616 1617#endif /* __NOUVEAU_DRV_H__ */ 1618