nouveau_drv.h revision 7375c95b343aa575940704a38482a334ea87ac6c
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 struct list_head vma_list; 120 unsigned page_shift; 121 122 uint32_t tile_mode; 123 uint32_t tile_flags; 124 struct nouveau_tile_reg *tile; 125 126 struct drm_gem_object *gem; 127 int pin_refcnt; 128}; 129 130#define nouveau_bo_tile_layout(nvbo) \ 131 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 132 133static inline struct nouveau_bo * 134nouveau_bo(struct ttm_buffer_object *bo) 135{ 136 return container_of(bo, struct nouveau_bo, bo); 137} 138 139static inline struct nouveau_bo * 140nouveau_gem_object(struct drm_gem_object *gem) 141{ 142 return gem ? gem->driver_private : NULL; 143} 144 145/* TODO: submit equivalent to TTM generic API upstream? */ 146static inline void __iomem * 147nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 148{ 149 bool is_iomem; 150 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 151 &nvbo->kmap, &is_iomem); 152 WARN_ON_ONCE(ioptr && !is_iomem); 153 return ioptr; 154} 155 156enum nouveau_flags { 157 NV_NFORCE = 0x10000000, 158 NV_NFORCE2 = 0x20000000 159}; 160 161#define NVOBJ_ENGINE_SW 0 162#define NVOBJ_ENGINE_GR 1 163#define NVOBJ_ENGINE_CRYPT 2 164#define NVOBJ_ENGINE_COPY0 3 165#define NVOBJ_ENGINE_COPY1 4 166#define NVOBJ_ENGINE_MPEG 5 167#define NVOBJ_ENGINE_DISPLAY 15 168#define NVOBJ_ENGINE_NR 16 169 170#define NVOBJ_FLAG_DONT_MAP (1 << 0) 171#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 172#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 173#define NVOBJ_FLAG_VM (1 << 3) 174#define NVOBJ_FLAG_VM_USER (1 << 4) 175 176#define NVOBJ_CINST_GLOBAL 0xdeadbeef 177 178struct nouveau_gpuobj { 179 struct drm_device *dev; 180 struct kref refcount; 181 struct list_head list; 182 183 void *node; 184 u32 *suspend; 185 186 uint32_t flags; 187 188 u32 size; 189 u32 pinst; /* PRAMIN BAR offset */ 190 u32 cinst; /* Channel offset */ 191 u64 vinst; /* VRAM address */ 192 u64 linst; /* VM address */ 193 194 uint32_t engine; 195 uint32_t class; 196 197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 198 void *priv; 199}; 200 201struct nouveau_page_flip_state { 202 struct list_head head; 203 struct drm_pending_vblank_event *event; 204 int crtc, bpp, pitch, x, y; 205 uint64_t offset; 206}; 207 208enum nouveau_channel_mutex_class { 209 NOUVEAU_UCHANNEL_MUTEX, 210 NOUVEAU_KCHANNEL_MUTEX 211}; 212 213struct nouveau_channel { 214 struct drm_device *dev; 215 struct list_head list; 216 int id; 217 218 /* references to the channel data structure */ 219 struct kref ref; 220 /* users of the hardware channel resources, the hardware 221 * context will be kicked off when it reaches zero. */ 222 atomic_t users; 223 struct mutex mutex; 224 225 /* owner of this fifo */ 226 struct drm_file *file_priv; 227 /* mapping of the fifo itself */ 228 struct drm_local_map *map; 229 230 /* mapping of the regs controlling the fifo */ 231 void __iomem *user; 232 uint32_t user_get; 233 uint32_t user_put; 234 235 /* Fencing */ 236 struct { 237 /* lock protects the pending list only */ 238 spinlock_t lock; 239 struct list_head pending; 240 uint32_t sequence; 241 uint32_t sequence_ack; 242 atomic_t last_sequence_irq; 243 struct nouveau_vma vma; 244 } fence; 245 246 /* DMA push buffer */ 247 struct nouveau_gpuobj *pushbuf; 248 struct nouveau_bo *pushbuf_bo; 249 struct nouveau_vma pushbuf_vma; 250 uint32_t pushbuf_base; 251 252 /* Notifier memory */ 253 struct nouveau_bo *notifier_bo; 254 struct nouveau_vma notifier_vma; 255 struct drm_mm notifier_heap; 256 257 /* PFIFO context */ 258 struct nouveau_gpuobj *ramfc; 259 struct nouveau_gpuobj *cache; 260 void *fifo_priv; 261 262 /* Execution engine contexts */ 263 void *engctx[NVOBJ_ENGINE_NR]; 264 265 /* NV50 VM */ 266 struct nouveau_vm *vm; 267 struct nouveau_gpuobj *vm_pd; 268 269 /* Objects */ 270 struct nouveau_gpuobj *ramin; /* Private instmem */ 271 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 272 struct nouveau_ramht *ramht; /* Hash table */ 273 274 /* GPU object info for stuff used in-kernel (mm_enabled) */ 275 uint32_t m2mf_ntfy; 276 uint32_t vram_handle; 277 uint32_t gart_handle; 278 bool accel_done; 279 280 /* Push buffer state (only for drm's channel on !mm_enabled) */ 281 struct { 282 int max; 283 int free; 284 int cur; 285 int put; 286 /* access via pushbuf_bo */ 287 288 int ib_base; 289 int ib_max; 290 int ib_free; 291 int ib_put; 292 } dma; 293 294 uint32_t sw_subchannel[8]; 295 296 struct nouveau_vma dispc_vma[2]; 297 struct { 298 struct nouveau_gpuobj *vblsem; 299 uint32_t vblsem_head; 300 uint32_t vblsem_offset; 301 uint32_t vblsem_rval; 302 struct list_head vbl_wait; 303 struct list_head flip; 304 } nvsw; 305 306 struct { 307 bool active; 308 char name[32]; 309 struct drm_info_list info; 310 } debugfs; 311}; 312 313struct nouveau_exec_engine { 314 void (*destroy)(struct drm_device *, int engine); 315 int (*init)(struct drm_device *, int engine); 316 int (*fini)(struct drm_device *, int engine); 317 int (*context_new)(struct nouveau_channel *, int engine); 318 void (*context_del)(struct nouveau_channel *, int engine); 319 int (*object_new)(struct nouveau_channel *, int engine, 320 u32 handle, u16 class); 321 void (*set_tile_region)(struct drm_device *dev, int i); 322 void (*tlb_flush)(struct drm_device *, int engine); 323}; 324 325struct nouveau_instmem_engine { 326 void *priv; 327 328 int (*init)(struct drm_device *dev); 329 void (*takedown)(struct drm_device *dev); 330 int (*suspend)(struct drm_device *dev); 331 void (*resume)(struct drm_device *dev); 332 333 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 334 u32 size, u32 align); 335 void (*put)(struct nouveau_gpuobj *); 336 int (*map)(struct nouveau_gpuobj *); 337 void (*unmap)(struct nouveau_gpuobj *); 338 339 void (*flush)(struct drm_device *); 340}; 341 342struct nouveau_mc_engine { 343 int (*init)(struct drm_device *dev); 344 void (*takedown)(struct drm_device *dev); 345}; 346 347struct nouveau_timer_engine { 348 int (*init)(struct drm_device *dev); 349 void (*takedown)(struct drm_device *dev); 350 uint64_t (*read)(struct drm_device *dev); 351}; 352 353struct nouveau_fb_engine { 354 int num_tiles; 355 struct drm_mm tag_heap; 356 void *priv; 357 358 int (*init)(struct drm_device *dev); 359 void (*takedown)(struct drm_device *dev); 360 361 void (*init_tile_region)(struct drm_device *dev, int i, 362 uint32_t addr, uint32_t size, 363 uint32_t pitch, uint32_t flags); 364 void (*set_tile_region)(struct drm_device *dev, int i); 365 void (*free_tile_region)(struct drm_device *dev, int i); 366}; 367 368struct nouveau_fifo_engine { 369 void *priv; 370 int channels; 371 372 struct nouveau_gpuobj *playlist[2]; 373 int cur_playlist; 374 375 int (*init)(struct drm_device *); 376 void (*takedown)(struct drm_device *); 377 378 void (*disable)(struct drm_device *); 379 void (*enable)(struct drm_device *); 380 bool (*reassign)(struct drm_device *, bool enable); 381 bool (*cache_pull)(struct drm_device *dev, bool enable); 382 383 int (*channel_id)(struct drm_device *); 384 385 int (*create_context)(struct nouveau_channel *); 386 void (*destroy_context)(struct nouveau_channel *); 387 int (*load_context)(struct nouveau_channel *); 388 int (*unload_context)(struct drm_device *); 389 void (*tlb_flush)(struct drm_device *dev); 390}; 391 392struct nouveau_display_engine { 393 void *priv; 394 int (*early_init)(struct drm_device *); 395 void (*late_takedown)(struct drm_device *); 396 int (*create)(struct drm_device *); 397 int (*init)(struct drm_device *); 398 void (*destroy)(struct drm_device *); 399}; 400 401struct nouveau_gpio_engine { 402 void *priv; 403 404 int (*init)(struct drm_device *); 405 void (*takedown)(struct drm_device *); 406 407 int (*get)(struct drm_device *, enum dcb_gpio_tag); 408 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 409 410 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 411 void (*)(void *, int), void *); 412 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 413 void (*)(void *, int), void *); 414 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 415}; 416 417struct nouveau_pm_voltage_level { 418 u8 voltage; 419 u8 vid; 420}; 421 422struct nouveau_pm_voltage { 423 bool supported; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_100220; 433 u32 reg_100224; 434 u32 reg_100228; 435 u32 reg_10022c; 436 u32 reg_100230; 437 u32 reg_100234; 438 u32 reg_100238; 439 u32 reg_10023c; 440 u32 reg_100240; 441}; 442 443#define NOUVEAU_PM_MAX_LEVEL 8 444struct nouveau_pm_level { 445 struct device_attribute dev_attr; 446 char name[32]; 447 int id; 448 449 u32 core; 450 u32 memory; 451 u32 shader; 452 u32 unk05; 453 u32 unk0a; 454 455 u8 voltage; 456 u8 fanspeed; 457 458 u16 memscript; 459 struct nouveau_pm_memtiming *timing; 460}; 461 462struct nouveau_pm_temp_sensor_constants { 463 u16 offset_constant; 464 s16 offset_mult; 465 u16 offset_div; 466 u16 slope_mult; 467 u16 slope_div; 468}; 469 470struct nouveau_pm_threshold_temp { 471 s16 critical; 472 s16 down_clock; 473 s16 fan_boost; 474}; 475 476struct nouveau_pm_memtimings { 477 bool supported; 478 struct nouveau_pm_memtiming *timing; 479 int nr_timing; 480}; 481 482struct nouveau_pm_engine { 483 struct nouveau_pm_voltage voltage; 484 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 485 int nr_perflvl; 486 struct nouveau_pm_memtimings memtimings; 487 struct nouveau_pm_temp_sensor_constants sensor_constants; 488 struct nouveau_pm_threshold_temp threshold_temp; 489 490 struct nouveau_pm_level boot; 491 struct nouveau_pm_level *cur; 492 493 struct device *hwmon; 494 struct notifier_block acpi_nb; 495 496 int (*clock_get)(struct drm_device *, u32 id); 497 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 498 u32 id, int khz); 499 void (*clock_set)(struct drm_device *, void *); 500 int (*voltage_get)(struct drm_device *); 501 int (*voltage_set)(struct drm_device *, int voltage); 502 int (*fanspeed_get)(struct drm_device *); 503 int (*fanspeed_set)(struct drm_device *, int fanspeed); 504 int (*temp_get)(struct drm_device *); 505}; 506 507struct nouveau_vram_engine { 508 int (*init)(struct drm_device *); 509 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 510 u32 type, struct nouveau_mem **); 511 void (*put)(struct drm_device *, struct nouveau_mem **); 512 513 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 514}; 515 516struct nouveau_engine { 517 struct nouveau_instmem_engine instmem; 518 struct nouveau_mc_engine mc; 519 struct nouveau_timer_engine timer; 520 struct nouveau_fb_engine fb; 521 struct nouveau_fifo_engine fifo; 522 struct nouveau_display_engine display; 523 struct nouveau_gpio_engine gpio; 524 struct nouveau_pm_engine pm; 525 struct nouveau_vram_engine vram; 526}; 527 528struct nouveau_pll_vals { 529 union { 530 struct { 531#ifdef __BIG_ENDIAN 532 uint8_t N1, M1, N2, M2; 533#else 534 uint8_t M1, N1, M2, N2; 535#endif 536 }; 537 struct { 538 uint16_t NM1, NM2; 539 } __attribute__((packed)); 540 }; 541 int log2P; 542 543 int refclk; 544}; 545 546enum nv04_fp_display_regs { 547 FP_DISPLAY_END, 548 FP_TOTAL, 549 FP_CRTC, 550 FP_SYNC_START, 551 FP_SYNC_END, 552 FP_VALID_START, 553 FP_VALID_END 554}; 555 556struct nv04_crtc_reg { 557 unsigned char MiscOutReg; 558 uint8_t CRTC[0xa0]; 559 uint8_t CR58[0x10]; 560 uint8_t Sequencer[5]; 561 uint8_t Graphics[9]; 562 uint8_t Attribute[21]; 563 unsigned char DAC[768]; 564 565 /* PCRTC regs */ 566 uint32_t fb_start; 567 uint32_t crtc_cfg; 568 uint32_t cursor_cfg; 569 uint32_t gpio_ext; 570 uint32_t crtc_830; 571 uint32_t crtc_834; 572 uint32_t crtc_850; 573 uint32_t crtc_eng_ctrl; 574 575 /* PRAMDAC regs */ 576 uint32_t nv10_cursync; 577 struct nouveau_pll_vals pllvals; 578 uint32_t ramdac_gen_ctrl; 579 uint32_t ramdac_630; 580 uint32_t ramdac_634; 581 uint32_t tv_setup; 582 uint32_t tv_vtotal; 583 uint32_t tv_vskew; 584 uint32_t tv_vsync_delay; 585 uint32_t tv_htotal; 586 uint32_t tv_hskew; 587 uint32_t tv_hsync_delay; 588 uint32_t tv_hsync_delay2; 589 uint32_t fp_horiz_regs[7]; 590 uint32_t fp_vert_regs[7]; 591 uint32_t dither; 592 uint32_t fp_control; 593 uint32_t dither_regs[6]; 594 uint32_t fp_debug_0; 595 uint32_t fp_debug_1; 596 uint32_t fp_debug_2; 597 uint32_t fp_margin_color; 598 uint32_t ramdac_8c0; 599 uint32_t ramdac_a20; 600 uint32_t ramdac_a24; 601 uint32_t ramdac_a34; 602 uint32_t ctv_regs[38]; 603}; 604 605struct nv04_output_reg { 606 uint32_t output; 607 int head; 608}; 609 610struct nv04_mode_state { 611 struct nv04_crtc_reg crtc_reg[2]; 612 uint32_t pllsel; 613 uint32_t sel_clk; 614}; 615 616enum nouveau_card_type { 617 NV_04 = 0x00, 618 NV_10 = 0x10, 619 NV_20 = 0x20, 620 NV_30 = 0x30, 621 NV_40 = 0x40, 622 NV_50 = 0x50, 623 NV_C0 = 0xc0, 624}; 625 626struct drm_nouveau_private { 627 struct drm_device *dev; 628 bool noaccel; 629 630 /* the card type, takes NV_* as values */ 631 enum nouveau_card_type card_type; 632 /* exact chipset, derived from NV_PMC_BOOT_0 */ 633 int chipset; 634 int stepping; 635 int flags; 636 637 void __iomem *mmio; 638 639 spinlock_t ramin_lock; 640 void __iomem *ramin; 641 u32 ramin_size; 642 u32 ramin_base; 643 bool ramin_available; 644 struct drm_mm ramin_heap; 645 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 646 struct list_head gpuobj_list; 647 struct list_head classes; 648 649 struct nouveau_bo *vga_ram; 650 651 /* interrupt handling */ 652 void (*irq_handler[32])(struct drm_device *); 653 bool msi_enabled; 654 655 struct list_head vbl_waiting; 656 657 struct { 658 struct drm_global_reference mem_global_ref; 659 struct ttm_bo_global_ref bo_global_ref; 660 struct ttm_bo_device bdev; 661 atomic_t validate_sequence; 662 } ttm; 663 664 struct { 665 spinlock_t lock; 666 struct drm_mm heap; 667 struct nouveau_bo *bo; 668 } fence; 669 670 struct { 671 spinlock_t lock; 672 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 673 } channels; 674 675 struct nouveau_engine engine; 676 struct nouveau_channel *channel; 677 678 /* For PFIFO and PGRAPH. */ 679 spinlock_t context_switch_lock; 680 681 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 682 spinlock_t vm_lock; 683 684 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 685 struct nouveau_ramht *ramht; 686 struct nouveau_gpuobj *ramfc; 687 struct nouveau_gpuobj *ramro; 688 689 uint32_t ramin_rsvd_vram; 690 691 struct { 692 enum { 693 NOUVEAU_GART_NONE = 0, 694 NOUVEAU_GART_AGP, /* AGP */ 695 NOUVEAU_GART_PDMA, /* paged dma object */ 696 NOUVEAU_GART_HW /* on-chip gart/vm */ 697 } type; 698 uint64_t aper_base; 699 uint64_t aper_size; 700 uint64_t aper_free; 701 702 struct ttm_backend_func *func; 703 704 struct { 705 struct page *page; 706 dma_addr_t addr; 707 } dummy; 708 709 struct nouveau_gpuobj *sg_ctxdma; 710 } gart_info; 711 712 /* nv10-nv40 tiling regions */ 713 struct { 714 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 715 spinlock_t lock; 716 } tile; 717 718 /* VRAM/fb configuration */ 719 uint64_t vram_size; 720 uint64_t vram_sys_base; 721 u32 vram_rblock_size; 722 723 uint64_t fb_phys; 724 uint64_t fb_available_size; 725 uint64_t fb_mappable_pages; 726 uint64_t fb_aper_free; 727 int fb_mtrr; 728 729 /* BAR control (NV50-) */ 730 struct nouveau_vm *bar1_vm; 731 struct nouveau_vm *bar3_vm; 732 733 /* G8x/G9x virtual address space */ 734 struct nouveau_vm *chan_vm; 735 736 struct nvbios vbios; 737 738 struct nv04_mode_state mode_reg; 739 struct nv04_mode_state saved_reg; 740 uint32_t saved_vga_font[4][16384]; 741 uint32_t crtc_owner; 742 uint32_t dac_users[4]; 743 744 struct backlight_device *backlight; 745 746 struct { 747 struct dentry *channel_root; 748 } debugfs; 749 750 struct nouveau_fbdev *nfbdev; 751 struct apertures_struct *apertures; 752}; 753 754static inline struct drm_nouveau_private * 755nouveau_private(struct drm_device *dev) 756{ 757 return dev->dev_private; 758} 759 760static inline struct drm_nouveau_private * 761nouveau_bdev(struct ttm_bo_device *bd) 762{ 763 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 764} 765 766static inline int 767nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 768{ 769 struct nouveau_bo *prev; 770 771 if (!pnvbo) 772 return -EINVAL; 773 prev = *pnvbo; 774 775 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 776 if (prev) { 777 struct ttm_buffer_object *bo = &prev->bo; 778 779 ttm_bo_unref(&bo); 780 } 781 782 return 0; 783} 784 785/* nouveau_drv.c */ 786extern int nouveau_agpmode; 787extern int nouveau_duallink; 788extern int nouveau_uscript_lvds; 789extern int nouveau_uscript_tmds; 790extern int nouveau_vram_pushbuf; 791extern int nouveau_vram_notify; 792extern int nouveau_fbpercrtc; 793extern int nouveau_tv_disable; 794extern char *nouveau_tv_norm; 795extern int nouveau_reg_debug; 796extern char *nouveau_vbios; 797extern int nouveau_ignorelid; 798extern int nouveau_nofbaccel; 799extern int nouveau_noaccel; 800extern int nouveau_force_post; 801extern int nouveau_override_conntype; 802extern char *nouveau_perflvl; 803extern int nouveau_perflvl_wr; 804extern int nouveau_msi; 805extern int nouveau_ctxfw; 806 807extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 808extern int nouveau_pci_resume(struct pci_dev *pdev); 809 810/* nouveau_state.c */ 811extern int nouveau_open(struct drm_device *, struct drm_file *); 812extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 813extern void nouveau_postclose(struct drm_device *, struct drm_file *); 814extern int nouveau_load(struct drm_device *, unsigned long flags); 815extern int nouveau_firstopen(struct drm_device *); 816extern void nouveau_lastclose(struct drm_device *); 817extern int nouveau_unload(struct drm_device *); 818extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 819 struct drm_file *); 820extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 821 struct drm_file *); 822extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 823 uint32_t reg, uint32_t mask, uint32_t val); 824extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 825 uint32_t reg, uint32_t mask, uint32_t val); 826extern bool nouveau_wait_for_idle(struct drm_device *); 827extern int nouveau_card_init(struct drm_device *); 828 829/* nouveau_mem.c */ 830extern int nouveau_mem_vram_init(struct drm_device *); 831extern void nouveau_mem_vram_fini(struct drm_device *); 832extern int nouveau_mem_gart_init(struct drm_device *); 833extern void nouveau_mem_gart_fini(struct drm_device *); 834extern int nouveau_mem_init_agp(struct drm_device *); 835extern int nouveau_mem_reset_agp(struct drm_device *); 836extern void nouveau_mem_close(struct drm_device *); 837extern int nouveau_mem_detect(struct drm_device *); 838extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 839extern struct nouveau_tile_reg *nv10_mem_set_tiling( 840 struct drm_device *dev, uint32_t addr, uint32_t size, 841 uint32_t pitch, uint32_t flags); 842extern void nv10_mem_put_tile_region(struct drm_device *dev, 843 struct nouveau_tile_reg *tile, 844 struct nouveau_fence *fence); 845extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 846extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 847 848/* nouveau_notifier.c */ 849extern int nouveau_notifier_init_channel(struct nouveau_channel *); 850extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 851extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 852 int cout, uint32_t start, uint32_t end, 853 uint32_t *offset); 854extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 855extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 856 struct drm_file *); 857extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 858 struct drm_file *); 859 860/* nouveau_channel.c */ 861extern struct drm_ioctl_desc nouveau_ioctls[]; 862extern int nouveau_max_ioctl; 863extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 864extern int nouveau_channel_alloc(struct drm_device *dev, 865 struct nouveau_channel **chan, 866 struct drm_file *file_priv, 867 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 868extern struct nouveau_channel * 869nouveau_channel_get_unlocked(struct nouveau_channel *); 870extern struct nouveau_channel * 871nouveau_channel_get(struct drm_file *, int id); 872extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 873extern void nouveau_channel_put(struct nouveau_channel **); 874extern void nouveau_channel_ref(struct nouveau_channel *chan, 875 struct nouveau_channel **pchan); 876extern void nouveau_channel_idle(struct nouveau_channel *chan); 877 878/* nouveau_object.c */ 879#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 880 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 881 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 882} while (0) 883 884#define NVOBJ_ENGINE_DEL(d, e) do { \ 885 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 886 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 887} while (0) 888 889#define NVOBJ_CLASS(d, c, e) do { \ 890 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 891 if (ret) \ 892 return ret; \ 893} while (0) 894 895#define NVOBJ_MTHD(d, c, m, e) do { \ 896 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 897 if (ret) \ 898 return ret; \ 899} while (0) 900 901extern int nouveau_gpuobj_early_init(struct drm_device *); 902extern int nouveau_gpuobj_init(struct drm_device *); 903extern void nouveau_gpuobj_takedown(struct drm_device *); 904extern int nouveau_gpuobj_suspend(struct drm_device *dev); 905extern void nouveau_gpuobj_resume(struct drm_device *dev); 906extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 907extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 908 int (*exec)(struct nouveau_channel *, 909 u32 class, u32 mthd, u32 data)); 910extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 911extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 912extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 913 uint32_t vram_h, uint32_t tt_h); 914extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 915extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 916 uint32_t size, int align, uint32_t flags, 917 struct nouveau_gpuobj **); 918extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 919 struct nouveau_gpuobj **); 920extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 921 u32 size, u32 flags, 922 struct nouveau_gpuobj **); 923extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 924 uint64_t offset, uint64_t size, int access, 925 int target, struct nouveau_gpuobj **); 926extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 927extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 928 u64 size, int target, int access, u32 type, 929 u32 comp, struct nouveau_gpuobj **pobj); 930extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 931 int class, u64 base, u64 size, int target, 932 int access, u32 type, u32 comp); 933extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 934 struct drm_file *); 935extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 936 struct drm_file *); 937 938/* nouveau_irq.c */ 939extern int nouveau_irq_init(struct drm_device *); 940extern void nouveau_irq_fini(struct drm_device *); 941extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 942extern void nouveau_irq_register(struct drm_device *, int status_bit, 943 void (*)(struct drm_device *)); 944extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 945extern void nouveau_irq_preinstall(struct drm_device *); 946extern int nouveau_irq_postinstall(struct drm_device *); 947extern void nouveau_irq_uninstall(struct drm_device *); 948 949/* nouveau_sgdma.c */ 950extern int nouveau_sgdma_init(struct drm_device *); 951extern void nouveau_sgdma_takedown(struct drm_device *); 952extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 953 uint32_t offset); 954extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 955 956/* nouveau_debugfs.c */ 957#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 958extern int nouveau_debugfs_init(struct drm_minor *); 959extern void nouveau_debugfs_takedown(struct drm_minor *); 960extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 961extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 962#else 963static inline int 964nouveau_debugfs_init(struct drm_minor *minor) 965{ 966 return 0; 967} 968 969static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 970{ 971} 972 973static inline int 974nouveau_debugfs_channel_init(struct nouveau_channel *chan) 975{ 976 return 0; 977} 978 979static inline void 980nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 981{ 982} 983#endif 984 985/* nouveau_dma.c */ 986extern void nouveau_dma_pre_init(struct nouveau_channel *); 987extern int nouveau_dma_init(struct nouveau_channel *); 988extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 989 990/* nouveau_acpi.c */ 991#define ROM_BIOS_PAGE 4096 992#if defined(CONFIG_ACPI) 993void nouveau_register_dsm_handler(void); 994void nouveau_unregister_dsm_handler(void); 995int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 996bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 997int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 998#else 999static inline void nouveau_register_dsm_handler(void) {} 1000static inline void nouveau_unregister_dsm_handler(void) {} 1001static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1002static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1003static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1004#endif 1005 1006/* nouveau_backlight.c */ 1007#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1008extern int nouveau_backlight_init(struct drm_connector *); 1009extern void nouveau_backlight_exit(struct drm_connector *); 1010#else 1011static inline int nouveau_backlight_init(struct drm_connector *dev) 1012{ 1013 return 0; 1014} 1015 1016static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1017#endif 1018 1019/* nouveau_bios.c */ 1020extern int nouveau_bios_init(struct drm_device *); 1021extern void nouveau_bios_takedown(struct drm_device *dev); 1022extern int nouveau_run_vbios_init(struct drm_device *); 1023extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1024 struct dcb_entry *); 1025extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1026 enum dcb_gpio_tag); 1027extern struct dcb_connector_table_entry * 1028nouveau_bios_connector_entry(struct drm_device *, int index); 1029extern u32 get_pll_register(struct drm_device *, enum pll_types); 1030extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1031 struct pll_lims *); 1032extern int nouveau_bios_run_display_table(struct drm_device *, 1033 struct dcb_entry *, 1034 uint32_t script, int pxclk); 1035extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1036 int *length); 1037extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1038extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1039extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1040 bool *dl, bool *if_is_24bit); 1041extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1042 int head, int pxclk); 1043extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1044 enum LVDS_script, int pxclk); 1045 1046/* nouveau_ttm.c */ 1047int nouveau_ttm_global_init(struct drm_nouveau_private *); 1048void nouveau_ttm_global_release(struct drm_nouveau_private *); 1049int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1050 1051/* nouveau_dp.c */ 1052int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1053 uint8_t *data, int data_nr); 1054bool nouveau_dp_detect(struct drm_encoder *); 1055bool nouveau_dp_link_train(struct drm_encoder *); 1056 1057/* nv04_fb.c */ 1058extern int nv04_fb_init(struct drm_device *); 1059extern void nv04_fb_takedown(struct drm_device *); 1060 1061/* nv10_fb.c */ 1062extern int nv10_fb_init(struct drm_device *); 1063extern void nv10_fb_takedown(struct drm_device *); 1064extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1065 uint32_t addr, uint32_t size, 1066 uint32_t pitch, uint32_t flags); 1067extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1068extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1069 1070/* nv30_fb.c */ 1071extern int nv30_fb_init(struct drm_device *); 1072extern void nv30_fb_takedown(struct drm_device *); 1073extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1074 uint32_t addr, uint32_t size, 1075 uint32_t pitch, uint32_t flags); 1076extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1077 1078/* nv40_fb.c */ 1079extern int nv40_fb_init(struct drm_device *); 1080extern void nv40_fb_takedown(struct drm_device *); 1081extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1082 1083/* nv50_fb.c */ 1084extern int nv50_fb_init(struct drm_device *); 1085extern void nv50_fb_takedown(struct drm_device *); 1086extern void nv50_fb_vm_trap(struct drm_device *, int display); 1087 1088/* nvc0_fb.c */ 1089extern int nvc0_fb_init(struct drm_device *); 1090extern void nvc0_fb_takedown(struct drm_device *); 1091 1092/* nv04_fifo.c */ 1093extern int nv04_fifo_init(struct drm_device *); 1094extern void nv04_fifo_fini(struct drm_device *); 1095extern void nv04_fifo_disable(struct drm_device *); 1096extern void nv04_fifo_enable(struct drm_device *); 1097extern bool nv04_fifo_reassign(struct drm_device *, bool); 1098extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1099extern int nv04_fifo_channel_id(struct drm_device *); 1100extern int nv04_fifo_create_context(struct nouveau_channel *); 1101extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1102extern int nv04_fifo_load_context(struct nouveau_channel *); 1103extern int nv04_fifo_unload_context(struct drm_device *); 1104extern void nv04_fifo_isr(struct drm_device *); 1105 1106/* nv10_fifo.c */ 1107extern int nv10_fifo_init(struct drm_device *); 1108extern int nv10_fifo_channel_id(struct drm_device *); 1109extern int nv10_fifo_create_context(struct nouveau_channel *); 1110extern int nv10_fifo_load_context(struct nouveau_channel *); 1111extern int nv10_fifo_unload_context(struct drm_device *); 1112 1113/* nv40_fifo.c */ 1114extern int nv40_fifo_init(struct drm_device *); 1115extern int nv40_fifo_create_context(struct nouveau_channel *); 1116extern int nv40_fifo_load_context(struct nouveau_channel *); 1117extern int nv40_fifo_unload_context(struct drm_device *); 1118 1119/* nv50_fifo.c */ 1120extern int nv50_fifo_init(struct drm_device *); 1121extern void nv50_fifo_takedown(struct drm_device *); 1122extern int nv50_fifo_channel_id(struct drm_device *); 1123extern int nv50_fifo_create_context(struct nouveau_channel *); 1124extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1125extern int nv50_fifo_load_context(struct nouveau_channel *); 1126extern int nv50_fifo_unload_context(struct drm_device *); 1127extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1128 1129/* nvc0_fifo.c */ 1130extern int nvc0_fifo_init(struct drm_device *); 1131extern void nvc0_fifo_takedown(struct drm_device *); 1132extern void nvc0_fifo_disable(struct drm_device *); 1133extern void nvc0_fifo_enable(struct drm_device *); 1134extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1135extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1136extern int nvc0_fifo_channel_id(struct drm_device *); 1137extern int nvc0_fifo_create_context(struct nouveau_channel *); 1138extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1139extern int nvc0_fifo_load_context(struct nouveau_channel *); 1140extern int nvc0_fifo_unload_context(struct drm_device *); 1141 1142/* nv04_graph.c */ 1143extern int nv04_graph_create(struct drm_device *); 1144extern void nv04_graph_fifo_access(struct drm_device *, bool); 1145extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1146extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1147 u32 class, u32 mthd, u32 data); 1148extern struct nouveau_bitfield nv04_graph_nsource[]; 1149 1150/* nv10_graph.c */ 1151extern int nv10_graph_create(struct drm_device *); 1152extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1153extern struct nouveau_bitfield nv10_graph_intr[]; 1154extern struct nouveau_bitfield nv10_graph_nstatus[]; 1155 1156/* nv20_graph.c */ 1157extern int nv20_graph_create(struct drm_device *); 1158 1159/* nv40_graph.c */ 1160extern int nv40_graph_create(struct drm_device *); 1161extern void nv40_grctx_init(struct nouveau_grctx *); 1162 1163/* nv50_graph.c */ 1164extern int nv50_graph_create(struct drm_device *); 1165extern int nv50_grctx_init(struct nouveau_grctx *); 1166extern struct nouveau_enum nv50_data_error_names[]; 1167extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1168 1169/* nvc0_graph.c */ 1170extern int nvc0_graph_create(struct drm_device *); 1171extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1172 1173/* nv84_crypt.c */ 1174extern int nv84_crypt_create(struct drm_device *); 1175 1176/* nva3_copy.c */ 1177extern int nva3_copy_create(struct drm_device *dev); 1178 1179/* nvc0_copy.c */ 1180extern int nvc0_copy_create(struct drm_device *dev, int engine); 1181 1182/* nv40_mpeg.c */ 1183extern int nv40_mpeg_create(struct drm_device *dev); 1184 1185/* nv50_mpeg.c */ 1186extern int nv50_mpeg_create(struct drm_device *dev); 1187 1188/* nv04_instmem.c */ 1189extern int nv04_instmem_init(struct drm_device *); 1190extern void nv04_instmem_takedown(struct drm_device *); 1191extern int nv04_instmem_suspend(struct drm_device *); 1192extern void nv04_instmem_resume(struct drm_device *); 1193extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1194 u32 size, u32 align); 1195extern void nv04_instmem_put(struct nouveau_gpuobj *); 1196extern int nv04_instmem_map(struct nouveau_gpuobj *); 1197extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1198extern void nv04_instmem_flush(struct drm_device *); 1199 1200/* nv50_instmem.c */ 1201extern int nv50_instmem_init(struct drm_device *); 1202extern void nv50_instmem_takedown(struct drm_device *); 1203extern int nv50_instmem_suspend(struct drm_device *); 1204extern void nv50_instmem_resume(struct drm_device *); 1205extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1206 u32 size, u32 align); 1207extern void nv50_instmem_put(struct nouveau_gpuobj *); 1208extern int nv50_instmem_map(struct nouveau_gpuobj *); 1209extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1210extern void nv50_instmem_flush(struct drm_device *); 1211extern void nv84_instmem_flush(struct drm_device *); 1212 1213/* nvc0_instmem.c */ 1214extern int nvc0_instmem_init(struct drm_device *); 1215extern void nvc0_instmem_takedown(struct drm_device *); 1216extern int nvc0_instmem_suspend(struct drm_device *); 1217extern void nvc0_instmem_resume(struct drm_device *); 1218 1219/* nv04_mc.c */ 1220extern int nv04_mc_init(struct drm_device *); 1221extern void nv04_mc_takedown(struct drm_device *); 1222 1223/* nv40_mc.c */ 1224extern int nv40_mc_init(struct drm_device *); 1225extern void nv40_mc_takedown(struct drm_device *); 1226 1227/* nv50_mc.c */ 1228extern int nv50_mc_init(struct drm_device *); 1229extern void nv50_mc_takedown(struct drm_device *); 1230 1231/* nv04_timer.c */ 1232extern int nv04_timer_init(struct drm_device *); 1233extern uint64_t nv04_timer_read(struct drm_device *); 1234extern void nv04_timer_takedown(struct drm_device *); 1235 1236extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1237 unsigned long arg); 1238 1239/* nv04_dac.c */ 1240extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1241extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1242extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1243extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1244extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1245 1246/* nv04_dfp.c */ 1247extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1248extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1249extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1250 int head, bool dl); 1251extern void nv04_dfp_disable(struct drm_device *dev, int head); 1252extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1253 1254/* nv04_tv.c */ 1255extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1256extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1257 1258/* nv17_tv.c */ 1259extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1260 1261/* nv04_display.c */ 1262extern int nv04_display_early_init(struct drm_device *); 1263extern void nv04_display_late_takedown(struct drm_device *); 1264extern int nv04_display_create(struct drm_device *); 1265extern int nv04_display_init(struct drm_device *); 1266extern void nv04_display_destroy(struct drm_device *); 1267 1268/* nv04_crtc.c */ 1269extern int nv04_crtc_create(struct drm_device *, int index); 1270 1271/* nouveau_bo.c */ 1272extern struct ttm_bo_driver nouveau_bo_driver; 1273extern int nouveau_bo_new(struct drm_device *, int size, int align, 1274 uint32_t flags, uint32_t tile_mode, 1275 uint32_t tile_flags, struct nouveau_bo **); 1276extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1277extern int nouveau_bo_unpin(struct nouveau_bo *); 1278extern int nouveau_bo_map(struct nouveau_bo *); 1279extern void nouveau_bo_unmap(struct nouveau_bo *); 1280extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1281 uint32_t busy); 1282extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1283extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1284extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1285extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1286extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1287extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1288 bool no_wait_reserve, bool no_wait_gpu); 1289 1290extern struct nouveau_vma * 1291nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1292extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1293 struct nouveau_vma *); 1294extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1295 1296/* nouveau_fence.c */ 1297struct nouveau_fence; 1298extern int nouveau_fence_init(struct drm_device *); 1299extern void nouveau_fence_fini(struct drm_device *); 1300extern int nouveau_fence_channel_init(struct nouveau_channel *); 1301extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1302extern void nouveau_fence_update(struct nouveau_channel *); 1303extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1304 bool emit); 1305extern int nouveau_fence_emit(struct nouveau_fence *); 1306extern void nouveau_fence_work(struct nouveau_fence *fence, 1307 void (*work)(void *priv, bool signalled), 1308 void *priv); 1309struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1310 1311extern bool __nouveau_fence_signalled(void *obj, void *arg); 1312extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1313extern int __nouveau_fence_flush(void *obj, void *arg); 1314extern void __nouveau_fence_unref(void **obj); 1315extern void *__nouveau_fence_ref(void *obj); 1316 1317static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1318{ 1319 return __nouveau_fence_signalled(obj, NULL); 1320} 1321static inline int 1322nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1323{ 1324 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1325} 1326extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1327static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1328{ 1329 return __nouveau_fence_flush(obj, NULL); 1330} 1331static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1332{ 1333 __nouveau_fence_unref((void **)obj); 1334} 1335static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1336{ 1337 return __nouveau_fence_ref(obj); 1338} 1339 1340/* nouveau_gem.c */ 1341extern int nouveau_gem_new(struct drm_device *, int size, int align, 1342 uint32_t domain, uint32_t tile_mode, 1343 uint32_t tile_flags, struct nouveau_bo **); 1344extern int nouveau_gem_object_new(struct drm_gem_object *); 1345extern void nouveau_gem_object_del(struct drm_gem_object *); 1346extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1347extern void nouveau_gem_object_close(struct drm_gem_object *, 1348 struct drm_file *); 1349extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1350 struct drm_file *); 1351extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1352 struct drm_file *); 1353extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1354 struct drm_file *); 1355extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1356 struct drm_file *); 1357extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1358 struct drm_file *); 1359 1360/* nouveau_display.c */ 1361int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1362void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1363int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1364 struct drm_pending_vblank_event *event); 1365int nouveau_finish_page_flip(struct nouveau_channel *, 1366 struct nouveau_page_flip_state *); 1367 1368/* nv10_gpio.c */ 1369int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1370int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1371 1372/* nv50_gpio.c */ 1373int nv50_gpio_init(struct drm_device *dev); 1374void nv50_gpio_fini(struct drm_device *dev); 1375int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1376int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1377int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1378 void (*)(void *, int), void *); 1379void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1380 void (*)(void *, int), void *); 1381bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1382 1383/* nv50_calc. */ 1384int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1385 int *N1, int *M1, int *N2, int *M2, int *P); 1386int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1387 int clk, int *N, int *fN, int *M, int *P); 1388 1389#ifndef ioread32_native 1390#ifdef __BIG_ENDIAN 1391#define ioread16_native ioread16be 1392#define iowrite16_native iowrite16be 1393#define ioread32_native ioread32be 1394#define iowrite32_native iowrite32be 1395#else /* def __BIG_ENDIAN */ 1396#define ioread16_native ioread16 1397#define iowrite16_native iowrite16 1398#define ioread32_native ioread32 1399#define iowrite32_native iowrite32 1400#endif /* def __BIG_ENDIAN else */ 1401#endif /* !ioread32_native */ 1402 1403/* channel control reg access */ 1404static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1405{ 1406 return ioread32_native(chan->user + reg); 1407} 1408 1409static inline void nvchan_wr32(struct nouveau_channel *chan, 1410 unsigned reg, u32 val) 1411{ 1412 iowrite32_native(val, chan->user + reg); 1413} 1414 1415/* register access */ 1416static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1417{ 1418 struct drm_nouveau_private *dev_priv = dev->dev_private; 1419 return ioread32_native(dev_priv->mmio + reg); 1420} 1421 1422static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1423{ 1424 struct drm_nouveau_private *dev_priv = dev->dev_private; 1425 iowrite32_native(val, dev_priv->mmio + reg); 1426} 1427 1428static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1429{ 1430 u32 tmp = nv_rd32(dev, reg); 1431 nv_wr32(dev, reg, (tmp & ~mask) | val); 1432 return tmp; 1433} 1434 1435static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1436{ 1437 struct drm_nouveau_private *dev_priv = dev->dev_private; 1438 return ioread8(dev_priv->mmio + reg); 1439} 1440 1441static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1442{ 1443 struct drm_nouveau_private *dev_priv = dev->dev_private; 1444 iowrite8(val, dev_priv->mmio + reg); 1445} 1446 1447#define nv_wait(dev, reg, mask, val) \ 1448 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1449#define nv_wait_ne(dev, reg, mask, val) \ 1450 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1451 1452/* PRAMIN access */ 1453static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1454{ 1455 struct drm_nouveau_private *dev_priv = dev->dev_private; 1456 return ioread32_native(dev_priv->ramin + offset); 1457} 1458 1459static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1460{ 1461 struct drm_nouveau_private *dev_priv = dev->dev_private; 1462 iowrite32_native(val, dev_priv->ramin + offset); 1463} 1464 1465/* object access */ 1466extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1467extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1468 1469/* 1470 * Logging 1471 * Argument d is (struct drm_device *). 1472 */ 1473#define NV_PRINTK(level, d, fmt, arg...) \ 1474 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1475 pci_name(d->pdev), ##arg) 1476#ifndef NV_DEBUG_NOTRACE 1477#define NV_DEBUG(d, fmt, arg...) do { \ 1478 if (drm_debug & DRM_UT_DRIVER) { \ 1479 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1480 __LINE__, ##arg); \ 1481 } \ 1482} while (0) 1483#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1484 if (drm_debug & DRM_UT_KMS) { \ 1485 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1486 __LINE__, ##arg); \ 1487 } \ 1488} while (0) 1489#else 1490#define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) \ 1492 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1493} while (0) 1494#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1495 if (drm_debug & DRM_UT_KMS) \ 1496 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1497} while (0) 1498#endif 1499#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1500#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1501#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1502#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1503#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1504 1505/* nouveau_reg_debug bitmask */ 1506enum { 1507 NOUVEAU_REG_DEBUG_MC = 0x1, 1508 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1509 NOUVEAU_REG_DEBUG_FB = 0x4, 1510 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1511 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1512 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1513 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1514 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1515 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1516 NOUVEAU_REG_DEBUG_EVO = 0x200, 1517}; 1518 1519#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1520 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1521 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1522} while (0) 1523 1524static inline bool 1525nv_two_heads(struct drm_device *dev) 1526{ 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 const int impl = dev->pci_device & 0x0ff0; 1529 1530 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1531 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1532 return true; 1533 1534 return false; 1535} 1536 1537static inline bool 1538nv_gf4_disp_arch(struct drm_device *dev) 1539{ 1540 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1541} 1542 1543static inline bool 1544nv_two_reg_pll(struct drm_device *dev) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 const int impl = dev->pci_device & 0x0ff0; 1548 1549 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1550 return true; 1551 return false; 1552} 1553 1554static inline bool 1555nv_match_device(struct drm_device *dev, unsigned device, 1556 unsigned sub_vendor, unsigned sub_device) 1557{ 1558 return dev->pdev->device == device && 1559 dev->pdev->subsystem_vendor == sub_vendor && 1560 dev->pdev->subsystem_device == sub_device; 1561} 1562 1563static inline void * 1564nv_engine(struct drm_device *dev, int engine) 1565{ 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 return (void *)dev_priv->eng[engine]; 1568} 1569 1570/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1571 * helpful to determine a number of other hardware features 1572 */ 1573static inline int 1574nv44_graph_class(struct drm_device *dev) 1575{ 1576 struct drm_nouveau_private *dev_priv = dev->dev_private; 1577 1578 if ((dev_priv->chipset & 0xf0) == 0x60) 1579 return 1; 1580 1581 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1582} 1583 1584/* memory type/access flags, do not match hardware values */ 1585#define NV_MEM_ACCESS_RO 1 1586#define NV_MEM_ACCESS_WO 2 1587#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1588#define NV_MEM_ACCESS_SYS 4 1589#define NV_MEM_ACCESS_VM 8 1590 1591#define NV_MEM_TARGET_VRAM 0 1592#define NV_MEM_TARGET_PCI 1 1593#define NV_MEM_TARGET_PCI_NOSNOOP 2 1594#define NV_MEM_TARGET_VM 3 1595#define NV_MEM_TARGET_GART 4 1596 1597#define NV_MEM_TYPE_VM 0x7f 1598#define NV_MEM_COMP_VM 0x03 1599 1600/* NV_SW object class */ 1601#define NV_SW 0x0000506e 1602#define NV_SW_DMA_SEMAPHORE 0x00000060 1603#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1604#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1605#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1606#define NV_SW_YIELD 0x00000080 1607#define NV_SW_DMA_VBLSEM 0x0000018c 1608#define NV_SW_VBLSEM_OFFSET 0x00000400 1609#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1610#define NV_SW_VBLSEM_RELEASE 0x00000408 1611#define NV_SW_PAGE_FLIP 0x00000500 1612 1613#endif /* __NOUVEAU_DRV_H__ */ 1614