nouveau_drv.h revision 77e7da6814623927cc4435d992bef9c84075594c
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_100220; 433 u32 reg_100224; 434 u32 reg_100228; 435 u32 reg_10022c; 436 u32 reg_100230; 437 u32 reg_100234; 438 u32 reg_100238; 439 u32 reg_10023c; 440 u32 reg_100240; 441}; 442 443#define NOUVEAU_PM_MAX_LEVEL 8 444struct nouveau_pm_level { 445 struct device_attribute dev_attr; 446 char name[32]; 447 int id; 448 449 u32 core; 450 u32 memory; 451 u32 shader; 452 u32 unk05; 453 u32 unk0a; 454 455 u32 volt_min; /* microvolts */ 456 u32 volt_max; 457 u8 fanspeed; 458 459 u16 memscript; 460 struct nouveau_pm_memtiming *timing; 461}; 462 463struct nouveau_pm_temp_sensor_constants { 464 u16 offset_constant; 465 s16 offset_mult; 466 s16 offset_div; 467 s16 slope_mult; 468 s16 slope_div; 469}; 470 471struct nouveau_pm_threshold_temp { 472 s16 critical; 473 s16 down_clock; 474 s16 fan_boost; 475}; 476 477struct nouveau_pm_memtimings { 478 bool supported; 479 struct nouveau_pm_memtiming *timing; 480 int nr_timing; 481}; 482 483struct nouveau_pm_engine { 484 struct nouveau_pm_voltage voltage; 485 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 486 int nr_perflvl; 487 struct nouveau_pm_memtimings memtimings; 488 struct nouveau_pm_temp_sensor_constants sensor_constants; 489 struct nouveau_pm_threshold_temp threshold_temp; 490 491 struct nouveau_pm_level boot; 492 struct nouveau_pm_level *cur; 493 494 struct device *hwmon; 495 struct notifier_block acpi_nb; 496 497 int (*clock_get)(struct drm_device *, u32 id); 498 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 499 u32 id, int khz); 500 void (*clock_set)(struct drm_device *, void *); 501 502 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 503 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 504 void (*clocks_set)(struct drm_device *, void *); 505 506 int (*voltage_get)(struct drm_device *); 507 int (*voltage_set)(struct drm_device *, int voltage); 508 int (*fanspeed_get)(struct drm_device *); 509 int (*fanspeed_set)(struct drm_device *, int fanspeed); 510 int (*temp_get)(struct drm_device *); 511}; 512 513struct nouveau_vram_engine { 514 struct nouveau_mm *mm; 515 516 int (*init)(struct drm_device *); 517 void (*takedown)(struct drm_device *dev); 518 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 519 u32 type, struct nouveau_mem **); 520 void (*put)(struct drm_device *, struct nouveau_mem **); 521 522 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 523}; 524 525struct nouveau_engine { 526 struct nouveau_instmem_engine instmem; 527 struct nouveau_mc_engine mc; 528 struct nouveau_timer_engine timer; 529 struct nouveau_fb_engine fb; 530 struct nouveau_fifo_engine fifo; 531 struct nouveau_display_engine display; 532 struct nouveau_gpio_engine gpio; 533 struct nouveau_pm_engine pm; 534 struct nouveau_vram_engine vram; 535}; 536 537struct nouveau_pll_vals { 538 union { 539 struct { 540#ifdef __BIG_ENDIAN 541 uint8_t N1, M1, N2, M2; 542#else 543 uint8_t M1, N1, M2, N2; 544#endif 545 }; 546 struct { 547 uint16_t NM1, NM2; 548 } __attribute__((packed)); 549 }; 550 int log2P; 551 552 int refclk; 553}; 554 555enum nv04_fp_display_regs { 556 FP_DISPLAY_END, 557 FP_TOTAL, 558 FP_CRTC, 559 FP_SYNC_START, 560 FP_SYNC_END, 561 FP_VALID_START, 562 FP_VALID_END 563}; 564 565struct nv04_crtc_reg { 566 unsigned char MiscOutReg; 567 uint8_t CRTC[0xa0]; 568 uint8_t CR58[0x10]; 569 uint8_t Sequencer[5]; 570 uint8_t Graphics[9]; 571 uint8_t Attribute[21]; 572 unsigned char DAC[768]; 573 574 /* PCRTC regs */ 575 uint32_t fb_start; 576 uint32_t crtc_cfg; 577 uint32_t cursor_cfg; 578 uint32_t gpio_ext; 579 uint32_t crtc_830; 580 uint32_t crtc_834; 581 uint32_t crtc_850; 582 uint32_t crtc_eng_ctrl; 583 584 /* PRAMDAC regs */ 585 uint32_t nv10_cursync; 586 struct nouveau_pll_vals pllvals; 587 uint32_t ramdac_gen_ctrl; 588 uint32_t ramdac_630; 589 uint32_t ramdac_634; 590 uint32_t tv_setup; 591 uint32_t tv_vtotal; 592 uint32_t tv_vskew; 593 uint32_t tv_vsync_delay; 594 uint32_t tv_htotal; 595 uint32_t tv_hskew; 596 uint32_t tv_hsync_delay; 597 uint32_t tv_hsync_delay2; 598 uint32_t fp_horiz_regs[7]; 599 uint32_t fp_vert_regs[7]; 600 uint32_t dither; 601 uint32_t fp_control; 602 uint32_t dither_regs[6]; 603 uint32_t fp_debug_0; 604 uint32_t fp_debug_1; 605 uint32_t fp_debug_2; 606 uint32_t fp_margin_color; 607 uint32_t ramdac_8c0; 608 uint32_t ramdac_a20; 609 uint32_t ramdac_a24; 610 uint32_t ramdac_a34; 611 uint32_t ctv_regs[38]; 612}; 613 614struct nv04_output_reg { 615 uint32_t output; 616 int head; 617}; 618 619struct nv04_mode_state { 620 struct nv04_crtc_reg crtc_reg[2]; 621 uint32_t pllsel; 622 uint32_t sel_clk; 623}; 624 625enum nouveau_card_type { 626 NV_04 = 0x00, 627 NV_10 = 0x10, 628 NV_20 = 0x20, 629 NV_30 = 0x30, 630 NV_40 = 0x40, 631 NV_50 = 0x50, 632 NV_C0 = 0xc0, 633}; 634 635struct drm_nouveau_private { 636 struct drm_device *dev; 637 bool noaccel; 638 639 /* the card type, takes NV_* as values */ 640 enum nouveau_card_type card_type; 641 /* exact chipset, derived from NV_PMC_BOOT_0 */ 642 int chipset; 643 int stepping; 644 int flags; 645 646 void __iomem *mmio; 647 648 spinlock_t ramin_lock; 649 void __iomem *ramin; 650 u32 ramin_size; 651 u32 ramin_base; 652 bool ramin_available; 653 struct drm_mm ramin_heap; 654 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 655 struct list_head gpuobj_list; 656 struct list_head classes; 657 658 struct nouveau_bo *vga_ram; 659 660 /* interrupt handling */ 661 void (*irq_handler[32])(struct drm_device *); 662 bool msi_enabled; 663 664 struct list_head vbl_waiting; 665 666 struct { 667 struct drm_global_reference mem_global_ref; 668 struct ttm_bo_global_ref bo_global_ref; 669 struct ttm_bo_device bdev; 670 atomic_t validate_sequence; 671 } ttm; 672 673 struct { 674 spinlock_t lock; 675 struct drm_mm heap; 676 struct nouveau_bo *bo; 677 } fence; 678 679 struct { 680 spinlock_t lock; 681 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 682 } channels; 683 684 struct nouveau_engine engine; 685 struct nouveau_channel *channel; 686 687 /* For PFIFO and PGRAPH. */ 688 spinlock_t context_switch_lock; 689 690 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 691 spinlock_t vm_lock; 692 693 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 694 struct nouveau_ramht *ramht; 695 struct nouveau_gpuobj *ramfc; 696 struct nouveau_gpuobj *ramro; 697 698 uint32_t ramin_rsvd_vram; 699 700 struct { 701 enum { 702 NOUVEAU_GART_NONE = 0, 703 NOUVEAU_GART_AGP, /* AGP */ 704 NOUVEAU_GART_PDMA, /* paged dma object */ 705 NOUVEAU_GART_HW /* on-chip gart/vm */ 706 } type; 707 uint64_t aper_base; 708 uint64_t aper_size; 709 uint64_t aper_free; 710 711 struct ttm_backend_func *func; 712 713 struct { 714 struct page *page; 715 dma_addr_t addr; 716 } dummy; 717 718 struct nouveau_gpuobj *sg_ctxdma; 719 } gart_info; 720 721 /* nv10-nv40 tiling regions */ 722 struct { 723 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 724 spinlock_t lock; 725 } tile; 726 727 /* VRAM/fb configuration */ 728 uint64_t vram_size; 729 uint64_t vram_sys_base; 730 731 uint64_t fb_phys; 732 uint64_t fb_available_size; 733 uint64_t fb_mappable_pages; 734 uint64_t fb_aper_free; 735 int fb_mtrr; 736 737 /* BAR control (NV50-) */ 738 struct nouveau_vm *bar1_vm; 739 struct nouveau_vm *bar3_vm; 740 741 /* G8x/G9x virtual address space */ 742 struct nouveau_vm *chan_vm; 743 744 struct nvbios vbios; 745 746 struct nv04_mode_state mode_reg; 747 struct nv04_mode_state saved_reg; 748 uint32_t saved_vga_font[4][16384]; 749 uint32_t crtc_owner; 750 uint32_t dac_users[4]; 751 752 struct backlight_device *backlight; 753 754 struct { 755 struct dentry *channel_root; 756 } debugfs; 757 758 struct nouveau_fbdev *nfbdev; 759 struct apertures_struct *apertures; 760}; 761 762static inline struct drm_nouveau_private * 763nouveau_private(struct drm_device *dev) 764{ 765 return dev->dev_private; 766} 767 768static inline struct drm_nouveau_private * 769nouveau_bdev(struct ttm_bo_device *bd) 770{ 771 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 772} 773 774static inline int 775nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 776{ 777 struct nouveau_bo *prev; 778 779 if (!pnvbo) 780 return -EINVAL; 781 prev = *pnvbo; 782 783 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 784 if (prev) { 785 struct ttm_buffer_object *bo = &prev->bo; 786 787 ttm_bo_unref(&bo); 788 } 789 790 return 0; 791} 792 793/* nouveau_drv.c */ 794extern int nouveau_agpmode; 795extern int nouveau_duallink; 796extern int nouveau_uscript_lvds; 797extern int nouveau_uscript_tmds; 798extern int nouveau_vram_pushbuf; 799extern int nouveau_vram_notify; 800extern int nouveau_fbpercrtc; 801extern int nouveau_tv_disable; 802extern char *nouveau_tv_norm; 803extern int nouveau_reg_debug; 804extern char *nouveau_vbios; 805extern int nouveau_ignorelid; 806extern int nouveau_nofbaccel; 807extern int nouveau_noaccel; 808extern int nouveau_force_post; 809extern int nouveau_override_conntype; 810extern char *nouveau_perflvl; 811extern int nouveau_perflvl_wr; 812extern int nouveau_msi; 813extern int nouveau_ctxfw; 814 815extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 816extern int nouveau_pci_resume(struct pci_dev *pdev); 817 818/* nouveau_state.c */ 819extern int nouveau_open(struct drm_device *, struct drm_file *); 820extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 821extern void nouveau_postclose(struct drm_device *, struct drm_file *); 822extern int nouveau_load(struct drm_device *, unsigned long flags); 823extern int nouveau_firstopen(struct drm_device *); 824extern void nouveau_lastclose(struct drm_device *); 825extern int nouveau_unload(struct drm_device *); 826extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 827 struct drm_file *); 828extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 829 struct drm_file *); 830extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 831 uint32_t reg, uint32_t mask, uint32_t val); 832extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 833 uint32_t reg, uint32_t mask, uint32_t val); 834extern bool nouveau_wait_for_idle(struct drm_device *); 835extern int nouveau_card_init(struct drm_device *); 836 837/* nouveau_mem.c */ 838extern int nouveau_mem_vram_init(struct drm_device *); 839extern void nouveau_mem_vram_fini(struct drm_device *); 840extern int nouveau_mem_gart_init(struct drm_device *); 841extern void nouveau_mem_gart_fini(struct drm_device *); 842extern int nouveau_mem_init_agp(struct drm_device *); 843extern int nouveau_mem_reset_agp(struct drm_device *); 844extern void nouveau_mem_close(struct drm_device *); 845extern int nouveau_mem_detect(struct drm_device *); 846extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 847extern struct nouveau_tile_reg *nv10_mem_set_tiling( 848 struct drm_device *dev, uint32_t addr, uint32_t size, 849 uint32_t pitch, uint32_t flags); 850extern void nv10_mem_put_tile_region(struct drm_device *dev, 851 struct nouveau_tile_reg *tile, 852 struct nouveau_fence *fence); 853extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 854extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 855 856/* nouveau_notifier.c */ 857extern int nouveau_notifier_init_channel(struct nouveau_channel *); 858extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 859extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 860 int cout, uint32_t start, uint32_t end, 861 uint32_t *offset); 862extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 863extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 864 struct drm_file *); 865extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 866 struct drm_file *); 867 868/* nouveau_channel.c */ 869extern struct drm_ioctl_desc nouveau_ioctls[]; 870extern int nouveau_max_ioctl; 871extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 872extern int nouveau_channel_alloc(struct drm_device *dev, 873 struct nouveau_channel **chan, 874 struct drm_file *file_priv, 875 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 876extern struct nouveau_channel * 877nouveau_channel_get_unlocked(struct nouveau_channel *); 878extern struct nouveau_channel * 879nouveau_channel_get(struct drm_file *, int id); 880extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 881extern void nouveau_channel_put(struct nouveau_channel **); 882extern void nouveau_channel_ref(struct nouveau_channel *chan, 883 struct nouveau_channel **pchan); 884extern void nouveau_channel_idle(struct nouveau_channel *chan); 885 886/* nouveau_object.c */ 887#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 888 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 889 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 890} while (0) 891 892#define NVOBJ_ENGINE_DEL(d, e) do { \ 893 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 894 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 895} while (0) 896 897#define NVOBJ_CLASS(d, c, e) do { \ 898 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 899 if (ret) \ 900 return ret; \ 901} while (0) 902 903#define NVOBJ_MTHD(d, c, m, e) do { \ 904 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 905 if (ret) \ 906 return ret; \ 907} while (0) 908 909extern int nouveau_gpuobj_early_init(struct drm_device *); 910extern int nouveau_gpuobj_init(struct drm_device *); 911extern void nouveau_gpuobj_takedown(struct drm_device *); 912extern int nouveau_gpuobj_suspend(struct drm_device *dev); 913extern void nouveau_gpuobj_resume(struct drm_device *dev); 914extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 915extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 916 int (*exec)(struct nouveau_channel *, 917 u32 class, u32 mthd, u32 data)); 918extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 919extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 920extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 921 uint32_t vram_h, uint32_t tt_h); 922extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 923extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 924 uint32_t size, int align, uint32_t flags, 925 struct nouveau_gpuobj **); 926extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 927 struct nouveau_gpuobj **); 928extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 929 u32 size, u32 flags, 930 struct nouveau_gpuobj **); 931extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 932 uint64_t offset, uint64_t size, int access, 933 int target, struct nouveau_gpuobj **); 934extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 935extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 936 u64 size, int target, int access, u32 type, 937 u32 comp, struct nouveau_gpuobj **pobj); 938extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 939 int class, u64 base, u64 size, int target, 940 int access, u32 type, u32 comp); 941extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 942 struct drm_file *); 943extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 944 struct drm_file *); 945 946/* nouveau_irq.c */ 947extern int nouveau_irq_init(struct drm_device *); 948extern void nouveau_irq_fini(struct drm_device *); 949extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 950extern void nouveau_irq_register(struct drm_device *, int status_bit, 951 void (*)(struct drm_device *)); 952extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 953extern void nouveau_irq_preinstall(struct drm_device *); 954extern int nouveau_irq_postinstall(struct drm_device *); 955extern void nouveau_irq_uninstall(struct drm_device *); 956 957/* nouveau_sgdma.c */ 958extern int nouveau_sgdma_init(struct drm_device *); 959extern void nouveau_sgdma_takedown(struct drm_device *); 960extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 961 uint32_t offset); 962extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 963 964/* nouveau_debugfs.c */ 965#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 966extern int nouveau_debugfs_init(struct drm_minor *); 967extern void nouveau_debugfs_takedown(struct drm_minor *); 968extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 969extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 970#else 971static inline int 972nouveau_debugfs_init(struct drm_minor *minor) 973{ 974 return 0; 975} 976 977static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 978{ 979} 980 981static inline int 982nouveau_debugfs_channel_init(struct nouveau_channel *chan) 983{ 984 return 0; 985} 986 987static inline void 988nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 989{ 990} 991#endif 992 993/* nouveau_dma.c */ 994extern void nouveau_dma_pre_init(struct nouveau_channel *); 995extern int nouveau_dma_init(struct nouveau_channel *); 996extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 997 998/* nouveau_acpi.c */ 999#define ROM_BIOS_PAGE 4096 1000#if defined(CONFIG_ACPI) 1001void nouveau_register_dsm_handler(void); 1002void nouveau_unregister_dsm_handler(void); 1003int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1004bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1005int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1006#else 1007static inline void nouveau_register_dsm_handler(void) {} 1008static inline void nouveau_unregister_dsm_handler(void) {} 1009static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1010static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1011static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1012#endif 1013 1014/* nouveau_backlight.c */ 1015#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1016extern int nouveau_backlight_init(struct drm_connector *); 1017extern void nouveau_backlight_exit(struct drm_connector *); 1018#else 1019static inline int nouveau_backlight_init(struct drm_connector *dev) 1020{ 1021 return 0; 1022} 1023 1024static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1025#endif 1026 1027/* nouveau_bios.c */ 1028extern int nouveau_bios_init(struct drm_device *); 1029extern void nouveau_bios_takedown(struct drm_device *dev); 1030extern int nouveau_run_vbios_init(struct drm_device *); 1031extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1032 struct dcb_entry *); 1033extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1034 enum dcb_gpio_tag); 1035extern struct dcb_connector_table_entry * 1036nouveau_bios_connector_entry(struct drm_device *, int index); 1037extern u32 get_pll_register(struct drm_device *, enum pll_types); 1038extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1039 struct pll_lims *); 1040extern int nouveau_bios_run_display_table(struct drm_device *, 1041 struct dcb_entry *, 1042 uint32_t script, int pxclk); 1043extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1044 int *length); 1045extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1046extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1047extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1048 bool *dl, bool *if_is_24bit); 1049extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1050 int head, int pxclk); 1051extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1052 enum LVDS_script, int pxclk); 1053 1054/* nouveau_ttm.c */ 1055int nouveau_ttm_global_init(struct drm_nouveau_private *); 1056void nouveau_ttm_global_release(struct drm_nouveau_private *); 1057int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1058 1059/* nouveau_dp.c */ 1060int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1061 uint8_t *data, int data_nr); 1062bool nouveau_dp_detect(struct drm_encoder *); 1063bool nouveau_dp_link_train(struct drm_encoder *); 1064 1065/* nv04_fb.c */ 1066extern int nv04_fb_init(struct drm_device *); 1067extern void nv04_fb_takedown(struct drm_device *); 1068 1069/* nv10_fb.c */ 1070extern int nv10_fb_init(struct drm_device *); 1071extern void nv10_fb_takedown(struct drm_device *); 1072extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1073 uint32_t addr, uint32_t size, 1074 uint32_t pitch, uint32_t flags); 1075extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1076extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1077 1078/* nv30_fb.c */ 1079extern int nv30_fb_init(struct drm_device *); 1080extern void nv30_fb_takedown(struct drm_device *); 1081extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1082 uint32_t addr, uint32_t size, 1083 uint32_t pitch, uint32_t flags); 1084extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1085 1086/* nv40_fb.c */ 1087extern int nv40_fb_init(struct drm_device *); 1088extern void nv40_fb_takedown(struct drm_device *); 1089extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1090 1091/* nv50_fb.c */ 1092extern int nv50_fb_init(struct drm_device *); 1093extern void nv50_fb_takedown(struct drm_device *); 1094extern void nv50_fb_vm_trap(struct drm_device *, int display); 1095 1096/* nvc0_fb.c */ 1097extern int nvc0_fb_init(struct drm_device *); 1098extern void nvc0_fb_takedown(struct drm_device *); 1099 1100/* nv04_fifo.c */ 1101extern int nv04_fifo_init(struct drm_device *); 1102extern void nv04_fifo_fini(struct drm_device *); 1103extern void nv04_fifo_disable(struct drm_device *); 1104extern void nv04_fifo_enable(struct drm_device *); 1105extern bool nv04_fifo_reassign(struct drm_device *, bool); 1106extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1107extern int nv04_fifo_channel_id(struct drm_device *); 1108extern int nv04_fifo_create_context(struct nouveau_channel *); 1109extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1110extern int nv04_fifo_load_context(struct nouveau_channel *); 1111extern int nv04_fifo_unload_context(struct drm_device *); 1112extern void nv04_fifo_isr(struct drm_device *); 1113 1114/* nv10_fifo.c */ 1115extern int nv10_fifo_init(struct drm_device *); 1116extern int nv10_fifo_channel_id(struct drm_device *); 1117extern int nv10_fifo_create_context(struct nouveau_channel *); 1118extern int nv10_fifo_load_context(struct nouveau_channel *); 1119extern int nv10_fifo_unload_context(struct drm_device *); 1120 1121/* nv40_fifo.c */ 1122extern int nv40_fifo_init(struct drm_device *); 1123extern int nv40_fifo_create_context(struct nouveau_channel *); 1124extern int nv40_fifo_load_context(struct nouveau_channel *); 1125extern int nv40_fifo_unload_context(struct drm_device *); 1126 1127/* nv50_fifo.c */ 1128extern int nv50_fifo_init(struct drm_device *); 1129extern void nv50_fifo_takedown(struct drm_device *); 1130extern int nv50_fifo_channel_id(struct drm_device *); 1131extern int nv50_fifo_create_context(struct nouveau_channel *); 1132extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1133extern int nv50_fifo_load_context(struct nouveau_channel *); 1134extern int nv50_fifo_unload_context(struct drm_device *); 1135extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1136 1137/* nvc0_fifo.c */ 1138extern int nvc0_fifo_init(struct drm_device *); 1139extern void nvc0_fifo_takedown(struct drm_device *); 1140extern void nvc0_fifo_disable(struct drm_device *); 1141extern void nvc0_fifo_enable(struct drm_device *); 1142extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1143extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1144extern int nvc0_fifo_channel_id(struct drm_device *); 1145extern int nvc0_fifo_create_context(struct nouveau_channel *); 1146extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1147extern int nvc0_fifo_load_context(struct nouveau_channel *); 1148extern int nvc0_fifo_unload_context(struct drm_device *); 1149 1150/* nv04_graph.c */ 1151extern int nv04_graph_create(struct drm_device *); 1152extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1153extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1154 u32 class, u32 mthd, u32 data); 1155extern struct nouveau_bitfield nv04_graph_nsource[]; 1156 1157/* nv10_graph.c */ 1158extern int nv10_graph_create(struct drm_device *); 1159extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1160extern struct nouveau_bitfield nv10_graph_intr[]; 1161extern struct nouveau_bitfield nv10_graph_nstatus[]; 1162 1163/* nv20_graph.c */ 1164extern int nv20_graph_create(struct drm_device *); 1165 1166/* nv40_graph.c */ 1167extern int nv40_graph_create(struct drm_device *); 1168extern void nv40_grctx_init(struct nouveau_grctx *); 1169 1170/* nv50_graph.c */ 1171extern int nv50_graph_create(struct drm_device *); 1172extern int nv50_grctx_init(struct nouveau_grctx *); 1173extern struct nouveau_enum nv50_data_error_names[]; 1174extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1175 1176/* nvc0_graph.c */ 1177extern int nvc0_graph_create(struct drm_device *); 1178extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1179 1180/* nv84_crypt.c */ 1181extern int nv84_crypt_create(struct drm_device *); 1182 1183/* nva3_copy.c */ 1184extern int nva3_copy_create(struct drm_device *dev); 1185 1186/* nvc0_copy.c */ 1187extern int nvc0_copy_create(struct drm_device *dev, int engine); 1188 1189/* nv40_mpeg.c */ 1190extern int nv40_mpeg_create(struct drm_device *dev); 1191 1192/* nv50_mpeg.c */ 1193extern int nv50_mpeg_create(struct drm_device *dev); 1194 1195/* nv04_instmem.c */ 1196extern int nv04_instmem_init(struct drm_device *); 1197extern void nv04_instmem_takedown(struct drm_device *); 1198extern int nv04_instmem_suspend(struct drm_device *); 1199extern void nv04_instmem_resume(struct drm_device *); 1200extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1201 u32 size, u32 align); 1202extern void nv04_instmem_put(struct nouveau_gpuobj *); 1203extern int nv04_instmem_map(struct nouveau_gpuobj *); 1204extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1205extern void nv04_instmem_flush(struct drm_device *); 1206 1207/* nv50_instmem.c */ 1208extern int nv50_instmem_init(struct drm_device *); 1209extern void nv50_instmem_takedown(struct drm_device *); 1210extern int nv50_instmem_suspend(struct drm_device *); 1211extern void nv50_instmem_resume(struct drm_device *); 1212extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1213 u32 size, u32 align); 1214extern void nv50_instmem_put(struct nouveau_gpuobj *); 1215extern int nv50_instmem_map(struct nouveau_gpuobj *); 1216extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1217extern void nv50_instmem_flush(struct drm_device *); 1218extern void nv84_instmem_flush(struct drm_device *); 1219 1220/* nvc0_instmem.c */ 1221extern int nvc0_instmem_init(struct drm_device *); 1222extern void nvc0_instmem_takedown(struct drm_device *); 1223extern int nvc0_instmem_suspend(struct drm_device *); 1224extern void nvc0_instmem_resume(struct drm_device *); 1225 1226/* nv04_mc.c */ 1227extern int nv04_mc_init(struct drm_device *); 1228extern void nv04_mc_takedown(struct drm_device *); 1229 1230/* nv40_mc.c */ 1231extern int nv40_mc_init(struct drm_device *); 1232extern void nv40_mc_takedown(struct drm_device *); 1233 1234/* nv50_mc.c */ 1235extern int nv50_mc_init(struct drm_device *); 1236extern void nv50_mc_takedown(struct drm_device *); 1237 1238/* nv04_timer.c */ 1239extern int nv04_timer_init(struct drm_device *); 1240extern uint64_t nv04_timer_read(struct drm_device *); 1241extern void nv04_timer_takedown(struct drm_device *); 1242 1243extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1244 unsigned long arg); 1245 1246/* nv04_dac.c */ 1247extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1248extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1249extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1250extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1251extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1252 1253/* nv04_dfp.c */ 1254extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1255extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1256extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1257 int head, bool dl); 1258extern void nv04_dfp_disable(struct drm_device *dev, int head); 1259extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1260 1261/* nv04_tv.c */ 1262extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1263extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1264 1265/* nv17_tv.c */ 1266extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1267 1268/* nv04_display.c */ 1269extern int nv04_display_early_init(struct drm_device *); 1270extern void nv04_display_late_takedown(struct drm_device *); 1271extern int nv04_display_create(struct drm_device *); 1272extern int nv04_display_init(struct drm_device *); 1273extern void nv04_display_destroy(struct drm_device *); 1274 1275/* nv04_crtc.c */ 1276extern int nv04_crtc_create(struct drm_device *, int index); 1277 1278/* nouveau_bo.c */ 1279extern struct ttm_bo_driver nouveau_bo_driver; 1280extern int nouveau_bo_new(struct drm_device *, int size, int align, 1281 uint32_t flags, uint32_t tile_mode, 1282 uint32_t tile_flags, struct nouveau_bo **); 1283extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1284extern int nouveau_bo_unpin(struct nouveau_bo *); 1285extern int nouveau_bo_map(struct nouveau_bo *); 1286extern void nouveau_bo_unmap(struct nouveau_bo *); 1287extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1288 uint32_t busy); 1289extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1290extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1291extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1292extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1293extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1294extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1295 bool no_wait_reserve, bool no_wait_gpu); 1296 1297extern struct nouveau_vma * 1298nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1299extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1300 struct nouveau_vma *); 1301extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1302 1303/* nouveau_fence.c */ 1304struct nouveau_fence; 1305extern int nouveau_fence_init(struct drm_device *); 1306extern void nouveau_fence_fini(struct drm_device *); 1307extern int nouveau_fence_channel_init(struct nouveau_channel *); 1308extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1309extern void nouveau_fence_update(struct nouveau_channel *); 1310extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1311 bool emit); 1312extern int nouveau_fence_emit(struct nouveau_fence *); 1313extern void nouveau_fence_work(struct nouveau_fence *fence, 1314 void (*work)(void *priv, bool signalled), 1315 void *priv); 1316struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1317 1318extern bool __nouveau_fence_signalled(void *obj, void *arg); 1319extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1320extern int __nouveau_fence_flush(void *obj, void *arg); 1321extern void __nouveau_fence_unref(void **obj); 1322extern void *__nouveau_fence_ref(void *obj); 1323 1324static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1325{ 1326 return __nouveau_fence_signalled(obj, NULL); 1327} 1328static inline int 1329nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1330{ 1331 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1332} 1333extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1334static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1335{ 1336 return __nouveau_fence_flush(obj, NULL); 1337} 1338static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1339{ 1340 __nouveau_fence_unref((void **)obj); 1341} 1342static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1343{ 1344 return __nouveau_fence_ref(obj); 1345} 1346 1347/* nouveau_gem.c */ 1348extern int nouveau_gem_new(struct drm_device *, int size, int align, 1349 uint32_t domain, uint32_t tile_mode, 1350 uint32_t tile_flags, struct nouveau_bo **); 1351extern int nouveau_gem_object_new(struct drm_gem_object *); 1352extern void nouveau_gem_object_del(struct drm_gem_object *); 1353extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1354extern void nouveau_gem_object_close(struct drm_gem_object *, 1355 struct drm_file *); 1356extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1357 struct drm_file *); 1358extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1359 struct drm_file *); 1360extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1361 struct drm_file *); 1362extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1363 struct drm_file *); 1364extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1365 struct drm_file *); 1366 1367/* nouveau_display.c */ 1368int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1369void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1370int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1371 struct drm_pending_vblank_event *event); 1372int nouveau_finish_page_flip(struct nouveau_channel *, 1373 struct nouveau_page_flip_state *); 1374 1375/* nv10_gpio.c */ 1376int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1377int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1378 1379/* nv50_gpio.c */ 1380int nv50_gpio_init(struct drm_device *dev); 1381void nv50_gpio_fini(struct drm_device *dev); 1382int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1383int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1384int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1385 void (*)(void *, int), void *); 1386void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1387 void (*)(void *, int), void *); 1388bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1389 1390/* nv50_calc. */ 1391int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1392 int *N1, int *M1, int *N2, int *M2, int *P); 1393int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1394 int clk, int *N, int *fN, int *M, int *P); 1395 1396#ifndef ioread32_native 1397#ifdef __BIG_ENDIAN 1398#define ioread16_native ioread16be 1399#define iowrite16_native iowrite16be 1400#define ioread32_native ioread32be 1401#define iowrite32_native iowrite32be 1402#else /* def __BIG_ENDIAN */ 1403#define ioread16_native ioread16 1404#define iowrite16_native iowrite16 1405#define ioread32_native ioread32 1406#define iowrite32_native iowrite32 1407#endif /* def __BIG_ENDIAN else */ 1408#endif /* !ioread32_native */ 1409 1410/* channel control reg access */ 1411static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1412{ 1413 return ioread32_native(chan->user + reg); 1414} 1415 1416static inline void nvchan_wr32(struct nouveau_channel *chan, 1417 unsigned reg, u32 val) 1418{ 1419 iowrite32_native(val, chan->user + reg); 1420} 1421 1422/* register access */ 1423static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1424{ 1425 struct drm_nouveau_private *dev_priv = dev->dev_private; 1426 return ioread32_native(dev_priv->mmio + reg); 1427} 1428 1429static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1430{ 1431 struct drm_nouveau_private *dev_priv = dev->dev_private; 1432 iowrite32_native(val, dev_priv->mmio + reg); 1433} 1434 1435static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1436{ 1437 u32 tmp = nv_rd32(dev, reg); 1438 nv_wr32(dev, reg, (tmp & ~mask) | val); 1439 return tmp; 1440} 1441 1442static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1443{ 1444 struct drm_nouveau_private *dev_priv = dev->dev_private; 1445 return ioread8(dev_priv->mmio + reg); 1446} 1447 1448static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1449{ 1450 struct drm_nouveau_private *dev_priv = dev->dev_private; 1451 iowrite8(val, dev_priv->mmio + reg); 1452} 1453 1454#define nv_wait(dev, reg, mask, val) \ 1455 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1456#define nv_wait_ne(dev, reg, mask, val) \ 1457 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1458 1459/* PRAMIN access */ 1460static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1461{ 1462 struct drm_nouveau_private *dev_priv = dev->dev_private; 1463 return ioread32_native(dev_priv->ramin + offset); 1464} 1465 1466static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1467{ 1468 struct drm_nouveau_private *dev_priv = dev->dev_private; 1469 iowrite32_native(val, dev_priv->ramin + offset); 1470} 1471 1472/* object access */ 1473extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1474extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1475 1476/* 1477 * Logging 1478 * Argument d is (struct drm_device *). 1479 */ 1480#define NV_PRINTK(level, d, fmt, arg...) \ 1481 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1482 pci_name(d->pdev), ##arg) 1483#ifndef NV_DEBUG_NOTRACE 1484#define NV_DEBUG(d, fmt, arg...) do { \ 1485 if (drm_debug & DRM_UT_DRIVER) { \ 1486 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1487 __LINE__, ##arg); \ 1488 } \ 1489} while (0) 1490#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_KMS) { \ 1492 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1493 __LINE__, ##arg); \ 1494 } \ 1495} while (0) 1496#else 1497#define NV_DEBUG(d, fmt, arg...) do { \ 1498 if (drm_debug & DRM_UT_DRIVER) \ 1499 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1500} while (0) 1501#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1502 if (drm_debug & DRM_UT_KMS) \ 1503 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1504} while (0) 1505#endif 1506#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1507#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1508#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1509#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1510#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1511 1512/* nouveau_reg_debug bitmask */ 1513enum { 1514 NOUVEAU_REG_DEBUG_MC = 0x1, 1515 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1516 NOUVEAU_REG_DEBUG_FB = 0x4, 1517 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1518 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1519 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1520 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1521 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1522 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1523 NOUVEAU_REG_DEBUG_EVO = 0x200, 1524}; 1525 1526#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1527 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1528 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1529} while (0) 1530 1531static inline bool 1532nv_two_heads(struct drm_device *dev) 1533{ 1534 struct drm_nouveau_private *dev_priv = dev->dev_private; 1535 const int impl = dev->pci_device & 0x0ff0; 1536 1537 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1538 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1539 return true; 1540 1541 return false; 1542} 1543 1544static inline bool 1545nv_gf4_disp_arch(struct drm_device *dev) 1546{ 1547 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1548} 1549 1550static inline bool 1551nv_two_reg_pll(struct drm_device *dev) 1552{ 1553 struct drm_nouveau_private *dev_priv = dev->dev_private; 1554 const int impl = dev->pci_device & 0x0ff0; 1555 1556 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1557 return true; 1558 return false; 1559} 1560 1561static inline bool 1562nv_match_device(struct drm_device *dev, unsigned device, 1563 unsigned sub_vendor, unsigned sub_device) 1564{ 1565 return dev->pdev->device == device && 1566 dev->pdev->subsystem_vendor == sub_vendor && 1567 dev->pdev->subsystem_device == sub_device; 1568} 1569 1570static inline void * 1571nv_engine(struct drm_device *dev, int engine) 1572{ 1573 struct drm_nouveau_private *dev_priv = dev->dev_private; 1574 return (void *)dev_priv->eng[engine]; 1575} 1576 1577/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1578 * helpful to determine a number of other hardware features 1579 */ 1580static inline int 1581nv44_graph_class(struct drm_device *dev) 1582{ 1583 struct drm_nouveau_private *dev_priv = dev->dev_private; 1584 1585 if ((dev_priv->chipset & 0xf0) == 0x60) 1586 return 1; 1587 1588 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1589} 1590 1591/* memory type/access flags, do not match hardware values */ 1592#define NV_MEM_ACCESS_RO 1 1593#define NV_MEM_ACCESS_WO 2 1594#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1595#define NV_MEM_ACCESS_SYS 4 1596#define NV_MEM_ACCESS_VM 8 1597 1598#define NV_MEM_TARGET_VRAM 0 1599#define NV_MEM_TARGET_PCI 1 1600#define NV_MEM_TARGET_PCI_NOSNOOP 2 1601#define NV_MEM_TARGET_VM 3 1602#define NV_MEM_TARGET_GART 4 1603 1604#define NV_MEM_TYPE_VM 0x7f 1605#define NV_MEM_COMP_VM 0x03 1606 1607/* NV_SW object class */ 1608#define NV_SW 0x0000506e 1609#define NV_SW_DMA_SEMAPHORE 0x00000060 1610#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1611#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1612#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1613#define NV_SW_YIELD 0x00000080 1614#define NV_SW_DMA_VBLSEM 0x0000018c 1615#define NV_SW_VBLSEM_OFFSET 0x00000400 1616#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1617#define NV_SW_VBLSEM_RELEASE 0x00000408 1618#define NV_SW_PAGE_FLIP 0x00000500 1619 1620#endif /* __NOUVEAU_DRV_H__ */ 1621