nouveau_drv.h revision 78e2933d07124ea28593a1bdadc546294f77a504
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_100220; 433 u32 reg_100224; 434 u32 reg_100228; 435 u32 reg_10022c; 436 u32 reg_100230; 437 u32 reg_100234; 438 u32 reg_100238; 439 u32 reg_10023c; 440 u32 reg_100240; 441}; 442 443#define NOUVEAU_PM_MAX_LEVEL 8 444struct nouveau_pm_level { 445 struct device_attribute dev_attr; 446 char name[32]; 447 int id; 448 449 u32 core; 450 u32 memory; 451 u32 shader; 452 u32 vdec; 453 u32 unk05; 454 u32 unk0a; 455 u32 unka0; 456 457 u32 volt_min; /* microvolts */ 458 u32 volt_max; 459 u8 fanspeed; 460 461 u16 memscript; 462 struct nouveau_pm_memtiming *timing; 463}; 464 465struct nouveau_pm_temp_sensor_constants { 466 u16 offset_constant; 467 s16 offset_mult; 468 s16 offset_div; 469 s16 slope_mult; 470 s16 slope_div; 471}; 472 473struct nouveau_pm_threshold_temp { 474 s16 critical; 475 s16 down_clock; 476 s16 fan_boost; 477}; 478 479struct nouveau_pm_memtimings { 480 bool supported; 481 struct nouveau_pm_memtiming *timing; 482 int nr_timing; 483}; 484 485struct nouveau_pm_engine { 486 struct nouveau_pm_voltage voltage; 487 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 488 int nr_perflvl; 489 struct nouveau_pm_memtimings memtimings; 490 struct nouveau_pm_temp_sensor_constants sensor_constants; 491 struct nouveau_pm_threshold_temp threshold_temp; 492 493 struct nouveau_pm_level boot; 494 struct nouveau_pm_level *cur; 495 496 struct device *hwmon; 497 struct notifier_block acpi_nb; 498 499 int (*clock_get)(struct drm_device *, u32 id); 500 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 501 u32 id, int khz); 502 void (*clock_set)(struct drm_device *, void *); 503 504 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 505 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 506 void (*clocks_set)(struct drm_device *, void *); 507 508 int (*voltage_get)(struct drm_device *); 509 int (*voltage_set)(struct drm_device *, int voltage); 510 int (*fanspeed_get)(struct drm_device *); 511 int (*fanspeed_set)(struct drm_device *, int fanspeed); 512 int (*temp_get)(struct drm_device *); 513}; 514 515struct nouveau_vram_engine { 516 struct nouveau_mm *mm; 517 518 int (*init)(struct drm_device *); 519 void (*takedown)(struct drm_device *dev); 520 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 521 u32 type, struct nouveau_mem **); 522 void (*put)(struct drm_device *, struct nouveau_mem **); 523 524 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 525}; 526 527struct nouveau_engine { 528 struct nouveau_instmem_engine instmem; 529 struct nouveau_mc_engine mc; 530 struct nouveau_timer_engine timer; 531 struct nouveau_fb_engine fb; 532 struct nouveau_fifo_engine fifo; 533 struct nouveau_display_engine display; 534 struct nouveau_gpio_engine gpio; 535 struct nouveau_pm_engine pm; 536 struct nouveau_vram_engine vram; 537}; 538 539struct nouveau_pll_vals { 540 union { 541 struct { 542#ifdef __BIG_ENDIAN 543 uint8_t N1, M1, N2, M2; 544#else 545 uint8_t M1, N1, M2, N2; 546#endif 547 }; 548 struct { 549 uint16_t NM1, NM2; 550 } __attribute__((packed)); 551 }; 552 int log2P; 553 554 int refclk; 555}; 556 557enum nv04_fp_display_regs { 558 FP_DISPLAY_END, 559 FP_TOTAL, 560 FP_CRTC, 561 FP_SYNC_START, 562 FP_SYNC_END, 563 FP_VALID_START, 564 FP_VALID_END 565}; 566 567struct nv04_crtc_reg { 568 unsigned char MiscOutReg; 569 uint8_t CRTC[0xa0]; 570 uint8_t CR58[0x10]; 571 uint8_t Sequencer[5]; 572 uint8_t Graphics[9]; 573 uint8_t Attribute[21]; 574 unsigned char DAC[768]; 575 576 /* PCRTC regs */ 577 uint32_t fb_start; 578 uint32_t crtc_cfg; 579 uint32_t cursor_cfg; 580 uint32_t gpio_ext; 581 uint32_t crtc_830; 582 uint32_t crtc_834; 583 uint32_t crtc_850; 584 uint32_t crtc_eng_ctrl; 585 586 /* PRAMDAC regs */ 587 uint32_t nv10_cursync; 588 struct nouveau_pll_vals pllvals; 589 uint32_t ramdac_gen_ctrl; 590 uint32_t ramdac_630; 591 uint32_t ramdac_634; 592 uint32_t tv_setup; 593 uint32_t tv_vtotal; 594 uint32_t tv_vskew; 595 uint32_t tv_vsync_delay; 596 uint32_t tv_htotal; 597 uint32_t tv_hskew; 598 uint32_t tv_hsync_delay; 599 uint32_t tv_hsync_delay2; 600 uint32_t fp_horiz_regs[7]; 601 uint32_t fp_vert_regs[7]; 602 uint32_t dither; 603 uint32_t fp_control; 604 uint32_t dither_regs[6]; 605 uint32_t fp_debug_0; 606 uint32_t fp_debug_1; 607 uint32_t fp_debug_2; 608 uint32_t fp_margin_color; 609 uint32_t ramdac_8c0; 610 uint32_t ramdac_a20; 611 uint32_t ramdac_a24; 612 uint32_t ramdac_a34; 613 uint32_t ctv_regs[38]; 614}; 615 616struct nv04_output_reg { 617 uint32_t output; 618 int head; 619}; 620 621struct nv04_mode_state { 622 struct nv04_crtc_reg crtc_reg[2]; 623 uint32_t pllsel; 624 uint32_t sel_clk; 625}; 626 627enum nouveau_card_type { 628 NV_04 = 0x00, 629 NV_10 = 0x10, 630 NV_20 = 0x20, 631 NV_30 = 0x30, 632 NV_40 = 0x40, 633 NV_50 = 0x50, 634 NV_C0 = 0xc0, 635}; 636 637struct drm_nouveau_private { 638 struct drm_device *dev; 639 bool noaccel; 640 641 /* the card type, takes NV_* as values */ 642 enum nouveau_card_type card_type; 643 /* exact chipset, derived from NV_PMC_BOOT_0 */ 644 int chipset; 645 int stepping; 646 int flags; 647 648 void __iomem *mmio; 649 650 spinlock_t ramin_lock; 651 void __iomem *ramin; 652 u32 ramin_size; 653 u32 ramin_base; 654 bool ramin_available; 655 struct drm_mm ramin_heap; 656 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 657 struct list_head gpuobj_list; 658 struct list_head classes; 659 660 struct nouveau_bo *vga_ram; 661 662 /* interrupt handling */ 663 void (*irq_handler[32])(struct drm_device *); 664 bool msi_enabled; 665 666 struct list_head vbl_waiting; 667 668 struct { 669 struct drm_global_reference mem_global_ref; 670 struct ttm_bo_global_ref bo_global_ref; 671 struct ttm_bo_device bdev; 672 atomic_t validate_sequence; 673 } ttm; 674 675 struct { 676 spinlock_t lock; 677 struct drm_mm heap; 678 struct nouveau_bo *bo; 679 } fence; 680 681 struct { 682 spinlock_t lock; 683 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 684 } channels; 685 686 struct nouveau_engine engine; 687 struct nouveau_channel *channel; 688 689 /* For PFIFO and PGRAPH. */ 690 spinlock_t context_switch_lock; 691 692 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 693 spinlock_t vm_lock; 694 695 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 696 struct nouveau_ramht *ramht; 697 struct nouveau_gpuobj *ramfc; 698 struct nouveau_gpuobj *ramro; 699 700 uint32_t ramin_rsvd_vram; 701 702 struct { 703 enum { 704 NOUVEAU_GART_NONE = 0, 705 NOUVEAU_GART_AGP, /* AGP */ 706 NOUVEAU_GART_PDMA, /* paged dma object */ 707 NOUVEAU_GART_HW /* on-chip gart/vm */ 708 } type; 709 uint64_t aper_base; 710 uint64_t aper_size; 711 uint64_t aper_free; 712 713 struct ttm_backend_func *func; 714 715 struct { 716 struct page *page; 717 dma_addr_t addr; 718 } dummy; 719 720 struct nouveau_gpuobj *sg_ctxdma; 721 } gart_info; 722 723 /* nv10-nv40 tiling regions */ 724 struct { 725 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 726 spinlock_t lock; 727 } tile; 728 729 /* VRAM/fb configuration */ 730 uint64_t vram_size; 731 uint64_t vram_sys_base; 732 733 uint64_t fb_phys; 734 uint64_t fb_available_size; 735 uint64_t fb_mappable_pages; 736 uint64_t fb_aper_free; 737 int fb_mtrr; 738 739 /* BAR control (NV50-) */ 740 struct nouveau_vm *bar1_vm; 741 struct nouveau_vm *bar3_vm; 742 743 /* G8x/G9x virtual address space */ 744 struct nouveau_vm *chan_vm; 745 746 struct nvbios vbios; 747 748 struct nv04_mode_state mode_reg; 749 struct nv04_mode_state saved_reg; 750 uint32_t saved_vga_font[4][16384]; 751 uint32_t crtc_owner; 752 uint32_t dac_users[4]; 753 754 struct backlight_device *backlight; 755 756 struct { 757 struct dentry *channel_root; 758 } debugfs; 759 760 struct nouveau_fbdev *nfbdev; 761 struct apertures_struct *apertures; 762}; 763 764static inline struct drm_nouveau_private * 765nouveau_private(struct drm_device *dev) 766{ 767 return dev->dev_private; 768} 769 770static inline struct drm_nouveau_private * 771nouveau_bdev(struct ttm_bo_device *bd) 772{ 773 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 774} 775 776static inline int 777nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 778{ 779 struct nouveau_bo *prev; 780 781 if (!pnvbo) 782 return -EINVAL; 783 prev = *pnvbo; 784 785 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 786 if (prev) { 787 struct ttm_buffer_object *bo = &prev->bo; 788 789 ttm_bo_unref(&bo); 790 } 791 792 return 0; 793} 794 795/* nouveau_drv.c */ 796extern int nouveau_agpmode; 797extern int nouveau_duallink; 798extern int nouveau_uscript_lvds; 799extern int nouveau_uscript_tmds; 800extern int nouveau_vram_pushbuf; 801extern int nouveau_vram_notify; 802extern int nouveau_fbpercrtc; 803extern int nouveau_tv_disable; 804extern char *nouveau_tv_norm; 805extern int nouveau_reg_debug; 806extern char *nouveau_vbios; 807extern int nouveau_ignorelid; 808extern int nouveau_nofbaccel; 809extern int nouveau_noaccel; 810extern int nouveau_force_post; 811extern int nouveau_override_conntype; 812extern char *nouveau_perflvl; 813extern int nouveau_perflvl_wr; 814extern int nouveau_msi; 815extern int nouveau_ctxfw; 816 817extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 818extern int nouveau_pci_resume(struct pci_dev *pdev); 819 820/* nouveau_state.c */ 821extern int nouveau_open(struct drm_device *, struct drm_file *); 822extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 823extern void nouveau_postclose(struct drm_device *, struct drm_file *); 824extern int nouveau_load(struct drm_device *, unsigned long flags); 825extern int nouveau_firstopen(struct drm_device *); 826extern void nouveau_lastclose(struct drm_device *); 827extern int nouveau_unload(struct drm_device *); 828extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 829 struct drm_file *); 830extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 831 struct drm_file *); 832extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 833 uint32_t reg, uint32_t mask, uint32_t val); 834extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 835 uint32_t reg, uint32_t mask, uint32_t val); 836extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 837 bool (*cond)(void *), void *); 838extern bool nouveau_wait_for_idle(struct drm_device *); 839extern int nouveau_card_init(struct drm_device *); 840 841/* nouveau_mem.c */ 842extern int nouveau_mem_vram_init(struct drm_device *); 843extern void nouveau_mem_vram_fini(struct drm_device *); 844extern int nouveau_mem_gart_init(struct drm_device *); 845extern void nouveau_mem_gart_fini(struct drm_device *); 846extern int nouveau_mem_init_agp(struct drm_device *); 847extern int nouveau_mem_reset_agp(struct drm_device *); 848extern void nouveau_mem_close(struct drm_device *); 849extern int nouveau_mem_detect(struct drm_device *); 850extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 851extern struct nouveau_tile_reg *nv10_mem_set_tiling( 852 struct drm_device *dev, uint32_t addr, uint32_t size, 853 uint32_t pitch, uint32_t flags); 854extern void nv10_mem_put_tile_region(struct drm_device *dev, 855 struct nouveau_tile_reg *tile, 856 struct nouveau_fence *fence); 857extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 858extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 859 860/* nouveau_notifier.c */ 861extern int nouveau_notifier_init_channel(struct nouveau_channel *); 862extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 863extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 864 int cout, uint32_t start, uint32_t end, 865 uint32_t *offset); 866extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 867extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 868 struct drm_file *); 869extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 870 struct drm_file *); 871 872/* nouveau_channel.c */ 873extern struct drm_ioctl_desc nouveau_ioctls[]; 874extern int nouveau_max_ioctl; 875extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 876extern int nouveau_channel_alloc(struct drm_device *dev, 877 struct nouveau_channel **chan, 878 struct drm_file *file_priv, 879 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 880extern struct nouveau_channel * 881nouveau_channel_get_unlocked(struct nouveau_channel *); 882extern struct nouveau_channel * 883nouveau_channel_get(struct drm_file *, int id); 884extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 885extern void nouveau_channel_put(struct nouveau_channel **); 886extern void nouveau_channel_ref(struct nouveau_channel *chan, 887 struct nouveau_channel **pchan); 888extern void nouveau_channel_idle(struct nouveau_channel *chan); 889 890/* nouveau_object.c */ 891#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 892 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 893 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 894} while (0) 895 896#define NVOBJ_ENGINE_DEL(d, e) do { \ 897 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 898 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 899} while (0) 900 901#define NVOBJ_CLASS(d, c, e) do { \ 902 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 903 if (ret) \ 904 return ret; \ 905} while (0) 906 907#define NVOBJ_MTHD(d, c, m, e) do { \ 908 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 909 if (ret) \ 910 return ret; \ 911} while (0) 912 913extern int nouveau_gpuobj_early_init(struct drm_device *); 914extern int nouveau_gpuobj_init(struct drm_device *); 915extern void nouveau_gpuobj_takedown(struct drm_device *); 916extern int nouveau_gpuobj_suspend(struct drm_device *dev); 917extern void nouveau_gpuobj_resume(struct drm_device *dev); 918extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 919extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 920 int (*exec)(struct nouveau_channel *, 921 u32 class, u32 mthd, u32 data)); 922extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 923extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 924extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 925 uint32_t vram_h, uint32_t tt_h); 926extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 927extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 928 uint32_t size, int align, uint32_t flags, 929 struct nouveau_gpuobj **); 930extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 931 struct nouveau_gpuobj **); 932extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 933 u32 size, u32 flags, 934 struct nouveau_gpuobj **); 935extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 936 uint64_t offset, uint64_t size, int access, 937 int target, struct nouveau_gpuobj **); 938extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 939extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 940 u64 size, int target, int access, u32 type, 941 u32 comp, struct nouveau_gpuobj **pobj); 942extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 943 int class, u64 base, u64 size, int target, 944 int access, u32 type, u32 comp); 945extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 946 struct drm_file *); 947extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 948 struct drm_file *); 949 950/* nouveau_irq.c */ 951extern int nouveau_irq_init(struct drm_device *); 952extern void nouveau_irq_fini(struct drm_device *); 953extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 954extern void nouveau_irq_register(struct drm_device *, int status_bit, 955 void (*)(struct drm_device *)); 956extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 957extern void nouveau_irq_preinstall(struct drm_device *); 958extern int nouveau_irq_postinstall(struct drm_device *); 959extern void nouveau_irq_uninstall(struct drm_device *); 960 961/* nouveau_sgdma.c */ 962extern int nouveau_sgdma_init(struct drm_device *); 963extern void nouveau_sgdma_takedown(struct drm_device *); 964extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 965 uint32_t offset); 966extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 967 968/* nouveau_debugfs.c */ 969#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 970extern int nouveau_debugfs_init(struct drm_minor *); 971extern void nouveau_debugfs_takedown(struct drm_minor *); 972extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 973extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 974#else 975static inline int 976nouveau_debugfs_init(struct drm_minor *minor) 977{ 978 return 0; 979} 980 981static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 982{ 983} 984 985static inline int 986nouveau_debugfs_channel_init(struct nouveau_channel *chan) 987{ 988 return 0; 989} 990 991static inline void 992nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 993{ 994} 995#endif 996 997/* nouveau_dma.c */ 998extern void nouveau_dma_pre_init(struct nouveau_channel *); 999extern int nouveau_dma_init(struct nouveau_channel *); 1000extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1001 1002/* nouveau_acpi.c */ 1003#define ROM_BIOS_PAGE 4096 1004#if defined(CONFIG_ACPI) 1005void nouveau_register_dsm_handler(void); 1006void nouveau_unregister_dsm_handler(void); 1007int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1008bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1009int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1010#else 1011static inline void nouveau_register_dsm_handler(void) {} 1012static inline void nouveau_unregister_dsm_handler(void) {} 1013static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1014static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1015static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1016#endif 1017 1018/* nouveau_backlight.c */ 1019#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1020extern int nouveau_backlight_init(struct drm_connector *); 1021extern void nouveau_backlight_exit(struct drm_connector *); 1022#else 1023static inline int nouveau_backlight_init(struct drm_connector *dev) 1024{ 1025 return 0; 1026} 1027 1028static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1029#endif 1030 1031/* nouveau_bios.c */ 1032extern int nouveau_bios_init(struct drm_device *); 1033extern void nouveau_bios_takedown(struct drm_device *dev); 1034extern int nouveau_run_vbios_init(struct drm_device *); 1035extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1036 struct dcb_entry *); 1037extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1038 enum dcb_gpio_tag); 1039extern struct dcb_connector_table_entry * 1040nouveau_bios_connector_entry(struct drm_device *, int index); 1041extern u32 get_pll_register(struct drm_device *, enum pll_types); 1042extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1043 struct pll_lims *); 1044extern int nouveau_bios_run_display_table(struct drm_device *, 1045 struct dcb_entry *, 1046 uint32_t script, int pxclk); 1047extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1048 int *length); 1049extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1050extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1051extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1052 bool *dl, bool *if_is_24bit); 1053extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1054 int head, int pxclk); 1055extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1056 enum LVDS_script, int pxclk); 1057 1058/* nouveau_ttm.c */ 1059int nouveau_ttm_global_init(struct drm_nouveau_private *); 1060void nouveau_ttm_global_release(struct drm_nouveau_private *); 1061int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1062 1063/* nouveau_dp.c */ 1064int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1065 uint8_t *data, int data_nr); 1066bool nouveau_dp_detect(struct drm_encoder *); 1067bool nouveau_dp_link_train(struct drm_encoder *); 1068 1069/* nv04_fb.c */ 1070extern int nv04_fb_init(struct drm_device *); 1071extern void nv04_fb_takedown(struct drm_device *); 1072 1073/* nv10_fb.c */ 1074extern int nv10_fb_init(struct drm_device *); 1075extern void nv10_fb_takedown(struct drm_device *); 1076extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1077 uint32_t addr, uint32_t size, 1078 uint32_t pitch, uint32_t flags); 1079extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1080extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1081 1082/* nv30_fb.c */ 1083extern int nv30_fb_init(struct drm_device *); 1084extern void nv30_fb_takedown(struct drm_device *); 1085extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1086 uint32_t addr, uint32_t size, 1087 uint32_t pitch, uint32_t flags); 1088extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1089 1090/* nv40_fb.c */ 1091extern int nv40_fb_init(struct drm_device *); 1092extern void nv40_fb_takedown(struct drm_device *); 1093extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1094 1095/* nv50_fb.c */ 1096extern int nv50_fb_init(struct drm_device *); 1097extern void nv50_fb_takedown(struct drm_device *); 1098extern void nv50_fb_vm_trap(struct drm_device *, int display); 1099 1100/* nvc0_fb.c */ 1101extern int nvc0_fb_init(struct drm_device *); 1102extern void nvc0_fb_takedown(struct drm_device *); 1103 1104/* nv04_fifo.c */ 1105extern int nv04_fifo_init(struct drm_device *); 1106extern void nv04_fifo_fini(struct drm_device *); 1107extern void nv04_fifo_disable(struct drm_device *); 1108extern void nv04_fifo_enable(struct drm_device *); 1109extern bool nv04_fifo_reassign(struct drm_device *, bool); 1110extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1111extern int nv04_fifo_channel_id(struct drm_device *); 1112extern int nv04_fifo_create_context(struct nouveau_channel *); 1113extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1114extern int nv04_fifo_load_context(struct nouveau_channel *); 1115extern int nv04_fifo_unload_context(struct drm_device *); 1116extern void nv04_fifo_isr(struct drm_device *); 1117 1118/* nv10_fifo.c */ 1119extern int nv10_fifo_init(struct drm_device *); 1120extern int nv10_fifo_channel_id(struct drm_device *); 1121extern int nv10_fifo_create_context(struct nouveau_channel *); 1122extern int nv10_fifo_load_context(struct nouveau_channel *); 1123extern int nv10_fifo_unload_context(struct drm_device *); 1124 1125/* nv40_fifo.c */ 1126extern int nv40_fifo_init(struct drm_device *); 1127extern int nv40_fifo_create_context(struct nouveau_channel *); 1128extern int nv40_fifo_load_context(struct nouveau_channel *); 1129extern int nv40_fifo_unload_context(struct drm_device *); 1130 1131/* nv50_fifo.c */ 1132extern int nv50_fifo_init(struct drm_device *); 1133extern void nv50_fifo_takedown(struct drm_device *); 1134extern int nv50_fifo_channel_id(struct drm_device *); 1135extern int nv50_fifo_create_context(struct nouveau_channel *); 1136extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1137extern int nv50_fifo_load_context(struct nouveau_channel *); 1138extern int nv50_fifo_unload_context(struct drm_device *); 1139extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1140 1141/* nvc0_fifo.c */ 1142extern int nvc0_fifo_init(struct drm_device *); 1143extern void nvc0_fifo_takedown(struct drm_device *); 1144extern void nvc0_fifo_disable(struct drm_device *); 1145extern void nvc0_fifo_enable(struct drm_device *); 1146extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1147extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1148extern int nvc0_fifo_channel_id(struct drm_device *); 1149extern int nvc0_fifo_create_context(struct nouveau_channel *); 1150extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1151extern int nvc0_fifo_load_context(struct nouveau_channel *); 1152extern int nvc0_fifo_unload_context(struct drm_device *); 1153 1154/* nv04_graph.c */ 1155extern int nv04_graph_create(struct drm_device *); 1156extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1157extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1158 u32 class, u32 mthd, u32 data); 1159extern struct nouveau_bitfield nv04_graph_nsource[]; 1160 1161/* nv10_graph.c */ 1162extern int nv10_graph_create(struct drm_device *); 1163extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1164extern struct nouveau_bitfield nv10_graph_intr[]; 1165extern struct nouveau_bitfield nv10_graph_nstatus[]; 1166 1167/* nv20_graph.c */ 1168extern int nv20_graph_create(struct drm_device *); 1169 1170/* nv40_graph.c */ 1171extern int nv40_graph_create(struct drm_device *); 1172extern void nv40_grctx_init(struct nouveau_grctx *); 1173 1174/* nv50_graph.c */ 1175extern int nv50_graph_create(struct drm_device *); 1176extern int nv50_grctx_init(struct nouveau_grctx *); 1177extern struct nouveau_enum nv50_data_error_names[]; 1178extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1179 1180/* nvc0_graph.c */ 1181extern int nvc0_graph_create(struct drm_device *); 1182extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1183 1184/* nv84_crypt.c */ 1185extern int nv84_crypt_create(struct drm_device *); 1186 1187/* nva3_copy.c */ 1188extern int nva3_copy_create(struct drm_device *dev); 1189 1190/* nvc0_copy.c */ 1191extern int nvc0_copy_create(struct drm_device *dev, int engine); 1192 1193/* nv40_mpeg.c */ 1194extern int nv40_mpeg_create(struct drm_device *dev); 1195 1196/* nv50_mpeg.c */ 1197extern int nv50_mpeg_create(struct drm_device *dev); 1198 1199/* nv04_instmem.c */ 1200extern int nv04_instmem_init(struct drm_device *); 1201extern void nv04_instmem_takedown(struct drm_device *); 1202extern int nv04_instmem_suspend(struct drm_device *); 1203extern void nv04_instmem_resume(struct drm_device *); 1204extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1205 u32 size, u32 align); 1206extern void nv04_instmem_put(struct nouveau_gpuobj *); 1207extern int nv04_instmem_map(struct nouveau_gpuobj *); 1208extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1209extern void nv04_instmem_flush(struct drm_device *); 1210 1211/* nv50_instmem.c */ 1212extern int nv50_instmem_init(struct drm_device *); 1213extern void nv50_instmem_takedown(struct drm_device *); 1214extern int nv50_instmem_suspend(struct drm_device *); 1215extern void nv50_instmem_resume(struct drm_device *); 1216extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1217 u32 size, u32 align); 1218extern void nv50_instmem_put(struct nouveau_gpuobj *); 1219extern int nv50_instmem_map(struct nouveau_gpuobj *); 1220extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1221extern void nv50_instmem_flush(struct drm_device *); 1222extern void nv84_instmem_flush(struct drm_device *); 1223 1224/* nvc0_instmem.c */ 1225extern int nvc0_instmem_init(struct drm_device *); 1226extern void nvc0_instmem_takedown(struct drm_device *); 1227extern int nvc0_instmem_suspend(struct drm_device *); 1228extern void nvc0_instmem_resume(struct drm_device *); 1229 1230/* nv04_mc.c */ 1231extern int nv04_mc_init(struct drm_device *); 1232extern void nv04_mc_takedown(struct drm_device *); 1233 1234/* nv40_mc.c */ 1235extern int nv40_mc_init(struct drm_device *); 1236extern void nv40_mc_takedown(struct drm_device *); 1237 1238/* nv50_mc.c */ 1239extern int nv50_mc_init(struct drm_device *); 1240extern void nv50_mc_takedown(struct drm_device *); 1241 1242/* nv04_timer.c */ 1243extern int nv04_timer_init(struct drm_device *); 1244extern uint64_t nv04_timer_read(struct drm_device *); 1245extern void nv04_timer_takedown(struct drm_device *); 1246 1247extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1248 unsigned long arg); 1249 1250/* nv04_dac.c */ 1251extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1252extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1253extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1254extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1255extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1256 1257/* nv04_dfp.c */ 1258extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1259extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1260extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1261 int head, bool dl); 1262extern void nv04_dfp_disable(struct drm_device *dev, int head); 1263extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1264 1265/* nv04_tv.c */ 1266extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1267extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1268 1269/* nv17_tv.c */ 1270extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1271 1272/* nv04_display.c */ 1273extern int nv04_display_early_init(struct drm_device *); 1274extern void nv04_display_late_takedown(struct drm_device *); 1275extern int nv04_display_create(struct drm_device *); 1276extern int nv04_display_init(struct drm_device *); 1277extern void nv04_display_destroy(struct drm_device *); 1278 1279/* nv04_crtc.c */ 1280extern int nv04_crtc_create(struct drm_device *, int index); 1281 1282/* nouveau_bo.c */ 1283extern struct ttm_bo_driver nouveau_bo_driver; 1284extern int nouveau_bo_new(struct drm_device *, int size, int align, 1285 uint32_t flags, uint32_t tile_mode, 1286 uint32_t tile_flags, struct nouveau_bo **); 1287extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1288extern int nouveau_bo_unpin(struct nouveau_bo *); 1289extern int nouveau_bo_map(struct nouveau_bo *); 1290extern void nouveau_bo_unmap(struct nouveau_bo *); 1291extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1292 uint32_t busy); 1293extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1294extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1295extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1296extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1297extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1298extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1299 bool no_wait_reserve, bool no_wait_gpu); 1300 1301extern struct nouveau_vma * 1302nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1303extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1304 struct nouveau_vma *); 1305extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1306 1307/* nouveau_fence.c */ 1308struct nouveau_fence; 1309extern int nouveau_fence_init(struct drm_device *); 1310extern void nouveau_fence_fini(struct drm_device *); 1311extern int nouveau_fence_channel_init(struct nouveau_channel *); 1312extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1313extern void nouveau_fence_update(struct nouveau_channel *); 1314extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1315 bool emit); 1316extern int nouveau_fence_emit(struct nouveau_fence *); 1317extern void nouveau_fence_work(struct nouveau_fence *fence, 1318 void (*work)(void *priv, bool signalled), 1319 void *priv); 1320struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1321 1322extern bool __nouveau_fence_signalled(void *obj, void *arg); 1323extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1324extern int __nouveau_fence_flush(void *obj, void *arg); 1325extern void __nouveau_fence_unref(void **obj); 1326extern void *__nouveau_fence_ref(void *obj); 1327 1328static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1329{ 1330 return __nouveau_fence_signalled(obj, NULL); 1331} 1332static inline int 1333nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1334{ 1335 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1336} 1337extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1338static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1339{ 1340 return __nouveau_fence_flush(obj, NULL); 1341} 1342static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1343{ 1344 __nouveau_fence_unref((void **)obj); 1345} 1346static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1347{ 1348 return __nouveau_fence_ref(obj); 1349} 1350 1351/* nouveau_gem.c */ 1352extern int nouveau_gem_new(struct drm_device *, int size, int align, 1353 uint32_t domain, uint32_t tile_mode, 1354 uint32_t tile_flags, struct nouveau_bo **); 1355extern int nouveau_gem_object_new(struct drm_gem_object *); 1356extern void nouveau_gem_object_del(struct drm_gem_object *); 1357extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1358extern void nouveau_gem_object_close(struct drm_gem_object *, 1359 struct drm_file *); 1360extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1361 struct drm_file *); 1362extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1363 struct drm_file *); 1364extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1365 struct drm_file *); 1366extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1367 struct drm_file *); 1368extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1369 struct drm_file *); 1370 1371/* nouveau_display.c */ 1372int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1373void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1374int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1375 struct drm_pending_vblank_event *event); 1376int nouveau_finish_page_flip(struct nouveau_channel *, 1377 struct nouveau_page_flip_state *); 1378 1379/* nv10_gpio.c */ 1380int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1381int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1382 1383/* nv50_gpio.c */ 1384int nv50_gpio_init(struct drm_device *dev); 1385void nv50_gpio_fini(struct drm_device *dev); 1386int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1387int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1388int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1389 void (*)(void *, int), void *); 1390void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1391 void (*)(void *, int), void *); 1392bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1393 1394/* nv50_calc. */ 1395int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1396 int *N1, int *M1, int *N2, int *M2, int *P); 1397int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1398 int clk, int *N, int *fN, int *M, int *P); 1399 1400#ifndef ioread32_native 1401#ifdef __BIG_ENDIAN 1402#define ioread16_native ioread16be 1403#define iowrite16_native iowrite16be 1404#define ioread32_native ioread32be 1405#define iowrite32_native iowrite32be 1406#else /* def __BIG_ENDIAN */ 1407#define ioread16_native ioread16 1408#define iowrite16_native iowrite16 1409#define ioread32_native ioread32 1410#define iowrite32_native iowrite32 1411#endif /* def __BIG_ENDIAN else */ 1412#endif /* !ioread32_native */ 1413 1414/* channel control reg access */ 1415static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1416{ 1417 return ioread32_native(chan->user + reg); 1418} 1419 1420static inline void nvchan_wr32(struct nouveau_channel *chan, 1421 unsigned reg, u32 val) 1422{ 1423 iowrite32_native(val, chan->user + reg); 1424} 1425 1426/* register access */ 1427static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1428{ 1429 struct drm_nouveau_private *dev_priv = dev->dev_private; 1430 return ioread32_native(dev_priv->mmio + reg); 1431} 1432 1433static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1434{ 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 iowrite32_native(val, dev_priv->mmio + reg); 1437} 1438 1439static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1440{ 1441 u32 tmp = nv_rd32(dev, reg); 1442 nv_wr32(dev, reg, (tmp & ~mask) | val); 1443 return tmp; 1444} 1445 1446static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1447{ 1448 struct drm_nouveau_private *dev_priv = dev->dev_private; 1449 return ioread8(dev_priv->mmio + reg); 1450} 1451 1452static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1453{ 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 iowrite8(val, dev_priv->mmio + reg); 1456} 1457 1458#define nv_wait(dev, reg, mask, val) \ 1459 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1460#define nv_wait_ne(dev, reg, mask, val) \ 1461 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1462#define nv_wait_cb(dev, func, data) \ 1463 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1464 1465/* PRAMIN access */ 1466static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1467{ 1468 struct drm_nouveau_private *dev_priv = dev->dev_private; 1469 return ioread32_native(dev_priv->ramin + offset); 1470} 1471 1472static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1473{ 1474 struct drm_nouveau_private *dev_priv = dev->dev_private; 1475 iowrite32_native(val, dev_priv->ramin + offset); 1476} 1477 1478/* object access */ 1479extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1480extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1481 1482/* 1483 * Logging 1484 * Argument d is (struct drm_device *). 1485 */ 1486#define NV_PRINTK(level, d, fmt, arg...) \ 1487 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1488 pci_name(d->pdev), ##arg) 1489#ifndef NV_DEBUG_NOTRACE 1490#define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) { \ 1492 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1493 __LINE__, ##arg); \ 1494 } \ 1495} while (0) 1496#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1497 if (drm_debug & DRM_UT_KMS) { \ 1498 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1499 __LINE__, ##arg); \ 1500 } \ 1501} while (0) 1502#else 1503#define NV_DEBUG(d, fmt, arg...) do { \ 1504 if (drm_debug & DRM_UT_DRIVER) \ 1505 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1506} while (0) 1507#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1508 if (drm_debug & DRM_UT_KMS) \ 1509 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1510} while (0) 1511#endif 1512#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1513#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1514#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1515#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1516#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1517 1518/* nouveau_reg_debug bitmask */ 1519enum { 1520 NOUVEAU_REG_DEBUG_MC = 0x1, 1521 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1522 NOUVEAU_REG_DEBUG_FB = 0x4, 1523 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1524 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1525 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1526 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1527 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1528 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1529 NOUVEAU_REG_DEBUG_EVO = 0x200, 1530}; 1531 1532#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1533 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1534 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1535} while (0) 1536 1537static inline bool 1538nv_two_heads(struct drm_device *dev) 1539{ 1540 struct drm_nouveau_private *dev_priv = dev->dev_private; 1541 const int impl = dev->pci_device & 0x0ff0; 1542 1543 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1544 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1545 return true; 1546 1547 return false; 1548} 1549 1550static inline bool 1551nv_gf4_disp_arch(struct drm_device *dev) 1552{ 1553 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1554} 1555 1556static inline bool 1557nv_two_reg_pll(struct drm_device *dev) 1558{ 1559 struct drm_nouveau_private *dev_priv = dev->dev_private; 1560 const int impl = dev->pci_device & 0x0ff0; 1561 1562 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1563 return true; 1564 return false; 1565} 1566 1567static inline bool 1568nv_match_device(struct drm_device *dev, unsigned device, 1569 unsigned sub_vendor, unsigned sub_device) 1570{ 1571 return dev->pdev->device == device && 1572 dev->pdev->subsystem_vendor == sub_vendor && 1573 dev->pdev->subsystem_device == sub_device; 1574} 1575 1576static inline void * 1577nv_engine(struct drm_device *dev, int engine) 1578{ 1579 struct drm_nouveau_private *dev_priv = dev->dev_private; 1580 return (void *)dev_priv->eng[engine]; 1581} 1582 1583/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1584 * helpful to determine a number of other hardware features 1585 */ 1586static inline int 1587nv44_graph_class(struct drm_device *dev) 1588{ 1589 struct drm_nouveau_private *dev_priv = dev->dev_private; 1590 1591 if ((dev_priv->chipset & 0xf0) == 0x60) 1592 return 1; 1593 1594 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1595} 1596 1597/* memory type/access flags, do not match hardware values */ 1598#define NV_MEM_ACCESS_RO 1 1599#define NV_MEM_ACCESS_WO 2 1600#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1601#define NV_MEM_ACCESS_SYS 4 1602#define NV_MEM_ACCESS_VM 8 1603 1604#define NV_MEM_TARGET_VRAM 0 1605#define NV_MEM_TARGET_PCI 1 1606#define NV_MEM_TARGET_PCI_NOSNOOP 2 1607#define NV_MEM_TARGET_VM 3 1608#define NV_MEM_TARGET_GART 4 1609 1610#define NV_MEM_TYPE_VM 0x7f 1611#define NV_MEM_COMP_VM 0x03 1612 1613/* NV_SW object class */ 1614#define NV_SW 0x0000506e 1615#define NV_SW_DMA_SEMAPHORE 0x00000060 1616#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1617#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1618#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1619#define NV_SW_YIELD 0x00000080 1620#define NV_SW_DMA_VBLSEM 0x0000018c 1621#define NV_SW_VBLSEM_OFFSET 0x00000400 1622#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1623#define NV_SW_VBLSEM_RELEASE 0x00000408 1624#define NV_SW_PAGE_FLIP 0x00000500 1625 1626#endif /* __NOUVEAU_DRV_H__ */ 1627