nouveau_drv.h revision 7948758d27be1b69b6a79ed4f3f22e36a3b95965
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78}; 79 80struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88}; 89 90struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 bool mappable; 108 bool no_vm; 109 110 uint32_t tile_mode; 111 uint32_t tile_flags; 112 struct nouveau_tile_reg *tile; 113 114 struct drm_gem_object *gem; 115 int pin_refcnt; 116}; 117 118#define nouveau_bo_tile_layout(nvbo) \ 119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 120 121static inline struct nouveau_bo * 122nouveau_bo(struct ttm_buffer_object *bo) 123{ 124 return container_of(bo, struct nouveau_bo, bo); 125} 126 127static inline struct nouveau_bo * 128nouveau_gem_object(struct drm_gem_object *gem) 129{ 130 return gem ? gem->driver_private : NULL; 131} 132 133/* TODO: submit equivalent to TTM generic API upstream? */ 134static inline void __iomem * 135nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 136{ 137 bool is_iomem; 138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 139 &nvbo->kmap, &is_iomem); 140 WARN_ON_ONCE(ioptr && !is_iomem); 141 return ioptr; 142} 143 144enum nouveau_flags { 145 NV_NFORCE = 0x10000000, 146 NV_NFORCE2 = 0x20000000 147}; 148 149#define NVOBJ_ENGINE_SW 0 150#define NVOBJ_ENGINE_GR 1 151#define NVOBJ_ENGINE_PPP 2 152#define NVOBJ_ENGINE_COPY 3 153#define NVOBJ_ENGINE_VP 4 154#define NVOBJ_ENGINE_CRYPT 5 155#define NVOBJ_ENGINE_BSP 6 156#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 157#define NVOBJ_ENGINE_INT 0xdeadbeef 158 159#define NVOBJ_FLAG_DONT_MAP (1 << 0) 160#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 161#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 162#define NVOBJ_FLAG_VM (1 << 3) 163#define NVOBJ_FLAG_VM_USER (1 << 4) 164 165#define NVOBJ_CINST_GLOBAL 0xdeadbeef 166 167struct nouveau_gpuobj { 168 struct drm_device *dev; 169 struct kref refcount; 170 struct list_head list; 171 172 void *node; 173 u32 *suspend; 174 175 uint32_t flags; 176 177 u32 size; 178 u32 pinst; 179 u32 cinst; 180 u64 vinst; 181 182 uint32_t engine; 183 uint32_t class; 184 185 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 186 void *priv; 187}; 188 189struct nouveau_page_flip_state { 190 struct list_head head; 191 struct drm_pending_vblank_event *event; 192 int crtc, bpp, pitch, x, y; 193 uint64_t offset; 194}; 195 196enum nouveau_channel_mutex_class { 197 NOUVEAU_UCHANNEL_MUTEX, 198 NOUVEAU_KCHANNEL_MUTEX 199}; 200 201struct nouveau_channel { 202 struct drm_device *dev; 203 int id; 204 205 /* references to the channel data structure */ 206 struct kref ref; 207 /* users of the hardware channel resources, the hardware 208 * context will be kicked off when it reaches zero. */ 209 atomic_t users; 210 struct mutex mutex; 211 212 /* owner of this fifo */ 213 struct drm_file *file_priv; 214 /* mapping of the fifo itself */ 215 struct drm_local_map *map; 216 217 /* mapping of the regs controling the fifo */ 218 void __iomem *user; 219 uint32_t user_get; 220 uint32_t user_put; 221 222 /* Fencing */ 223 struct { 224 /* lock protects the pending list only */ 225 spinlock_t lock; 226 struct list_head pending; 227 uint32_t sequence; 228 uint32_t sequence_ack; 229 atomic_t last_sequence_irq; 230 } fence; 231 232 /* DMA push buffer */ 233 struct nouveau_gpuobj *pushbuf; 234 struct nouveau_bo *pushbuf_bo; 235 uint32_t pushbuf_base; 236 237 /* Notifier memory */ 238 struct nouveau_bo *notifier_bo; 239 struct drm_mm notifier_heap; 240 241 /* PFIFO context */ 242 struct nouveau_gpuobj *ramfc; 243 struct nouveau_gpuobj *cache; 244 void *fifo_priv; 245 246 /* PGRAPH context */ 247 /* XXX may be merge 2 pointers as private data ??? */ 248 struct nouveau_gpuobj *ramin_grctx; 249 struct nouveau_gpuobj *crypt_ctx; 250 void *pgraph_ctx; 251 252 /* NV50 VM */ 253 struct nouveau_vm *vm; 254 struct nouveau_gpuobj *vm_pd; 255 256 /* Objects */ 257 struct nouveau_gpuobj *ramin; /* Private instmem */ 258 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 259 struct nouveau_ramht *ramht; /* Hash table */ 260 261 /* GPU object info for stuff used in-kernel (mm_enabled) */ 262 uint32_t m2mf_ntfy; 263 uint32_t vram_handle; 264 uint32_t gart_handle; 265 bool accel_done; 266 267 /* Push buffer state (only for drm's channel on !mm_enabled) */ 268 struct { 269 int max; 270 int free; 271 int cur; 272 int put; 273 /* access via pushbuf_bo */ 274 275 int ib_base; 276 int ib_max; 277 int ib_free; 278 int ib_put; 279 } dma; 280 281 uint32_t sw_subchannel[8]; 282 283 struct { 284 struct nouveau_gpuobj *vblsem; 285 uint32_t vblsem_head; 286 uint32_t vblsem_offset; 287 uint32_t vblsem_rval; 288 struct list_head vbl_wait; 289 struct list_head flip; 290 } nvsw; 291 292 struct { 293 bool active; 294 char name[32]; 295 struct drm_info_list info; 296 } debugfs; 297}; 298 299struct nouveau_instmem_engine { 300 void *priv; 301 302 int (*init)(struct drm_device *dev); 303 void (*takedown)(struct drm_device *dev); 304 int (*suspend)(struct drm_device *dev); 305 void (*resume)(struct drm_device *dev); 306 307 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 308 void (*put)(struct nouveau_gpuobj *); 309 int (*map)(struct nouveau_gpuobj *); 310 void (*unmap)(struct nouveau_gpuobj *); 311 312 void (*flush)(struct drm_device *); 313}; 314 315struct nouveau_mc_engine { 316 int (*init)(struct drm_device *dev); 317 void (*takedown)(struct drm_device *dev); 318}; 319 320struct nouveau_timer_engine { 321 int (*init)(struct drm_device *dev); 322 void (*takedown)(struct drm_device *dev); 323 uint64_t (*read)(struct drm_device *dev); 324}; 325 326struct nouveau_fb_engine { 327 int num_tiles; 328 struct drm_mm tag_heap; 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 334 void (*init_tile_region)(struct drm_device *dev, int i, 335 uint32_t addr, uint32_t size, 336 uint32_t pitch, uint32_t flags); 337 void (*set_tile_region)(struct drm_device *dev, int i); 338 void (*free_tile_region)(struct drm_device *dev, int i); 339}; 340 341struct nouveau_fifo_engine { 342 void *priv; 343 int channels; 344 345 struct nouveau_gpuobj *playlist[2]; 346 int cur_playlist; 347 348 int (*init)(struct drm_device *); 349 void (*takedown)(struct drm_device *); 350 351 void (*disable)(struct drm_device *); 352 void (*enable)(struct drm_device *); 353 bool (*reassign)(struct drm_device *, bool enable); 354 bool (*cache_pull)(struct drm_device *dev, bool enable); 355 356 int (*channel_id)(struct drm_device *); 357 358 int (*create_context)(struct nouveau_channel *); 359 void (*destroy_context)(struct nouveau_channel *); 360 int (*load_context)(struct nouveau_channel *); 361 int (*unload_context)(struct drm_device *); 362 void (*tlb_flush)(struct drm_device *dev); 363}; 364 365struct nouveau_pgraph_engine { 366 bool accel_blocked; 367 bool registered; 368 int grctx_size; 369 void *priv; 370 371 /* NV2x/NV3x context table (0x400780) */ 372 struct nouveau_gpuobj *ctx_table; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*fifo_access)(struct drm_device *, bool); 378 379 struct nouveau_channel *(*channel)(struct drm_device *); 380 int (*create_context)(struct nouveau_channel *); 381 void (*destroy_context)(struct nouveau_channel *); 382 int (*load_context)(struct nouveau_channel *); 383 int (*unload_context)(struct drm_device *); 384 void (*tlb_flush)(struct drm_device *dev); 385 386 void (*set_tile_region)(struct drm_device *dev, int i); 387}; 388 389struct nouveau_display_engine { 390 int (*early_init)(struct drm_device *); 391 void (*late_takedown)(struct drm_device *); 392 int (*create)(struct drm_device *); 393 int (*init)(struct drm_device *); 394 void (*destroy)(struct drm_device *); 395}; 396 397struct nouveau_gpio_engine { 398 void *priv; 399 400 int (*init)(struct drm_device *); 401 void (*takedown)(struct drm_device *); 402 403 int (*get)(struct drm_device *, enum dcb_gpio_tag); 404 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 405 406 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 407 void (*)(void *, int), void *); 408 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 409 void (*)(void *, int), void *); 410 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 411}; 412 413struct nouveau_pm_voltage_level { 414 u8 voltage; 415 u8 vid; 416}; 417 418struct nouveau_pm_voltage { 419 bool supported; 420 u8 vid_mask; 421 422 struct nouveau_pm_voltage_level *level; 423 int nr_level; 424}; 425 426#define NOUVEAU_PM_MAX_LEVEL 8 427struct nouveau_pm_level { 428 struct device_attribute dev_attr; 429 char name[32]; 430 int id; 431 432 u32 core; 433 u32 memory; 434 u32 shader; 435 u32 unk05; 436 437 u8 voltage; 438 u8 fanspeed; 439 440 u16 memscript; 441}; 442 443struct nouveau_pm_temp_sensor_constants { 444 u16 offset_constant; 445 s16 offset_mult; 446 u16 offset_div; 447 u16 slope_mult; 448 u16 slope_div; 449}; 450 451struct nouveau_pm_threshold_temp { 452 s16 critical; 453 s16 down_clock; 454 s16 fan_boost; 455}; 456 457struct nouveau_pm_memtiming { 458 u32 reg_100220; 459 u32 reg_100224; 460 u32 reg_100228; 461 u32 reg_10022c; 462 u32 reg_100230; 463 u32 reg_100234; 464 u32 reg_100238; 465 u32 reg_10023c; 466}; 467 468struct nouveau_pm_memtimings { 469 bool supported; 470 struct nouveau_pm_memtiming *timing; 471 int nr_timing; 472}; 473 474struct nouveau_pm_engine { 475 struct nouveau_pm_voltage voltage; 476 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 477 int nr_perflvl; 478 struct nouveau_pm_memtimings memtimings; 479 struct nouveau_pm_temp_sensor_constants sensor_constants; 480 struct nouveau_pm_threshold_temp threshold_temp; 481 482 struct nouveau_pm_level boot; 483 struct nouveau_pm_level *cur; 484 485 struct device *hwmon; 486 struct notifier_block acpi_nb; 487 488 int (*clock_get)(struct drm_device *, u32 id); 489 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 490 u32 id, int khz); 491 void (*clock_set)(struct drm_device *, void *); 492 int (*voltage_get)(struct drm_device *); 493 int (*voltage_set)(struct drm_device *, int voltage); 494 int (*fanspeed_get)(struct drm_device *); 495 int (*fanspeed_set)(struct drm_device *, int fanspeed); 496 int (*temp_get)(struct drm_device *); 497}; 498 499struct nouveau_crypt_engine { 500 bool registered; 501 502 int (*init)(struct drm_device *); 503 void (*takedown)(struct drm_device *); 504 int (*create_context)(struct nouveau_channel *); 505 void (*destroy_context)(struct nouveau_channel *); 506 void (*tlb_flush)(struct drm_device *dev); 507}; 508 509struct nouveau_vram_engine { 510 int (*init)(struct drm_device *); 511 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 512 u32 type, struct nouveau_vram **); 513 void (*put)(struct drm_device *, struct nouveau_vram **); 514 515 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 516}; 517 518struct nouveau_engine { 519 struct nouveau_instmem_engine instmem; 520 struct nouveau_mc_engine mc; 521 struct nouveau_timer_engine timer; 522 struct nouveau_fb_engine fb; 523 struct nouveau_pgraph_engine graph; 524 struct nouveau_fifo_engine fifo; 525 struct nouveau_display_engine display; 526 struct nouveau_gpio_engine gpio; 527 struct nouveau_pm_engine pm; 528 struct nouveau_crypt_engine crypt; 529 struct nouveau_vram_engine vram; 530}; 531 532struct nouveau_pll_vals { 533 union { 534 struct { 535#ifdef __BIG_ENDIAN 536 uint8_t N1, M1, N2, M2; 537#else 538 uint8_t M1, N1, M2, N2; 539#endif 540 }; 541 struct { 542 uint16_t NM1, NM2; 543 } __attribute__((packed)); 544 }; 545 int log2P; 546 547 int refclk; 548}; 549 550enum nv04_fp_display_regs { 551 FP_DISPLAY_END, 552 FP_TOTAL, 553 FP_CRTC, 554 FP_SYNC_START, 555 FP_SYNC_END, 556 FP_VALID_START, 557 FP_VALID_END 558}; 559 560struct nv04_crtc_reg { 561 unsigned char MiscOutReg; 562 uint8_t CRTC[0xa0]; 563 uint8_t CR58[0x10]; 564 uint8_t Sequencer[5]; 565 uint8_t Graphics[9]; 566 uint8_t Attribute[21]; 567 unsigned char DAC[768]; 568 569 /* PCRTC regs */ 570 uint32_t fb_start; 571 uint32_t crtc_cfg; 572 uint32_t cursor_cfg; 573 uint32_t gpio_ext; 574 uint32_t crtc_830; 575 uint32_t crtc_834; 576 uint32_t crtc_850; 577 uint32_t crtc_eng_ctrl; 578 579 /* PRAMDAC regs */ 580 uint32_t nv10_cursync; 581 struct nouveau_pll_vals pllvals; 582 uint32_t ramdac_gen_ctrl; 583 uint32_t ramdac_630; 584 uint32_t ramdac_634; 585 uint32_t tv_setup; 586 uint32_t tv_vtotal; 587 uint32_t tv_vskew; 588 uint32_t tv_vsync_delay; 589 uint32_t tv_htotal; 590 uint32_t tv_hskew; 591 uint32_t tv_hsync_delay; 592 uint32_t tv_hsync_delay2; 593 uint32_t fp_horiz_regs[7]; 594 uint32_t fp_vert_regs[7]; 595 uint32_t dither; 596 uint32_t fp_control; 597 uint32_t dither_regs[6]; 598 uint32_t fp_debug_0; 599 uint32_t fp_debug_1; 600 uint32_t fp_debug_2; 601 uint32_t fp_margin_color; 602 uint32_t ramdac_8c0; 603 uint32_t ramdac_a20; 604 uint32_t ramdac_a24; 605 uint32_t ramdac_a34; 606 uint32_t ctv_regs[38]; 607}; 608 609struct nv04_output_reg { 610 uint32_t output; 611 int head; 612}; 613 614struct nv04_mode_state { 615 struct nv04_crtc_reg crtc_reg[2]; 616 uint32_t pllsel; 617 uint32_t sel_clk; 618}; 619 620enum nouveau_card_type { 621 NV_04 = 0x00, 622 NV_10 = 0x10, 623 NV_20 = 0x20, 624 NV_30 = 0x30, 625 NV_40 = 0x40, 626 NV_50 = 0x50, 627 NV_C0 = 0xc0, 628}; 629 630struct drm_nouveau_private { 631 struct drm_device *dev; 632 633 /* the card type, takes NV_* as values */ 634 enum nouveau_card_type card_type; 635 /* exact chipset, derived from NV_PMC_BOOT_0 */ 636 int chipset; 637 int flags; 638 639 void __iomem *mmio; 640 641 spinlock_t ramin_lock; 642 void __iomem *ramin; 643 u32 ramin_size; 644 u32 ramin_base; 645 bool ramin_available; 646 struct drm_mm ramin_heap; 647 struct list_head gpuobj_list; 648 struct list_head classes; 649 650 struct nouveau_bo *vga_ram; 651 652 /* interrupt handling */ 653 void (*irq_handler[32])(struct drm_device *); 654 bool msi_enabled; 655 struct workqueue_struct *wq; 656 struct work_struct irq_work; 657 658 struct list_head vbl_waiting; 659 660 struct { 661 struct drm_global_reference mem_global_ref; 662 struct ttm_bo_global_ref bo_global_ref; 663 struct ttm_bo_device bdev; 664 atomic_t validate_sequence; 665 } ttm; 666 667 struct { 668 spinlock_t lock; 669 struct drm_mm heap; 670 struct nouveau_bo *bo; 671 } fence; 672 673 struct { 674 spinlock_t lock; 675 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 676 } channels; 677 678 struct nouveau_engine engine; 679 struct nouveau_channel *channel; 680 681 /* For PFIFO and PGRAPH. */ 682 spinlock_t context_switch_lock; 683 684 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 685 struct nouveau_ramht *ramht; 686 struct nouveau_gpuobj *ramfc; 687 struct nouveau_gpuobj *ramro; 688 689 uint32_t ramin_rsvd_vram; 690 691 struct { 692 enum { 693 NOUVEAU_GART_NONE = 0, 694 NOUVEAU_GART_AGP, /* AGP */ 695 NOUVEAU_GART_PDMA, /* paged dma object */ 696 NOUVEAU_GART_HW /* on-chip gart/vm */ 697 } type; 698 uint64_t aper_base; 699 uint64_t aper_size; 700 uint64_t aper_free; 701 702 struct ttm_backend_func *func; 703 704 struct { 705 struct page *page; 706 dma_addr_t addr; 707 } dummy; 708 709 struct nouveau_gpuobj *sg_ctxdma; 710 struct nouveau_vma vma; 711 } gart_info; 712 713 /* nv10-nv40 tiling regions */ 714 struct { 715 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 716 spinlock_t lock; 717 } tile; 718 719 /* VRAM/fb configuration */ 720 uint64_t vram_size; 721 uint64_t vram_sys_base; 722 u32 vram_rblock_size; 723 724 uint64_t fb_phys; 725 uint64_t fb_available_size; 726 uint64_t fb_mappable_pages; 727 uint64_t fb_aper_free; 728 int fb_mtrr; 729 730 /* BAR control (NV50-) */ 731 struct nouveau_vm *bar1_vm; 732 struct nouveau_vm *bar3_vm; 733 734 /* G8x/G9x virtual address space */ 735 struct nouveau_vm *chan_vm; 736 737 struct nvbios vbios; 738 739 struct nv04_mode_state mode_reg; 740 struct nv04_mode_state saved_reg; 741 uint32_t saved_vga_font[4][16384]; 742 uint32_t crtc_owner; 743 uint32_t dac_users[4]; 744 745 struct nouveau_suspend_resume { 746 uint32_t *ramin_copy; 747 } susres; 748 749 struct backlight_device *backlight; 750 751 struct nouveau_channel *evo; 752 u32 evo_alloc; 753 struct { 754 struct dcb_entry *dcb; 755 u16 script; 756 u32 pclk; 757 } evo_irq; 758 759 struct { 760 struct dentry *channel_root; 761 } debugfs; 762 763 struct nouveau_fbdev *nfbdev; 764 struct apertures_struct *apertures; 765 766 bool powered_down; 767}; 768 769static inline struct drm_nouveau_private * 770nouveau_private(struct drm_device *dev) 771{ 772 return dev->dev_private; 773} 774 775static inline struct drm_nouveau_private * 776nouveau_bdev(struct ttm_bo_device *bd) 777{ 778 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 779} 780 781static inline int 782nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 783{ 784 struct nouveau_bo *prev; 785 786 if (!pnvbo) 787 return -EINVAL; 788 prev = *pnvbo; 789 790 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 791 if (prev) { 792 struct ttm_buffer_object *bo = &prev->bo; 793 794 ttm_bo_unref(&bo); 795 } 796 797 return 0; 798} 799 800/* nouveau_drv.c */ 801extern int nouveau_agpmode; 802extern int nouveau_duallink; 803extern int nouveau_uscript_lvds; 804extern int nouveau_uscript_tmds; 805extern int nouveau_vram_pushbuf; 806extern int nouveau_vram_notify; 807extern int nouveau_fbpercrtc; 808extern int nouveau_tv_disable; 809extern char *nouveau_tv_norm; 810extern int nouveau_reg_debug; 811extern char *nouveau_vbios; 812extern int nouveau_ignorelid; 813extern int nouveau_nofbaccel; 814extern int nouveau_noaccel; 815extern int nouveau_force_post; 816extern int nouveau_override_conntype; 817extern char *nouveau_perflvl; 818extern int nouveau_perflvl_wr; 819extern int nouveau_msi; 820 821extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 822extern int nouveau_pci_resume(struct pci_dev *pdev); 823 824/* nouveau_state.c */ 825extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 826extern int nouveau_load(struct drm_device *, unsigned long flags); 827extern int nouveau_firstopen(struct drm_device *); 828extern void nouveau_lastclose(struct drm_device *); 829extern int nouveau_unload(struct drm_device *); 830extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 831 struct drm_file *); 832extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 833 struct drm_file *); 834extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 835 uint32_t reg, uint32_t mask, uint32_t val); 836extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 837 uint32_t reg, uint32_t mask, uint32_t val); 838extern bool nouveau_wait_for_idle(struct drm_device *); 839extern int nouveau_card_init(struct drm_device *); 840 841/* nouveau_mem.c */ 842extern int nouveau_mem_vram_init(struct drm_device *); 843extern void nouveau_mem_vram_fini(struct drm_device *); 844extern int nouveau_mem_gart_init(struct drm_device *); 845extern void nouveau_mem_gart_fini(struct drm_device *); 846extern int nouveau_mem_init_agp(struct drm_device *); 847extern int nouveau_mem_reset_agp(struct drm_device *); 848extern void nouveau_mem_close(struct drm_device *); 849extern int nouveau_mem_detect(struct drm_device *); 850extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 851extern struct nouveau_tile_reg *nv10_mem_set_tiling( 852 struct drm_device *dev, uint32_t addr, uint32_t size, 853 uint32_t pitch, uint32_t flags); 854extern void nv10_mem_put_tile_region(struct drm_device *dev, 855 struct nouveau_tile_reg *tile, 856 struct nouveau_fence *fence); 857extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 858 859/* nouveau_notifier.c */ 860extern int nouveau_notifier_init_channel(struct nouveau_channel *); 861extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 862extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 863 int cout, uint32_t *offset); 864extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 865extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 866 struct drm_file *); 867extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 868 struct drm_file *); 869 870/* nouveau_channel.c */ 871extern struct drm_ioctl_desc nouveau_ioctls[]; 872extern int nouveau_max_ioctl; 873extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 874extern int nouveau_channel_alloc(struct drm_device *dev, 875 struct nouveau_channel **chan, 876 struct drm_file *file_priv, 877 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 878extern struct nouveau_channel * 879nouveau_channel_get_unlocked(struct nouveau_channel *); 880extern struct nouveau_channel * 881nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 882extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 883extern void nouveau_channel_put(struct nouveau_channel **); 884extern void nouveau_channel_ref(struct nouveau_channel *chan, 885 struct nouveau_channel **pchan); 886extern void nouveau_channel_idle(struct nouveau_channel *chan); 887 888/* nouveau_object.c */ 889#define NVOBJ_CLASS(d,c,e) do { \ 890 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 891 if (ret) \ 892 return ret; \ 893} while(0) 894 895#define NVOBJ_MTHD(d,c,m,e) do { \ 896 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 897 if (ret) \ 898 return ret; \ 899} while(0) 900 901extern int nouveau_gpuobj_early_init(struct drm_device *); 902extern int nouveau_gpuobj_init(struct drm_device *); 903extern void nouveau_gpuobj_takedown(struct drm_device *); 904extern int nouveau_gpuobj_suspend(struct drm_device *dev); 905extern void nouveau_gpuobj_resume(struct drm_device *dev); 906extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 907extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 908 int (*exec)(struct nouveau_channel *, 909 u32 class, u32 mthd, u32 data)); 910extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 911extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 912extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 913 uint32_t vram_h, uint32_t tt_h); 914extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 915extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 916 uint32_t size, int align, uint32_t flags, 917 struct nouveau_gpuobj **); 918extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 919 struct nouveau_gpuobj **); 920extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 921 u32 size, u32 flags, 922 struct nouveau_gpuobj **); 923extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 924 uint64_t offset, uint64_t size, int access, 925 int target, struct nouveau_gpuobj **); 926extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 927extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 928 u64 size, int target, int access, u32 type, 929 u32 comp, struct nouveau_gpuobj **pobj); 930extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 931 int class, u64 base, u64 size, int target, 932 int access, u32 type, u32 comp); 933extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 934 struct drm_file *); 935extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 936 struct drm_file *); 937 938/* nouveau_irq.c */ 939extern int nouveau_irq_init(struct drm_device *); 940extern void nouveau_irq_fini(struct drm_device *); 941extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 942extern void nouveau_irq_register(struct drm_device *, int status_bit, 943 void (*)(struct drm_device *)); 944extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 945extern void nouveau_irq_preinstall(struct drm_device *); 946extern int nouveau_irq_postinstall(struct drm_device *); 947extern void nouveau_irq_uninstall(struct drm_device *); 948 949/* nouveau_sgdma.c */ 950extern int nouveau_sgdma_init(struct drm_device *); 951extern void nouveau_sgdma_takedown(struct drm_device *); 952extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 953 uint32_t offset); 954extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 955 956/* nouveau_debugfs.c */ 957#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 958extern int nouveau_debugfs_init(struct drm_minor *); 959extern void nouveau_debugfs_takedown(struct drm_minor *); 960extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 961extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 962#else 963static inline int 964nouveau_debugfs_init(struct drm_minor *minor) 965{ 966 return 0; 967} 968 969static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 970{ 971} 972 973static inline int 974nouveau_debugfs_channel_init(struct nouveau_channel *chan) 975{ 976 return 0; 977} 978 979static inline void 980nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 981{ 982} 983#endif 984 985/* nouveau_dma.c */ 986extern void nouveau_dma_pre_init(struct nouveau_channel *); 987extern int nouveau_dma_init(struct nouveau_channel *); 988extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 989 990/* nouveau_acpi.c */ 991#define ROM_BIOS_PAGE 4096 992#if defined(CONFIG_ACPI) 993void nouveau_register_dsm_handler(void); 994void nouveau_unregister_dsm_handler(void); 995int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 996bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 997int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 998#else 999static inline void nouveau_register_dsm_handler(void) {} 1000static inline void nouveau_unregister_dsm_handler(void) {} 1001static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1002static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1003static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1004#endif 1005 1006/* nouveau_backlight.c */ 1007#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1008extern int nouveau_backlight_init(struct drm_device *); 1009extern void nouveau_backlight_exit(struct drm_device *); 1010#else 1011static inline int nouveau_backlight_init(struct drm_device *dev) 1012{ 1013 return 0; 1014} 1015 1016static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1017#endif 1018 1019/* nouveau_bios.c */ 1020extern int nouveau_bios_init(struct drm_device *); 1021extern void nouveau_bios_takedown(struct drm_device *dev); 1022extern int nouveau_run_vbios_init(struct drm_device *); 1023extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1024 struct dcb_entry *); 1025extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1026 enum dcb_gpio_tag); 1027extern struct dcb_connector_table_entry * 1028nouveau_bios_connector_entry(struct drm_device *, int index); 1029extern u32 get_pll_register(struct drm_device *, enum pll_types); 1030extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1031 struct pll_lims *); 1032extern int nouveau_bios_run_display_table(struct drm_device *, 1033 struct dcb_entry *, 1034 uint32_t script, int pxclk); 1035extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1036 int *length); 1037extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1038extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1039extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1040 bool *dl, bool *if_is_24bit); 1041extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1042 int head, int pxclk); 1043extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1044 enum LVDS_script, int pxclk); 1045 1046/* nouveau_ttm.c */ 1047int nouveau_ttm_global_init(struct drm_nouveau_private *); 1048void nouveau_ttm_global_release(struct drm_nouveau_private *); 1049int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1050 1051/* nouveau_dp.c */ 1052int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1053 uint8_t *data, int data_nr); 1054bool nouveau_dp_detect(struct drm_encoder *); 1055bool nouveau_dp_link_train(struct drm_encoder *); 1056 1057/* nv04_fb.c */ 1058extern int nv04_fb_init(struct drm_device *); 1059extern void nv04_fb_takedown(struct drm_device *); 1060 1061/* nv10_fb.c */ 1062extern int nv10_fb_init(struct drm_device *); 1063extern void nv10_fb_takedown(struct drm_device *); 1064extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1065 uint32_t addr, uint32_t size, 1066 uint32_t pitch, uint32_t flags); 1067extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1068extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1069 1070/* nv30_fb.c */ 1071extern int nv30_fb_init(struct drm_device *); 1072extern void nv30_fb_takedown(struct drm_device *); 1073extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1074 uint32_t addr, uint32_t size, 1075 uint32_t pitch, uint32_t flags); 1076extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1077 1078/* nv40_fb.c */ 1079extern int nv40_fb_init(struct drm_device *); 1080extern void nv40_fb_takedown(struct drm_device *); 1081extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1082 1083/* nv50_fb.c */ 1084extern int nv50_fb_init(struct drm_device *); 1085extern void nv50_fb_takedown(struct drm_device *); 1086extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1087 1088/* nvc0_fb.c */ 1089extern int nvc0_fb_init(struct drm_device *); 1090extern void nvc0_fb_takedown(struct drm_device *); 1091 1092/* nv04_fifo.c */ 1093extern int nv04_fifo_init(struct drm_device *); 1094extern void nv04_fifo_fini(struct drm_device *); 1095extern void nv04_fifo_disable(struct drm_device *); 1096extern void nv04_fifo_enable(struct drm_device *); 1097extern bool nv04_fifo_reassign(struct drm_device *, bool); 1098extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1099extern int nv04_fifo_channel_id(struct drm_device *); 1100extern int nv04_fifo_create_context(struct nouveau_channel *); 1101extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1102extern int nv04_fifo_load_context(struct nouveau_channel *); 1103extern int nv04_fifo_unload_context(struct drm_device *); 1104extern void nv04_fifo_isr(struct drm_device *); 1105 1106/* nv10_fifo.c */ 1107extern int nv10_fifo_init(struct drm_device *); 1108extern int nv10_fifo_channel_id(struct drm_device *); 1109extern int nv10_fifo_create_context(struct nouveau_channel *); 1110extern int nv10_fifo_load_context(struct nouveau_channel *); 1111extern int nv10_fifo_unload_context(struct drm_device *); 1112 1113/* nv40_fifo.c */ 1114extern int nv40_fifo_init(struct drm_device *); 1115extern int nv40_fifo_create_context(struct nouveau_channel *); 1116extern int nv40_fifo_load_context(struct nouveau_channel *); 1117extern int nv40_fifo_unload_context(struct drm_device *); 1118 1119/* nv50_fifo.c */ 1120extern int nv50_fifo_init(struct drm_device *); 1121extern void nv50_fifo_takedown(struct drm_device *); 1122extern int nv50_fifo_channel_id(struct drm_device *); 1123extern int nv50_fifo_create_context(struct nouveau_channel *); 1124extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1125extern int nv50_fifo_load_context(struct nouveau_channel *); 1126extern int nv50_fifo_unload_context(struct drm_device *); 1127extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1128 1129/* nvc0_fifo.c */ 1130extern int nvc0_fifo_init(struct drm_device *); 1131extern void nvc0_fifo_takedown(struct drm_device *); 1132extern void nvc0_fifo_disable(struct drm_device *); 1133extern void nvc0_fifo_enable(struct drm_device *); 1134extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1135extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1136extern int nvc0_fifo_channel_id(struct drm_device *); 1137extern int nvc0_fifo_create_context(struct nouveau_channel *); 1138extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1139extern int nvc0_fifo_load_context(struct nouveau_channel *); 1140extern int nvc0_fifo_unload_context(struct drm_device *); 1141 1142/* nv04_graph.c */ 1143extern int nv04_graph_init(struct drm_device *); 1144extern void nv04_graph_takedown(struct drm_device *); 1145extern void nv04_graph_fifo_access(struct drm_device *, bool); 1146extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1147extern int nv04_graph_create_context(struct nouveau_channel *); 1148extern void nv04_graph_destroy_context(struct nouveau_channel *); 1149extern int nv04_graph_load_context(struct nouveau_channel *); 1150extern int nv04_graph_unload_context(struct drm_device *); 1151extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1152 u32 class, u32 mthd, u32 data); 1153extern struct nouveau_bitfield nv04_graph_nsource[]; 1154 1155/* nv10_graph.c */ 1156extern int nv10_graph_init(struct drm_device *); 1157extern void nv10_graph_takedown(struct drm_device *); 1158extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1159extern int nv10_graph_create_context(struct nouveau_channel *); 1160extern void nv10_graph_destroy_context(struct nouveau_channel *); 1161extern int nv10_graph_load_context(struct nouveau_channel *); 1162extern int nv10_graph_unload_context(struct drm_device *); 1163extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1164extern struct nouveau_bitfield nv10_graph_intr[]; 1165extern struct nouveau_bitfield nv10_graph_nstatus[]; 1166 1167/* nv20_graph.c */ 1168extern int nv20_graph_create_context(struct nouveau_channel *); 1169extern void nv20_graph_destroy_context(struct nouveau_channel *); 1170extern int nv20_graph_load_context(struct nouveau_channel *); 1171extern int nv20_graph_unload_context(struct drm_device *); 1172extern int nv20_graph_init(struct drm_device *); 1173extern void nv20_graph_takedown(struct drm_device *); 1174extern int nv30_graph_init(struct drm_device *); 1175extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1176 1177/* nv40_graph.c */ 1178extern int nv40_graph_init(struct drm_device *); 1179extern void nv40_graph_takedown(struct drm_device *); 1180extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1181extern int nv40_graph_create_context(struct nouveau_channel *); 1182extern void nv40_graph_destroy_context(struct nouveau_channel *); 1183extern int nv40_graph_load_context(struct nouveau_channel *); 1184extern int nv40_graph_unload_context(struct drm_device *); 1185extern void nv40_grctx_init(struct nouveau_grctx *); 1186extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1187 1188/* nv50_graph.c */ 1189extern int nv50_graph_init(struct drm_device *); 1190extern void nv50_graph_takedown(struct drm_device *); 1191extern void nv50_graph_fifo_access(struct drm_device *, bool); 1192extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1193extern int nv50_graph_create_context(struct nouveau_channel *); 1194extern void nv50_graph_destroy_context(struct nouveau_channel *); 1195extern int nv50_graph_load_context(struct nouveau_channel *); 1196extern int nv50_graph_unload_context(struct drm_device *); 1197extern int nv50_grctx_init(struct nouveau_grctx *); 1198extern void nv50_graph_tlb_flush(struct drm_device *dev); 1199extern void nv86_graph_tlb_flush(struct drm_device *dev); 1200extern struct nouveau_enum nv50_data_error_names[]; 1201 1202/* nvc0_graph.c */ 1203extern int nvc0_graph_init(struct drm_device *); 1204extern void nvc0_graph_takedown(struct drm_device *); 1205extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1206extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1207extern int nvc0_graph_create_context(struct nouveau_channel *); 1208extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1209extern int nvc0_graph_load_context(struct nouveau_channel *); 1210extern int nvc0_graph_unload_context(struct drm_device *); 1211 1212/* nv84_crypt.c */ 1213extern int nv84_crypt_init(struct drm_device *dev); 1214extern void nv84_crypt_fini(struct drm_device *dev); 1215extern int nv84_crypt_create_context(struct nouveau_channel *); 1216extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1217extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1218 1219/* nv04_instmem.c */ 1220extern int nv04_instmem_init(struct drm_device *); 1221extern void nv04_instmem_takedown(struct drm_device *); 1222extern int nv04_instmem_suspend(struct drm_device *); 1223extern void nv04_instmem_resume(struct drm_device *); 1224extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1225extern void nv04_instmem_put(struct nouveau_gpuobj *); 1226extern int nv04_instmem_map(struct nouveau_gpuobj *); 1227extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1228extern void nv04_instmem_flush(struct drm_device *); 1229 1230/* nv50_instmem.c */ 1231extern int nv50_instmem_init(struct drm_device *); 1232extern void nv50_instmem_takedown(struct drm_device *); 1233extern int nv50_instmem_suspend(struct drm_device *); 1234extern void nv50_instmem_resume(struct drm_device *); 1235extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1236extern void nv50_instmem_put(struct nouveau_gpuobj *); 1237extern int nv50_instmem_map(struct nouveau_gpuobj *); 1238extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1239extern void nv50_instmem_flush(struct drm_device *); 1240extern void nv84_instmem_flush(struct drm_device *); 1241 1242/* nvc0_instmem.c */ 1243extern int nvc0_instmem_init(struct drm_device *); 1244extern void nvc0_instmem_takedown(struct drm_device *); 1245extern int nvc0_instmem_suspend(struct drm_device *); 1246extern void nvc0_instmem_resume(struct drm_device *); 1247 1248/* nv04_mc.c */ 1249extern int nv04_mc_init(struct drm_device *); 1250extern void nv04_mc_takedown(struct drm_device *); 1251 1252/* nv40_mc.c */ 1253extern int nv40_mc_init(struct drm_device *); 1254extern void nv40_mc_takedown(struct drm_device *); 1255 1256/* nv50_mc.c */ 1257extern int nv50_mc_init(struct drm_device *); 1258extern void nv50_mc_takedown(struct drm_device *); 1259 1260/* nv04_timer.c */ 1261extern int nv04_timer_init(struct drm_device *); 1262extern uint64_t nv04_timer_read(struct drm_device *); 1263extern void nv04_timer_takedown(struct drm_device *); 1264 1265extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1266 unsigned long arg); 1267 1268/* nv04_dac.c */ 1269extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1270extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1271extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1272extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1273extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1274 1275/* nv04_dfp.c */ 1276extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1277extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1278extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1279 int head, bool dl); 1280extern void nv04_dfp_disable(struct drm_device *dev, int head); 1281extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1282 1283/* nv04_tv.c */ 1284extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1285extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1286 1287/* nv17_tv.c */ 1288extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1289 1290/* nv04_display.c */ 1291extern int nv04_display_early_init(struct drm_device *); 1292extern void nv04_display_late_takedown(struct drm_device *); 1293extern int nv04_display_create(struct drm_device *); 1294extern int nv04_display_init(struct drm_device *); 1295extern void nv04_display_destroy(struct drm_device *); 1296 1297/* nv04_crtc.c */ 1298extern int nv04_crtc_create(struct drm_device *, int index); 1299 1300/* nouveau_bo.c */ 1301extern struct ttm_bo_driver nouveau_bo_driver; 1302extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1303 int size, int align, uint32_t flags, 1304 uint32_t tile_mode, uint32_t tile_flags, 1305 bool no_vm, bool mappable, struct nouveau_bo **); 1306extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1307extern int nouveau_bo_unpin(struct nouveau_bo *); 1308extern int nouveau_bo_map(struct nouveau_bo *); 1309extern void nouveau_bo_unmap(struct nouveau_bo *); 1310extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1311 uint32_t busy); 1312extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1313extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1314extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1315extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1316extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1317extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1318 bool no_wait_reserve, bool no_wait_gpu); 1319 1320/* nouveau_fence.c */ 1321struct nouveau_fence; 1322extern int nouveau_fence_init(struct drm_device *); 1323extern void nouveau_fence_fini(struct drm_device *); 1324extern int nouveau_fence_channel_init(struct nouveau_channel *); 1325extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1326extern void nouveau_fence_update(struct nouveau_channel *); 1327extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1328 bool emit); 1329extern int nouveau_fence_emit(struct nouveau_fence *); 1330extern void nouveau_fence_work(struct nouveau_fence *fence, 1331 void (*work)(void *priv, bool signalled), 1332 void *priv); 1333struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1334 1335extern bool __nouveau_fence_signalled(void *obj, void *arg); 1336extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1337extern int __nouveau_fence_flush(void *obj, void *arg); 1338extern void __nouveau_fence_unref(void **obj); 1339extern void *__nouveau_fence_ref(void *obj); 1340 1341static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1342{ 1343 return __nouveau_fence_signalled(obj, NULL); 1344} 1345static inline int 1346nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1347{ 1348 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1349} 1350extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1351static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1352{ 1353 return __nouveau_fence_flush(obj, NULL); 1354} 1355static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1356{ 1357 __nouveau_fence_unref((void **)obj); 1358} 1359static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1360{ 1361 return __nouveau_fence_ref(obj); 1362} 1363 1364/* nouveau_gem.c */ 1365extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1366 int size, int align, uint32_t flags, 1367 uint32_t tile_mode, uint32_t tile_flags, 1368 bool no_vm, bool mappable, struct nouveau_bo **); 1369extern int nouveau_gem_object_new(struct drm_gem_object *); 1370extern void nouveau_gem_object_del(struct drm_gem_object *); 1371extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1372 struct drm_file *); 1373extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1374 struct drm_file *); 1375extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1376 struct drm_file *); 1377extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1378 struct drm_file *); 1379extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1380 struct drm_file *); 1381 1382/* nouveau_display.c */ 1383int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1384void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1385int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1386 struct drm_pending_vblank_event *event); 1387int nouveau_finish_page_flip(struct nouveau_channel *, 1388 struct nouveau_page_flip_state *); 1389 1390/* nv10_gpio.c */ 1391int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1392int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1393 1394/* nv50_gpio.c */ 1395int nv50_gpio_init(struct drm_device *dev); 1396void nv50_gpio_fini(struct drm_device *dev); 1397int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1398int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1399int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1400 void (*)(void *, int), void *); 1401void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1402 void (*)(void *, int), void *); 1403bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1404 1405/* nv50_calc. */ 1406int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1407 int *N1, int *M1, int *N2, int *M2, int *P); 1408int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1409 int clk, int *N, int *fN, int *M, int *P); 1410 1411#ifndef ioread32_native 1412#ifdef __BIG_ENDIAN 1413#define ioread16_native ioread16be 1414#define iowrite16_native iowrite16be 1415#define ioread32_native ioread32be 1416#define iowrite32_native iowrite32be 1417#else /* def __BIG_ENDIAN */ 1418#define ioread16_native ioread16 1419#define iowrite16_native iowrite16 1420#define ioread32_native ioread32 1421#define iowrite32_native iowrite32 1422#endif /* def __BIG_ENDIAN else */ 1423#endif /* !ioread32_native */ 1424 1425/* channel control reg access */ 1426static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1427{ 1428 return ioread32_native(chan->user + reg); 1429} 1430 1431static inline void nvchan_wr32(struct nouveau_channel *chan, 1432 unsigned reg, u32 val) 1433{ 1434 iowrite32_native(val, chan->user + reg); 1435} 1436 1437/* register access */ 1438static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 return ioread32_native(dev_priv->mmio + reg); 1442} 1443 1444static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1445{ 1446 struct drm_nouveau_private *dev_priv = dev->dev_private; 1447 iowrite32_native(val, dev_priv->mmio + reg); 1448} 1449 1450static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1451{ 1452 u32 tmp = nv_rd32(dev, reg); 1453 nv_wr32(dev, reg, (tmp & ~mask) | val); 1454 return tmp; 1455} 1456 1457static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1458{ 1459 struct drm_nouveau_private *dev_priv = dev->dev_private; 1460 return ioread8(dev_priv->mmio + reg); 1461} 1462 1463static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1464{ 1465 struct drm_nouveau_private *dev_priv = dev->dev_private; 1466 iowrite8(val, dev_priv->mmio + reg); 1467} 1468 1469#define nv_wait(dev, reg, mask, val) \ 1470 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1471#define nv_wait_ne(dev, reg, mask, val) \ 1472 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1473 1474/* PRAMIN access */ 1475static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1476{ 1477 struct drm_nouveau_private *dev_priv = dev->dev_private; 1478 return ioread32_native(dev_priv->ramin + offset); 1479} 1480 1481static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1482{ 1483 struct drm_nouveau_private *dev_priv = dev->dev_private; 1484 iowrite32_native(val, dev_priv->ramin + offset); 1485} 1486 1487/* object access */ 1488extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1489extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1490 1491/* 1492 * Logging 1493 * Argument d is (struct drm_device *). 1494 */ 1495#define NV_PRINTK(level, d, fmt, arg...) \ 1496 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1497 pci_name(d->pdev), ##arg) 1498#ifndef NV_DEBUG_NOTRACE 1499#define NV_DEBUG(d, fmt, arg...) do { \ 1500 if (drm_debug & DRM_UT_DRIVER) { \ 1501 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1502 __LINE__, ##arg); \ 1503 } \ 1504} while (0) 1505#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1506 if (drm_debug & DRM_UT_KMS) { \ 1507 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1508 __LINE__, ##arg); \ 1509 } \ 1510} while (0) 1511#else 1512#define NV_DEBUG(d, fmt, arg...) do { \ 1513 if (drm_debug & DRM_UT_DRIVER) \ 1514 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1515} while (0) 1516#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1517 if (drm_debug & DRM_UT_KMS) \ 1518 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1519} while (0) 1520#endif 1521#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1522#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1523#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1524#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1525#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1526 1527/* nouveau_reg_debug bitmask */ 1528enum { 1529 NOUVEAU_REG_DEBUG_MC = 0x1, 1530 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1531 NOUVEAU_REG_DEBUG_FB = 0x4, 1532 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1533 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1534 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1535 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1536 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1537 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1538 NOUVEAU_REG_DEBUG_EVO = 0x200, 1539}; 1540 1541#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1542 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1543 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1544} while (0) 1545 1546static inline bool 1547nv_two_heads(struct drm_device *dev) 1548{ 1549 struct drm_nouveau_private *dev_priv = dev->dev_private; 1550 const int impl = dev->pci_device & 0x0ff0; 1551 1552 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1553 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1554 return true; 1555 1556 return false; 1557} 1558 1559static inline bool 1560nv_gf4_disp_arch(struct drm_device *dev) 1561{ 1562 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1563} 1564 1565static inline bool 1566nv_two_reg_pll(struct drm_device *dev) 1567{ 1568 struct drm_nouveau_private *dev_priv = dev->dev_private; 1569 const int impl = dev->pci_device & 0x0ff0; 1570 1571 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1572 return true; 1573 return false; 1574} 1575 1576static inline bool 1577nv_match_device(struct drm_device *dev, unsigned device, 1578 unsigned sub_vendor, unsigned sub_device) 1579{ 1580 return dev->pdev->device == device && 1581 dev->pdev->subsystem_vendor == sub_vendor && 1582 dev->pdev->subsystem_device == sub_device; 1583} 1584 1585/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1586 * helpful to determine a number of other hardware features 1587 */ 1588static inline int 1589nv44_graph_class(struct drm_device *dev) 1590{ 1591 struct drm_nouveau_private *dev_priv = dev->dev_private; 1592 1593 if ((dev_priv->chipset & 0xf0) == 0x60) 1594 return 1; 1595 1596 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1597} 1598 1599/* memory type/access flags, do not match hardware values */ 1600#define NV_MEM_ACCESS_RO 1 1601#define NV_MEM_ACCESS_WO 2 1602#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1603#define NV_MEM_ACCESS_SYS 4 1604#define NV_MEM_ACCESS_VM 8 1605 1606#define NV_MEM_TARGET_VRAM 0 1607#define NV_MEM_TARGET_PCI 1 1608#define NV_MEM_TARGET_PCI_NOSNOOP 2 1609#define NV_MEM_TARGET_VM 3 1610#define NV_MEM_TARGET_GART 4 1611 1612#define NV_MEM_TYPE_VM 0x7f 1613#define NV_MEM_COMP_VM 0x03 1614 1615/* NV_SW object class */ 1616#define NV_SW 0x0000506e 1617#define NV_SW_DMA_SEMAPHORE 0x00000060 1618#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1619#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1620#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1621#define NV_SW_YIELD 0x00000080 1622#define NV_SW_DMA_VBLSEM 0x0000018c 1623#define NV_SW_VBLSEM_OFFSET 0x00000400 1624#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1625#define NV_SW_VBLSEM_RELEASE 0x00000408 1626#define NV_SW_PAGE_FLIP 0x00000500 1627 1628#endif /* __NOUVEAU_DRV_H__ */ 1629