nouveau_drv.h revision 855a95e4fc2ac6b758145ca7d6a0c95b66a57ef8
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_pull)(struct drm_device *dev, bool enable); 300 301 int (*channel_id)(struct drm_device *); 302 303 int (*create_context)(struct nouveau_channel *); 304 void (*destroy_context)(struct nouveau_channel *); 305 int (*load_context)(struct nouveau_channel *); 306 int (*unload_context)(struct drm_device *); 307}; 308 309struct nouveau_pgraph_object_method { 310 int id; 311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 312 uint32_t data); 313}; 314 315struct nouveau_pgraph_object_class { 316 int id; 317 bool software; 318 struct nouveau_pgraph_object_method *methods; 319}; 320 321struct nouveau_pgraph_engine { 322 struct nouveau_pgraph_object_class *grclass; 323 bool accel_blocked; 324 int grctx_size; 325 326 /* NV2x/NV3x context table (0x400780) */ 327 struct nouveau_gpuobj *ctx_table; 328 329 int (*init)(struct drm_device *); 330 void (*takedown)(struct drm_device *); 331 332 void (*fifo_access)(struct drm_device *, bool); 333 334 struct nouveau_channel *(*channel)(struct drm_device *); 335 int (*create_context)(struct nouveau_channel *); 336 void (*destroy_context)(struct nouveau_channel *); 337 int (*load_context)(struct nouveau_channel *); 338 int (*unload_context)(struct drm_device *); 339 340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 341 uint32_t size, uint32_t pitch); 342}; 343 344struct nouveau_display_engine { 345 int (*early_init)(struct drm_device *); 346 void (*late_takedown)(struct drm_device *); 347 int (*create)(struct drm_device *); 348 int (*init)(struct drm_device *); 349 void (*destroy)(struct drm_device *); 350}; 351 352struct nouveau_gpio_engine { 353 int (*init)(struct drm_device *); 354 void (*takedown)(struct drm_device *); 355 356 int (*get)(struct drm_device *, enum dcb_gpio_tag); 357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 358 359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 360}; 361 362struct nouveau_engine { 363 struct nouveau_instmem_engine instmem; 364 struct nouveau_mc_engine mc; 365 struct nouveau_timer_engine timer; 366 struct nouveau_fb_engine fb; 367 struct nouveau_pgraph_engine graph; 368 struct nouveau_fifo_engine fifo; 369 struct nouveau_display_engine display; 370 struct nouveau_gpio_engine gpio; 371}; 372 373struct nouveau_pll_vals { 374 union { 375 struct { 376#ifdef __BIG_ENDIAN 377 uint8_t N1, M1, N2, M2; 378#else 379 uint8_t M1, N1, M2, N2; 380#endif 381 }; 382 struct { 383 uint16_t NM1, NM2; 384 } __attribute__((packed)); 385 }; 386 int log2P; 387 388 int refclk; 389}; 390 391enum nv04_fp_display_regs { 392 FP_DISPLAY_END, 393 FP_TOTAL, 394 FP_CRTC, 395 FP_SYNC_START, 396 FP_SYNC_END, 397 FP_VALID_START, 398 FP_VALID_END 399}; 400 401struct nv04_crtc_reg { 402 unsigned char MiscOutReg; /* */ 403 uint8_t CRTC[0xa0]; 404 uint8_t CR58[0x10]; 405 uint8_t Sequencer[5]; 406 uint8_t Graphics[9]; 407 uint8_t Attribute[21]; 408 unsigned char DAC[768]; /* Internal Colorlookuptable */ 409 410 /* PCRTC regs */ 411 uint32_t fb_start; 412 uint32_t crtc_cfg; 413 uint32_t cursor_cfg; 414 uint32_t gpio_ext; 415 uint32_t crtc_830; 416 uint32_t crtc_834; 417 uint32_t crtc_850; 418 uint32_t crtc_eng_ctrl; 419 420 /* PRAMDAC regs */ 421 uint32_t nv10_cursync; 422 struct nouveau_pll_vals pllvals; 423 uint32_t ramdac_gen_ctrl; 424 uint32_t ramdac_630; 425 uint32_t ramdac_634; 426 uint32_t tv_setup; 427 uint32_t tv_vtotal; 428 uint32_t tv_vskew; 429 uint32_t tv_vsync_delay; 430 uint32_t tv_htotal; 431 uint32_t tv_hskew; 432 uint32_t tv_hsync_delay; 433 uint32_t tv_hsync_delay2; 434 uint32_t fp_horiz_regs[7]; 435 uint32_t fp_vert_regs[7]; 436 uint32_t dither; 437 uint32_t fp_control; 438 uint32_t dither_regs[6]; 439 uint32_t fp_debug_0; 440 uint32_t fp_debug_1; 441 uint32_t fp_debug_2; 442 uint32_t fp_margin_color; 443 uint32_t ramdac_8c0; 444 uint32_t ramdac_a20; 445 uint32_t ramdac_a24; 446 uint32_t ramdac_a34; 447 uint32_t ctv_regs[38]; 448}; 449 450struct nv04_output_reg { 451 uint32_t output; 452 int head; 453}; 454 455struct nv04_mode_state { 456 uint32_t bpp; 457 uint32_t width; 458 uint32_t height; 459 uint32_t interlace; 460 uint32_t repaint0; 461 uint32_t repaint1; 462 uint32_t screen; 463 uint32_t scale; 464 uint32_t dither; 465 uint32_t extra; 466 uint32_t fifo; 467 uint32_t pixel; 468 uint32_t horiz; 469 int arbitration0; 470 int arbitration1; 471 uint32_t pll; 472 uint32_t pllB; 473 uint32_t vpll; 474 uint32_t vpll2; 475 uint32_t vpllB; 476 uint32_t vpll2B; 477 uint32_t pllsel; 478 uint32_t sel_clk; 479 uint32_t general; 480 uint32_t crtcOwner; 481 uint32_t head; 482 uint32_t head2; 483 uint32_t cursorConfig; 484 uint32_t cursor0; 485 uint32_t cursor1; 486 uint32_t cursor2; 487 uint32_t timingH; 488 uint32_t timingV; 489 uint32_t displayV; 490 uint32_t crtcSync; 491 492 struct nv04_crtc_reg crtc_reg[2]; 493}; 494 495enum nouveau_card_type { 496 NV_04 = 0x00, 497 NV_10 = 0x10, 498 NV_20 = 0x20, 499 NV_30 = 0x30, 500 NV_40 = 0x40, 501 NV_50 = 0x50, 502 NV_C0 = 0xc0, 503}; 504 505struct drm_nouveau_private { 506 struct drm_device *dev; 507 508 /* the card type, takes NV_* as values */ 509 enum nouveau_card_type card_type; 510 /* exact chipset, derived from NV_PMC_BOOT_0 */ 511 int chipset; 512 int flags; 513 514 void __iomem *mmio; 515 516 spinlock_t ramin_lock; 517 void __iomem *ramin; 518 u32 ramin_size; 519 u32 ramin_base; 520 bool ramin_available; 521 struct drm_mm ramin_heap; 522 struct list_head gpuobj_list; 523 524 struct nouveau_bo *vga_ram; 525 526 struct workqueue_struct *wq; 527 struct work_struct irq_work; 528 struct work_struct hpd_work; 529 530 struct list_head vbl_waiting; 531 532 struct { 533 struct drm_global_reference mem_global_ref; 534 struct ttm_bo_global_ref bo_global_ref; 535 struct ttm_bo_device bdev; 536 atomic_t validate_sequence; 537 } ttm; 538 539 int fifo_alloc_count; 540 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 541 542 struct nouveau_engine engine; 543 struct nouveau_channel *channel; 544 545 /* For PFIFO and PGRAPH. */ 546 spinlock_t context_switch_lock; 547 548 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 549 struct nouveau_ramht *ramht; 550 struct nouveau_gpuobj *ramfc; 551 struct nouveau_gpuobj *ramro; 552 553 uint32_t ramin_rsvd_vram; 554 555 struct { 556 enum { 557 NOUVEAU_GART_NONE = 0, 558 NOUVEAU_GART_AGP, 559 NOUVEAU_GART_SGDMA 560 } type; 561 uint64_t aper_base; 562 uint64_t aper_size; 563 uint64_t aper_free; 564 565 struct nouveau_gpuobj *sg_ctxdma; 566 struct page *sg_dummy_page; 567 dma_addr_t sg_dummy_bus; 568 } gart_info; 569 570 /* nv10-nv40 tiling regions */ 571 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 572 573 /* VRAM/fb configuration */ 574 uint64_t vram_size; 575 uint64_t vram_sys_base; 576 u32 vram_rblock_size; 577 578 uint64_t fb_phys; 579 uint64_t fb_available_size; 580 uint64_t fb_mappable_pages; 581 uint64_t fb_aper_free; 582 int fb_mtrr; 583 584 /* G8x/G9x virtual address space */ 585 uint64_t vm_gart_base; 586 uint64_t vm_gart_size; 587 uint64_t vm_vram_base; 588 uint64_t vm_vram_size; 589 uint64_t vm_end; 590 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 591 int vm_vram_pt_nr; 592 593 struct nvbios vbios; 594 595 struct nv04_mode_state mode_reg; 596 struct nv04_mode_state saved_reg; 597 uint32_t saved_vga_font[4][16384]; 598 uint32_t crtc_owner; 599 uint32_t dac_users[4]; 600 601 struct nouveau_suspend_resume { 602 uint32_t *ramin_copy; 603 } susres; 604 605 struct backlight_device *backlight; 606 607 struct nouveau_channel *evo; 608 struct { 609 struct dcb_entry *dcb; 610 u16 script; 611 u32 pclk; 612 } evo_irq; 613 614 struct { 615 struct dentry *channel_root; 616 } debugfs; 617 618 struct nouveau_fbdev *nfbdev; 619 struct apertures_struct *apertures; 620}; 621 622static inline struct drm_nouveau_private * 623nouveau_bdev(struct ttm_bo_device *bd) 624{ 625 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 626} 627 628static inline int 629nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 630{ 631 struct nouveau_bo *prev; 632 633 if (!pnvbo) 634 return -EINVAL; 635 prev = *pnvbo; 636 637 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 638 if (prev) { 639 struct ttm_buffer_object *bo = &prev->bo; 640 641 ttm_bo_unref(&bo); 642 } 643 644 return 0; 645} 646 647#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 648 struct drm_nouveau_private *nv = dev->dev_private; \ 649 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 650 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 651 DRM_CURRENTPID, (id)); \ 652 return -EPERM; \ 653 } \ 654 (ch) = nv->fifos[(id)]; \ 655} while (0) 656 657/* nouveau_drv.c */ 658extern int nouveau_agpmode; 659extern int nouveau_duallink; 660extern int nouveau_uscript_lvds; 661extern int nouveau_uscript_tmds; 662extern int nouveau_vram_pushbuf; 663extern int nouveau_vram_notify; 664extern int nouveau_fbpercrtc; 665extern int nouveau_tv_disable; 666extern char *nouveau_tv_norm; 667extern int nouveau_reg_debug; 668extern char *nouveau_vbios; 669extern int nouveau_ignorelid; 670extern int nouveau_nofbaccel; 671extern int nouveau_noaccel; 672extern int nouveau_override_conntype; 673 674extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 675extern int nouveau_pci_resume(struct pci_dev *pdev); 676 677/* nouveau_state.c */ 678extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 679extern int nouveau_load(struct drm_device *, unsigned long flags); 680extern int nouveau_firstopen(struct drm_device *); 681extern void nouveau_lastclose(struct drm_device *); 682extern int nouveau_unload(struct drm_device *); 683extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 684 struct drm_file *); 685extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 686 struct drm_file *); 687extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 688 uint32_t reg, uint32_t mask, uint32_t val); 689extern bool nouveau_wait_for_idle(struct drm_device *); 690extern int nouveau_card_init(struct drm_device *); 691 692/* nouveau_mem.c */ 693extern int nouveau_mem_vram_init(struct drm_device *); 694extern void nouveau_mem_vram_fini(struct drm_device *); 695extern int nouveau_mem_gart_init(struct drm_device *); 696extern void nouveau_mem_gart_fini(struct drm_device *); 697extern int nouveau_mem_init_agp(struct drm_device *); 698extern int nouveau_mem_reset_agp(struct drm_device *); 699extern void nouveau_mem_close(struct drm_device *); 700extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 701 uint32_t addr, 702 uint32_t size, 703 uint32_t pitch); 704extern void nv10_mem_expire_tiling(struct drm_device *dev, 705 struct nouveau_tile_reg *tile, 706 struct nouveau_fence *fence); 707extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 708 uint32_t size, uint32_t flags, 709 uint64_t phys); 710extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 711 uint32_t size); 712 713/* nouveau_notifier.c */ 714extern int nouveau_notifier_init_channel(struct nouveau_channel *); 715extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 716extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 717 int cout, uint32_t *offset); 718extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 719extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 720 struct drm_file *); 721extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 722 struct drm_file *); 723 724/* nouveau_channel.c */ 725extern struct drm_ioctl_desc nouveau_ioctls[]; 726extern int nouveau_max_ioctl; 727extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 728extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 729 int channel); 730extern int nouveau_channel_alloc(struct drm_device *dev, 731 struct nouveau_channel **chan, 732 struct drm_file *file_priv, 733 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 734extern void nouveau_channel_free(struct nouveau_channel *); 735 736/* nouveau_object.c */ 737extern int nouveau_gpuobj_early_init(struct drm_device *); 738extern int nouveau_gpuobj_init(struct drm_device *); 739extern void nouveau_gpuobj_takedown(struct drm_device *); 740extern int nouveau_gpuobj_suspend(struct drm_device *dev); 741extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 742extern void nouveau_gpuobj_resume(struct drm_device *dev); 743extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 744 uint32_t vram_h, uint32_t tt_h); 745extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 746extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 747 uint32_t size, int align, uint32_t flags, 748 struct nouveau_gpuobj **); 749extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 750 struct nouveau_gpuobj **); 751extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 752 u32 size, u32 flags, 753 struct nouveau_gpuobj **); 754extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 755 uint64_t offset, uint64_t size, int access, 756 int target, struct nouveau_gpuobj **); 757extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 758 uint64_t offset, uint64_t size, 759 int access, struct nouveau_gpuobj **, 760 uint32_t *o_ret); 761extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 762 struct nouveau_gpuobj **); 763extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 764 struct nouveau_gpuobj **); 765extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 766 struct drm_file *); 767extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 768 struct drm_file *); 769 770/* nouveau_irq.c */ 771extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 772extern void nouveau_irq_preinstall(struct drm_device *); 773extern int nouveau_irq_postinstall(struct drm_device *); 774extern void nouveau_irq_uninstall(struct drm_device *); 775 776/* nouveau_sgdma.c */ 777extern int nouveau_sgdma_init(struct drm_device *); 778extern void nouveau_sgdma_takedown(struct drm_device *); 779extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 780 uint32_t *page); 781extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 782 783/* nouveau_debugfs.c */ 784#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 785extern int nouveau_debugfs_init(struct drm_minor *); 786extern void nouveau_debugfs_takedown(struct drm_minor *); 787extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 788extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 789#else 790static inline int 791nouveau_debugfs_init(struct drm_minor *minor) 792{ 793 return 0; 794} 795 796static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 797{ 798} 799 800static inline int 801nouveau_debugfs_channel_init(struct nouveau_channel *chan) 802{ 803 return 0; 804} 805 806static inline void 807nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 808{ 809} 810#endif 811 812/* nouveau_dma.c */ 813extern void nouveau_dma_pre_init(struct nouveau_channel *); 814extern int nouveau_dma_init(struct nouveau_channel *); 815extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 816 817/* nouveau_acpi.c */ 818#define ROM_BIOS_PAGE 4096 819#if defined(CONFIG_ACPI) 820void nouveau_register_dsm_handler(void); 821void nouveau_unregister_dsm_handler(void); 822int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 823bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 824int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 825#else 826static inline void nouveau_register_dsm_handler(void) {} 827static inline void nouveau_unregister_dsm_handler(void) {} 828static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 829static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 830static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 831#endif 832 833/* nouveau_backlight.c */ 834#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 835extern int nouveau_backlight_init(struct drm_device *); 836extern void nouveau_backlight_exit(struct drm_device *); 837#else 838static inline int nouveau_backlight_init(struct drm_device *dev) 839{ 840 return 0; 841} 842 843static inline void nouveau_backlight_exit(struct drm_device *dev) { } 844#endif 845 846/* nouveau_bios.c */ 847extern int nouveau_bios_init(struct drm_device *); 848extern void nouveau_bios_takedown(struct drm_device *dev); 849extern int nouveau_run_vbios_init(struct drm_device *); 850extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 851 struct dcb_entry *); 852extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 853 enum dcb_gpio_tag); 854extern struct dcb_connector_table_entry * 855nouveau_bios_connector_entry(struct drm_device *, int index); 856extern u32 get_pll_register(struct drm_device *, enum pll_types); 857extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 858 struct pll_lims *); 859extern int nouveau_bios_run_display_table(struct drm_device *, 860 struct dcb_entry *, 861 uint32_t script, int pxclk); 862extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 863 int *length); 864extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 865extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 866extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 867 bool *dl, bool *if_is_24bit); 868extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 869 int head, int pxclk); 870extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 871 enum LVDS_script, int pxclk); 872 873/* nouveau_ttm.c */ 874int nouveau_ttm_global_init(struct drm_nouveau_private *); 875void nouveau_ttm_global_release(struct drm_nouveau_private *); 876int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 877 878/* nouveau_dp.c */ 879int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 880 uint8_t *data, int data_nr); 881bool nouveau_dp_detect(struct drm_encoder *); 882bool nouveau_dp_link_train(struct drm_encoder *); 883 884/* nv04_fb.c */ 885extern int nv04_fb_init(struct drm_device *); 886extern void nv04_fb_takedown(struct drm_device *); 887 888/* nv10_fb.c */ 889extern int nv10_fb_init(struct drm_device *); 890extern void nv10_fb_takedown(struct drm_device *); 891extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 892 uint32_t, uint32_t); 893 894/* nv30_fb.c */ 895extern int nv30_fb_init(struct drm_device *); 896extern void nv30_fb_takedown(struct drm_device *); 897 898/* nv40_fb.c */ 899extern int nv40_fb_init(struct drm_device *); 900extern void nv40_fb_takedown(struct drm_device *); 901extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 902 uint32_t, uint32_t); 903/* nv50_fb.c */ 904extern int nv50_fb_init(struct drm_device *); 905extern void nv50_fb_takedown(struct drm_device *); 906extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 907 908/* nvc0_fb.c */ 909extern int nvc0_fb_init(struct drm_device *); 910extern void nvc0_fb_takedown(struct drm_device *); 911 912/* nv04_fifo.c */ 913extern int nv04_fifo_init(struct drm_device *); 914extern void nv04_fifo_disable(struct drm_device *); 915extern void nv04_fifo_enable(struct drm_device *); 916extern bool nv04_fifo_reassign(struct drm_device *, bool); 917extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 918extern int nv04_fifo_channel_id(struct drm_device *); 919extern int nv04_fifo_create_context(struct nouveau_channel *); 920extern void nv04_fifo_destroy_context(struct nouveau_channel *); 921extern int nv04_fifo_load_context(struct nouveau_channel *); 922extern int nv04_fifo_unload_context(struct drm_device *); 923 924/* nv10_fifo.c */ 925extern int nv10_fifo_init(struct drm_device *); 926extern int nv10_fifo_channel_id(struct drm_device *); 927extern int nv10_fifo_create_context(struct nouveau_channel *); 928extern void nv10_fifo_destroy_context(struct nouveau_channel *); 929extern int nv10_fifo_load_context(struct nouveau_channel *); 930extern int nv10_fifo_unload_context(struct drm_device *); 931 932/* nv40_fifo.c */ 933extern int nv40_fifo_init(struct drm_device *); 934extern int nv40_fifo_create_context(struct nouveau_channel *); 935extern void nv40_fifo_destroy_context(struct nouveau_channel *); 936extern int nv40_fifo_load_context(struct nouveau_channel *); 937extern int nv40_fifo_unload_context(struct drm_device *); 938 939/* nv50_fifo.c */ 940extern int nv50_fifo_init(struct drm_device *); 941extern void nv50_fifo_takedown(struct drm_device *); 942extern int nv50_fifo_channel_id(struct drm_device *); 943extern int nv50_fifo_create_context(struct nouveau_channel *); 944extern void nv50_fifo_destroy_context(struct nouveau_channel *); 945extern int nv50_fifo_load_context(struct nouveau_channel *); 946extern int nv50_fifo_unload_context(struct drm_device *); 947 948/* nvc0_fifo.c */ 949extern int nvc0_fifo_init(struct drm_device *); 950extern void nvc0_fifo_takedown(struct drm_device *); 951extern void nvc0_fifo_disable(struct drm_device *); 952extern void nvc0_fifo_enable(struct drm_device *); 953extern bool nvc0_fifo_reassign(struct drm_device *, bool); 954extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 955extern int nvc0_fifo_channel_id(struct drm_device *); 956extern int nvc0_fifo_create_context(struct nouveau_channel *); 957extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 958extern int nvc0_fifo_load_context(struct nouveau_channel *); 959extern int nvc0_fifo_unload_context(struct drm_device *); 960 961/* nv04_graph.c */ 962extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 963extern int nv04_graph_init(struct drm_device *); 964extern void nv04_graph_takedown(struct drm_device *); 965extern void nv04_graph_fifo_access(struct drm_device *, bool); 966extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 967extern int nv04_graph_create_context(struct nouveau_channel *); 968extern void nv04_graph_destroy_context(struct nouveau_channel *); 969extern int nv04_graph_load_context(struct nouveau_channel *); 970extern int nv04_graph_unload_context(struct drm_device *); 971extern void nv04_graph_context_switch(struct drm_device *); 972 973/* nv10_graph.c */ 974extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 975extern int nv10_graph_init(struct drm_device *); 976extern void nv10_graph_takedown(struct drm_device *); 977extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 978extern int nv10_graph_create_context(struct nouveau_channel *); 979extern void nv10_graph_destroy_context(struct nouveau_channel *); 980extern int nv10_graph_load_context(struct nouveau_channel *); 981extern int nv10_graph_unload_context(struct drm_device *); 982extern void nv10_graph_context_switch(struct drm_device *); 983extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 984 uint32_t, uint32_t); 985 986/* nv20_graph.c */ 987extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 988extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 989extern int nv20_graph_create_context(struct nouveau_channel *); 990extern void nv20_graph_destroy_context(struct nouveau_channel *); 991extern int nv20_graph_load_context(struct nouveau_channel *); 992extern int nv20_graph_unload_context(struct drm_device *); 993extern int nv20_graph_init(struct drm_device *); 994extern void nv20_graph_takedown(struct drm_device *); 995extern int nv30_graph_init(struct drm_device *); 996extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 997 uint32_t, uint32_t); 998 999/* nv40_graph.c */ 1000extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1001extern int nv40_graph_init(struct drm_device *); 1002extern void nv40_graph_takedown(struct drm_device *); 1003extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1004extern int nv40_graph_create_context(struct nouveau_channel *); 1005extern void nv40_graph_destroy_context(struct nouveau_channel *); 1006extern int nv40_graph_load_context(struct nouveau_channel *); 1007extern int nv40_graph_unload_context(struct drm_device *); 1008extern void nv40_grctx_init(struct nouveau_grctx *); 1009extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1010 uint32_t, uint32_t); 1011 1012/* nv50_graph.c */ 1013extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1014extern int nv50_graph_init(struct drm_device *); 1015extern void nv50_graph_takedown(struct drm_device *); 1016extern void nv50_graph_fifo_access(struct drm_device *, bool); 1017extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1018extern int nv50_graph_create_context(struct nouveau_channel *); 1019extern void nv50_graph_destroy_context(struct nouveau_channel *); 1020extern int nv50_graph_load_context(struct nouveau_channel *); 1021extern int nv50_graph_unload_context(struct drm_device *); 1022extern void nv50_graph_context_switch(struct drm_device *); 1023extern int nv50_grctx_init(struct nouveau_grctx *); 1024 1025/* nvc0_graph.c */ 1026extern int nvc0_graph_init(struct drm_device *); 1027extern void nvc0_graph_takedown(struct drm_device *); 1028extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1029extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1030extern int nvc0_graph_create_context(struct nouveau_channel *); 1031extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1032extern int nvc0_graph_load_context(struct nouveau_channel *); 1033extern int nvc0_graph_unload_context(struct drm_device *); 1034 1035/* nv04_instmem.c */ 1036extern int nv04_instmem_init(struct drm_device *); 1037extern void nv04_instmem_takedown(struct drm_device *); 1038extern int nv04_instmem_suspend(struct drm_device *); 1039extern void nv04_instmem_resume(struct drm_device *); 1040extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1041 uint32_t *size); 1042extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1043extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1044extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1045extern void nv04_instmem_flush(struct drm_device *); 1046 1047/* nv50_instmem.c */ 1048extern int nv50_instmem_init(struct drm_device *); 1049extern void nv50_instmem_takedown(struct drm_device *); 1050extern int nv50_instmem_suspend(struct drm_device *); 1051extern void nv50_instmem_resume(struct drm_device *); 1052extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1053 uint32_t *size); 1054extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1055extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1056extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1057extern void nv50_instmem_flush(struct drm_device *); 1058extern void nv84_instmem_flush(struct drm_device *); 1059extern void nv50_vm_flush(struct drm_device *, int engine); 1060 1061/* nvc0_instmem.c */ 1062extern int nvc0_instmem_init(struct drm_device *); 1063extern void nvc0_instmem_takedown(struct drm_device *); 1064extern int nvc0_instmem_suspend(struct drm_device *); 1065extern void nvc0_instmem_resume(struct drm_device *); 1066extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1067 uint32_t *size); 1068extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1069extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1070extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1071extern void nvc0_instmem_flush(struct drm_device *); 1072 1073/* nv04_mc.c */ 1074extern int nv04_mc_init(struct drm_device *); 1075extern void nv04_mc_takedown(struct drm_device *); 1076 1077/* nv40_mc.c */ 1078extern int nv40_mc_init(struct drm_device *); 1079extern void nv40_mc_takedown(struct drm_device *); 1080 1081/* nv50_mc.c */ 1082extern int nv50_mc_init(struct drm_device *); 1083extern void nv50_mc_takedown(struct drm_device *); 1084 1085/* nv04_timer.c */ 1086extern int nv04_timer_init(struct drm_device *); 1087extern uint64_t nv04_timer_read(struct drm_device *); 1088extern void nv04_timer_takedown(struct drm_device *); 1089 1090extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1091 unsigned long arg); 1092 1093/* nv04_dac.c */ 1094extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1095extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1096extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1097extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1098extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1099 1100/* nv04_dfp.c */ 1101extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1102extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1103extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1104 int head, bool dl); 1105extern void nv04_dfp_disable(struct drm_device *dev, int head); 1106extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1107 1108/* nv04_tv.c */ 1109extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1110extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1111 1112/* nv17_tv.c */ 1113extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1114 1115/* nv04_display.c */ 1116extern int nv04_display_early_init(struct drm_device *); 1117extern void nv04_display_late_takedown(struct drm_device *); 1118extern int nv04_display_create(struct drm_device *); 1119extern int nv04_display_init(struct drm_device *); 1120extern void nv04_display_destroy(struct drm_device *); 1121 1122/* nv04_crtc.c */ 1123extern int nv04_crtc_create(struct drm_device *, int index); 1124 1125/* nouveau_bo.c */ 1126extern struct ttm_bo_driver nouveau_bo_driver; 1127extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1128 int size, int align, uint32_t flags, 1129 uint32_t tile_mode, uint32_t tile_flags, 1130 bool no_vm, bool mappable, struct nouveau_bo **); 1131extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1132extern int nouveau_bo_unpin(struct nouveau_bo *); 1133extern int nouveau_bo_map(struct nouveau_bo *); 1134extern void nouveau_bo_unmap(struct nouveau_bo *); 1135extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1136 uint32_t busy); 1137extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1138extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1139extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1140extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1141extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1142 1143/* nouveau_fence.c */ 1144struct nouveau_fence; 1145extern int nouveau_fence_init(struct nouveau_channel *); 1146extern void nouveau_fence_fini(struct nouveau_channel *); 1147extern void nouveau_fence_update(struct nouveau_channel *); 1148extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1149 bool emit); 1150extern int nouveau_fence_emit(struct nouveau_fence *); 1151struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1152extern bool nouveau_fence_signalled(void *obj, void *arg); 1153extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1154extern int nouveau_fence_flush(void *obj, void *arg); 1155extern void nouveau_fence_unref(void **obj); 1156extern void *nouveau_fence_ref(void *obj); 1157 1158/* nouveau_gem.c */ 1159extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1160 int size, int align, uint32_t flags, 1161 uint32_t tile_mode, uint32_t tile_flags, 1162 bool no_vm, bool mappable, struct nouveau_bo **); 1163extern int nouveau_gem_object_new(struct drm_gem_object *); 1164extern void nouveau_gem_object_del(struct drm_gem_object *); 1165extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1166 struct drm_file *); 1167extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1168 struct drm_file *); 1169extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1170 struct drm_file *); 1171extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1172 struct drm_file *); 1173extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1174 struct drm_file *); 1175 1176/* nv10_gpio.c */ 1177int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1178int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1179 1180/* nv50_gpio.c */ 1181int nv50_gpio_init(struct drm_device *dev); 1182int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1183int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1184void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1185 1186/* nv50_calc. */ 1187int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1188 int *N1, int *M1, int *N2, int *M2, int *P); 1189int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1190 int clk, int *N, int *fN, int *M, int *P); 1191 1192#ifndef ioread32_native 1193#ifdef __BIG_ENDIAN 1194#define ioread16_native ioread16be 1195#define iowrite16_native iowrite16be 1196#define ioread32_native ioread32be 1197#define iowrite32_native iowrite32be 1198#else /* def __BIG_ENDIAN */ 1199#define ioread16_native ioread16 1200#define iowrite16_native iowrite16 1201#define ioread32_native ioread32 1202#define iowrite32_native iowrite32 1203#endif /* def __BIG_ENDIAN else */ 1204#endif /* !ioread32_native */ 1205 1206/* channel control reg access */ 1207static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1208{ 1209 return ioread32_native(chan->user + reg); 1210} 1211 1212static inline void nvchan_wr32(struct nouveau_channel *chan, 1213 unsigned reg, u32 val) 1214{ 1215 iowrite32_native(val, chan->user + reg); 1216} 1217 1218/* register access */ 1219static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1220{ 1221 struct drm_nouveau_private *dev_priv = dev->dev_private; 1222 return ioread32_native(dev_priv->mmio + reg); 1223} 1224 1225static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1226{ 1227 struct drm_nouveau_private *dev_priv = dev->dev_private; 1228 iowrite32_native(val, dev_priv->mmio + reg); 1229} 1230 1231static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1232{ 1233 u32 tmp = nv_rd32(dev, reg); 1234 nv_wr32(dev, reg, (tmp & ~mask) | val); 1235 return tmp; 1236} 1237 1238static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1239{ 1240 struct drm_nouveau_private *dev_priv = dev->dev_private; 1241 return ioread8(dev_priv->mmio + reg); 1242} 1243 1244static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1245{ 1246 struct drm_nouveau_private *dev_priv = dev->dev_private; 1247 iowrite8(val, dev_priv->mmio + reg); 1248} 1249 1250#define nv_wait(dev, reg, mask, val) \ 1251 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1252 1253/* PRAMIN access */ 1254static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1255{ 1256 struct drm_nouveau_private *dev_priv = dev->dev_private; 1257 return ioread32_native(dev_priv->ramin + offset); 1258} 1259 1260static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1261{ 1262 struct drm_nouveau_private *dev_priv = dev->dev_private; 1263 iowrite32_native(val, dev_priv->ramin + offset); 1264} 1265 1266/* object access */ 1267extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1268extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1269 1270/* 1271 * Logging 1272 * Argument d is (struct drm_device *). 1273 */ 1274#define NV_PRINTK(level, d, fmt, arg...) \ 1275 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1276 pci_name(d->pdev), ##arg) 1277#ifndef NV_DEBUG_NOTRACE 1278#define NV_DEBUG(d, fmt, arg...) do { \ 1279 if (drm_debug & DRM_UT_DRIVER) { \ 1280 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1281 __LINE__, ##arg); \ 1282 } \ 1283} while (0) 1284#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1285 if (drm_debug & DRM_UT_KMS) { \ 1286 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1287 __LINE__, ##arg); \ 1288 } \ 1289} while (0) 1290#else 1291#define NV_DEBUG(d, fmt, arg...) do { \ 1292 if (drm_debug & DRM_UT_DRIVER) \ 1293 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1294} while (0) 1295#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1296 if (drm_debug & DRM_UT_KMS) \ 1297 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1298} while (0) 1299#endif 1300#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1301#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1302#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1303#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1304#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1305 1306/* nouveau_reg_debug bitmask */ 1307enum { 1308 NOUVEAU_REG_DEBUG_MC = 0x1, 1309 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1310 NOUVEAU_REG_DEBUG_FB = 0x4, 1311 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1312 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1313 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1314 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1315 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1316 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1317 NOUVEAU_REG_DEBUG_EVO = 0x200, 1318}; 1319 1320#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1321 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1322 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1323} while (0) 1324 1325static inline bool 1326nv_two_heads(struct drm_device *dev) 1327{ 1328 struct drm_nouveau_private *dev_priv = dev->dev_private; 1329 const int impl = dev->pci_device & 0x0ff0; 1330 1331 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1332 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1333 return true; 1334 1335 return false; 1336} 1337 1338static inline bool 1339nv_gf4_disp_arch(struct drm_device *dev) 1340{ 1341 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1342} 1343 1344static inline bool 1345nv_two_reg_pll(struct drm_device *dev) 1346{ 1347 struct drm_nouveau_private *dev_priv = dev->dev_private; 1348 const int impl = dev->pci_device & 0x0ff0; 1349 1350 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1351 return true; 1352 return false; 1353} 1354 1355static inline bool 1356nv_match_device(struct drm_device *dev, unsigned device, 1357 unsigned sub_vendor, unsigned sub_device) 1358{ 1359 return dev->pdev->device == device && 1360 dev->pdev->subsystem_vendor == sub_vendor && 1361 dev->pdev->subsystem_device == sub_device; 1362} 1363 1364#define NV_SW 0x0000506e 1365#define NV_SW_DMA_SEMAPHORE 0x00000060 1366#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1367#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1368#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1369#define NV_SW_DMA_VBLSEM 0x0000018c 1370#define NV_SW_VBLSEM_OFFSET 0x00000400 1371#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1372#define NV_SW_VBLSEM_RELEASE 0x00000408 1373 1374#endif /* __NOUVEAU_DRV_H__ */ 1375