nouveau_drv.h revision 8984e046153eb1d6b0b24626169f9c6e58232e1b
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78}; 79 80struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88}; 89 90struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 bool mappable; 108 bool no_vm; 109 110 uint32_t tile_mode; 111 uint32_t tile_flags; 112 struct nouveau_tile_reg *tile; 113 114 struct drm_gem_object *gem; 115 int pin_refcnt; 116}; 117 118#define nouveau_bo_tile_layout(nvbo) \ 119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 120 121static inline struct nouveau_bo * 122nouveau_bo(struct ttm_buffer_object *bo) 123{ 124 return container_of(bo, struct nouveau_bo, bo); 125} 126 127static inline struct nouveau_bo * 128nouveau_gem_object(struct drm_gem_object *gem) 129{ 130 return gem ? gem->driver_private : NULL; 131} 132 133/* TODO: submit equivalent to TTM generic API upstream? */ 134static inline void __iomem * 135nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 136{ 137 bool is_iomem; 138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 139 &nvbo->kmap, &is_iomem); 140 WARN_ON_ONCE(ioptr && !is_iomem); 141 return ioptr; 142} 143 144enum nouveau_flags { 145 NV_NFORCE = 0x10000000, 146 NV_NFORCE2 = 0x20000000 147}; 148 149#define NVOBJ_ENGINE_SW 0 150#define NVOBJ_ENGINE_GR 1 151#define NVOBJ_ENGINE_PPP 2 152#define NVOBJ_ENGINE_COPY 3 153#define NVOBJ_ENGINE_VP 4 154#define NVOBJ_ENGINE_CRYPT 5 155#define NVOBJ_ENGINE_BSP 6 156#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 157#define NVOBJ_ENGINE_INT 0xdeadbeef 158 159#define NVOBJ_FLAG_DONT_MAP (1 << 0) 160#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 161#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 162#define NVOBJ_FLAG_VM (1 << 3) 163 164#define NVOBJ_CINST_GLOBAL 0xdeadbeef 165 166struct nouveau_gpuobj { 167 struct drm_device *dev; 168 struct kref refcount; 169 struct list_head list; 170 171 void *node; 172 u32 *suspend; 173 174 uint32_t flags; 175 176 u32 size; 177 u32 pinst; 178 u32 cinst; 179 u64 vinst; 180 181 uint32_t engine; 182 uint32_t class; 183 184 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 185 void *priv; 186}; 187 188struct nouveau_page_flip_state { 189 struct list_head head; 190 struct drm_pending_vblank_event *event; 191 int crtc, bpp, pitch, x, y; 192 uint64_t offset; 193}; 194 195enum nouveau_channel_mutex_class { 196 NOUVEAU_UCHANNEL_MUTEX, 197 NOUVEAU_KCHANNEL_MUTEX 198}; 199 200struct nouveau_channel { 201 struct drm_device *dev; 202 int id; 203 204 /* references to the channel data structure */ 205 struct kref ref; 206 /* users of the hardware channel resources, the hardware 207 * context will be kicked off when it reaches zero. */ 208 atomic_t users; 209 struct mutex mutex; 210 211 /* owner of this fifo */ 212 struct drm_file *file_priv; 213 /* mapping of the fifo itself */ 214 struct drm_local_map *map; 215 216 /* mapping of the regs controling the fifo */ 217 void __iomem *user; 218 uint32_t user_get; 219 uint32_t user_put; 220 221 /* Fencing */ 222 struct { 223 /* lock protects the pending list only */ 224 spinlock_t lock; 225 struct list_head pending; 226 uint32_t sequence; 227 uint32_t sequence_ack; 228 atomic_t last_sequence_irq; 229 } fence; 230 231 /* DMA push buffer */ 232 struct nouveau_gpuobj *pushbuf; 233 struct nouveau_bo *pushbuf_bo; 234 uint32_t pushbuf_base; 235 236 /* Notifier memory */ 237 struct nouveau_bo *notifier_bo; 238 struct drm_mm notifier_heap; 239 240 /* PFIFO context */ 241 struct nouveau_gpuobj *ramfc; 242 struct nouveau_gpuobj *cache; 243 244 /* PGRAPH context */ 245 /* XXX may be merge 2 pointers as private data ??? */ 246 struct nouveau_gpuobj *ramin_grctx; 247 struct nouveau_gpuobj *crypt_ctx; 248 void *pgraph_ctx; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295}; 296 297struct nouveau_instmem_engine { 298 void *priv; 299 300 int (*init)(struct drm_device *dev); 301 void (*takedown)(struct drm_device *dev); 302 int (*suspend)(struct drm_device *dev); 303 void (*resume)(struct drm_device *dev); 304 305 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 306 void (*put)(struct nouveau_gpuobj *); 307 int (*map)(struct nouveau_gpuobj *); 308 void (*unmap)(struct nouveau_gpuobj *); 309 310 void (*flush)(struct drm_device *); 311}; 312 313struct nouveau_mc_engine { 314 int (*init)(struct drm_device *dev); 315 void (*takedown)(struct drm_device *dev); 316}; 317 318struct nouveau_timer_engine { 319 int (*init)(struct drm_device *dev); 320 void (*takedown)(struct drm_device *dev); 321 uint64_t (*read)(struct drm_device *dev); 322}; 323 324struct nouveau_fb_engine { 325 int num_tiles; 326 struct drm_mm tag_heap; 327 void *priv; 328 329 int (*init)(struct drm_device *dev); 330 void (*takedown)(struct drm_device *dev); 331 332 void (*init_tile_region)(struct drm_device *dev, int i, 333 uint32_t addr, uint32_t size, 334 uint32_t pitch, uint32_t flags); 335 void (*set_tile_region)(struct drm_device *dev, int i); 336 void (*free_tile_region)(struct drm_device *dev, int i); 337}; 338 339struct nouveau_fifo_engine { 340 int channels; 341 342 struct nouveau_gpuobj *playlist[2]; 343 int cur_playlist; 344 345 int (*init)(struct drm_device *); 346 void (*takedown)(struct drm_device *); 347 348 void (*disable)(struct drm_device *); 349 void (*enable)(struct drm_device *); 350 bool (*reassign)(struct drm_device *, bool enable); 351 bool (*cache_pull)(struct drm_device *dev, bool enable); 352 353 int (*channel_id)(struct drm_device *); 354 355 int (*create_context)(struct nouveau_channel *); 356 void (*destroy_context)(struct nouveau_channel *); 357 int (*load_context)(struct nouveau_channel *); 358 int (*unload_context)(struct drm_device *); 359 void (*tlb_flush)(struct drm_device *dev); 360}; 361 362struct nouveau_pgraph_engine { 363 bool accel_blocked; 364 bool registered; 365 int grctx_size; 366 367 /* NV2x/NV3x context table (0x400780) */ 368 struct nouveau_gpuobj *ctx_table; 369 370 int (*init)(struct drm_device *); 371 void (*takedown)(struct drm_device *); 372 373 void (*fifo_access)(struct drm_device *, bool); 374 375 struct nouveau_channel *(*channel)(struct drm_device *); 376 int (*create_context)(struct nouveau_channel *); 377 void (*destroy_context)(struct nouveau_channel *); 378 int (*load_context)(struct nouveau_channel *); 379 int (*unload_context)(struct drm_device *); 380 void (*tlb_flush)(struct drm_device *dev); 381 382 void (*set_tile_region)(struct drm_device *dev, int i); 383}; 384 385struct nouveau_display_engine { 386 int (*early_init)(struct drm_device *); 387 void (*late_takedown)(struct drm_device *); 388 int (*create)(struct drm_device *); 389 int (*init)(struct drm_device *); 390 void (*destroy)(struct drm_device *); 391}; 392 393struct nouveau_gpio_engine { 394 void *priv; 395 396 int (*init)(struct drm_device *); 397 void (*takedown)(struct drm_device *); 398 399 int (*get)(struct drm_device *, enum dcb_gpio_tag); 400 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 401 402 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 403 void (*)(void *, int), void *); 404 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 405 void (*)(void *, int), void *); 406 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 407}; 408 409struct nouveau_pm_voltage_level { 410 u8 voltage; 411 u8 vid; 412}; 413 414struct nouveau_pm_voltage { 415 bool supported; 416 u8 vid_mask; 417 418 struct nouveau_pm_voltage_level *level; 419 int nr_level; 420}; 421 422#define NOUVEAU_PM_MAX_LEVEL 8 423struct nouveau_pm_level { 424 struct device_attribute dev_attr; 425 char name[32]; 426 int id; 427 428 u32 core; 429 u32 memory; 430 u32 shader; 431 u32 unk05; 432 433 u8 voltage; 434 u8 fanspeed; 435 436 u16 memscript; 437}; 438 439struct nouveau_pm_temp_sensor_constants { 440 u16 offset_constant; 441 s16 offset_mult; 442 u16 offset_div; 443 u16 slope_mult; 444 u16 slope_div; 445}; 446 447struct nouveau_pm_threshold_temp { 448 s16 critical; 449 s16 down_clock; 450 s16 fan_boost; 451}; 452 453struct nouveau_pm_memtiming { 454 u32 reg_100220; 455 u32 reg_100224; 456 u32 reg_100228; 457 u32 reg_10022c; 458 u32 reg_100230; 459 u32 reg_100234; 460 u32 reg_100238; 461 u32 reg_10023c; 462}; 463 464struct nouveau_pm_memtimings { 465 bool supported; 466 struct nouveau_pm_memtiming *timing; 467 int nr_timing; 468}; 469 470struct nouveau_pm_engine { 471 struct nouveau_pm_voltage voltage; 472 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 473 int nr_perflvl; 474 struct nouveau_pm_memtimings memtimings; 475 struct nouveau_pm_temp_sensor_constants sensor_constants; 476 struct nouveau_pm_threshold_temp threshold_temp; 477 478 struct nouveau_pm_level boot; 479 struct nouveau_pm_level *cur; 480 481 struct device *hwmon; 482 struct notifier_block acpi_nb; 483 484 int (*clock_get)(struct drm_device *, u32 id); 485 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 486 u32 id, int khz); 487 void (*clock_set)(struct drm_device *, void *); 488 int (*voltage_get)(struct drm_device *); 489 int (*voltage_set)(struct drm_device *, int voltage); 490 int (*fanspeed_get)(struct drm_device *); 491 int (*fanspeed_set)(struct drm_device *, int fanspeed); 492 int (*temp_get)(struct drm_device *); 493}; 494 495struct nouveau_crypt_engine { 496 bool registered; 497 498 int (*init)(struct drm_device *); 499 void (*takedown)(struct drm_device *); 500 int (*create_context)(struct nouveau_channel *); 501 void (*destroy_context)(struct nouveau_channel *); 502 void (*tlb_flush)(struct drm_device *dev); 503}; 504 505struct nouveau_vram_engine { 506 int (*init)(struct drm_device *); 507 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 508 u32 type, struct nouveau_vram **); 509 void (*put)(struct drm_device *, struct nouveau_vram **); 510 511 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 512}; 513 514struct nouveau_engine { 515 struct nouveau_instmem_engine instmem; 516 struct nouveau_mc_engine mc; 517 struct nouveau_timer_engine timer; 518 struct nouveau_fb_engine fb; 519 struct nouveau_pgraph_engine graph; 520 struct nouveau_fifo_engine fifo; 521 struct nouveau_display_engine display; 522 struct nouveau_gpio_engine gpio; 523 struct nouveau_pm_engine pm; 524 struct nouveau_crypt_engine crypt; 525 struct nouveau_vram_engine vram; 526}; 527 528struct nouveau_pll_vals { 529 union { 530 struct { 531#ifdef __BIG_ENDIAN 532 uint8_t N1, M1, N2, M2; 533#else 534 uint8_t M1, N1, M2, N2; 535#endif 536 }; 537 struct { 538 uint16_t NM1, NM2; 539 } __attribute__((packed)); 540 }; 541 int log2P; 542 543 int refclk; 544}; 545 546enum nv04_fp_display_regs { 547 FP_DISPLAY_END, 548 FP_TOTAL, 549 FP_CRTC, 550 FP_SYNC_START, 551 FP_SYNC_END, 552 FP_VALID_START, 553 FP_VALID_END 554}; 555 556struct nv04_crtc_reg { 557 unsigned char MiscOutReg; 558 uint8_t CRTC[0xa0]; 559 uint8_t CR58[0x10]; 560 uint8_t Sequencer[5]; 561 uint8_t Graphics[9]; 562 uint8_t Attribute[21]; 563 unsigned char DAC[768]; 564 565 /* PCRTC regs */ 566 uint32_t fb_start; 567 uint32_t crtc_cfg; 568 uint32_t cursor_cfg; 569 uint32_t gpio_ext; 570 uint32_t crtc_830; 571 uint32_t crtc_834; 572 uint32_t crtc_850; 573 uint32_t crtc_eng_ctrl; 574 575 /* PRAMDAC regs */ 576 uint32_t nv10_cursync; 577 struct nouveau_pll_vals pllvals; 578 uint32_t ramdac_gen_ctrl; 579 uint32_t ramdac_630; 580 uint32_t ramdac_634; 581 uint32_t tv_setup; 582 uint32_t tv_vtotal; 583 uint32_t tv_vskew; 584 uint32_t tv_vsync_delay; 585 uint32_t tv_htotal; 586 uint32_t tv_hskew; 587 uint32_t tv_hsync_delay; 588 uint32_t tv_hsync_delay2; 589 uint32_t fp_horiz_regs[7]; 590 uint32_t fp_vert_regs[7]; 591 uint32_t dither; 592 uint32_t fp_control; 593 uint32_t dither_regs[6]; 594 uint32_t fp_debug_0; 595 uint32_t fp_debug_1; 596 uint32_t fp_debug_2; 597 uint32_t fp_margin_color; 598 uint32_t ramdac_8c0; 599 uint32_t ramdac_a20; 600 uint32_t ramdac_a24; 601 uint32_t ramdac_a34; 602 uint32_t ctv_regs[38]; 603}; 604 605struct nv04_output_reg { 606 uint32_t output; 607 int head; 608}; 609 610struct nv04_mode_state { 611 struct nv04_crtc_reg crtc_reg[2]; 612 uint32_t pllsel; 613 uint32_t sel_clk; 614}; 615 616enum nouveau_card_type { 617 NV_04 = 0x00, 618 NV_10 = 0x10, 619 NV_20 = 0x20, 620 NV_30 = 0x30, 621 NV_40 = 0x40, 622 NV_50 = 0x50, 623 NV_C0 = 0xc0, 624}; 625 626struct drm_nouveau_private { 627 struct drm_device *dev; 628 629 /* the card type, takes NV_* as values */ 630 enum nouveau_card_type card_type; 631 /* exact chipset, derived from NV_PMC_BOOT_0 */ 632 int chipset; 633 int flags; 634 635 void __iomem *mmio; 636 637 spinlock_t ramin_lock; 638 void __iomem *ramin; 639 u32 ramin_size; 640 u32 ramin_base; 641 bool ramin_available; 642 struct drm_mm ramin_heap; 643 struct list_head gpuobj_list; 644 struct list_head classes; 645 646 struct nouveau_bo *vga_ram; 647 648 /* interrupt handling */ 649 void (*irq_handler[32])(struct drm_device *); 650 bool msi_enabled; 651 struct workqueue_struct *wq; 652 struct work_struct irq_work; 653 654 struct list_head vbl_waiting; 655 656 struct { 657 struct drm_global_reference mem_global_ref; 658 struct ttm_bo_global_ref bo_global_ref; 659 struct ttm_bo_device bdev; 660 atomic_t validate_sequence; 661 } ttm; 662 663 struct { 664 spinlock_t lock; 665 struct drm_mm heap; 666 struct nouveau_bo *bo; 667 } fence; 668 669 struct { 670 spinlock_t lock; 671 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 672 } channels; 673 674 struct nouveau_engine engine; 675 struct nouveau_channel *channel; 676 677 /* For PFIFO and PGRAPH. */ 678 spinlock_t context_switch_lock; 679 680 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 681 struct nouveau_ramht *ramht; 682 struct nouveau_gpuobj *ramfc; 683 struct nouveau_gpuobj *ramro; 684 685 uint32_t ramin_rsvd_vram; 686 687 struct { 688 enum { 689 NOUVEAU_GART_NONE = 0, 690 NOUVEAU_GART_AGP, 691 NOUVEAU_GART_SGDMA 692 } type; 693 uint64_t aper_base; 694 uint64_t aper_size; 695 uint64_t aper_free; 696 697 struct nouveau_gpuobj *sg_ctxdma; 698 struct nouveau_vma vma; 699 } gart_info; 700 701 /* nv10-nv40 tiling regions */ 702 struct { 703 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 704 spinlock_t lock; 705 } tile; 706 707 /* VRAM/fb configuration */ 708 uint64_t vram_size; 709 uint64_t vram_sys_base; 710 u32 vram_rblock_size; 711 712 uint64_t fb_phys; 713 uint64_t fb_available_size; 714 uint64_t fb_mappable_pages; 715 uint64_t fb_aper_free; 716 int fb_mtrr; 717 718 /* BAR control (NV50-) */ 719 struct nouveau_vm *bar1_vm; 720 struct nouveau_vm *bar3_vm; 721 722 /* G8x/G9x virtual address space */ 723 struct nouveau_vm *chan_vm; 724 725 struct nvbios vbios; 726 727 struct nv04_mode_state mode_reg; 728 struct nv04_mode_state saved_reg; 729 uint32_t saved_vga_font[4][16384]; 730 uint32_t crtc_owner; 731 uint32_t dac_users[4]; 732 733 struct nouveau_suspend_resume { 734 uint32_t *ramin_copy; 735 } susres; 736 737 struct backlight_device *backlight; 738 739 struct nouveau_channel *evo; 740 u32 evo_alloc; 741 struct { 742 struct dcb_entry *dcb; 743 u16 script; 744 u32 pclk; 745 } evo_irq; 746 747 struct { 748 struct dentry *channel_root; 749 } debugfs; 750 751 struct nouveau_fbdev *nfbdev; 752 struct apertures_struct *apertures; 753}; 754 755static inline struct drm_nouveau_private * 756nouveau_private(struct drm_device *dev) 757{ 758 return dev->dev_private; 759} 760 761static inline struct drm_nouveau_private * 762nouveau_bdev(struct ttm_bo_device *bd) 763{ 764 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 765} 766 767static inline int 768nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 769{ 770 struct nouveau_bo *prev; 771 772 if (!pnvbo) 773 return -EINVAL; 774 prev = *pnvbo; 775 776 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 777 if (prev) { 778 struct ttm_buffer_object *bo = &prev->bo; 779 780 ttm_bo_unref(&bo); 781 } 782 783 return 0; 784} 785 786/* nouveau_drv.c */ 787extern int nouveau_agpmode; 788extern int nouveau_duallink; 789extern int nouveau_uscript_lvds; 790extern int nouveau_uscript_tmds; 791extern int nouveau_vram_pushbuf; 792extern int nouveau_vram_notify; 793extern int nouveau_fbpercrtc; 794extern int nouveau_tv_disable; 795extern char *nouveau_tv_norm; 796extern int nouveau_reg_debug; 797extern char *nouveau_vbios; 798extern int nouveau_ignorelid; 799extern int nouveau_nofbaccel; 800extern int nouveau_noaccel; 801extern int nouveau_force_post; 802extern int nouveau_override_conntype; 803extern char *nouveau_perflvl; 804extern int nouveau_perflvl_wr; 805extern int nouveau_msi; 806 807extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 808extern int nouveau_pci_resume(struct pci_dev *pdev); 809 810/* nouveau_state.c */ 811extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 812extern int nouveau_load(struct drm_device *, unsigned long flags); 813extern int nouveau_firstopen(struct drm_device *); 814extern void nouveau_lastclose(struct drm_device *); 815extern int nouveau_unload(struct drm_device *); 816extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 817 struct drm_file *); 818extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 819 struct drm_file *); 820extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 821 uint32_t reg, uint32_t mask, uint32_t val); 822extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 823 uint32_t reg, uint32_t mask, uint32_t val); 824extern bool nouveau_wait_for_idle(struct drm_device *); 825extern int nouveau_card_init(struct drm_device *); 826 827/* nouveau_mem.c */ 828extern int nouveau_mem_vram_init(struct drm_device *); 829extern void nouveau_mem_vram_fini(struct drm_device *); 830extern int nouveau_mem_gart_init(struct drm_device *); 831extern void nouveau_mem_gart_fini(struct drm_device *); 832extern int nouveau_mem_init_agp(struct drm_device *); 833extern int nouveau_mem_reset_agp(struct drm_device *); 834extern void nouveau_mem_close(struct drm_device *); 835extern int nouveau_mem_detect(struct drm_device *); 836extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 837extern struct nouveau_tile_reg *nv10_mem_set_tiling( 838 struct drm_device *dev, uint32_t addr, uint32_t size, 839 uint32_t pitch, uint32_t flags); 840extern void nv10_mem_put_tile_region(struct drm_device *dev, 841 struct nouveau_tile_reg *tile, 842 struct nouveau_fence *fence); 843extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 844 845/* nvc0_vram.c */ 846extern const struct ttm_mem_type_manager_func nvc0_vram_manager; 847 848/* nouveau_notifier.c */ 849extern int nouveau_notifier_init_channel(struct nouveau_channel *); 850extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 851extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 852 int cout, uint32_t *offset); 853extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 854extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 855 struct drm_file *); 856extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 857 struct drm_file *); 858 859/* nouveau_channel.c */ 860extern struct drm_ioctl_desc nouveau_ioctls[]; 861extern int nouveau_max_ioctl; 862extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 863extern int nouveau_channel_alloc(struct drm_device *dev, 864 struct nouveau_channel **chan, 865 struct drm_file *file_priv, 866 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 867extern struct nouveau_channel * 868nouveau_channel_get_unlocked(struct nouveau_channel *); 869extern struct nouveau_channel * 870nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 871extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 872extern void nouveau_channel_put(struct nouveau_channel **); 873extern void nouveau_channel_ref(struct nouveau_channel *chan, 874 struct nouveau_channel **pchan); 875extern void nouveau_channel_idle(struct nouveau_channel *chan); 876 877/* nouveau_object.c */ 878#define NVOBJ_CLASS(d,c,e) do { \ 879 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 880 if (ret) \ 881 return ret; \ 882} while(0) 883 884#define NVOBJ_MTHD(d,c,m,e) do { \ 885 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 886 if (ret) \ 887 return ret; \ 888} while(0) 889 890extern int nouveau_gpuobj_early_init(struct drm_device *); 891extern int nouveau_gpuobj_init(struct drm_device *); 892extern void nouveau_gpuobj_takedown(struct drm_device *); 893extern int nouveau_gpuobj_suspend(struct drm_device *dev); 894extern void nouveau_gpuobj_resume(struct drm_device *dev); 895extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 896extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 897 int (*exec)(struct nouveau_channel *, 898 u32 class, u32 mthd, u32 data)); 899extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 900extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 901extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 902 uint32_t vram_h, uint32_t tt_h); 903extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 904extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 905 uint32_t size, int align, uint32_t flags, 906 struct nouveau_gpuobj **); 907extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 908 struct nouveau_gpuobj **); 909extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 910 u32 size, u32 flags, 911 struct nouveau_gpuobj **); 912extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 913 uint64_t offset, uint64_t size, int access, 914 int target, struct nouveau_gpuobj **); 915extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 916extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 917 u64 size, int target, int access, u32 type, 918 u32 comp, struct nouveau_gpuobj **pobj); 919extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 920 int class, u64 base, u64 size, int target, 921 int access, u32 type, u32 comp); 922extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 923 struct drm_file *); 924extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 925 struct drm_file *); 926 927/* nouveau_irq.c */ 928extern int nouveau_irq_init(struct drm_device *); 929extern void nouveau_irq_fini(struct drm_device *); 930extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 931extern void nouveau_irq_register(struct drm_device *, int status_bit, 932 void (*)(struct drm_device *)); 933extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 934extern void nouveau_irq_preinstall(struct drm_device *); 935extern int nouveau_irq_postinstall(struct drm_device *); 936extern void nouveau_irq_uninstall(struct drm_device *); 937 938/* nouveau_sgdma.c */ 939extern int nouveau_sgdma_init(struct drm_device *); 940extern void nouveau_sgdma_takedown(struct drm_device *); 941extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 942 uint32_t offset); 943extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 944 945/* nouveau_debugfs.c */ 946#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 947extern int nouveau_debugfs_init(struct drm_minor *); 948extern void nouveau_debugfs_takedown(struct drm_minor *); 949extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 950extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 951#else 952static inline int 953nouveau_debugfs_init(struct drm_minor *minor) 954{ 955 return 0; 956} 957 958static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 959{ 960} 961 962static inline int 963nouveau_debugfs_channel_init(struct nouveau_channel *chan) 964{ 965 return 0; 966} 967 968static inline void 969nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 970{ 971} 972#endif 973 974/* nouveau_dma.c */ 975extern void nouveau_dma_pre_init(struct nouveau_channel *); 976extern int nouveau_dma_init(struct nouveau_channel *); 977extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 978 979/* nouveau_acpi.c */ 980#define ROM_BIOS_PAGE 4096 981#if defined(CONFIG_ACPI) 982void nouveau_register_dsm_handler(void); 983void nouveau_unregister_dsm_handler(void); 984int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 985bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 986int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 987#else 988static inline void nouveau_register_dsm_handler(void) {} 989static inline void nouveau_unregister_dsm_handler(void) {} 990static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 991static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 992static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 993#endif 994 995/* nouveau_backlight.c */ 996#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 997extern int nouveau_backlight_init(struct drm_device *); 998extern void nouveau_backlight_exit(struct drm_device *); 999#else 1000static inline int nouveau_backlight_init(struct drm_device *dev) 1001{ 1002 return 0; 1003} 1004 1005static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1006#endif 1007 1008/* nouveau_bios.c */ 1009extern int nouveau_bios_init(struct drm_device *); 1010extern void nouveau_bios_takedown(struct drm_device *dev); 1011extern int nouveau_run_vbios_init(struct drm_device *); 1012extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1013 struct dcb_entry *); 1014extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1015 enum dcb_gpio_tag); 1016extern struct dcb_connector_table_entry * 1017nouveau_bios_connector_entry(struct drm_device *, int index); 1018extern u32 get_pll_register(struct drm_device *, enum pll_types); 1019extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1020 struct pll_lims *); 1021extern int nouveau_bios_run_display_table(struct drm_device *, 1022 struct dcb_entry *, 1023 uint32_t script, int pxclk); 1024extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1025 int *length); 1026extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1027extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1028extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1029 bool *dl, bool *if_is_24bit); 1030extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1031 int head, int pxclk); 1032extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1033 enum LVDS_script, int pxclk); 1034 1035/* nouveau_ttm.c */ 1036int nouveau_ttm_global_init(struct drm_nouveau_private *); 1037void nouveau_ttm_global_release(struct drm_nouveau_private *); 1038int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1039 1040/* nouveau_dp.c */ 1041int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1042 uint8_t *data, int data_nr); 1043bool nouveau_dp_detect(struct drm_encoder *); 1044bool nouveau_dp_link_train(struct drm_encoder *); 1045 1046/* nv04_fb.c */ 1047extern int nv04_fb_init(struct drm_device *); 1048extern void nv04_fb_takedown(struct drm_device *); 1049 1050/* nv10_fb.c */ 1051extern int nv10_fb_init(struct drm_device *); 1052extern void nv10_fb_takedown(struct drm_device *); 1053extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1054 uint32_t addr, uint32_t size, 1055 uint32_t pitch, uint32_t flags); 1056extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1057extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1058 1059/* nv30_fb.c */ 1060extern int nv30_fb_init(struct drm_device *); 1061extern void nv30_fb_takedown(struct drm_device *); 1062extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1063 uint32_t addr, uint32_t size, 1064 uint32_t pitch, uint32_t flags); 1065extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1066 1067/* nv40_fb.c */ 1068extern int nv40_fb_init(struct drm_device *); 1069extern void nv40_fb_takedown(struct drm_device *); 1070extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1071 1072/* nv50_fb.c */ 1073extern int nv50_fb_init(struct drm_device *); 1074extern void nv50_fb_takedown(struct drm_device *); 1075extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1076 1077/* nvc0_fb.c */ 1078extern int nvc0_fb_init(struct drm_device *); 1079extern void nvc0_fb_takedown(struct drm_device *); 1080 1081/* nv04_fifo.c */ 1082extern int nv04_fifo_init(struct drm_device *); 1083extern void nv04_fifo_fini(struct drm_device *); 1084extern void nv04_fifo_disable(struct drm_device *); 1085extern void nv04_fifo_enable(struct drm_device *); 1086extern bool nv04_fifo_reassign(struct drm_device *, bool); 1087extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1088extern int nv04_fifo_channel_id(struct drm_device *); 1089extern int nv04_fifo_create_context(struct nouveau_channel *); 1090extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1091extern int nv04_fifo_load_context(struct nouveau_channel *); 1092extern int nv04_fifo_unload_context(struct drm_device *); 1093extern void nv04_fifo_isr(struct drm_device *); 1094 1095/* nv10_fifo.c */ 1096extern int nv10_fifo_init(struct drm_device *); 1097extern int nv10_fifo_channel_id(struct drm_device *); 1098extern int nv10_fifo_create_context(struct nouveau_channel *); 1099extern int nv10_fifo_load_context(struct nouveau_channel *); 1100extern int nv10_fifo_unload_context(struct drm_device *); 1101 1102/* nv40_fifo.c */ 1103extern int nv40_fifo_init(struct drm_device *); 1104extern int nv40_fifo_create_context(struct nouveau_channel *); 1105extern int nv40_fifo_load_context(struct nouveau_channel *); 1106extern int nv40_fifo_unload_context(struct drm_device *); 1107 1108/* nv50_fifo.c */ 1109extern int nv50_fifo_init(struct drm_device *); 1110extern void nv50_fifo_takedown(struct drm_device *); 1111extern int nv50_fifo_channel_id(struct drm_device *); 1112extern int nv50_fifo_create_context(struct nouveau_channel *); 1113extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1114extern int nv50_fifo_load_context(struct nouveau_channel *); 1115extern int nv50_fifo_unload_context(struct drm_device *); 1116extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1117 1118/* nvc0_fifo.c */ 1119extern int nvc0_fifo_init(struct drm_device *); 1120extern void nvc0_fifo_takedown(struct drm_device *); 1121extern void nvc0_fifo_disable(struct drm_device *); 1122extern void nvc0_fifo_enable(struct drm_device *); 1123extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1124extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1125extern int nvc0_fifo_channel_id(struct drm_device *); 1126extern int nvc0_fifo_create_context(struct nouveau_channel *); 1127extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1128extern int nvc0_fifo_load_context(struct nouveau_channel *); 1129extern int nvc0_fifo_unload_context(struct drm_device *); 1130 1131/* nv04_graph.c */ 1132extern int nv04_graph_init(struct drm_device *); 1133extern void nv04_graph_takedown(struct drm_device *); 1134extern void nv04_graph_fifo_access(struct drm_device *, bool); 1135extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1136extern int nv04_graph_create_context(struct nouveau_channel *); 1137extern void nv04_graph_destroy_context(struct nouveau_channel *); 1138extern int nv04_graph_load_context(struct nouveau_channel *); 1139extern int nv04_graph_unload_context(struct drm_device *); 1140extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1141 u32 class, u32 mthd, u32 data); 1142extern struct nouveau_bitfield nv04_graph_nsource[]; 1143 1144/* nv10_graph.c */ 1145extern int nv10_graph_init(struct drm_device *); 1146extern void nv10_graph_takedown(struct drm_device *); 1147extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1148extern int nv10_graph_create_context(struct nouveau_channel *); 1149extern void nv10_graph_destroy_context(struct nouveau_channel *); 1150extern int nv10_graph_load_context(struct nouveau_channel *); 1151extern int nv10_graph_unload_context(struct drm_device *); 1152extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1153extern struct nouveau_bitfield nv10_graph_intr[]; 1154extern struct nouveau_bitfield nv10_graph_nstatus[]; 1155 1156/* nv20_graph.c */ 1157extern int nv20_graph_create_context(struct nouveau_channel *); 1158extern void nv20_graph_destroy_context(struct nouveau_channel *); 1159extern int nv20_graph_load_context(struct nouveau_channel *); 1160extern int nv20_graph_unload_context(struct drm_device *); 1161extern int nv20_graph_init(struct drm_device *); 1162extern void nv20_graph_takedown(struct drm_device *); 1163extern int nv30_graph_init(struct drm_device *); 1164extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1165 1166/* nv40_graph.c */ 1167extern int nv40_graph_init(struct drm_device *); 1168extern void nv40_graph_takedown(struct drm_device *); 1169extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1170extern int nv40_graph_create_context(struct nouveau_channel *); 1171extern void nv40_graph_destroy_context(struct nouveau_channel *); 1172extern int nv40_graph_load_context(struct nouveau_channel *); 1173extern int nv40_graph_unload_context(struct drm_device *); 1174extern void nv40_grctx_init(struct nouveau_grctx *); 1175extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1176 1177/* nv50_graph.c */ 1178extern int nv50_graph_init(struct drm_device *); 1179extern void nv50_graph_takedown(struct drm_device *); 1180extern void nv50_graph_fifo_access(struct drm_device *, bool); 1181extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1182extern int nv50_graph_create_context(struct nouveau_channel *); 1183extern void nv50_graph_destroy_context(struct nouveau_channel *); 1184extern int nv50_graph_load_context(struct nouveau_channel *); 1185extern int nv50_graph_unload_context(struct drm_device *); 1186extern int nv50_grctx_init(struct nouveau_grctx *); 1187extern void nv50_graph_tlb_flush(struct drm_device *dev); 1188extern void nv86_graph_tlb_flush(struct drm_device *dev); 1189 1190/* nvc0_graph.c */ 1191extern int nvc0_graph_init(struct drm_device *); 1192extern void nvc0_graph_takedown(struct drm_device *); 1193extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1194extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1195extern int nvc0_graph_create_context(struct nouveau_channel *); 1196extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1197extern int nvc0_graph_load_context(struct nouveau_channel *); 1198extern int nvc0_graph_unload_context(struct drm_device *); 1199 1200/* nv84_crypt.c */ 1201extern int nv84_crypt_init(struct drm_device *dev); 1202extern void nv84_crypt_fini(struct drm_device *dev); 1203extern int nv84_crypt_create_context(struct nouveau_channel *); 1204extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1205extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1206 1207/* nv04_instmem.c */ 1208extern int nv04_instmem_init(struct drm_device *); 1209extern void nv04_instmem_takedown(struct drm_device *); 1210extern int nv04_instmem_suspend(struct drm_device *); 1211extern void nv04_instmem_resume(struct drm_device *); 1212extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1213extern void nv04_instmem_put(struct nouveau_gpuobj *); 1214extern int nv04_instmem_map(struct nouveau_gpuobj *); 1215extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1216extern void nv04_instmem_flush(struct drm_device *); 1217 1218/* nv50_instmem.c */ 1219extern int nv50_instmem_init(struct drm_device *); 1220extern void nv50_instmem_takedown(struct drm_device *); 1221extern int nv50_instmem_suspend(struct drm_device *); 1222extern void nv50_instmem_resume(struct drm_device *); 1223extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1224extern void nv50_instmem_put(struct nouveau_gpuobj *); 1225extern int nv50_instmem_map(struct nouveau_gpuobj *); 1226extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1227extern void nv50_instmem_flush(struct drm_device *); 1228extern void nv84_instmem_flush(struct drm_device *); 1229 1230/* nvc0_instmem.c */ 1231extern int nvc0_instmem_init(struct drm_device *); 1232extern void nvc0_instmem_takedown(struct drm_device *); 1233extern int nvc0_instmem_suspend(struct drm_device *); 1234extern void nvc0_instmem_resume(struct drm_device *); 1235 1236/* nv04_mc.c */ 1237extern int nv04_mc_init(struct drm_device *); 1238extern void nv04_mc_takedown(struct drm_device *); 1239 1240/* nv40_mc.c */ 1241extern int nv40_mc_init(struct drm_device *); 1242extern void nv40_mc_takedown(struct drm_device *); 1243 1244/* nv50_mc.c */ 1245extern int nv50_mc_init(struct drm_device *); 1246extern void nv50_mc_takedown(struct drm_device *); 1247 1248/* nv04_timer.c */ 1249extern int nv04_timer_init(struct drm_device *); 1250extern uint64_t nv04_timer_read(struct drm_device *); 1251extern void nv04_timer_takedown(struct drm_device *); 1252 1253extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1254 unsigned long arg); 1255 1256/* nv04_dac.c */ 1257extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1258extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1259extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1260extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1261extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1262 1263/* nv04_dfp.c */ 1264extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1265extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1266extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1267 int head, bool dl); 1268extern void nv04_dfp_disable(struct drm_device *dev, int head); 1269extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1270 1271/* nv04_tv.c */ 1272extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1273extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1274 1275/* nv17_tv.c */ 1276extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1277 1278/* nv04_display.c */ 1279extern int nv04_display_early_init(struct drm_device *); 1280extern void nv04_display_late_takedown(struct drm_device *); 1281extern int nv04_display_create(struct drm_device *); 1282extern int nv04_display_init(struct drm_device *); 1283extern void nv04_display_destroy(struct drm_device *); 1284 1285/* nv04_crtc.c */ 1286extern int nv04_crtc_create(struct drm_device *, int index); 1287 1288/* nouveau_bo.c */ 1289extern struct ttm_bo_driver nouveau_bo_driver; 1290extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1291 int size, int align, uint32_t flags, 1292 uint32_t tile_mode, uint32_t tile_flags, 1293 bool no_vm, bool mappable, struct nouveau_bo **); 1294extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1295extern int nouveau_bo_unpin(struct nouveau_bo *); 1296extern int nouveau_bo_map(struct nouveau_bo *); 1297extern void nouveau_bo_unmap(struct nouveau_bo *); 1298extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1299 uint32_t busy); 1300extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1301extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1302extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1303extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1304extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1305extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1306 bool no_wait_reserve, bool no_wait_gpu); 1307 1308/* nouveau_fence.c */ 1309struct nouveau_fence; 1310extern int nouveau_fence_init(struct drm_device *); 1311extern void nouveau_fence_fini(struct drm_device *); 1312extern int nouveau_fence_channel_init(struct nouveau_channel *); 1313extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1314extern void nouveau_fence_update(struct nouveau_channel *); 1315extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1316 bool emit); 1317extern int nouveau_fence_emit(struct nouveau_fence *); 1318extern void nouveau_fence_work(struct nouveau_fence *fence, 1319 void (*work)(void *priv, bool signalled), 1320 void *priv); 1321struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1322 1323extern bool __nouveau_fence_signalled(void *obj, void *arg); 1324extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1325extern int __nouveau_fence_flush(void *obj, void *arg); 1326extern void __nouveau_fence_unref(void **obj); 1327extern void *__nouveau_fence_ref(void *obj); 1328 1329static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1330{ 1331 return __nouveau_fence_signalled(obj, NULL); 1332} 1333static inline int 1334nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1335{ 1336 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1337} 1338extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1339static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1340{ 1341 return __nouveau_fence_flush(obj, NULL); 1342} 1343static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1344{ 1345 __nouveau_fence_unref((void **)obj); 1346} 1347static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1348{ 1349 return __nouveau_fence_ref(obj); 1350} 1351 1352/* nouveau_gem.c */ 1353extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1354 int size, int align, uint32_t flags, 1355 uint32_t tile_mode, uint32_t tile_flags, 1356 bool no_vm, bool mappable, struct nouveau_bo **); 1357extern int nouveau_gem_object_new(struct drm_gem_object *); 1358extern void nouveau_gem_object_del(struct drm_gem_object *); 1359extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1360 struct drm_file *); 1361extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1362 struct drm_file *); 1363extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1364 struct drm_file *); 1365extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1366 struct drm_file *); 1367extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1368 struct drm_file *); 1369 1370/* nouveau_display.c */ 1371int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1372void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1373int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1374 struct drm_pending_vblank_event *event); 1375int nouveau_finish_page_flip(struct nouveau_channel *, 1376 struct nouveau_page_flip_state *); 1377 1378/* nv10_gpio.c */ 1379int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1380int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1381 1382/* nv50_gpio.c */ 1383int nv50_gpio_init(struct drm_device *dev); 1384void nv50_gpio_fini(struct drm_device *dev); 1385int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1386int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1387int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1388 void (*)(void *, int), void *); 1389void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1390 void (*)(void *, int), void *); 1391bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1392 1393/* nv50_calc. */ 1394int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1395 int *N1, int *M1, int *N2, int *M2, int *P); 1396int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1397 int clk, int *N, int *fN, int *M, int *P); 1398 1399#ifndef ioread32_native 1400#ifdef __BIG_ENDIAN 1401#define ioread16_native ioread16be 1402#define iowrite16_native iowrite16be 1403#define ioread32_native ioread32be 1404#define iowrite32_native iowrite32be 1405#else /* def __BIG_ENDIAN */ 1406#define ioread16_native ioread16 1407#define iowrite16_native iowrite16 1408#define ioread32_native ioread32 1409#define iowrite32_native iowrite32 1410#endif /* def __BIG_ENDIAN else */ 1411#endif /* !ioread32_native */ 1412 1413/* channel control reg access */ 1414static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1415{ 1416 return ioread32_native(chan->user + reg); 1417} 1418 1419static inline void nvchan_wr32(struct nouveau_channel *chan, 1420 unsigned reg, u32 val) 1421{ 1422 iowrite32_native(val, chan->user + reg); 1423} 1424 1425/* register access */ 1426static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1427{ 1428 struct drm_nouveau_private *dev_priv = dev->dev_private; 1429 return ioread32_native(dev_priv->mmio + reg); 1430} 1431 1432static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1433{ 1434 struct drm_nouveau_private *dev_priv = dev->dev_private; 1435 iowrite32_native(val, dev_priv->mmio + reg); 1436} 1437 1438static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1439{ 1440 u32 tmp = nv_rd32(dev, reg); 1441 nv_wr32(dev, reg, (tmp & ~mask) | val); 1442 return tmp; 1443} 1444 1445static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1446{ 1447 struct drm_nouveau_private *dev_priv = dev->dev_private; 1448 return ioread8(dev_priv->mmio + reg); 1449} 1450 1451static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1452{ 1453 struct drm_nouveau_private *dev_priv = dev->dev_private; 1454 iowrite8(val, dev_priv->mmio + reg); 1455} 1456 1457#define nv_wait(dev, reg, mask, val) \ 1458 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1459#define nv_wait_ne(dev, reg, mask, val) \ 1460 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1461 1462/* PRAMIN access */ 1463static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1464{ 1465 struct drm_nouveau_private *dev_priv = dev->dev_private; 1466 return ioread32_native(dev_priv->ramin + offset); 1467} 1468 1469static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1470{ 1471 struct drm_nouveau_private *dev_priv = dev->dev_private; 1472 iowrite32_native(val, dev_priv->ramin + offset); 1473} 1474 1475/* object access */ 1476extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1477extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1478 1479/* 1480 * Logging 1481 * Argument d is (struct drm_device *). 1482 */ 1483#define NV_PRINTK(level, d, fmt, arg...) \ 1484 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1485 pci_name(d->pdev), ##arg) 1486#ifndef NV_DEBUG_NOTRACE 1487#define NV_DEBUG(d, fmt, arg...) do { \ 1488 if (drm_debug & DRM_UT_DRIVER) { \ 1489 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1490 __LINE__, ##arg); \ 1491 } \ 1492} while (0) 1493#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1494 if (drm_debug & DRM_UT_KMS) { \ 1495 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1496 __LINE__, ##arg); \ 1497 } \ 1498} while (0) 1499#else 1500#define NV_DEBUG(d, fmt, arg...) do { \ 1501 if (drm_debug & DRM_UT_DRIVER) \ 1502 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1503} while (0) 1504#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1505 if (drm_debug & DRM_UT_KMS) \ 1506 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1507} while (0) 1508#endif 1509#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1510#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1511#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1512#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1513#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1514 1515/* nouveau_reg_debug bitmask */ 1516enum { 1517 NOUVEAU_REG_DEBUG_MC = 0x1, 1518 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1519 NOUVEAU_REG_DEBUG_FB = 0x4, 1520 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1521 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1522 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1523 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1524 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1525 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1526 NOUVEAU_REG_DEBUG_EVO = 0x200, 1527}; 1528 1529#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1530 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1531 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1532} while (0) 1533 1534static inline bool 1535nv_two_heads(struct drm_device *dev) 1536{ 1537 struct drm_nouveau_private *dev_priv = dev->dev_private; 1538 const int impl = dev->pci_device & 0x0ff0; 1539 1540 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1541 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1542 return true; 1543 1544 return false; 1545} 1546 1547static inline bool 1548nv_gf4_disp_arch(struct drm_device *dev) 1549{ 1550 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1551} 1552 1553static inline bool 1554nv_two_reg_pll(struct drm_device *dev) 1555{ 1556 struct drm_nouveau_private *dev_priv = dev->dev_private; 1557 const int impl = dev->pci_device & 0x0ff0; 1558 1559 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1560 return true; 1561 return false; 1562} 1563 1564static inline bool 1565nv_match_device(struct drm_device *dev, unsigned device, 1566 unsigned sub_vendor, unsigned sub_device) 1567{ 1568 return dev->pdev->device == device && 1569 dev->pdev->subsystem_vendor == sub_vendor && 1570 dev->pdev->subsystem_device == sub_device; 1571} 1572 1573/* memory type/access flags, do not match hardware values */ 1574#define NV_MEM_ACCESS_RO 1 1575#define NV_MEM_ACCESS_WO 2 1576#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1577#define NV_MEM_ACCESS_SYS 4 1578#define NV_MEM_ACCESS_VM 8 1579 1580#define NV_MEM_TARGET_VRAM 0 1581#define NV_MEM_TARGET_PCI 1 1582#define NV_MEM_TARGET_PCI_NOSNOOP 2 1583#define NV_MEM_TARGET_VM 3 1584#define NV_MEM_TARGET_GART 4 1585 1586#define NV_MEM_TYPE_VM 0x7f 1587#define NV_MEM_COMP_VM 0x03 1588 1589/* NV_SW object class */ 1590#define NV_SW 0x0000506e 1591#define NV_SW_DMA_SEMAPHORE 0x00000060 1592#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1593#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1594#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1595#define NV_SW_YIELD 0x00000080 1596#define NV_SW_DMA_VBLSEM 0x0000018c 1597#define NV_SW_VBLSEM_OFFSET 0x00000400 1598#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1599#define NV_SW_VBLSEM_RELEASE 0x00000408 1600#define NV_SW_PAGE_FLIP 0x00000500 1601 1602#endif /* __NOUVEAU_DRV_H__ */ 1603