nouveau_drv.h revision 8af29ccd7917ab448ea7b5cf581fa7b2b4ea3cba
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_pull)(struct drm_device *dev, bool enable); 300 301 int (*channel_id)(struct drm_device *); 302 303 int (*create_context)(struct nouveau_channel *); 304 void (*destroy_context)(struct nouveau_channel *); 305 int (*load_context)(struct nouveau_channel *); 306 int (*unload_context)(struct drm_device *); 307}; 308 309struct nouveau_pgraph_object_method { 310 int id; 311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 312 uint32_t data); 313}; 314 315struct nouveau_pgraph_object_class { 316 int id; 317 bool software; 318 struct nouveau_pgraph_object_method *methods; 319}; 320 321struct nouveau_pgraph_engine { 322 struct nouveau_pgraph_object_class *grclass; 323 bool accel_blocked; 324 int grctx_size; 325 326 /* NV2x/NV3x context table (0x400780) */ 327 struct nouveau_gpuobj *ctx_table; 328 329 int (*init)(struct drm_device *); 330 void (*takedown)(struct drm_device *); 331 332 void (*fifo_access)(struct drm_device *, bool); 333 334 struct nouveau_channel *(*channel)(struct drm_device *); 335 int (*create_context)(struct nouveau_channel *); 336 void (*destroy_context)(struct nouveau_channel *); 337 int (*load_context)(struct nouveau_channel *); 338 int (*unload_context)(struct drm_device *); 339 340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 341 uint32_t size, uint32_t pitch); 342}; 343 344struct nouveau_display_engine { 345 int (*early_init)(struct drm_device *); 346 void (*late_takedown)(struct drm_device *); 347 int (*create)(struct drm_device *); 348 int (*init)(struct drm_device *); 349 void (*destroy)(struct drm_device *); 350}; 351 352struct nouveau_gpio_engine { 353 int (*init)(struct drm_device *); 354 void (*takedown)(struct drm_device *); 355 356 int (*get)(struct drm_device *, enum dcb_gpio_tag); 357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 358 359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 360}; 361 362struct nouveau_pm_voltage_level { 363 u8 voltage; 364 u8 vid; 365}; 366 367struct nouveau_pm_voltage { 368 bool supported; 369 u8 vid_mask; 370 371 struct nouveau_pm_voltage_level *level; 372 int nr_level; 373}; 374 375#define NOUVEAU_PM_MAX_LEVEL 8 376struct nouveau_pm_level { 377 struct device_attribute dev_attr; 378 char name[32]; 379 int id; 380 381 u32 core; 382 u32 memory; 383 u32 shader; 384 u32 unk05; 385 386 u8 voltage; 387 u8 fanspeed; 388 389 u16 memscript; 390}; 391 392struct nouveau_pm_temp_sensor_constants { 393 u16 offset_constant; 394 s16 offset_mult; 395 u16 offset_div; 396 u16 slope_mult; 397 u16 slope_div; 398}; 399 400struct nouveau_pm_threshold_temp { 401 s16 critical; 402 s16 down_clock; 403 s16 fan_boost; 404}; 405 406struct nouveau_pm_memtiming { 407 u32 reg_100220; 408 u32 reg_100224; 409 u32 reg_100228; 410 u32 reg_10022c; 411 u32 reg_100230; 412 u32 reg_100234; 413 u32 reg_100238; 414 u32 reg_10023c; 415}; 416 417struct nouveau_pm_memtimings { 418 bool supported; 419 struct nouveau_pm_memtiming *timing; 420 int nr_timing; 421}; 422 423struct nouveau_pm_engine { 424 struct nouveau_pm_voltage voltage; 425 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 426 int nr_perflvl; 427 struct nouveau_pm_memtimings memtimings; 428 struct nouveau_pm_temp_sensor_constants sensor_constants; 429 struct nouveau_pm_threshold_temp threshold_temp; 430 431 struct nouveau_pm_level boot; 432 struct nouveau_pm_level *cur; 433 434 struct device *hwmon; 435 436 int (*clock_get)(struct drm_device *, u32 id); 437 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 438 u32 id, int khz); 439 void (*clock_set)(struct drm_device *, void *); 440 int (*voltage_get)(struct drm_device *); 441 int (*voltage_set)(struct drm_device *, int voltage); 442 int (*fanspeed_get)(struct drm_device *); 443 int (*fanspeed_set)(struct drm_device *, int fanspeed); 444 int (*temp_get)(struct drm_device *); 445}; 446 447struct nouveau_engine { 448 struct nouveau_instmem_engine instmem; 449 struct nouveau_mc_engine mc; 450 struct nouveau_timer_engine timer; 451 struct nouveau_fb_engine fb; 452 struct nouveau_pgraph_engine graph; 453 struct nouveau_fifo_engine fifo; 454 struct nouveau_display_engine display; 455 struct nouveau_gpio_engine gpio; 456 struct nouveau_pm_engine pm; 457}; 458 459struct nouveau_pll_vals { 460 union { 461 struct { 462#ifdef __BIG_ENDIAN 463 uint8_t N1, M1, N2, M2; 464#else 465 uint8_t M1, N1, M2, N2; 466#endif 467 }; 468 struct { 469 uint16_t NM1, NM2; 470 } __attribute__((packed)); 471 }; 472 int log2P; 473 474 int refclk; 475}; 476 477enum nv04_fp_display_regs { 478 FP_DISPLAY_END, 479 FP_TOTAL, 480 FP_CRTC, 481 FP_SYNC_START, 482 FP_SYNC_END, 483 FP_VALID_START, 484 FP_VALID_END 485}; 486 487struct nv04_crtc_reg { 488 unsigned char MiscOutReg; /* */ 489 uint8_t CRTC[0xa0]; 490 uint8_t CR58[0x10]; 491 uint8_t Sequencer[5]; 492 uint8_t Graphics[9]; 493 uint8_t Attribute[21]; 494 unsigned char DAC[768]; /* Internal Colorlookuptable */ 495 496 /* PCRTC regs */ 497 uint32_t fb_start; 498 uint32_t crtc_cfg; 499 uint32_t cursor_cfg; 500 uint32_t gpio_ext; 501 uint32_t crtc_830; 502 uint32_t crtc_834; 503 uint32_t crtc_850; 504 uint32_t crtc_eng_ctrl; 505 506 /* PRAMDAC regs */ 507 uint32_t nv10_cursync; 508 struct nouveau_pll_vals pllvals; 509 uint32_t ramdac_gen_ctrl; 510 uint32_t ramdac_630; 511 uint32_t ramdac_634; 512 uint32_t tv_setup; 513 uint32_t tv_vtotal; 514 uint32_t tv_vskew; 515 uint32_t tv_vsync_delay; 516 uint32_t tv_htotal; 517 uint32_t tv_hskew; 518 uint32_t tv_hsync_delay; 519 uint32_t tv_hsync_delay2; 520 uint32_t fp_horiz_regs[7]; 521 uint32_t fp_vert_regs[7]; 522 uint32_t dither; 523 uint32_t fp_control; 524 uint32_t dither_regs[6]; 525 uint32_t fp_debug_0; 526 uint32_t fp_debug_1; 527 uint32_t fp_debug_2; 528 uint32_t fp_margin_color; 529 uint32_t ramdac_8c0; 530 uint32_t ramdac_a20; 531 uint32_t ramdac_a24; 532 uint32_t ramdac_a34; 533 uint32_t ctv_regs[38]; 534}; 535 536struct nv04_output_reg { 537 uint32_t output; 538 int head; 539}; 540 541struct nv04_mode_state { 542 uint32_t bpp; 543 uint32_t width; 544 uint32_t height; 545 uint32_t interlace; 546 uint32_t repaint0; 547 uint32_t repaint1; 548 uint32_t screen; 549 uint32_t scale; 550 uint32_t dither; 551 uint32_t extra; 552 uint32_t fifo; 553 uint32_t pixel; 554 uint32_t horiz; 555 int arbitration0; 556 int arbitration1; 557 uint32_t pll; 558 uint32_t pllB; 559 uint32_t vpll; 560 uint32_t vpll2; 561 uint32_t vpllB; 562 uint32_t vpll2B; 563 uint32_t pllsel; 564 uint32_t sel_clk; 565 uint32_t general; 566 uint32_t crtcOwner; 567 uint32_t head; 568 uint32_t head2; 569 uint32_t cursorConfig; 570 uint32_t cursor0; 571 uint32_t cursor1; 572 uint32_t cursor2; 573 uint32_t timingH; 574 uint32_t timingV; 575 uint32_t displayV; 576 uint32_t crtcSync; 577 578 struct nv04_crtc_reg crtc_reg[2]; 579}; 580 581enum nouveau_card_type { 582 NV_04 = 0x00, 583 NV_10 = 0x10, 584 NV_20 = 0x20, 585 NV_30 = 0x30, 586 NV_40 = 0x40, 587 NV_50 = 0x50, 588 NV_C0 = 0xc0, 589}; 590 591struct drm_nouveau_private { 592 struct drm_device *dev; 593 594 /* the card type, takes NV_* as values */ 595 enum nouveau_card_type card_type; 596 /* exact chipset, derived from NV_PMC_BOOT_0 */ 597 int chipset; 598 int flags; 599 600 void __iomem *mmio; 601 602 spinlock_t ramin_lock; 603 void __iomem *ramin; 604 u32 ramin_size; 605 u32 ramin_base; 606 bool ramin_available; 607 struct drm_mm ramin_heap; 608 struct list_head gpuobj_list; 609 610 struct nouveau_bo *vga_ram; 611 612 struct workqueue_struct *wq; 613 struct work_struct irq_work; 614 struct work_struct hpd_work; 615 616 struct list_head vbl_waiting; 617 618 struct { 619 struct drm_global_reference mem_global_ref; 620 struct ttm_bo_global_ref bo_global_ref; 621 struct ttm_bo_device bdev; 622 atomic_t validate_sequence; 623 } ttm; 624 625 struct { 626 spinlock_t lock; 627 struct drm_mm heap; 628 struct nouveau_bo *bo; 629 } fence; 630 631 int fifo_alloc_count; 632 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 633 634 struct nouveau_engine engine; 635 struct nouveau_channel *channel; 636 637 /* For PFIFO and PGRAPH. */ 638 spinlock_t context_switch_lock; 639 640 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 641 struct nouveau_ramht *ramht; 642 struct nouveau_gpuobj *ramfc; 643 struct nouveau_gpuobj *ramro; 644 645 uint32_t ramin_rsvd_vram; 646 647 struct { 648 enum { 649 NOUVEAU_GART_NONE = 0, 650 NOUVEAU_GART_AGP, 651 NOUVEAU_GART_SGDMA 652 } type; 653 uint64_t aper_base; 654 uint64_t aper_size; 655 uint64_t aper_free; 656 657 struct nouveau_gpuobj *sg_ctxdma; 658 struct page *sg_dummy_page; 659 dma_addr_t sg_dummy_bus; 660 } gart_info; 661 662 /* nv10-nv40 tiling regions */ 663 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 664 665 /* VRAM/fb configuration */ 666 uint64_t vram_size; 667 uint64_t vram_sys_base; 668 u32 vram_rblock_size; 669 670 uint64_t fb_phys; 671 uint64_t fb_available_size; 672 uint64_t fb_mappable_pages; 673 uint64_t fb_aper_free; 674 int fb_mtrr; 675 676 /* G8x/G9x virtual address space */ 677 uint64_t vm_gart_base; 678 uint64_t vm_gart_size; 679 uint64_t vm_vram_base; 680 uint64_t vm_vram_size; 681 uint64_t vm_end; 682 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 683 int vm_vram_pt_nr; 684 685 struct nvbios vbios; 686 687 struct nv04_mode_state mode_reg; 688 struct nv04_mode_state saved_reg; 689 uint32_t saved_vga_font[4][16384]; 690 uint32_t crtc_owner; 691 uint32_t dac_users[4]; 692 693 struct nouveau_suspend_resume { 694 uint32_t *ramin_copy; 695 } susres; 696 697 struct backlight_device *backlight; 698 699 struct nouveau_channel *evo; 700 struct { 701 struct dcb_entry *dcb; 702 u16 script; 703 u32 pclk; 704 } evo_irq; 705 706 struct { 707 struct dentry *channel_root; 708 } debugfs; 709 710 struct nouveau_fbdev *nfbdev; 711 struct apertures_struct *apertures; 712}; 713 714static inline struct drm_nouveau_private * 715nouveau_private(struct drm_device *dev) 716{ 717 return dev->dev_private; 718} 719 720static inline struct drm_nouveau_private * 721nouveau_bdev(struct ttm_bo_device *bd) 722{ 723 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 724} 725 726static inline int 727nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 728{ 729 struct nouveau_bo *prev; 730 731 if (!pnvbo) 732 return -EINVAL; 733 prev = *pnvbo; 734 735 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 736 if (prev) { 737 struct ttm_buffer_object *bo = &prev->bo; 738 739 ttm_bo_unref(&bo); 740 } 741 742 return 0; 743} 744 745#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 746 struct drm_nouveau_private *nv = dev->dev_private; \ 747 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 748 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 749 DRM_CURRENTPID, (id)); \ 750 return -EPERM; \ 751 } \ 752 (ch) = nv->fifos[(id)]; \ 753} while (0) 754 755/* nouveau_drv.c */ 756extern int nouveau_agpmode; 757extern int nouveau_duallink; 758extern int nouveau_uscript_lvds; 759extern int nouveau_uscript_tmds; 760extern int nouveau_vram_pushbuf; 761extern int nouveau_vram_notify; 762extern int nouveau_fbpercrtc; 763extern int nouveau_tv_disable; 764extern char *nouveau_tv_norm; 765extern int nouveau_reg_debug; 766extern char *nouveau_vbios; 767extern int nouveau_ignorelid; 768extern int nouveau_nofbaccel; 769extern int nouveau_noaccel; 770extern int nouveau_force_post; 771extern int nouveau_override_conntype; 772extern char *nouveau_perflvl; 773extern int nouveau_perflvl_wr; 774 775extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 776extern int nouveau_pci_resume(struct pci_dev *pdev); 777 778/* nouveau_state.c */ 779extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 780extern int nouveau_load(struct drm_device *, unsigned long flags); 781extern int nouveau_firstopen(struct drm_device *); 782extern void nouveau_lastclose(struct drm_device *); 783extern int nouveau_unload(struct drm_device *); 784extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 785 struct drm_file *); 786extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 787 struct drm_file *); 788extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 789 uint32_t reg, uint32_t mask, uint32_t val); 790extern bool nouveau_wait_for_idle(struct drm_device *); 791extern int nouveau_card_init(struct drm_device *); 792 793/* nouveau_mem.c */ 794extern int nouveau_mem_vram_init(struct drm_device *); 795extern void nouveau_mem_vram_fini(struct drm_device *); 796extern int nouveau_mem_gart_init(struct drm_device *); 797extern void nouveau_mem_gart_fini(struct drm_device *); 798extern int nouveau_mem_init_agp(struct drm_device *); 799extern int nouveau_mem_reset_agp(struct drm_device *); 800extern void nouveau_mem_close(struct drm_device *); 801extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 802 uint32_t addr, 803 uint32_t size, 804 uint32_t pitch); 805extern void nv10_mem_expire_tiling(struct drm_device *dev, 806 struct nouveau_tile_reg *tile, 807 struct nouveau_fence *fence); 808extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 809 uint32_t size, uint32_t flags, 810 uint64_t phys); 811extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 812 uint32_t size); 813 814/* nouveau_notifier.c */ 815extern int nouveau_notifier_init_channel(struct nouveau_channel *); 816extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 817extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 818 int cout, uint32_t *offset); 819extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 820extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 821 struct drm_file *); 822extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 823 struct drm_file *); 824 825/* nouveau_channel.c */ 826extern struct drm_ioctl_desc nouveau_ioctls[]; 827extern int nouveau_max_ioctl; 828extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 829extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 830 int channel); 831extern int nouveau_channel_alloc(struct drm_device *dev, 832 struct nouveau_channel **chan, 833 struct drm_file *file_priv, 834 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 835extern void nouveau_channel_free(struct nouveau_channel *); 836 837/* nouveau_object.c */ 838extern int nouveau_gpuobj_early_init(struct drm_device *); 839extern int nouveau_gpuobj_init(struct drm_device *); 840extern void nouveau_gpuobj_takedown(struct drm_device *); 841extern int nouveau_gpuobj_suspend(struct drm_device *dev); 842extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 843extern void nouveau_gpuobj_resume(struct drm_device *dev); 844extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 845 uint32_t vram_h, uint32_t tt_h); 846extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 847extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 848 uint32_t size, int align, uint32_t flags, 849 struct nouveau_gpuobj **); 850extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 851 struct nouveau_gpuobj **); 852extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 853 u32 size, u32 flags, 854 struct nouveau_gpuobj **); 855extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 856 uint64_t offset, uint64_t size, int access, 857 int target, struct nouveau_gpuobj **); 858extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 859 uint64_t offset, uint64_t size, 860 int access, struct nouveau_gpuobj **, 861 uint32_t *o_ret); 862extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 863 struct nouveau_gpuobj **); 864extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 865 struct nouveau_gpuobj **); 866extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 867 struct drm_file *); 868extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 869 struct drm_file *); 870 871/* nouveau_irq.c */ 872extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 873extern void nouveau_irq_preinstall(struct drm_device *); 874extern int nouveau_irq_postinstall(struct drm_device *); 875extern void nouveau_irq_uninstall(struct drm_device *); 876 877/* nouveau_sgdma.c */ 878extern int nouveau_sgdma_init(struct drm_device *); 879extern void nouveau_sgdma_takedown(struct drm_device *); 880extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 881 uint32_t *page); 882extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 883 884/* nouveau_debugfs.c */ 885#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 886extern int nouveau_debugfs_init(struct drm_minor *); 887extern void nouveau_debugfs_takedown(struct drm_minor *); 888extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 889extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 890#else 891static inline int 892nouveau_debugfs_init(struct drm_minor *minor) 893{ 894 return 0; 895} 896 897static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 898{ 899} 900 901static inline int 902nouveau_debugfs_channel_init(struct nouveau_channel *chan) 903{ 904 return 0; 905} 906 907static inline void 908nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 909{ 910} 911#endif 912 913/* nouveau_dma.c */ 914extern void nouveau_dma_pre_init(struct nouveau_channel *); 915extern int nouveau_dma_init(struct nouveau_channel *); 916extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 917 918/* nouveau_acpi.c */ 919#define ROM_BIOS_PAGE 4096 920#if defined(CONFIG_ACPI) 921void nouveau_register_dsm_handler(void); 922void nouveau_unregister_dsm_handler(void); 923int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 924bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 925int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 926#else 927static inline void nouveau_register_dsm_handler(void) {} 928static inline void nouveau_unregister_dsm_handler(void) {} 929static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 930static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 931static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 932#endif 933 934/* nouveau_backlight.c */ 935#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 936extern int nouveau_backlight_init(struct drm_device *); 937extern void nouveau_backlight_exit(struct drm_device *); 938#else 939static inline int nouveau_backlight_init(struct drm_device *dev) 940{ 941 return 0; 942} 943 944static inline void nouveau_backlight_exit(struct drm_device *dev) { } 945#endif 946 947/* nouveau_bios.c */ 948extern int nouveau_bios_init(struct drm_device *); 949extern void nouveau_bios_takedown(struct drm_device *dev); 950extern int nouveau_run_vbios_init(struct drm_device *); 951extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 952 struct dcb_entry *); 953extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 954 enum dcb_gpio_tag); 955extern struct dcb_connector_table_entry * 956nouveau_bios_connector_entry(struct drm_device *, int index); 957extern u32 get_pll_register(struct drm_device *, enum pll_types); 958extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 959 struct pll_lims *); 960extern int nouveau_bios_run_display_table(struct drm_device *, 961 struct dcb_entry *, 962 uint32_t script, int pxclk); 963extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 964 int *length); 965extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 966extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 967extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 968 bool *dl, bool *if_is_24bit); 969extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 970 int head, int pxclk); 971extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 972 enum LVDS_script, int pxclk); 973 974/* nouveau_ttm.c */ 975int nouveau_ttm_global_init(struct drm_nouveau_private *); 976void nouveau_ttm_global_release(struct drm_nouveau_private *); 977int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 978 979/* nouveau_dp.c */ 980int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 981 uint8_t *data, int data_nr); 982bool nouveau_dp_detect(struct drm_encoder *); 983bool nouveau_dp_link_train(struct drm_encoder *); 984 985/* nv04_fb.c */ 986extern int nv04_fb_init(struct drm_device *); 987extern void nv04_fb_takedown(struct drm_device *); 988 989/* nv10_fb.c */ 990extern int nv10_fb_init(struct drm_device *); 991extern void nv10_fb_takedown(struct drm_device *); 992extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 993 uint32_t, uint32_t); 994 995/* nv30_fb.c */ 996extern int nv30_fb_init(struct drm_device *); 997extern void nv30_fb_takedown(struct drm_device *); 998 999/* nv40_fb.c */ 1000extern int nv40_fb_init(struct drm_device *); 1001extern void nv40_fb_takedown(struct drm_device *); 1002extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 1003 uint32_t, uint32_t); 1004/* nv50_fb.c */ 1005extern int nv50_fb_init(struct drm_device *); 1006extern void nv50_fb_takedown(struct drm_device *); 1007extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1008 1009/* nvc0_fb.c */ 1010extern int nvc0_fb_init(struct drm_device *); 1011extern void nvc0_fb_takedown(struct drm_device *); 1012 1013/* nv04_fifo.c */ 1014extern int nv04_fifo_init(struct drm_device *); 1015extern void nv04_fifo_disable(struct drm_device *); 1016extern void nv04_fifo_enable(struct drm_device *); 1017extern bool nv04_fifo_reassign(struct drm_device *, bool); 1018extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1019extern int nv04_fifo_channel_id(struct drm_device *); 1020extern int nv04_fifo_create_context(struct nouveau_channel *); 1021extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1022extern int nv04_fifo_load_context(struct nouveau_channel *); 1023extern int nv04_fifo_unload_context(struct drm_device *); 1024 1025/* nv10_fifo.c */ 1026extern int nv10_fifo_init(struct drm_device *); 1027extern int nv10_fifo_channel_id(struct drm_device *); 1028extern int nv10_fifo_create_context(struct nouveau_channel *); 1029extern void nv10_fifo_destroy_context(struct nouveau_channel *); 1030extern int nv10_fifo_load_context(struct nouveau_channel *); 1031extern int nv10_fifo_unload_context(struct drm_device *); 1032 1033/* nv40_fifo.c */ 1034extern int nv40_fifo_init(struct drm_device *); 1035extern int nv40_fifo_create_context(struct nouveau_channel *); 1036extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1037extern int nv40_fifo_load_context(struct nouveau_channel *); 1038extern int nv40_fifo_unload_context(struct drm_device *); 1039 1040/* nv50_fifo.c */ 1041extern int nv50_fifo_init(struct drm_device *); 1042extern void nv50_fifo_takedown(struct drm_device *); 1043extern int nv50_fifo_channel_id(struct drm_device *); 1044extern int nv50_fifo_create_context(struct nouveau_channel *); 1045extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1046extern int nv50_fifo_load_context(struct nouveau_channel *); 1047extern int nv50_fifo_unload_context(struct drm_device *); 1048 1049/* nvc0_fifo.c */ 1050extern int nvc0_fifo_init(struct drm_device *); 1051extern void nvc0_fifo_takedown(struct drm_device *); 1052extern void nvc0_fifo_disable(struct drm_device *); 1053extern void nvc0_fifo_enable(struct drm_device *); 1054extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1055extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1056extern int nvc0_fifo_channel_id(struct drm_device *); 1057extern int nvc0_fifo_create_context(struct nouveau_channel *); 1058extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1059extern int nvc0_fifo_load_context(struct nouveau_channel *); 1060extern int nvc0_fifo_unload_context(struct drm_device *); 1061 1062/* nv04_graph.c */ 1063extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1064extern int nv04_graph_init(struct drm_device *); 1065extern void nv04_graph_takedown(struct drm_device *); 1066extern void nv04_graph_fifo_access(struct drm_device *, bool); 1067extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1068extern int nv04_graph_create_context(struct nouveau_channel *); 1069extern void nv04_graph_destroy_context(struct nouveau_channel *); 1070extern int nv04_graph_load_context(struct nouveau_channel *); 1071extern int nv04_graph_unload_context(struct drm_device *); 1072extern void nv04_graph_context_switch(struct drm_device *); 1073 1074/* nv10_graph.c */ 1075extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1076extern int nv10_graph_init(struct drm_device *); 1077extern void nv10_graph_takedown(struct drm_device *); 1078extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1079extern int nv10_graph_create_context(struct nouveau_channel *); 1080extern void nv10_graph_destroy_context(struct nouveau_channel *); 1081extern int nv10_graph_load_context(struct nouveau_channel *); 1082extern int nv10_graph_unload_context(struct drm_device *); 1083extern void nv10_graph_context_switch(struct drm_device *); 1084extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1085 uint32_t, uint32_t); 1086 1087/* nv20_graph.c */ 1088extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1089extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1090extern int nv20_graph_create_context(struct nouveau_channel *); 1091extern void nv20_graph_destroy_context(struct nouveau_channel *); 1092extern int nv20_graph_load_context(struct nouveau_channel *); 1093extern int nv20_graph_unload_context(struct drm_device *); 1094extern int nv20_graph_init(struct drm_device *); 1095extern void nv20_graph_takedown(struct drm_device *); 1096extern int nv30_graph_init(struct drm_device *); 1097extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1098 uint32_t, uint32_t); 1099 1100/* nv40_graph.c */ 1101extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1102extern int nv40_graph_init(struct drm_device *); 1103extern void nv40_graph_takedown(struct drm_device *); 1104extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1105extern int nv40_graph_create_context(struct nouveau_channel *); 1106extern void nv40_graph_destroy_context(struct nouveau_channel *); 1107extern int nv40_graph_load_context(struct nouveau_channel *); 1108extern int nv40_graph_unload_context(struct drm_device *); 1109extern void nv40_grctx_init(struct nouveau_grctx *); 1110extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1111 uint32_t, uint32_t); 1112 1113/* nv50_graph.c */ 1114extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1115extern int nv50_graph_init(struct drm_device *); 1116extern void nv50_graph_takedown(struct drm_device *); 1117extern void nv50_graph_fifo_access(struct drm_device *, bool); 1118extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1119extern int nv50_graph_create_context(struct nouveau_channel *); 1120extern void nv50_graph_destroy_context(struct nouveau_channel *); 1121extern int nv50_graph_load_context(struct nouveau_channel *); 1122extern int nv50_graph_unload_context(struct drm_device *); 1123extern void nv50_graph_context_switch(struct drm_device *); 1124extern int nv50_grctx_init(struct nouveau_grctx *); 1125 1126/* nvc0_graph.c */ 1127extern int nvc0_graph_init(struct drm_device *); 1128extern void nvc0_graph_takedown(struct drm_device *); 1129extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1130extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1131extern int nvc0_graph_create_context(struct nouveau_channel *); 1132extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1133extern int nvc0_graph_load_context(struct nouveau_channel *); 1134extern int nvc0_graph_unload_context(struct drm_device *); 1135 1136/* nv04_instmem.c */ 1137extern int nv04_instmem_init(struct drm_device *); 1138extern void nv04_instmem_takedown(struct drm_device *); 1139extern int nv04_instmem_suspend(struct drm_device *); 1140extern void nv04_instmem_resume(struct drm_device *); 1141extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1142 uint32_t *size); 1143extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1144extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1145extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1146extern void nv04_instmem_flush(struct drm_device *); 1147 1148/* nv50_instmem.c */ 1149extern int nv50_instmem_init(struct drm_device *); 1150extern void nv50_instmem_takedown(struct drm_device *); 1151extern int nv50_instmem_suspend(struct drm_device *); 1152extern void nv50_instmem_resume(struct drm_device *); 1153extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1154 uint32_t *size); 1155extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1156extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1157extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1158extern void nv50_instmem_flush(struct drm_device *); 1159extern void nv84_instmem_flush(struct drm_device *); 1160extern void nv50_vm_flush(struct drm_device *, int engine); 1161 1162/* nvc0_instmem.c */ 1163extern int nvc0_instmem_init(struct drm_device *); 1164extern void nvc0_instmem_takedown(struct drm_device *); 1165extern int nvc0_instmem_suspend(struct drm_device *); 1166extern void nvc0_instmem_resume(struct drm_device *); 1167extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1168 uint32_t *size); 1169extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1170extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1171extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1172extern void nvc0_instmem_flush(struct drm_device *); 1173 1174/* nv04_mc.c */ 1175extern int nv04_mc_init(struct drm_device *); 1176extern void nv04_mc_takedown(struct drm_device *); 1177 1178/* nv40_mc.c */ 1179extern int nv40_mc_init(struct drm_device *); 1180extern void nv40_mc_takedown(struct drm_device *); 1181 1182/* nv50_mc.c */ 1183extern int nv50_mc_init(struct drm_device *); 1184extern void nv50_mc_takedown(struct drm_device *); 1185 1186/* nv04_timer.c */ 1187extern int nv04_timer_init(struct drm_device *); 1188extern uint64_t nv04_timer_read(struct drm_device *); 1189extern void nv04_timer_takedown(struct drm_device *); 1190 1191extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1192 unsigned long arg); 1193 1194/* nv04_dac.c */ 1195extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1196extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1197extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1198extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1199extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1200 1201/* nv04_dfp.c */ 1202extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1203extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1204extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1205 int head, bool dl); 1206extern void nv04_dfp_disable(struct drm_device *dev, int head); 1207extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1208 1209/* nv04_tv.c */ 1210extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1211extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1212 1213/* nv17_tv.c */ 1214extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1215 1216/* nv04_display.c */ 1217extern int nv04_display_early_init(struct drm_device *); 1218extern void nv04_display_late_takedown(struct drm_device *); 1219extern int nv04_display_create(struct drm_device *); 1220extern int nv04_display_init(struct drm_device *); 1221extern void nv04_display_destroy(struct drm_device *); 1222 1223/* nv04_crtc.c */ 1224extern int nv04_crtc_create(struct drm_device *, int index); 1225 1226/* nouveau_bo.c */ 1227extern struct ttm_bo_driver nouveau_bo_driver; 1228extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1229 int size, int align, uint32_t flags, 1230 uint32_t tile_mode, uint32_t tile_flags, 1231 bool no_vm, bool mappable, struct nouveau_bo **); 1232extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1233extern int nouveau_bo_unpin(struct nouveau_bo *); 1234extern int nouveau_bo_map(struct nouveau_bo *); 1235extern void nouveau_bo_unmap(struct nouveau_bo *); 1236extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1237 uint32_t busy); 1238extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1239extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1240extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1241extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1242extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1243 1244/* nouveau_fence.c */ 1245struct nouveau_fence; 1246extern int nouveau_fence_init(struct drm_device *); 1247extern void nouveau_fence_fini(struct drm_device *); 1248extern int nouveau_fence_channel_init(struct nouveau_channel *); 1249extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1250extern void nouveau_fence_update(struct nouveau_channel *); 1251extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1252 bool emit); 1253extern int nouveau_fence_emit(struct nouveau_fence *); 1254extern void nouveau_fence_work(struct nouveau_fence *fence, 1255 void (*work)(void *priv, bool signalled), 1256 void *priv); 1257struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1258extern bool nouveau_fence_signalled(void *obj, void *arg); 1259extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1260extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1261extern int nouveau_fence_flush(void *obj, void *arg); 1262extern void nouveau_fence_unref(void **obj); 1263extern void *nouveau_fence_ref(void *obj); 1264 1265/* nouveau_gem.c */ 1266extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1267 int size, int align, uint32_t flags, 1268 uint32_t tile_mode, uint32_t tile_flags, 1269 bool no_vm, bool mappable, struct nouveau_bo **); 1270extern int nouveau_gem_object_new(struct drm_gem_object *); 1271extern void nouveau_gem_object_del(struct drm_gem_object *); 1272extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1273 struct drm_file *); 1274extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1275 struct drm_file *); 1276extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1277 struct drm_file *); 1278extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1279 struct drm_file *); 1280extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1281 struct drm_file *); 1282 1283/* nv10_gpio.c */ 1284int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1285int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1286 1287/* nv50_gpio.c */ 1288int nv50_gpio_init(struct drm_device *dev); 1289int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1290int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1291void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1292 1293/* nv50_calc. */ 1294int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1295 int *N1, int *M1, int *N2, int *M2, int *P); 1296int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1297 int clk, int *N, int *fN, int *M, int *P); 1298 1299#ifndef ioread32_native 1300#ifdef __BIG_ENDIAN 1301#define ioread16_native ioread16be 1302#define iowrite16_native iowrite16be 1303#define ioread32_native ioread32be 1304#define iowrite32_native iowrite32be 1305#else /* def __BIG_ENDIAN */ 1306#define ioread16_native ioread16 1307#define iowrite16_native iowrite16 1308#define ioread32_native ioread32 1309#define iowrite32_native iowrite32 1310#endif /* def __BIG_ENDIAN else */ 1311#endif /* !ioread32_native */ 1312 1313/* channel control reg access */ 1314static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1315{ 1316 return ioread32_native(chan->user + reg); 1317} 1318 1319static inline void nvchan_wr32(struct nouveau_channel *chan, 1320 unsigned reg, u32 val) 1321{ 1322 iowrite32_native(val, chan->user + reg); 1323} 1324 1325/* register access */ 1326static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1327{ 1328 struct drm_nouveau_private *dev_priv = dev->dev_private; 1329 return ioread32_native(dev_priv->mmio + reg); 1330} 1331 1332static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1333{ 1334 struct drm_nouveau_private *dev_priv = dev->dev_private; 1335 iowrite32_native(val, dev_priv->mmio + reg); 1336} 1337 1338static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1339{ 1340 u32 tmp = nv_rd32(dev, reg); 1341 nv_wr32(dev, reg, (tmp & ~mask) | val); 1342 return tmp; 1343} 1344 1345static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1346{ 1347 struct drm_nouveau_private *dev_priv = dev->dev_private; 1348 return ioread8(dev_priv->mmio + reg); 1349} 1350 1351static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1352{ 1353 struct drm_nouveau_private *dev_priv = dev->dev_private; 1354 iowrite8(val, dev_priv->mmio + reg); 1355} 1356 1357#define nv_wait(dev, reg, mask, val) \ 1358 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1359 1360/* PRAMIN access */ 1361static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1362{ 1363 struct drm_nouveau_private *dev_priv = dev->dev_private; 1364 return ioread32_native(dev_priv->ramin + offset); 1365} 1366 1367static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1368{ 1369 struct drm_nouveau_private *dev_priv = dev->dev_private; 1370 iowrite32_native(val, dev_priv->ramin + offset); 1371} 1372 1373/* object access */ 1374extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1375extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1376 1377/* 1378 * Logging 1379 * Argument d is (struct drm_device *). 1380 */ 1381#define NV_PRINTK(level, d, fmt, arg...) \ 1382 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1383 pci_name(d->pdev), ##arg) 1384#ifndef NV_DEBUG_NOTRACE 1385#define NV_DEBUG(d, fmt, arg...) do { \ 1386 if (drm_debug & DRM_UT_DRIVER) { \ 1387 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1388 __LINE__, ##arg); \ 1389 } \ 1390} while (0) 1391#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1392 if (drm_debug & DRM_UT_KMS) { \ 1393 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1394 __LINE__, ##arg); \ 1395 } \ 1396} while (0) 1397#else 1398#define NV_DEBUG(d, fmt, arg...) do { \ 1399 if (drm_debug & DRM_UT_DRIVER) \ 1400 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1401} while (0) 1402#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1403 if (drm_debug & DRM_UT_KMS) \ 1404 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1405} while (0) 1406#endif 1407#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1408#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1409#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1410#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1411#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1412 1413/* nouveau_reg_debug bitmask */ 1414enum { 1415 NOUVEAU_REG_DEBUG_MC = 0x1, 1416 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1417 NOUVEAU_REG_DEBUG_FB = 0x4, 1418 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1419 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1420 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1421 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1422 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1423 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1424 NOUVEAU_REG_DEBUG_EVO = 0x200, 1425}; 1426 1427#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1428 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1429 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1430} while (0) 1431 1432static inline bool 1433nv_two_heads(struct drm_device *dev) 1434{ 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 const int impl = dev->pci_device & 0x0ff0; 1437 1438 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1439 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1440 return true; 1441 1442 return false; 1443} 1444 1445static inline bool 1446nv_gf4_disp_arch(struct drm_device *dev) 1447{ 1448 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1449} 1450 1451static inline bool 1452nv_two_reg_pll(struct drm_device *dev) 1453{ 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 const int impl = dev->pci_device & 0x0ff0; 1456 1457 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1458 return true; 1459 return false; 1460} 1461 1462static inline bool 1463nv_match_device(struct drm_device *dev, unsigned device, 1464 unsigned sub_vendor, unsigned sub_device) 1465{ 1466 return dev->pdev->device == device && 1467 dev->pdev->subsystem_vendor == sub_vendor && 1468 dev->pdev->subsystem_device == sub_device; 1469} 1470 1471#define NV_SW 0x0000506e 1472#define NV_SW_DMA_SEMAPHORE 0x00000060 1473#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1474#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1475#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1476#define NV_SW_YIELD 0x00000080 1477#define NV_SW_DMA_VBLSEM 0x0000018c 1478#define NV_SW_VBLSEM_OFFSET 0x00000400 1479#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1480#define NV_SW_VBLSEM_RELEASE 0x00000408 1481 1482#endif /* __NOUVEAU_DRV_H__ */ 1483