nouveau_drv.h revision 8d7bb400638906075c38cb07891993cf95076aa7
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435/* Exclusive upper limits */ 436#define NV_MEM_CL_DDR2_MAX 8 437#define NV_MEM_WR_DDR2_MAX 9 438#define NV_MEM_CL_DDR3_MAX 17 439#define NV_MEM_WR_DDR3_MAX 17 440#define NV_MEM_CL_GDDR3_MAX 16 441#define NV_MEM_WR_GDDR3_MAX 18 442#define NV_MEM_CL_GDDR5_MAX 21 443#define NV_MEM_WR_GDDR5_MAX 20 444 445struct nouveau_pm_memtiming { 446 int id; 447 448 u32 reg[9]; 449 u32 mr[4]; 450 451 u8 tCWL; 452 453 u8 odt; 454 u8 drive_strength; 455}; 456 457struct nouveau_pm_tbl_header { 458 u8 version; 459 u8 header_len; 460 u8 entry_cnt; 461 u8 entry_len; 462}; 463 464struct nouveau_pm_tbl_entry { 465 u8 tWR; 466 u8 tWTR; 467 u8 tCL; 468 u8 tRC; 469 u8 empty_4; 470 u8 tRFC; /* Byte 5 */ 471 u8 empty_6; 472 u8 tRAS; /* Byte 7 */ 473 u8 empty_8; 474 u8 tRP; /* Byte 9 */ 475 u8 tRCDRD; 476 u8 tRCDWR; 477 u8 tRRD; 478 u8 tUNK_13; 479 u8 RAM_FT1; /* 14, a bitmask of random RAM features */ 480 u8 empty_15; 481 u8 tUNK_16; 482 u8 empty_17; 483 u8 tUNK_18; 484 u8 tCWL; 485 u8 tUNK_20, tUNK_21; 486}; 487 488struct nouveau_pm_profile; 489struct nouveau_pm_profile_func { 490 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); 491}; 492 493struct nouveau_pm_profile { 494 const struct nouveau_pm_profile_func *func; 495 struct list_head head; 496 char name[8]; 497}; 498 499#define NOUVEAU_PM_MAX_LEVEL 8 500struct nouveau_pm_level { 501 struct nouveau_pm_profile profile; 502 struct device_attribute dev_attr; 503 char name[32]; 504 int id; 505 506 struct nouveau_pm_memtiming timing; 507 u32 memory; 508 u16 memscript; 509 510 u32 core; 511 u32 shader; 512 u32 rop; 513 u32 copy; 514 u32 daemon; 515 u32 vdec; 516 u32 dom6; 517 u32 unka0; /* nva3:nvc0 */ 518 u32 hub01; /* nvc0- */ 519 u32 hub06; /* nvc0- */ 520 u32 hub07; /* nvc0- */ 521 522 u32 volt_min; /* microvolts */ 523 u32 volt_max; 524 u8 fanspeed; 525}; 526 527struct nouveau_pm_temp_sensor_constants { 528 u16 offset_constant; 529 s16 offset_mult; 530 s16 offset_div; 531 s16 slope_mult; 532 s16 slope_div; 533}; 534 535struct nouveau_pm_threshold_temp { 536 s16 critical; 537 s16 down_clock; 538 s16 fan_boost; 539}; 540 541struct nouveau_pm_fan { 542 u32 percent; 543 u32 min_duty; 544 u32 max_duty; 545 u32 pwm_freq; 546 u32 pwm_divisor; 547}; 548 549struct nouveau_pm_engine { 550 struct nouveau_pm_voltage voltage; 551 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 552 int nr_perflvl; 553 struct nouveau_pm_temp_sensor_constants sensor_constants; 554 struct nouveau_pm_threshold_temp threshold_temp; 555 struct nouveau_pm_fan fan; 556 557 struct nouveau_pm_profile *profile_ac; 558 struct nouveau_pm_profile *profile_dc; 559 struct list_head profiles; 560 561 struct nouveau_pm_level boot; 562 struct nouveau_pm_level *cur; 563 564 struct device *hwmon; 565 struct notifier_block acpi_nb; 566 567 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 568 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 569 int (*clocks_set)(struct drm_device *, void *); 570 571 int (*voltage_get)(struct drm_device *); 572 int (*voltage_set)(struct drm_device *, int voltage); 573 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 574 int (*pwm_set)(struct drm_device *, int line, u32, u32); 575 int (*temp_get)(struct drm_device *); 576}; 577 578struct nouveau_vram_engine { 579 struct nouveau_mm mm; 580 581 int (*init)(struct drm_device *); 582 void (*takedown)(struct drm_device *dev); 583 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 584 u32 type, struct nouveau_mem **); 585 void (*put)(struct drm_device *, struct nouveau_mem **); 586 587 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 588}; 589 590struct nouveau_engine { 591 struct nouveau_instmem_engine instmem; 592 struct nouveau_mc_engine mc; 593 struct nouveau_timer_engine timer; 594 struct nouveau_fb_engine fb; 595 struct nouveau_fifo_engine fifo; 596 struct nouveau_display_engine display; 597 struct nouveau_gpio_engine gpio; 598 struct nouveau_pm_engine pm; 599 struct nouveau_vram_engine vram; 600}; 601 602struct nouveau_pll_vals { 603 union { 604 struct { 605#ifdef __BIG_ENDIAN 606 uint8_t N1, M1, N2, M2; 607#else 608 uint8_t M1, N1, M2, N2; 609#endif 610 }; 611 struct { 612 uint16_t NM1, NM2; 613 } __attribute__((packed)); 614 }; 615 int log2P; 616 617 int refclk; 618}; 619 620enum nv04_fp_display_regs { 621 FP_DISPLAY_END, 622 FP_TOTAL, 623 FP_CRTC, 624 FP_SYNC_START, 625 FP_SYNC_END, 626 FP_VALID_START, 627 FP_VALID_END 628}; 629 630struct nv04_crtc_reg { 631 unsigned char MiscOutReg; 632 uint8_t CRTC[0xa0]; 633 uint8_t CR58[0x10]; 634 uint8_t Sequencer[5]; 635 uint8_t Graphics[9]; 636 uint8_t Attribute[21]; 637 unsigned char DAC[768]; 638 639 /* PCRTC regs */ 640 uint32_t fb_start; 641 uint32_t crtc_cfg; 642 uint32_t cursor_cfg; 643 uint32_t gpio_ext; 644 uint32_t crtc_830; 645 uint32_t crtc_834; 646 uint32_t crtc_850; 647 uint32_t crtc_eng_ctrl; 648 649 /* PRAMDAC regs */ 650 uint32_t nv10_cursync; 651 struct nouveau_pll_vals pllvals; 652 uint32_t ramdac_gen_ctrl; 653 uint32_t ramdac_630; 654 uint32_t ramdac_634; 655 uint32_t tv_setup; 656 uint32_t tv_vtotal; 657 uint32_t tv_vskew; 658 uint32_t tv_vsync_delay; 659 uint32_t tv_htotal; 660 uint32_t tv_hskew; 661 uint32_t tv_hsync_delay; 662 uint32_t tv_hsync_delay2; 663 uint32_t fp_horiz_regs[7]; 664 uint32_t fp_vert_regs[7]; 665 uint32_t dither; 666 uint32_t fp_control; 667 uint32_t dither_regs[6]; 668 uint32_t fp_debug_0; 669 uint32_t fp_debug_1; 670 uint32_t fp_debug_2; 671 uint32_t fp_margin_color; 672 uint32_t ramdac_8c0; 673 uint32_t ramdac_a20; 674 uint32_t ramdac_a24; 675 uint32_t ramdac_a34; 676 uint32_t ctv_regs[38]; 677}; 678 679struct nv04_output_reg { 680 uint32_t output; 681 int head; 682}; 683 684struct nv04_mode_state { 685 struct nv04_crtc_reg crtc_reg[2]; 686 uint32_t pllsel; 687 uint32_t sel_clk; 688}; 689 690enum nouveau_card_type { 691 NV_04 = 0x00, 692 NV_10 = 0x10, 693 NV_20 = 0x20, 694 NV_30 = 0x30, 695 NV_40 = 0x40, 696 NV_50 = 0x50, 697 NV_C0 = 0xc0, 698 NV_D0 = 0xd0 699}; 700 701struct drm_nouveau_private { 702 struct drm_device *dev; 703 bool noaccel; 704 705 /* the card type, takes NV_* as values */ 706 enum nouveau_card_type card_type; 707 /* exact chipset, derived from NV_PMC_BOOT_0 */ 708 int chipset; 709 int flags; 710 u32 crystal; 711 712 void __iomem *mmio; 713 714 spinlock_t ramin_lock; 715 void __iomem *ramin; 716 u32 ramin_size; 717 u32 ramin_base; 718 bool ramin_available; 719 struct drm_mm ramin_heap; 720 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 721 struct list_head gpuobj_list; 722 struct list_head classes; 723 724 struct nouveau_bo *vga_ram; 725 726 /* interrupt handling */ 727 void (*irq_handler[32])(struct drm_device *); 728 bool msi_enabled; 729 730 struct list_head vbl_waiting; 731 732 struct { 733 struct drm_global_reference mem_global_ref; 734 struct ttm_bo_global_ref bo_global_ref; 735 struct ttm_bo_device bdev; 736 atomic_t validate_sequence; 737 } ttm; 738 739 struct { 740 spinlock_t lock; 741 struct drm_mm heap; 742 struct nouveau_bo *bo; 743 } fence; 744 745 struct { 746 spinlock_t lock; 747 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 748 } channels; 749 750 struct nouveau_engine engine; 751 struct nouveau_channel *channel; 752 753 /* For PFIFO and PGRAPH. */ 754 spinlock_t context_switch_lock; 755 756 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 757 spinlock_t vm_lock; 758 759 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 760 struct nouveau_ramht *ramht; 761 struct nouveau_gpuobj *ramfc; 762 struct nouveau_gpuobj *ramro; 763 764 uint32_t ramin_rsvd_vram; 765 766 struct { 767 enum { 768 NOUVEAU_GART_NONE = 0, 769 NOUVEAU_GART_AGP, /* AGP */ 770 NOUVEAU_GART_PDMA, /* paged dma object */ 771 NOUVEAU_GART_HW /* on-chip gart/vm */ 772 } type; 773 uint64_t aper_base; 774 uint64_t aper_size; 775 uint64_t aper_free; 776 777 struct ttm_backend_func *func; 778 779 struct { 780 struct page *page; 781 dma_addr_t addr; 782 } dummy; 783 784 struct nouveau_gpuobj *sg_ctxdma; 785 } gart_info; 786 787 /* nv10-nv40 tiling regions */ 788 struct { 789 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 790 spinlock_t lock; 791 } tile; 792 793 /* VRAM/fb configuration */ 794 enum { 795 NV_MEM_TYPE_UNKNOWN = 0, 796 NV_MEM_TYPE_STOLEN, 797 NV_MEM_TYPE_SGRAM, 798 NV_MEM_TYPE_SDRAM, 799 NV_MEM_TYPE_DDR1, 800 NV_MEM_TYPE_DDR2, 801 NV_MEM_TYPE_DDR3, 802 NV_MEM_TYPE_GDDR2, 803 NV_MEM_TYPE_GDDR3, 804 NV_MEM_TYPE_GDDR4, 805 NV_MEM_TYPE_GDDR5 806 } vram_type; 807 uint64_t vram_size; 808 uint64_t vram_sys_base; 809 bool vram_rank_B; 810 811 uint64_t fb_available_size; 812 uint64_t fb_mappable_pages; 813 uint64_t fb_aper_free; 814 int fb_mtrr; 815 816 /* BAR control (NV50-) */ 817 struct nouveau_vm *bar1_vm; 818 struct nouveau_vm *bar3_vm; 819 820 /* G8x/G9x virtual address space */ 821 struct nouveau_vm *chan_vm; 822 823 struct nvbios vbios; 824 u8 *mxms; 825 struct list_head i2c_ports; 826 827 struct nv04_mode_state mode_reg; 828 struct nv04_mode_state saved_reg; 829 uint32_t saved_vga_font[4][16384]; 830 uint32_t crtc_owner; 831 uint32_t dac_users[4]; 832 833 struct backlight_device *backlight; 834 835 struct { 836 struct dentry *channel_root; 837 } debugfs; 838 839 struct nouveau_fbdev *nfbdev; 840 struct apertures_struct *apertures; 841}; 842 843static inline struct drm_nouveau_private * 844nouveau_private(struct drm_device *dev) 845{ 846 return dev->dev_private; 847} 848 849static inline struct drm_nouveau_private * 850nouveau_bdev(struct ttm_bo_device *bd) 851{ 852 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 853} 854 855static inline int 856nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 857{ 858 struct nouveau_bo *prev; 859 860 if (!pnvbo) 861 return -EINVAL; 862 prev = *pnvbo; 863 864 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 865 if (prev) { 866 struct ttm_buffer_object *bo = &prev->bo; 867 868 ttm_bo_unref(&bo); 869 } 870 871 return 0; 872} 873 874/* nouveau_drv.c */ 875extern int nouveau_modeset; 876extern int nouveau_agpmode; 877extern int nouveau_duallink; 878extern int nouveau_uscript_lvds; 879extern int nouveau_uscript_tmds; 880extern int nouveau_vram_pushbuf; 881extern int nouveau_vram_notify; 882extern char *nouveau_vram_type; 883extern int nouveau_fbpercrtc; 884extern int nouveau_tv_disable; 885extern char *nouveau_tv_norm; 886extern int nouveau_reg_debug; 887extern char *nouveau_vbios; 888extern int nouveau_ignorelid; 889extern int nouveau_nofbaccel; 890extern int nouveau_noaccel; 891extern int nouveau_force_post; 892extern int nouveau_override_conntype; 893extern char *nouveau_perflvl; 894extern int nouveau_perflvl_wr; 895extern int nouveau_msi; 896extern int nouveau_ctxfw; 897extern int nouveau_mxmdcb; 898 899extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 900extern int nouveau_pci_resume(struct pci_dev *pdev); 901 902/* nouveau_state.c */ 903extern int nouveau_open(struct drm_device *, struct drm_file *); 904extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 905extern void nouveau_postclose(struct drm_device *, struct drm_file *); 906extern int nouveau_load(struct drm_device *, unsigned long flags); 907extern int nouveau_firstopen(struct drm_device *); 908extern void nouveau_lastclose(struct drm_device *); 909extern int nouveau_unload(struct drm_device *); 910extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 911 struct drm_file *); 912extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 913 struct drm_file *); 914extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 915 uint32_t reg, uint32_t mask, uint32_t val); 916extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 917 uint32_t reg, uint32_t mask, uint32_t val); 918extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 919 bool (*cond)(void *), void *); 920extern bool nouveau_wait_for_idle(struct drm_device *); 921extern int nouveau_card_init(struct drm_device *); 922 923/* nouveau_mem.c */ 924extern int nouveau_mem_vram_init(struct drm_device *); 925extern void nouveau_mem_vram_fini(struct drm_device *); 926extern int nouveau_mem_gart_init(struct drm_device *); 927extern void nouveau_mem_gart_fini(struct drm_device *); 928extern int nouveau_mem_init_agp(struct drm_device *); 929extern int nouveau_mem_reset_agp(struct drm_device *); 930extern void nouveau_mem_close(struct drm_device *); 931extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 932extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, 933 struct nouveau_pm_memtiming *); 934extern void nouveau_mem_timing_read(struct drm_device *, 935 struct nouveau_pm_memtiming *); 936extern int nouveau_mem_vbios_type(struct drm_device *); 937extern struct nouveau_tile_reg *nv10_mem_set_tiling( 938 struct drm_device *dev, uint32_t addr, uint32_t size, 939 uint32_t pitch, uint32_t flags); 940extern void nv10_mem_put_tile_region(struct drm_device *dev, 941 struct nouveau_tile_reg *tile, 942 struct nouveau_fence *fence); 943extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 944extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 945 946/* nouveau_notifier.c */ 947extern int nouveau_notifier_init_channel(struct nouveau_channel *); 948extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 949extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 950 int cout, uint32_t start, uint32_t end, 951 uint32_t *offset); 952extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 953extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 954 struct drm_file *); 955extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 956 struct drm_file *); 957 958/* nouveau_channel.c */ 959extern struct drm_ioctl_desc nouveau_ioctls[]; 960extern int nouveau_max_ioctl; 961extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 962extern int nouveau_channel_alloc(struct drm_device *dev, 963 struct nouveau_channel **chan, 964 struct drm_file *file_priv, 965 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 966extern struct nouveau_channel * 967nouveau_channel_get_unlocked(struct nouveau_channel *); 968extern struct nouveau_channel * 969nouveau_channel_get(struct drm_file *, int id); 970extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 971extern void nouveau_channel_put(struct nouveau_channel **); 972extern void nouveau_channel_ref(struct nouveau_channel *chan, 973 struct nouveau_channel **pchan); 974extern void nouveau_channel_idle(struct nouveau_channel *chan); 975 976/* nouveau_object.c */ 977#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 978 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 979 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 980} while (0) 981 982#define NVOBJ_ENGINE_DEL(d, e) do { \ 983 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 984 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 985} while (0) 986 987#define NVOBJ_CLASS(d, c, e) do { \ 988 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 989 if (ret) \ 990 return ret; \ 991} while (0) 992 993#define NVOBJ_MTHD(d, c, m, e) do { \ 994 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 995 if (ret) \ 996 return ret; \ 997} while (0) 998 999extern int nouveau_gpuobj_early_init(struct drm_device *); 1000extern int nouveau_gpuobj_init(struct drm_device *); 1001extern void nouveau_gpuobj_takedown(struct drm_device *); 1002extern int nouveau_gpuobj_suspend(struct drm_device *dev); 1003extern void nouveau_gpuobj_resume(struct drm_device *dev); 1004extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 1005extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 1006 int (*exec)(struct nouveau_channel *, 1007 u32 class, u32 mthd, u32 data)); 1008extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 1009extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 1010extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 1011 uint32_t vram_h, uint32_t tt_h); 1012extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 1013extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 1014 uint32_t size, int align, uint32_t flags, 1015 struct nouveau_gpuobj **); 1016extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 1017 struct nouveau_gpuobj **); 1018extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 1019 u32 size, u32 flags, 1020 struct nouveau_gpuobj **); 1021extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 1022 uint64_t offset, uint64_t size, int access, 1023 int target, struct nouveau_gpuobj **); 1024extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1025extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1026 u64 size, int target, int access, u32 type, 1027 u32 comp, struct nouveau_gpuobj **pobj); 1028extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1029 int class, u64 base, u64 size, int target, 1030 int access, u32 type, u32 comp); 1031extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1032 struct drm_file *); 1033extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1034 struct drm_file *); 1035 1036/* nouveau_irq.c */ 1037extern int nouveau_irq_init(struct drm_device *); 1038extern void nouveau_irq_fini(struct drm_device *); 1039extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1040extern void nouveau_irq_register(struct drm_device *, int status_bit, 1041 void (*)(struct drm_device *)); 1042extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1043extern void nouveau_irq_preinstall(struct drm_device *); 1044extern int nouveau_irq_postinstall(struct drm_device *); 1045extern void nouveau_irq_uninstall(struct drm_device *); 1046 1047/* nouveau_sgdma.c */ 1048extern int nouveau_sgdma_init(struct drm_device *); 1049extern void nouveau_sgdma_takedown(struct drm_device *); 1050extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1051 uint32_t offset); 1052extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1053 unsigned long size, 1054 uint32_t page_flags, 1055 struct page *dummy_read_page); 1056 1057/* nouveau_debugfs.c */ 1058#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1059extern int nouveau_debugfs_init(struct drm_minor *); 1060extern void nouveau_debugfs_takedown(struct drm_minor *); 1061extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1062extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1063#else 1064static inline int 1065nouveau_debugfs_init(struct drm_minor *minor) 1066{ 1067 return 0; 1068} 1069 1070static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1071{ 1072} 1073 1074static inline int 1075nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1076{ 1077 return 0; 1078} 1079 1080static inline void 1081nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1082{ 1083} 1084#endif 1085 1086/* nouveau_dma.c */ 1087extern void nouveau_dma_pre_init(struct nouveau_channel *); 1088extern int nouveau_dma_init(struct nouveau_channel *); 1089extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1090 1091/* nouveau_acpi.c */ 1092#define ROM_BIOS_PAGE 4096 1093#if defined(CONFIG_ACPI) 1094void nouveau_register_dsm_handler(void); 1095void nouveau_unregister_dsm_handler(void); 1096void nouveau_switcheroo_optimus_dsm(void); 1097int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1098bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1099int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1100#else 1101static inline void nouveau_register_dsm_handler(void) {} 1102static inline void nouveau_unregister_dsm_handler(void) {} 1103static inline void nouveau_switcheroo_optimus_dsm(void) {} 1104static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1105static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1106static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1107#endif 1108 1109/* nouveau_backlight.c */ 1110#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1111extern int nouveau_backlight_init(struct drm_device *); 1112extern void nouveau_backlight_exit(struct drm_device *); 1113#else 1114static inline int nouveau_backlight_init(struct drm_device *dev) 1115{ 1116 return 0; 1117} 1118 1119static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1120#endif 1121 1122/* nouveau_bios.c */ 1123extern int nouveau_bios_init(struct drm_device *); 1124extern void nouveau_bios_takedown(struct drm_device *dev); 1125extern int nouveau_run_vbios_init(struct drm_device *); 1126extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1127 struct dcb_entry *, int crtc); 1128extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1129extern struct dcb_connector_table_entry * 1130nouveau_bios_connector_entry(struct drm_device *, int index); 1131extern u32 get_pll_register(struct drm_device *, enum pll_types); 1132extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1133 struct pll_lims *); 1134extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1135 struct dcb_entry *, int crtc); 1136extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1137extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1138extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1139 bool *dl, bool *if_is_24bit); 1140extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1141 int head, int pxclk); 1142extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1143 enum LVDS_script, int pxclk); 1144bool bios_encoder_match(struct dcb_entry *, u32 hash); 1145 1146/* nouveau_mxm.c */ 1147int nouveau_mxm_init(struct drm_device *dev); 1148void nouveau_mxm_fini(struct drm_device *dev); 1149 1150/* nouveau_ttm.c */ 1151int nouveau_ttm_global_init(struct drm_nouveau_private *); 1152void nouveau_ttm_global_release(struct drm_nouveau_private *); 1153int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1154 1155/* nouveau_hdmi.c */ 1156void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1157 1158/* nouveau_dp.c */ 1159int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1160 uint8_t *data, int data_nr); 1161bool nouveau_dp_detect(struct drm_encoder *); 1162bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1163void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1164u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1165 1166/* nv04_fb.c */ 1167extern int nv04_fb_vram_init(struct drm_device *); 1168extern int nv04_fb_init(struct drm_device *); 1169extern void nv04_fb_takedown(struct drm_device *); 1170 1171/* nv10_fb.c */ 1172extern int nv10_fb_vram_init(struct drm_device *dev); 1173extern int nv1a_fb_vram_init(struct drm_device *dev); 1174extern int nv10_fb_init(struct drm_device *); 1175extern void nv10_fb_takedown(struct drm_device *); 1176extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1177 uint32_t addr, uint32_t size, 1178 uint32_t pitch, uint32_t flags); 1179extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1180extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1181 1182/* nv20_fb.c */ 1183extern int nv20_fb_vram_init(struct drm_device *dev); 1184extern int nv20_fb_init(struct drm_device *); 1185extern void nv20_fb_takedown(struct drm_device *); 1186extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1187 uint32_t addr, uint32_t size, 1188 uint32_t pitch, uint32_t flags); 1189extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1190extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1191 1192/* nv30_fb.c */ 1193extern int nv30_fb_init(struct drm_device *); 1194extern void nv30_fb_takedown(struct drm_device *); 1195extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1196 uint32_t addr, uint32_t size, 1197 uint32_t pitch, uint32_t flags); 1198extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1199 1200/* nv40_fb.c */ 1201extern int nv40_fb_vram_init(struct drm_device *dev); 1202extern int nv40_fb_init(struct drm_device *); 1203extern void nv40_fb_takedown(struct drm_device *); 1204extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1205 1206/* nv50_fb.c */ 1207extern int nv50_fb_init(struct drm_device *); 1208extern void nv50_fb_takedown(struct drm_device *); 1209extern void nv50_fb_vm_trap(struct drm_device *, int display); 1210 1211/* nvc0_fb.c */ 1212extern int nvc0_fb_init(struct drm_device *); 1213extern void nvc0_fb_takedown(struct drm_device *); 1214 1215/* nv04_fifo.c */ 1216extern int nv04_fifo_init(struct drm_device *); 1217extern void nv04_fifo_fini(struct drm_device *); 1218extern void nv04_fifo_disable(struct drm_device *); 1219extern void nv04_fifo_enable(struct drm_device *); 1220extern bool nv04_fifo_reassign(struct drm_device *, bool); 1221extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1222extern int nv04_fifo_channel_id(struct drm_device *); 1223extern int nv04_fifo_create_context(struct nouveau_channel *); 1224extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1225extern int nv04_fifo_load_context(struct nouveau_channel *); 1226extern int nv04_fifo_unload_context(struct drm_device *); 1227extern void nv04_fifo_isr(struct drm_device *); 1228 1229/* nv10_fifo.c */ 1230extern int nv10_fifo_init(struct drm_device *); 1231extern int nv10_fifo_channel_id(struct drm_device *); 1232extern int nv10_fifo_create_context(struct nouveau_channel *); 1233extern int nv10_fifo_load_context(struct nouveau_channel *); 1234extern int nv10_fifo_unload_context(struct drm_device *); 1235 1236/* nv40_fifo.c */ 1237extern int nv40_fifo_init(struct drm_device *); 1238extern int nv40_fifo_create_context(struct nouveau_channel *); 1239extern int nv40_fifo_load_context(struct nouveau_channel *); 1240extern int nv40_fifo_unload_context(struct drm_device *); 1241 1242/* nv50_fifo.c */ 1243extern int nv50_fifo_init(struct drm_device *); 1244extern void nv50_fifo_takedown(struct drm_device *); 1245extern int nv50_fifo_channel_id(struct drm_device *); 1246extern int nv50_fifo_create_context(struct nouveau_channel *); 1247extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1248extern int nv50_fifo_load_context(struct nouveau_channel *); 1249extern int nv50_fifo_unload_context(struct drm_device *); 1250extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1251 1252/* nvc0_fifo.c */ 1253extern int nvc0_fifo_init(struct drm_device *); 1254extern void nvc0_fifo_takedown(struct drm_device *); 1255extern void nvc0_fifo_disable(struct drm_device *); 1256extern void nvc0_fifo_enable(struct drm_device *); 1257extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1258extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1259extern int nvc0_fifo_channel_id(struct drm_device *); 1260extern int nvc0_fifo_create_context(struct nouveau_channel *); 1261extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1262extern int nvc0_fifo_load_context(struct nouveau_channel *); 1263extern int nvc0_fifo_unload_context(struct drm_device *); 1264 1265/* nv04_graph.c */ 1266extern int nv04_graph_create(struct drm_device *); 1267extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1268extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1269 u32 class, u32 mthd, u32 data); 1270extern struct nouveau_bitfield nv04_graph_nsource[]; 1271 1272/* nv10_graph.c */ 1273extern int nv10_graph_create(struct drm_device *); 1274extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1275extern struct nouveau_bitfield nv10_graph_intr[]; 1276extern struct nouveau_bitfield nv10_graph_nstatus[]; 1277 1278/* nv20_graph.c */ 1279extern int nv20_graph_create(struct drm_device *); 1280 1281/* nv40_graph.c */ 1282extern int nv40_graph_create(struct drm_device *); 1283extern void nv40_grctx_init(struct nouveau_grctx *); 1284 1285/* nv50_graph.c */ 1286extern int nv50_graph_create(struct drm_device *); 1287extern int nv50_grctx_init(struct nouveau_grctx *); 1288extern struct nouveau_enum nv50_data_error_names[]; 1289extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1290 1291/* nvc0_graph.c */ 1292extern int nvc0_graph_create(struct drm_device *); 1293extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1294 1295/* nv84_crypt.c */ 1296extern int nv84_crypt_create(struct drm_device *); 1297 1298/* nv98_crypt.c */ 1299extern int nv98_crypt_create(struct drm_device *dev); 1300 1301/* nva3_copy.c */ 1302extern int nva3_copy_create(struct drm_device *dev); 1303 1304/* nvc0_copy.c */ 1305extern int nvc0_copy_create(struct drm_device *dev, int engine); 1306 1307/* nv31_mpeg.c */ 1308extern int nv31_mpeg_create(struct drm_device *dev); 1309 1310/* nv50_mpeg.c */ 1311extern int nv50_mpeg_create(struct drm_device *dev); 1312 1313/* nv84_bsp.c */ 1314/* nv98_bsp.c */ 1315extern int nv84_bsp_create(struct drm_device *dev); 1316 1317/* nv84_vp.c */ 1318/* nv98_vp.c */ 1319extern int nv84_vp_create(struct drm_device *dev); 1320 1321/* nv98_ppp.c */ 1322extern int nv98_ppp_create(struct drm_device *dev); 1323 1324/* nv04_instmem.c */ 1325extern int nv04_instmem_init(struct drm_device *); 1326extern void nv04_instmem_takedown(struct drm_device *); 1327extern int nv04_instmem_suspend(struct drm_device *); 1328extern void nv04_instmem_resume(struct drm_device *); 1329extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1330 u32 size, u32 align); 1331extern void nv04_instmem_put(struct nouveau_gpuobj *); 1332extern int nv04_instmem_map(struct nouveau_gpuobj *); 1333extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1334extern void nv04_instmem_flush(struct drm_device *); 1335 1336/* nv50_instmem.c */ 1337extern int nv50_instmem_init(struct drm_device *); 1338extern void nv50_instmem_takedown(struct drm_device *); 1339extern int nv50_instmem_suspend(struct drm_device *); 1340extern void nv50_instmem_resume(struct drm_device *); 1341extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1342 u32 size, u32 align); 1343extern void nv50_instmem_put(struct nouveau_gpuobj *); 1344extern int nv50_instmem_map(struct nouveau_gpuobj *); 1345extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1346extern void nv50_instmem_flush(struct drm_device *); 1347extern void nv84_instmem_flush(struct drm_device *); 1348 1349/* nvc0_instmem.c */ 1350extern int nvc0_instmem_init(struct drm_device *); 1351extern void nvc0_instmem_takedown(struct drm_device *); 1352extern int nvc0_instmem_suspend(struct drm_device *); 1353extern void nvc0_instmem_resume(struct drm_device *); 1354 1355/* nv04_mc.c */ 1356extern int nv04_mc_init(struct drm_device *); 1357extern void nv04_mc_takedown(struct drm_device *); 1358 1359/* nv40_mc.c */ 1360extern int nv40_mc_init(struct drm_device *); 1361extern void nv40_mc_takedown(struct drm_device *); 1362 1363/* nv50_mc.c */ 1364extern int nv50_mc_init(struct drm_device *); 1365extern void nv50_mc_takedown(struct drm_device *); 1366 1367/* nv04_timer.c */ 1368extern int nv04_timer_init(struct drm_device *); 1369extern uint64_t nv04_timer_read(struct drm_device *); 1370extern void nv04_timer_takedown(struct drm_device *); 1371 1372extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1373 unsigned long arg); 1374 1375/* nv04_dac.c */ 1376extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1377extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1378extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1379extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1380extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1381 1382/* nv04_dfp.c */ 1383extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1384extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1385extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1386 int head, bool dl); 1387extern void nv04_dfp_disable(struct drm_device *dev, int head); 1388extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1389 1390/* nv04_tv.c */ 1391extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1392extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1393 1394/* nv17_tv.c */ 1395extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1396 1397/* nv04_display.c */ 1398extern int nv04_display_early_init(struct drm_device *); 1399extern void nv04_display_late_takedown(struct drm_device *); 1400extern int nv04_display_create(struct drm_device *); 1401extern void nv04_display_destroy(struct drm_device *); 1402extern int nv04_display_init(struct drm_device *); 1403extern void nv04_display_fini(struct drm_device *); 1404 1405/* nvd0_display.c */ 1406extern int nvd0_display_create(struct drm_device *); 1407extern void nvd0_display_destroy(struct drm_device *); 1408extern int nvd0_display_init(struct drm_device *); 1409extern void nvd0_display_fini(struct drm_device *); 1410struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1411void nvd0_display_flip_stop(struct drm_crtc *); 1412int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1413 struct nouveau_channel *, u32 swap_interval); 1414 1415/* nv04_crtc.c */ 1416extern int nv04_crtc_create(struct drm_device *, int index); 1417 1418/* nouveau_bo.c */ 1419extern struct ttm_bo_driver nouveau_bo_driver; 1420extern int nouveau_bo_new(struct drm_device *, int size, int align, 1421 uint32_t flags, uint32_t tile_mode, 1422 uint32_t tile_flags, struct nouveau_bo **); 1423extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1424extern int nouveau_bo_unpin(struct nouveau_bo *); 1425extern int nouveau_bo_map(struct nouveau_bo *); 1426extern void nouveau_bo_unmap(struct nouveau_bo *); 1427extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1428 uint32_t busy); 1429extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1430extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1431extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1432extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1433extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1434extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1435 bool no_wait_reserve, bool no_wait_gpu); 1436 1437extern struct nouveau_vma * 1438nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1439extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1440 struct nouveau_vma *); 1441extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1442 1443/* nouveau_fence.c */ 1444struct nouveau_fence; 1445extern int nouveau_fence_init(struct drm_device *); 1446extern void nouveau_fence_fini(struct drm_device *); 1447extern int nouveau_fence_channel_init(struct nouveau_channel *); 1448extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1449extern void nouveau_fence_update(struct nouveau_channel *); 1450extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1451 bool emit); 1452extern int nouveau_fence_emit(struct nouveau_fence *); 1453extern void nouveau_fence_work(struct nouveau_fence *fence, 1454 void (*work)(void *priv, bool signalled), 1455 void *priv); 1456struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1457 1458extern bool __nouveau_fence_signalled(void *obj, void *arg); 1459extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1460extern int __nouveau_fence_flush(void *obj, void *arg); 1461extern void __nouveau_fence_unref(void **obj); 1462extern void *__nouveau_fence_ref(void *obj); 1463 1464static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1465{ 1466 return __nouveau_fence_signalled(obj, NULL); 1467} 1468static inline int 1469nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1470{ 1471 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1472} 1473extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1474static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1475{ 1476 return __nouveau_fence_flush(obj, NULL); 1477} 1478static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1479{ 1480 __nouveau_fence_unref((void **)obj); 1481} 1482static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1483{ 1484 return __nouveau_fence_ref(obj); 1485} 1486 1487/* nouveau_gem.c */ 1488extern int nouveau_gem_new(struct drm_device *, int size, int align, 1489 uint32_t domain, uint32_t tile_mode, 1490 uint32_t tile_flags, struct nouveau_bo **); 1491extern int nouveau_gem_object_new(struct drm_gem_object *); 1492extern void nouveau_gem_object_del(struct drm_gem_object *); 1493extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1494extern void nouveau_gem_object_close(struct drm_gem_object *, 1495 struct drm_file *); 1496extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1497 struct drm_file *); 1498extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1499 struct drm_file *); 1500extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1501 struct drm_file *); 1502extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1503 struct drm_file *); 1504extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1505 struct drm_file *); 1506 1507/* nouveau_display.c */ 1508int nouveau_display_create(struct drm_device *dev); 1509void nouveau_display_destroy(struct drm_device *dev); 1510int nouveau_display_init(struct drm_device *dev); 1511void nouveau_display_fini(struct drm_device *dev); 1512int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1513void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1514int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1515 struct drm_pending_vblank_event *event); 1516int nouveau_finish_page_flip(struct nouveau_channel *, 1517 struct nouveau_page_flip_state *); 1518int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1519 struct drm_mode_create_dumb *args); 1520int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1521 uint32_t handle, uint64_t *offset); 1522int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1523 uint32_t handle); 1524 1525/* nv10_gpio.c */ 1526int nv10_gpio_init(struct drm_device *dev); 1527void nv10_gpio_fini(struct drm_device *dev); 1528int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1529int nv10_gpio_sense(struct drm_device *dev, int line); 1530void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1531 1532/* nv50_gpio.c */ 1533int nv50_gpio_init(struct drm_device *dev); 1534void nv50_gpio_fini(struct drm_device *dev); 1535int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1536int nv50_gpio_sense(struct drm_device *dev, int line); 1537void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1538int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1539int nvd0_gpio_sense(struct drm_device *dev, int line); 1540 1541/* nv50_calc.c */ 1542int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1543 int *N1, int *M1, int *N2, int *M2, int *P); 1544int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1545 int clk, int *N, int *fN, int *M, int *P); 1546 1547#ifndef ioread32_native 1548#ifdef __BIG_ENDIAN 1549#define ioread16_native ioread16be 1550#define iowrite16_native iowrite16be 1551#define ioread32_native ioread32be 1552#define iowrite32_native iowrite32be 1553#else /* def __BIG_ENDIAN */ 1554#define ioread16_native ioread16 1555#define iowrite16_native iowrite16 1556#define ioread32_native ioread32 1557#define iowrite32_native iowrite32 1558#endif /* def __BIG_ENDIAN else */ 1559#endif /* !ioread32_native */ 1560 1561/* channel control reg access */ 1562static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1563{ 1564 return ioread32_native(chan->user + reg); 1565} 1566 1567static inline void nvchan_wr32(struct nouveau_channel *chan, 1568 unsigned reg, u32 val) 1569{ 1570 iowrite32_native(val, chan->user + reg); 1571} 1572 1573/* register access */ 1574static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1575{ 1576 struct drm_nouveau_private *dev_priv = dev->dev_private; 1577 return ioread32_native(dev_priv->mmio + reg); 1578} 1579 1580static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1581{ 1582 struct drm_nouveau_private *dev_priv = dev->dev_private; 1583 iowrite32_native(val, dev_priv->mmio + reg); 1584} 1585 1586static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1587{ 1588 u32 tmp = nv_rd32(dev, reg); 1589 nv_wr32(dev, reg, (tmp & ~mask) | val); 1590 return tmp; 1591} 1592 1593static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1594{ 1595 struct drm_nouveau_private *dev_priv = dev->dev_private; 1596 return ioread8(dev_priv->mmio + reg); 1597} 1598 1599static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1600{ 1601 struct drm_nouveau_private *dev_priv = dev->dev_private; 1602 iowrite8(val, dev_priv->mmio + reg); 1603} 1604 1605#define nv_wait(dev, reg, mask, val) \ 1606 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1607#define nv_wait_ne(dev, reg, mask, val) \ 1608 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1609#define nv_wait_cb(dev, func, data) \ 1610 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1611 1612/* PRAMIN access */ 1613static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1614{ 1615 struct drm_nouveau_private *dev_priv = dev->dev_private; 1616 return ioread32_native(dev_priv->ramin + offset); 1617} 1618 1619static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1620{ 1621 struct drm_nouveau_private *dev_priv = dev->dev_private; 1622 iowrite32_native(val, dev_priv->ramin + offset); 1623} 1624 1625/* object access */ 1626extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1627extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1628 1629/* 1630 * Logging 1631 * Argument d is (struct drm_device *). 1632 */ 1633#define NV_PRINTK(level, d, fmt, arg...) \ 1634 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1635 pci_name(d->pdev), ##arg) 1636#ifndef NV_DEBUG_NOTRACE 1637#define NV_DEBUG(d, fmt, arg...) do { \ 1638 if (drm_debug & DRM_UT_DRIVER) { \ 1639 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1640 __LINE__, ##arg); \ 1641 } \ 1642} while (0) 1643#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1644 if (drm_debug & DRM_UT_KMS) { \ 1645 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1646 __LINE__, ##arg); \ 1647 } \ 1648} while (0) 1649#else 1650#define NV_DEBUG(d, fmt, arg...) do { \ 1651 if (drm_debug & DRM_UT_DRIVER) \ 1652 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1653} while (0) 1654#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1655 if (drm_debug & DRM_UT_KMS) \ 1656 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1657} while (0) 1658#endif 1659#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1660#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1661#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1662#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1663#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1664#define NV_WARNONCE(d, fmt, arg...) do { \ 1665 static int _warned = 0; \ 1666 if (!_warned) { \ 1667 NV_WARN(d, fmt, ##arg); \ 1668 _warned = 1; \ 1669 } \ 1670} while(0) 1671 1672/* nouveau_reg_debug bitmask */ 1673enum { 1674 NOUVEAU_REG_DEBUG_MC = 0x1, 1675 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1676 NOUVEAU_REG_DEBUG_FB = 0x4, 1677 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1678 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1679 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1680 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1681 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1682 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1683 NOUVEAU_REG_DEBUG_EVO = 0x200, 1684 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1685}; 1686 1687#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1688 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1689 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1690} while (0) 1691 1692static inline bool 1693nv_two_heads(struct drm_device *dev) 1694{ 1695 struct drm_nouveau_private *dev_priv = dev->dev_private; 1696 const int impl = dev->pci_device & 0x0ff0; 1697 1698 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1699 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1700 return true; 1701 1702 return false; 1703} 1704 1705static inline bool 1706nv_gf4_disp_arch(struct drm_device *dev) 1707{ 1708 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1709} 1710 1711static inline bool 1712nv_two_reg_pll(struct drm_device *dev) 1713{ 1714 struct drm_nouveau_private *dev_priv = dev->dev_private; 1715 const int impl = dev->pci_device & 0x0ff0; 1716 1717 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1718 return true; 1719 return false; 1720} 1721 1722static inline bool 1723nv_match_device(struct drm_device *dev, unsigned device, 1724 unsigned sub_vendor, unsigned sub_device) 1725{ 1726 return dev->pdev->device == device && 1727 dev->pdev->subsystem_vendor == sub_vendor && 1728 dev->pdev->subsystem_device == sub_device; 1729} 1730 1731static inline void * 1732nv_engine(struct drm_device *dev, int engine) 1733{ 1734 struct drm_nouveau_private *dev_priv = dev->dev_private; 1735 return (void *)dev_priv->eng[engine]; 1736} 1737 1738/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1739 * helpful to determine a number of other hardware features 1740 */ 1741static inline int 1742nv44_graph_class(struct drm_device *dev) 1743{ 1744 struct drm_nouveau_private *dev_priv = dev->dev_private; 1745 1746 if ((dev_priv->chipset & 0xf0) == 0x60) 1747 return 1; 1748 1749 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1750} 1751 1752/* memory type/access flags, do not match hardware values */ 1753#define NV_MEM_ACCESS_RO 1 1754#define NV_MEM_ACCESS_WO 2 1755#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1756#define NV_MEM_ACCESS_SYS 4 1757#define NV_MEM_ACCESS_VM 8 1758 1759#define NV_MEM_TARGET_VRAM 0 1760#define NV_MEM_TARGET_PCI 1 1761#define NV_MEM_TARGET_PCI_NOSNOOP 2 1762#define NV_MEM_TARGET_VM 3 1763#define NV_MEM_TARGET_GART 4 1764 1765#define NV_MEM_TYPE_VM 0x7f 1766#define NV_MEM_COMP_VM 0x03 1767 1768/* NV_SW object class */ 1769#define NV_SW 0x0000506e 1770#define NV_SW_DMA_SEMAPHORE 0x00000060 1771#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1772#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1773#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1774#define NV_SW_YIELD 0x00000080 1775#define NV_SW_DMA_VBLSEM 0x0000018c 1776#define NV_SW_VBLSEM_OFFSET 0x00000400 1777#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1778#define NV_SW_VBLSEM_RELEASE 0x00000408 1779#define NV_SW_PAGE_FLIP 0x00000500 1780 1781#endif /* __NOUVEAU_DRV_H__ */ 1782