nouveau_drv.h revision 8f27c54342dffbfbafbddd6e43f011e6cb16d285
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401}; 402 403struct nouveau_gpio_engine { 404 void *priv; 405 406 int (*init)(struct drm_device *); 407 void (*takedown)(struct drm_device *); 408 409 int (*get)(struct drm_device *, enum dcb_gpio_tag); 410 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 411 412 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 413 void (*)(void *, int), void *); 414 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 415 void (*)(void *, int), void *); 416 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 417}; 418 419struct nouveau_pm_voltage_level { 420 u32 voltage; /* microvolts */ 421 u8 vid; 422}; 423 424struct nouveau_pm_voltage { 425 bool supported; 426 u8 version; 427 u8 vid_mask; 428 429 struct nouveau_pm_voltage_level *level; 430 int nr_level; 431}; 432 433struct nouveau_pm_memtiming { 434 int id; 435 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 436 u32 reg_1; 437 u32 reg_2; 438 u32 reg_3; 439 u32 reg_4; 440 u32 reg_5; 441 u32 reg_6; 442 u32 reg_7; 443 u32 reg_8; 444 /* To be written to 0x1002c0 */ 445 u8 CL; 446 u8 WR; 447}; 448 449struct nouveau_pm_tbl_header{ 450 u8 version; 451 u8 header_len; 452 u8 entry_cnt; 453 u8 entry_len; 454}; 455 456struct nouveau_pm_tbl_entry{ 457 u8 tWR; 458 u8 tUNK_1; 459 u8 tCL; 460 u8 tRP; /* Byte 3 */ 461 u8 empty_4; 462 u8 tRAS; /* Byte 5 */ 463 u8 empty_6; 464 u8 tRFC; /* Byte 7 */ 465 u8 empty_8; 466 u8 tRC; /* Byte 9 */ 467 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 468 u8 empty_15,empty_16,empty_17; 469 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 470}; 471 472/* nouveau_mem.c */ 473void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 474 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 475 struct nouveau_pm_memtiming *timing); 476 477#define NOUVEAU_PM_MAX_LEVEL 8 478struct nouveau_pm_level { 479 struct device_attribute dev_attr; 480 char name[32]; 481 int id; 482 483 u32 core; 484 u32 memory; 485 u32 shader; 486 u32 rop; 487 u32 copy; 488 u32 daemon; 489 u32 vdec; 490 u32 unk05; /* nv50:nva3, roughly.. */ 491 u32 unka0; /* nva3:nvc0 */ 492 u32 hub01; /* nvc0- */ 493 u32 hub06; /* nvc0- */ 494 u32 hub07; /* nvc0- */ 495 496 u32 volt_min; /* microvolts */ 497 u32 volt_max; 498 u8 fanspeed; 499 500 u16 memscript; 501 struct nouveau_pm_memtiming *timing; 502}; 503 504struct nouveau_pm_temp_sensor_constants { 505 u16 offset_constant; 506 s16 offset_mult; 507 s16 offset_div; 508 s16 slope_mult; 509 s16 slope_div; 510}; 511 512struct nouveau_pm_threshold_temp { 513 s16 critical; 514 s16 down_clock; 515 s16 fan_boost; 516}; 517 518struct nouveau_pm_memtimings { 519 bool supported; 520 struct nouveau_pm_memtiming *timing; 521 int nr_timing; 522}; 523 524struct nouveau_pm_engine { 525 struct nouveau_pm_voltage voltage; 526 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 527 int nr_perflvl; 528 struct nouveau_pm_memtimings memtimings; 529 struct nouveau_pm_temp_sensor_constants sensor_constants; 530 struct nouveau_pm_threshold_temp threshold_temp; 531 u32 pwm_divisor; 532 533 struct nouveau_pm_level boot; 534 struct nouveau_pm_level *cur; 535 536 struct device *hwmon; 537 struct notifier_block acpi_nb; 538 539 int (*clock_get)(struct drm_device *, u32 id); 540 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 541 u32 id, int khz); 542 void (*clock_set)(struct drm_device *, void *); 543 544 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 545 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 546 void (*clocks_set)(struct drm_device *, void *); 547 548 int (*voltage_get)(struct drm_device *); 549 int (*voltage_set)(struct drm_device *, int voltage); 550 int (*fanspeed_get)(struct drm_device *); 551 int (*fanspeed_set)(struct drm_device *, int fanspeed); 552 int (*temp_get)(struct drm_device *); 553}; 554 555struct nouveau_vram_engine { 556 struct nouveau_mm mm; 557 558 int (*init)(struct drm_device *); 559 void (*takedown)(struct drm_device *dev); 560 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 561 u32 type, struct nouveau_mem **); 562 void (*put)(struct drm_device *, struct nouveau_mem **); 563 564 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 565}; 566 567struct nouveau_engine { 568 struct nouveau_instmem_engine instmem; 569 struct nouveau_mc_engine mc; 570 struct nouveau_timer_engine timer; 571 struct nouveau_fb_engine fb; 572 struct nouveau_fifo_engine fifo; 573 struct nouveau_display_engine display; 574 struct nouveau_gpio_engine gpio; 575 struct nouveau_pm_engine pm; 576 struct nouveau_vram_engine vram; 577}; 578 579struct nouveau_pll_vals { 580 union { 581 struct { 582#ifdef __BIG_ENDIAN 583 uint8_t N1, M1, N2, M2; 584#else 585 uint8_t M1, N1, M2, N2; 586#endif 587 }; 588 struct { 589 uint16_t NM1, NM2; 590 } __attribute__((packed)); 591 }; 592 int log2P; 593 594 int refclk; 595}; 596 597enum nv04_fp_display_regs { 598 FP_DISPLAY_END, 599 FP_TOTAL, 600 FP_CRTC, 601 FP_SYNC_START, 602 FP_SYNC_END, 603 FP_VALID_START, 604 FP_VALID_END 605}; 606 607struct nv04_crtc_reg { 608 unsigned char MiscOutReg; 609 uint8_t CRTC[0xa0]; 610 uint8_t CR58[0x10]; 611 uint8_t Sequencer[5]; 612 uint8_t Graphics[9]; 613 uint8_t Attribute[21]; 614 unsigned char DAC[768]; 615 616 /* PCRTC regs */ 617 uint32_t fb_start; 618 uint32_t crtc_cfg; 619 uint32_t cursor_cfg; 620 uint32_t gpio_ext; 621 uint32_t crtc_830; 622 uint32_t crtc_834; 623 uint32_t crtc_850; 624 uint32_t crtc_eng_ctrl; 625 626 /* PRAMDAC regs */ 627 uint32_t nv10_cursync; 628 struct nouveau_pll_vals pllvals; 629 uint32_t ramdac_gen_ctrl; 630 uint32_t ramdac_630; 631 uint32_t ramdac_634; 632 uint32_t tv_setup; 633 uint32_t tv_vtotal; 634 uint32_t tv_vskew; 635 uint32_t tv_vsync_delay; 636 uint32_t tv_htotal; 637 uint32_t tv_hskew; 638 uint32_t tv_hsync_delay; 639 uint32_t tv_hsync_delay2; 640 uint32_t fp_horiz_regs[7]; 641 uint32_t fp_vert_regs[7]; 642 uint32_t dither; 643 uint32_t fp_control; 644 uint32_t dither_regs[6]; 645 uint32_t fp_debug_0; 646 uint32_t fp_debug_1; 647 uint32_t fp_debug_2; 648 uint32_t fp_margin_color; 649 uint32_t ramdac_8c0; 650 uint32_t ramdac_a20; 651 uint32_t ramdac_a24; 652 uint32_t ramdac_a34; 653 uint32_t ctv_regs[38]; 654}; 655 656struct nv04_output_reg { 657 uint32_t output; 658 int head; 659}; 660 661struct nv04_mode_state { 662 struct nv04_crtc_reg crtc_reg[2]; 663 uint32_t pllsel; 664 uint32_t sel_clk; 665}; 666 667enum nouveau_card_type { 668 NV_04 = 0x00, 669 NV_10 = 0x10, 670 NV_20 = 0x20, 671 NV_30 = 0x30, 672 NV_40 = 0x40, 673 NV_50 = 0x50, 674 NV_C0 = 0xc0, 675 NV_D0 = 0xd0 676}; 677 678struct drm_nouveau_private { 679 struct drm_device *dev; 680 bool noaccel; 681 682 /* the card type, takes NV_* as values */ 683 enum nouveau_card_type card_type; 684 /* exact chipset, derived from NV_PMC_BOOT_0 */ 685 int chipset; 686 int flags; 687 u32 crystal; 688 689 void __iomem *mmio; 690 691 spinlock_t ramin_lock; 692 void __iomem *ramin; 693 u32 ramin_size; 694 u32 ramin_base; 695 bool ramin_available; 696 struct drm_mm ramin_heap; 697 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 698 struct list_head gpuobj_list; 699 struct list_head classes; 700 701 struct nouveau_bo *vga_ram; 702 703 /* interrupt handling */ 704 void (*irq_handler[32])(struct drm_device *); 705 bool msi_enabled; 706 707 struct list_head vbl_waiting; 708 709 struct { 710 struct drm_global_reference mem_global_ref; 711 struct ttm_bo_global_ref bo_global_ref; 712 struct ttm_bo_device bdev; 713 atomic_t validate_sequence; 714 } ttm; 715 716 struct { 717 spinlock_t lock; 718 struct drm_mm heap; 719 struct nouveau_bo *bo; 720 } fence; 721 722 struct { 723 spinlock_t lock; 724 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 725 } channels; 726 727 struct nouveau_engine engine; 728 struct nouveau_channel *channel; 729 730 /* For PFIFO and PGRAPH. */ 731 spinlock_t context_switch_lock; 732 733 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 734 spinlock_t vm_lock; 735 736 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 737 struct nouveau_ramht *ramht; 738 struct nouveau_gpuobj *ramfc; 739 struct nouveau_gpuobj *ramro; 740 741 uint32_t ramin_rsvd_vram; 742 743 struct { 744 enum { 745 NOUVEAU_GART_NONE = 0, 746 NOUVEAU_GART_AGP, /* AGP */ 747 NOUVEAU_GART_PDMA, /* paged dma object */ 748 NOUVEAU_GART_HW /* on-chip gart/vm */ 749 } type; 750 uint64_t aper_base; 751 uint64_t aper_size; 752 uint64_t aper_free; 753 754 struct ttm_backend_func *func; 755 756 struct { 757 struct page *page; 758 dma_addr_t addr; 759 } dummy; 760 761 struct nouveau_gpuobj *sg_ctxdma; 762 } gart_info; 763 764 /* nv10-nv40 tiling regions */ 765 struct { 766 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 767 spinlock_t lock; 768 } tile; 769 770 /* VRAM/fb configuration */ 771 uint64_t vram_size; 772 uint64_t vram_sys_base; 773 774 uint64_t fb_available_size; 775 uint64_t fb_mappable_pages; 776 uint64_t fb_aper_free; 777 int fb_mtrr; 778 779 /* BAR control (NV50-) */ 780 struct nouveau_vm *bar1_vm; 781 struct nouveau_vm *bar3_vm; 782 783 /* G8x/G9x virtual address space */ 784 struct nouveau_vm *chan_vm; 785 786 struct nvbios vbios; 787 788 struct nv04_mode_state mode_reg; 789 struct nv04_mode_state saved_reg; 790 uint32_t saved_vga_font[4][16384]; 791 uint32_t crtc_owner; 792 uint32_t dac_users[4]; 793 794 struct backlight_device *backlight; 795 796 struct { 797 struct dentry *channel_root; 798 } debugfs; 799 800 struct nouveau_fbdev *nfbdev; 801 struct apertures_struct *apertures; 802}; 803 804static inline struct drm_nouveau_private * 805nouveau_private(struct drm_device *dev) 806{ 807 return dev->dev_private; 808} 809 810static inline struct drm_nouveau_private * 811nouveau_bdev(struct ttm_bo_device *bd) 812{ 813 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 814} 815 816static inline int 817nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 818{ 819 struct nouveau_bo *prev; 820 821 if (!pnvbo) 822 return -EINVAL; 823 prev = *pnvbo; 824 825 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 826 if (prev) { 827 struct ttm_buffer_object *bo = &prev->bo; 828 829 ttm_bo_unref(&bo); 830 } 831 832 return 0; 833} 834 835/* nouveau_drv.c */ 836extern int nouveau_modeset; 837extern int nouveau_agpmode; 838extern int nouveau_duallink; 839extern int nouveau_uscript_lvds; 840extern int nouveau_uscript_tmds; 841extern int nouveau_vram_pushbuf; 842extern int nouveau_vram_notify; 843extern int nouveau_fbpercrtc; 844extern int nouveau_tv_disable; 845extern char *nouveau_tv_norm; 846extern int nouveau_reg_debug; 847extern char *nouveau_vbios; 848extern int nouveau_ignorelid; 849extern int nouveau_nofbaccel; 850extern int nouveau_noaccel; 851extern int nouveau_force_post; 852extern int nouveau_override_conntype; 853extern char *nouveau_perflvl; 854extern int nouveau_perflvl_wr; 855extern int nouveau_msi; 856extern int nouveau_ctxfw; 857 858extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 859extern int nouveau_pci_resume(struct pci_dev *pdev); 860 861/* nouveau_state.c */ 862extern int nouveau_open(struct drm_device *, struct drm_file *); 863extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 864extern void nouveau_postclose(struct drm_device *, struct drm_file *); 865extern int nouveau_load(struct drm_device *, unsigned long flags); 866extern int nouveau_firstopen(struct drm_device *); 867extern void nouveau_lastclose(struct drm_device *); 868extern int nouveau_unload(struct drm_device *); 869extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 870 struct drm_file *); 871extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 872 struct drm_file *); 873extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 874 uint32_t reg, uint32_t mask, uint32_t val); 875extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 876 uint32_t reg, uint32_t mask, uint32_t val); 877extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 878 bool (*cond)(void *), void *); 879extern bool nouveau_wait_for_idle(struct drm_device *); 880extern int nouveau_card_init(struct drm_device *); 881 882/* nouveau_mem.c */ 883extern int nouveau_mem_vram_init(struct drm_device *); 884extern void nouveau_mem_vram_fini(struct drm_device *); 885extern int nouveau_mem_gart_init(struct drm_device *); 886extern void nouveau_mem_gart_fini(struct drm_device *); 887extern int nouveau_mem_init_agp(struct drm_device *); 888extern int nouveau_mem_reset_agp(struct drm_device *); 889extern void nouveau_mem_close(struct drm_device *); 890extern int nouveau_mem_detect(struct drm_device *); 891extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 892extern struct nouveau_tile_reg *nv10_mem_set_tiling( 893 struct drm_device *dev, uint32_t addr, uint32_t size, 894 uint32_t pitch, uint32_t flags); 895extern void nv10_mem_put_tile_region(struct drm_device *dev, 896 struct nouveau_tile_reg *tile, 897 struct nouveau_fence *fence); 898extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 899extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 900 901/* nouveau_notifier.c */ 902extern int nouveau_notifier_init_channel(struct nouveau_channel *); 903extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 904extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 905 int cout, uint32_t start, uint32_t end, 906 uint32_t *offset); 907extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 908extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 909 struct drm_file *); 910extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 911 struct drm_file *); 912 913/* nouveau_channel.c */ 914extern struct drm_ioctl_desc nouveau_ioctls[]; 915extern int nouveau_max_ioctl; 916extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 917extern int nouveau_channel_alloc(struct drm_device *dev, 918 struct nouveau_channel **chan, 919 struct drm_file *file_priv, 920 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 921extern struct nouveau_channel * 922nouveau_channel_get_unlocked(struct nouveau_channel *); 923extern struct nouveau_channel * 924nouveau_channel_get(struct drm_file *, int id); 925extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 926extern void nouveau_channel_put(struct nouveau_channel **); 927extern void nouveau_channel_ref(struct nouveau_channel *chan, 928 struct nouveau_channel **pchan); 929extern void nouveau_channel_idle(struct nouveau_channel *chan); 930 931/* nouveau_object.c */ 932#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 933 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 934 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 935} while (0) 936 937#define NVOBJ_ENGINE_DEL(d, e) do { \ 938 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 939 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 940} while (0) 941 942#define NVOBJ_CLASS(d, c, e) do { \ 943 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 944 if (ret) \ 945 return ret; \ 946} while (0) 947 948#define NVOBJ_MTHD(d, c, m, e) do { \ 949 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 950 if (ret) \ 951 return ret; \ 952} while (0) 953 954extern int nouveau_gpuobj_early_init(struct drm_device *); 955extern int nouveau_gpuobj_init(struct drm_device *); 956extern void nouveau_gpuobj_takedown(struct drm_device *); 957extern int nouveau_gpuobj_suspend(struct drm_device *dev); 958extern void nouveau_gpuobj_resume(struct drm_device *dev); 959extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 960extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 961 int (*exec)(struct nouveau_channel *, 962 u32 class, u32 mthd, u32 data)); 963extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 964extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 965extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 966 uint32_t vram_h, uint32_t tt_h); 967extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 968extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 969 uint32_t size, int align, uint32_t flags, 970 struct nouveau_gpuobj **); 971extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 972 struct nouveau_gpuobj **); 973extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 974 u32 size, u32 flags, 975 struct nouveau_gpuobj **); 976extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 977 uint64_t offset, uint64_t size, int access, 978 int target, struct nouveau_gpuobj **); 979extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 980extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 981 u64 size, int target, int access, u32 type, 982 u32 comp, struct nouveau_gpuobj **pobj); 983extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 984 int class, u64 base, u64 size, int target, 985 int access, u32 type, u32 comp); 986extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 987 struct drm_file *); 988extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 989 struct drm_file *); 990 991/* nouveau_irq.c */ 992extern int nouveau_irq_init(struct drm_device *); 993extern void nouveau_irq_fini(struct drm_device *); 994extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 995extern void nouveau_irq_register(struct drm_device *, int status_bit, 996 void (*)(struct drm_device *)); 997extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 998extern void nouveau_irq_preinstall(struct drm_device *); 999extern int nouveau_irq_postinstall(struct drm_device *); 1000extern void nouveau_irq_uninstall(struct drm_device *); 1001 1002/* nouveau_sgdma.c */ 1003extern int nouveau_sgdma_init(struct drm_device *); 1004extern void nouveau_sgdma_takedown(struct drm_device *); 1005extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1006 uint32_t offset); 1007extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1008 unsigned long size, 1009 uint32_t page_flags, 1010 struct page *dummy_read_page); 1011 1012/* nouveau_debugfs.c */ 1013#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1014extern int nouveau_debugfs_init(struct drm_minor *); 1015extern void nouveau_debugfs_takedown(struct drm_minor *); 1016extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1017extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1018#else 1019static inline int 1020nouveau_debugfs_init(struct drm_minor *minor) 1021{ 1022 return 0; 1023} 1024 1025static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1026{ 1027} 1028 1029static inline int 1030nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1031{ 1032 return 0; 1033} 1034 1035static inline void 1036nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1037{ 1038} 1039#endif 1040 1041/* nouveau_dma.c */ 1042extern void nouveau_dma_pre_init(struct nouveau_channel *); 1043extern int nouveau_dma_init(struct nouveau_channel *); 1044extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1045 1046/* nouveau_acpi.c */ 1047#define ROM_BIOS_PAGE 4096 1048#if defined(CONFIG_ACPI) 1049void nouveau_register_dsm_handler(void); 1050void nouveau_unregister_dsm_handler(void); 1051int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1052bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1053int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1054#else 1055static inline void nouveau_register_dsm_handler(void) {} 1056static inline void nouveau_unregister_dsm_handler(void) {} 1057static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1058static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1059static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1060#endif 1061 1062/* nouveau_backlight.c */ 1063#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1064extern int nouveau_backlight_init(struct drm_device *); 1065extern void nouveau_backlight_exit(struct drm_device *); 1066#else 1067static inline int nouveau_backlight_init(struct drm_device *dev) 1068{ 1069 return 0; 1070} 1071 1072static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1073#endif 1074 1075/* nouveau_bios.c */ 1076extern int nouveau_bios_init(struct drm_device *); 1077extern void nouveau_bios_takedown(struct drm_device *dev); 1078extern int nouveau_run_vbios_init(struct drm_device *); 1079extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1080 struct dcb_entry *, int crtc); 1081extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1082extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1083 enum dcb_gpio_tag); 1084extern struct dcb_connector_table_entry * 1085nouveau_bios_connector_entry(struct drm_device *, int index); 1086extern u32 get_pll_register(struct drm_device *, enum pll_types); 1087extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1088 struct pll_lims *); 1089extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1090 struct dcb_entry *, int crtc); 1091extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1092extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1093extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1094 bool *dl, bool *if_is_24bit); 1095extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1096 int head, int pxclk); 1097extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1098 enum LVDS_script, int pxclk); 1099bool bios_encoder_match(struct dcb_entry *, u32 hash); 1100 1101/* nouveau_ttm.c */ 1102int nouveau_ttm_global_init(struct drm_nouveau_private *); 1103void nouveau_ttm_global_release(struct drm_nouveau_private *); 1104int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1105 1106/* nouveau_dp.c */ 1107int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1108 uint8_t *data, int data_nr); 1109bool nouveau_dp_detect(struct drm_encoder *); 1110bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1111void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1112u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1113 1114/* nv04_fb.c */ 1115extern int nv04_fb_init(struct drm_device *); 1116extern void nv04_fb_takedown(struct drm_device *); 1117 1118/* nv10_fb.c */ 1119extern int nv10_fb_init(struct drm_device *); 1120extern void nv10_fb_takedown(struct drm_device *); 1121extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1122 uint32_t addr, uint32_t size, 1123 uint32_t pitch, uint32_t flags); 1124extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1125extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1126 1127/* nv30_fb.c */ 1128extern int nv30_fb_init(struct drm_device *); 1129extern void nv30_fb_takedown(struct drm_device *); 1130extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1131 uint32_t addr, uint32_t size, 1132 uint32_t pitch, uint32_t flags); 1133extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1134 1135/* nv40_fb.c */ 1136extern int nv40_fb_init(struct drm_device *); 1137extern void nv40_fb_takedown(struct drm_device *); 1138extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1139 1140/* nv50_fb.c */ 1141extern int nv50_fb_init(struct drm_device *); 1142extern void nv50_fb_takedown(struct drm_device *); 1143extern void nv50_fb_vm_trap(struct drm_device *, int display); 1144 1145/* nvc0_fb.c */ 1146extern int nvc0_fb_init(struct drm_device *); 1147extern void nvc0_fb_takedown(struct drm_device *); 1148 1149/* nv04_fifo.c */ 1150extern int nv04_fifo_init(struct drm_device *); 1151extern void nv04_fifo_fini(struct drm_device *); 1152extern void nv04_fifo_disable(struct drm_device *); 1153extern void nv04_fifo_enable(struct drm_device *); 1154extern bool nv04_fifo_reassign(struct drm_device *, bool); 1155extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1156extern int nv04_fifo_channel_id(struct drm_device *); 1157extern int nv04_fifo_create_context(struct nouveau_channel *); 1158extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1159extern int nv04_fifo_load_context(struct nouveau_channel *); 1160extern int nv04_fifo_unload_context(struct drm_device *); 1161extern void nv04_fifo_isr(struct drm_device *); 1162 1163/* nv10_fifo.c */ 1164extern int nv10_fifo_init(struct drm_device *); 1165extern int nv10_fifo_channel_id(struct drm_device *); 1166extern int nv10_fifo_create_context(struct nouveau_channel *); 1167extern int nv10_fifo_load_context(struct nouveau_channel *); 1168extern int nv10_fifo_unload_context(struct drm_device *); 1169 1170/* nv40_fifo.c */ 1171extern int nv40_fifo_init(struct drm_device *); 1172extern int nv40_fifo_create_context(struct nouveau_channel *); 1173extern int nv40_fifo_load_context(struct nouveau_channel *); 1174extern int nv40_fifo_unload_context(struct drm_device *); 1175 1176/* nv50_fifo.c */ 1177extern int nv50_fifo_init(struct drm_device *); 1178extern void nv50_fifo_takedown(struct drm_device *); 1179extern int nv50_fifo_channel_id(struct drm_device *); 1180extern int nv50_fifo_create_context(struct nouveau_channel *); 1181extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1182extern int nv50_fifo_load_context(struct nouveau_channel *); 1183extern int nv50_fifo_unload_context(struct drm_device *); 1184extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1185 1186/* nvc0_fifo.c */ 1187extern int nvc0_fifo_init(struct drm_device *); 1188extern void nvc0_fifo_takedown(struct drm_device *); 1189extern void nvc0_fifo_disable(struct drm_device *); 1190extern void nvc0_fifo_enable(struct drm_device *); 1191extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1192extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1193extern int nvc0_fifo_channel_id(struct drm_device *); 1194extern int nvc0_fifo_create_context(struct nouveau_channel *); 1195extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1196extern int nvc0_fifo_load_context(struct nouveau_channel *); 1197extern int nvc0_fifo_unload_context(struct drm_device *); 1198 1199/* nv04_graph.c */ 1200extern int nv04_graph_create(struct drm_device *); 1201extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1202extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1203 u32 class, u32 mthd, u32 data); 1204extern struct nouveau_bitfield nv04_graph_nsource[]; 1205 1206/* nv10_graph.c */ 1207extern int nv10_graph_create(struct drm_device *); 1208extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1209extern struct nouveau_bitfield nv10_graph_intr[]; 1210extern struct nouveau_bitfield nv10_graph_nstatus[]; 1211 1212/* nv20_graph.c */ 1213extern int nv20_graph_create(struct drm_device *); 1214 1215/* nv40_graph.c */ 1216extern int nv40_graph_create(struct drm_device *); 1217extern void nv40_grctx_init(struct nouveau_grctx *); 1218 1219/* nv50_graph.c */ 1220extern int nv50_graph_create(struct drm_device *); 1221extern int nv50_grctx_init(struct nouveau_grctx *); 1222extern struct nouveau_enum nv50_data_error_names[]; 1223extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1224 1225/* nvc0_graph.c */ 1226extern int nvc0_graph_create(struct drm_device *); 1227extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1228 1229/* nv84_crypt.c */ 1230extern int nv84_crypt_create(struct drm_device *); 1231 1232/* nv98_crypt.c */ 1233extern int nv98_crypt_create(struct drm_device *dev); 1234 1235/* nva3_copy.c */ 1236extern int nva3_copy_create(struct drm_device *dev); 1237 1238/* nvc0_copy.c */ 1239extern int nvc0_copy_create(struct drm_device *dev, int engine); 1240 1241/* nv31_mpeg.c */ 1242extern int nv31_mpeg_create(struct drm_device *dev); 1243 1244/* nv50_mpeg.c */ 1245extern int nv50_mpeg_create(struct drm_device *dev); 1246 1247/* nv84_bsp.c */ 1248/* nv98_bsp.c */ 1249extern int nv84_bsp_create(struct drm_device *dev); 1250 1251/* nv84_vp.c */ 1252/* nv98_vp.c */ 1253extern int nv84_vp_create(struct drm_device *dev); 1254 1255/* nv98_ppp.c */ 1256extern int nv98_ppp_create(struct drm_device *dev); 1257 1258/* nv04_instmem.c */ 1259extern int nv04_instmem_init(struct drm_device *); 1260extern void nv04_instmem_takedown(struct drm_device *); 1261extern int nv04_instmem_suspend(struct drm_device *); 1262extern void nv04_instmem_resume(struct drm_device *); 1263extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1264 u32 size, u32 align); 1265extern void nv04_instmem_put(struct nouveau_gpuobj *); 1266extern int nv04_instmem_map(struct nouveau_gpuobj *); 1267extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1268extern void nv04_instmem_flush(struct drm_device *); 1269 1270/* nv50_instmem.c */ 1271extern int nv50_instmem_init(struct drm_device *); 1272extern void nv50_instmem_takedown(struct drm_device *); 1273extern int nv50_instmem_suspend(struct drm_device *); 1274extern void nv50_instmem_resume(struct drm_device *); 1275extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1276 u32 size, u32 align); 1277extern void nv50_instmem_put(struct nouveau_gpuobj *); 1278extern int nv50_instmem_map(struct nouveau_gpuobj *); 1279extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1280extern void nv50_instmem_flush(struct drm_device *); 1281extern void nv84_instmem_flush(struct drm_device *); 1282 1283/* nvc0_instmem.c */ 1284extern int nvc0_instmem_init(struct drm_device *); 1285extern void nvc0_instmem_takedown(struct drm_device *); 1286extern int nvc0_instmem_suspend(struct drm_device *); 1287extern void nvc0_instmem_resume(struct drm_device *); 1288 1289/* nv04_mc.c */ 1290extern int nv04_mc_init(struct drm_device *); 1291extern void nv04_mc_takedown(struct drm_device *); 1292 1293/* nv40_mc.c */ 1294extern int nv40_mc_init(struct drm_device *); 1295extern void nv40_mc_takedown(struct drm_device *); 1296 1297/* nv50_mc.c */ 1298extern int nv50_mc_init(struct drm_device *); 1299extern void nv50_mc_takedown(struct drm_device *); 1300 1301/* nv04_timer.c */ 1302extern int nv04_timer_init(struct drm_device *); 1303extern uint64_t nv04_timer_read(struct drm_device *); 1304extern void nv04_timer_takedown(struct drm_device *); 1305 1306extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1307 unsigned long arg); 1308 1309/* nv04_dac.c */ 1310extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1311extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1312extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1313extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1314extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1315 1316/* nv04_dfp.c */ 1317extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1318extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1319extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1320 int head, bool dl); 1321extern void nv04_dfp_disable(struct drm_device *dev, int head); 1322extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1323 1324/* nv04_tv.c */ 1325extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1326extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1327 1328/* nv17_tv.c */ 1329extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1330 1331/* nv04_display.c */ 1332extern int nv04_display_early_init(struct drm_device *); 1333extern void nv04_display_late_takedown(struct drm_device *); 1334extern int nv04_display_create(struct drm_device *); 1335extern int nv04_display_init(struct drm_device *); 1336extern void nv04_display_destroy(struct drm_device *); 1337 1338/* nvd0_display.c */ 1339extern int nvd0_display_create(struct drm_device *); 1340extern int nvd0_display_init(struct drm_device *); 1341extern void nvd0_display_destroy(struct drm_device *); 1342 1343/* nv04_crtc.c */ 1344extern int nv04_crtc_create(struct drm_device *, int index); 1345 1346/* nouveau_bo.c */ 1347extern struct ttm_bo_driver nouveau_bo_driver; 1348extern int nouveau_bo_new(struct drm_device *, int size, int align, 1349 uint32_t flags, uint32_t tile_mode, 1350 uint32_t tile_flags, struct nouveau_bo **); 1351extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1352extern int nouveau_bo_unpin(struct nouveau_bo *); 1353extern int nouveau_bo_map(struct nouveau_bo *); 1354extern void nouveau_bo_unmap(struct nouveau_bo *); 1355extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1356 uint32_t busy); 1357extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1358extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1359extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1360extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1361extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1362extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1363 bool no_wait_reserve, bool no_wait_gpu); 1364 1365extern struct nouveau_vma * 1366nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1367extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1368 struct nouveau_vma *); 1369extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1370 1371/* nouveau_fence.c */ 1372struct nouveau_fence; 1373extern int nouveau_fence_init(struct drm_device *); 1374extern void nouveau_fence_fini(struct drm_device *); 1375extern int nouveau_fence_channel_init(struct nouveau_channel *); 1376extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1377extern void nouveau_fence_update(struct nouveau_channel *); 1378extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1379 bool emit); 1380extern int nouveau_fence_emit(struct nouveau_fence *); 1381extern void nouveau_fence_work(struct nouveau_fence *fence, 1382 void (*work)(void *priv, bool signalled), 1383 void *priv); 1384struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1385 1386extern bool __nouveau_fence_signalled(void *obj, void *arg); 1387extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1388extern int __nouveau_fence_flush(void *obj, void *arg); 1389extern void __nouveau_fence_unref(void **obj); 1390extern void *__nouveau_fence_ref(void *obj); 1391 1392static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1393{ 1394 return __nouveau_fence_signalled(obj, NULL); 1395} 1396static inline int 1397nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1398{ 1399 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1400} 1401extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1402static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1403{ 1404 return __nouveau_fence_flush(obj, NULL); 1405} 1406static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1407{ 1408 __nouveau_fence_unref((void **)obj); 1409} 1410static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1411{ 1412 return __nouveau_fence_ref(obj); 1413} 1414 1415/* nouveau_gem.c */ 1416extern int nouveau_gem_new(struct drm_device *, int size, int align, 1417 uint32_t domain, uint32_t tile_mode, 1418 uint32_t tile_flags, struct nouveau_bo **); 1419extern int nouveau_gem_object_new(struct drm_gem_object *); 1420extern void nouveau_gem_object_del(struct drm_gem_object *); 1421extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1422extern void nouveau_gem_object_close(struct drm_gem_object *, 1423 struct drm_file *); 1424extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1425 struct drm_file *); 1426extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1427 struct drm_file *); 1428extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1429 struct drm_file *); 1430extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1431 struct drm_file *); 1432extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1433 struct drm_file *); 1434 1435/* nouveau_display.c */ 1436int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1437void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1438int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1439 struct drm_pending_vblank_event *event); 1440int nouveau_finish_page_flip(struct nouveau_channel *, 1441 struct nouveau_page_flip_state *); 1442int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1443 struct drm_mode_create_dumb *args); 1444int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1445 uint32_t handle, uint64_t *offset); 1446int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1447 uint32_t handle); 1448 1449/* nv10_gpio.c */ 1450int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1451int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1452 1453/* nv50_gpio.c */ 1454int nv50_gpio_init(struct drm_device *dev); 1455void nv50_gpio_fini(struct drm_device *dev); 1456int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1457int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1458int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1459int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1460int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1461 void (*)(void *, int), void *); 1462void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1463 void (*)(void *, int), void *); 1464bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1465 1466/* nv50_calc. */ 1467int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1468 int *N1, int *M1, int *N2, int *M2, int *P); 1469int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1470 int clk, int *N, int *fN, int *M, int *P); 1471 1472#ifndef ioread32_native 1473#ifdef __BIG_ENDIAN 1474#define ioread16_native ioread16be 1475#define iowrite16_native iowrite16be 1476#define ioread32_native ioread32be 1477#define iowrite32_native iowrite32be 1478#else /* def __BIG_ENDIAN */ 1479#define ioread16_native ioread16 1480#define iowrite16_native iowrite16 1481#define ioread32_native ioread32 1482#define iowrite32_native iowrite32 1483#endif /* def __BIG_ENDIAN else */ 1484#endif /* !ioread32_native */ 1485 1486/* channel control reg access */ 1487static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1488{ 1489 return ioread32_native(chan->user + reg); 1490} 1491 1492static inline void nvchan_wr32(struct nouveau_channel *chan, 1493 unsigned reg, u32 val) 1494{ 1495 iowrite32_native(val, chan->user + reg); 1496} 1497 1498/* register access */ 1499static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1500{ 1501 struct drm_nouveau_private *dev_priv = dev->dev_private; 1502 return ioread32_native(dev_priv->mmio + reg); 1503} 1504 1505static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1506{ 1507 struct drm_nouveau_private *dev_priv = dev->dev_private; 1508 iowrite32_native(val, dev_priv->mmio + reg); 1509} 1510 1511static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1512{ 1513 u32 tmp = nv_rd32(dev, reg); 1514 nv_wr32(dev, reg, (tmp & ~mask) | val); 1515 return tmp; 1516} 1517 1518static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1519{ 1520 struct drm_nouveau_private *dev_priv = dev->dev_private; 1521 return ioread8(dev_priv->mmio + reg); 1522} 1523 1524static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1525{ 1526 struct drm_nouveau_private *dev_priv = dev->dev_private; 1527 iowrite8(val, dev_priv->mmio + reg); 1528} 1529 1530#define nv_wait(dev, reg, mask, val) \ 1531 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1532#define nv_wait_ne(dev, reg, mask, val) \ 1533 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1534#define nv_wait_cb(dev, func, data) \ 1535 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1536 1537/* PRAMIN access */ 1538static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1539{ 1540 struct drm_nouveau_private *dev_priv = dev->dev_private; 1541 return ioread32_native(dev_priv->ramin + offset); 1542} 1543 1544static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 iowrite32_native(val, dev_priv->ramin + offset); 1548} 1549 1550/* object access */ 1551extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1552extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1553 1554/* 1555 * Logging 1556 * Argument d is (struct drm_device *). 1557 */ 1558#define NV_PRINTK(level, d, fmt, arg...) \ 1559 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1560 pci_name(d->pdev), ##arg) 1561#ifndef NV_DEBUG_NOTRACE 1562#define NV_DEBUG(d, fmt, arg...) do { \ 1563 if (drm_debug & DRM_UT_DRIVER) { \ 1564 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1565 __LINE__, ##arg); \ 1566 } \ 1567} while (0) 1568#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1569 if (drm_debug & DRM_UT_KMS) { \ 1570 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1571 __LINE__, ##arg); \ 1572 } \ 1573} while (0) 1574#else 1575#define NV_DEBUG(d, fmt, arg...) do { \ 1576 if (drm_debug & DRM_UT_DRIVER) \ 1577 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1578} while (0) 1579#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1580 if (drm_debug & DRM_UT_KMS) \ 1581 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1582} while (0) 1583#endif 1584#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1585#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1586#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1587#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1588#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1589 1590/* nouveau_reg_debug bitmask */ 1591enum { 1592 NOUVEAU_REG_DEBUG_MC = 0x1, 1593 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1594 NOUVEAU_REG_DEBUG_FB = 0x4, 1595 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1596 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1597 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1598 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1599 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1600 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1601 NOUVEAU_REG_DEBUG_EVO = 0x200, 1602 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1603}; 1604 1605#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1606 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1607 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1608} while (0) 1609 1610static inline bool 1611nv_two_heads(struct drm_device *dev) 1612{ 1613 struct drm_nouveau_private *dev_priv = dev->dev_private; 1614 const int impl = dev->pci_device & 0x0ff0; 1615 1616 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1617 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1618 return true; 1619 1620 return false; 1621} 1622 1623static inline bool 1624nv_gf4_disp_arch(struct drm_device *dev) 1625{ 1626 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1627} 1628 1629static inline bool 1630nv_two_reg_pll(struct drm_device *dev) 1631{ 1632 struct drm_nouveau_private *dev_priv = dev->dev_private; 1633 const int impl = dev->pci_device & 0x0ff0; 1634 1635 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1636 return true; 1637 return false; 1638} 1639 1640static inline bool 1641nv_match_device(struct drm_device *dev, unsigned device, 1642 unsigned sub_vendor, unsigned sub_device) 1643{ 1644 return dev->pdev->device == device && 1645 dev->pdev->subsystem_vendor == sub_vendor && 1646 dev->pdev->subsystem_device == sub_device; 1647} 1648 1649static inline void * 1650nv_engine(struct drm_device *dev, int engine) 1651{ 1652 struct drm_nouveau_private *dev_priv = dev->dev_private; 1653 return (void *)dev_priv->eng[engine]; 1654} 1655 1656/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1657 * helpful to determine a number of other hardware features 1658 */ 1659static inline int 1660nv44_graph_class(struct drm_device *dev) 1661{ 1662 struct drm_nouveau_private *dev_priv = dev->dev_private; 1663 1664 if ((dev_priv->chipset & 0xf0) == 0x60) 1665 return 1; 1666 1667 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1668} 1669 1670/* memory type/access flags, do not match hardware values */ 1671#define NV_MEM_ACCESS_RO 1 1672#define NV_MEM_ACCESS_WO 2 1673#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1674#define NV_MEM_ACCESS_SYS 4 1675#define NV_MEM_ACCESS_VM 8 1676 1677#define NV_MEM_TARGET_VRAM 0 1678#define NV_MEM_TARGET_PCI 1 1679#define NV_MEM_TARGET_PCI_NOSNOOP 2 1680#define NV_MEM_TARGET_VM 3 1681#define NV_MEM_TARGET_GART 4 1682 1683#define NV_MEM_TYPE_VM 0x7f 1684#define NV_MEM_COMP_VM 0x03 1685 1686/* NV_SW object class */ 1687#define NV_SW 0x0000506e 1688#define NV_SW_DMA_SEMAPHORE 0x00000060 1689#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1690#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1691#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1692#define NV_SW_YIELD 0x00000080 1693#define NV_SW_DMA_VBLSEM 0x0000018c 1694#define NV_SW_VBLSEM_OFFSET 0x00000400 1695#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1696#define NV_SW_VBLSEM_RELEASE 0x00000408 1697#define NV_SW_PAGE_FLIP 0x00000500 1698 1699#endif /* __NOUVEAU_DRV_H__ */ 1700