nouveau_drv.h revision 9a7824887690836448eb73ccf0d8232da2e5bee3
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u32 voltage; /* microvolts */ 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 version; 424 u8 vid_mask; 425 426 struct nouveau_pm_voltage_level *level; 427 int nr_level; 428}; 429 430struct nouveau_pm_memtiming { 431 int id; 432 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 433 u32 reg_1; 434 u32 reg_2; 435 u32 reg_3; 436 u32 reg_4; 437 u32 reg_5; 438 u32 reg_6; 439 u32 reg_7; 440 u32 reg_8; 441}; 442 443struct nouveau_pm_tbl_header{ 444 u8 version; 445 u8 header_len; 446 u8 entry_cnt; 447 u8 entry_len; 448}; 449 450struct nouveau_pm_tbl_entry{ 451 u8 tUNK_0, tUNK_1, tUNK_2; 452 u8 tRP; /* Byte 3 */ 453 u8 empty_4; 454 u8 tRAS; /* Byte 5 */ 455 u8 empty_6; 456 u8 tRFC; /* Byte 7 */ 457 u8 empty_8; 458 u8 tRC; /* Byte 9 */ 459 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 460 u8 empty_15,empty_16,empty_17; 461 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 462}; 463 464/* nouveau_mem.c */ 465void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 466 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 467 struct nouveau_pm_memtiming *timing); 468 469#define NOUVEAU_PM_MAX_LEVEL 8 470struct nouveau_pm_level { 471 struct device_attribute dev_attr; 472 char name[32]; 473 int id; 474 475 u32 core; 476 u32 memory; 477 u32 shader; 478 u32 rop; 479 u32 copy; 480 u32 daemon; 481 u32 vdec; 482 u32 unk05; /* nv50:nva3, roughly.. */ 483 u32 unka0; /* nva3:nvc0 */ 484 u32 hub01; /* nvc0- */ 485 u32 hub06; /* nvc0- */ 486 u32 hub07; /* nvc0- */ 487 488 u32 volt_min; /* microvolts */ 489 u32 volt_max; 490 u8 fanspeed; 491 492 u16 memscript; 493 struct nouveau_pm_memtiming *timing; 494}; 495 496struct nouveau_pm_temp_sensor_constants { 497 u16 offset_constant; 498 s16 offset_mult; 499 s16 offset_div; 500 s16 slope_mult; 501 s16 slope_div; 502}; 503 504struct nouveau_pm_threshold_temp { 505 s16 critical; 506 s16 down_clock; 507 s16 fan_boost; 508}; 509 510struct nouveau_pm_memtimings { 511 bool supported; 512 struct nouveau_pm_memtiming *timing; 513 int nr_timing; 514}; 515 516struct nouveau_pm_engine { 517 struct nouveau_pm_voltage voltage; 518 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 519 int nr_perflvl; 520 struct nouveau_pm_memtimings memtimings; 521 struct nouveau_pm_temp_sensor_constants sensor_constants; 522 struct nouveau_pm_threshold_temp threshold_temp; 523 524 struct nouveau_pm_level boot; 525 struct nouveau_pm_level *cur; 526 527 struct device *hwmon; 528 struct notifier_block acpi_nb; 529 530 int (*clock_get)(struct drm_device *, u32 id); 531 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 532 u32 id, int khz); 533 void (*clock_set)(struct drm_device *, void *); 534 535 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 536 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 537 void (*clocks_set)(struct drm_device *, void *); 538 539 int (*voltage_get)(struct drm_device *); 540 int (*voltage_set)(struct drm_device *, int voltage); 541 int (*fanspeed_get)(struct drm_device *); 542 int (*fanspeed_set)(struct drm_device *, int fanspeed); 543 int (*temp_get)(struct drm_device *); 544}; 545 546struct nouveau_vram_engine { 547 struct nouveau_mm mm; 548 549 int (*init)(struct drm_device *); 550 void (*takedown)(struct drm_device *dev); 551 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 552 u32 type, struct nouveau_mem **); 553 void (*put)(struct drm_device *, struct nouveau_mem **); 554 555 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 556}; 557 558struct nouveau_engine { 559 struct nouveau_instmem_engine instmem; 560 struct nouveau_mc_engine mc; 561 struct nouveau_timer_engine timer; 562 struct nouveau_fb_engine fb; 563 struct nouveau_fifo_engine fifo; 564 struct nouveau_display_engine display; 565 struct nouveau_gpio_engine gpio; 566 struct nouveau_pm_engine pm; 567 struct nouveau_vram_engine vram; 568}; 569 570struct nouveau_pll_vals { 571 union { 572 struct { 573#ifdef __BIG_ENDIAN 574 uint8_t N1, M1, N2, M2; 575#else 576 uint8_t M1, N1, M2, N2; 577#endif 578 }; 579 struct { 580 uint16_t NM1, NM2; 581 } __attribute__((packed)); 582 }; 583 int log2P; 584 585 int refclk; 586}; 587 588enum nv04_fp_display_regs { 589 FP_DISPLAY_END, 590 FP_TOTAL, 591 FP_CRTC, 592 FP_SYNC_START, 593 FP_SYNC_END, 594 FP_VALID_START, 595 FP_VALID_END 596}; 597 598struct nv04_crtc_reg { 599 unsigned char MiscOutReg; 600 uint8_t CRTC[0xa0]; 601 uint8_t CR58[0x10]; 602 uint8_t Sequencer[5]; 603 uint8_t Graphics[9]; 604 uint8_t Attribute[21]; 605 unsigned char DAC[768]; 606 607 /* PCRTC regs */ 608 uint32_t fb_start; 609 uint32_t crtc_cfg; 610 uint32_t cursor_cfg; 611 uint32_t gpio_ext; 612 uint32_t crtc_830; 613 uint32_t crtc_834; 614 uint32_t crtc_850; 615 uint32_t crtc_eng_ctrl; 616 617 /* PRAMDAC regs */ 618 uint32_t nv10_cursync; 619 struct nouveau_pll_vals pllvals; 620 uint32_t ramdac_gen_ctrl; 621 uint32_t ramdac_630; 622 uint32_t ramdac_634; 623 uint32_t tv_setup; 624 uint32_t tv_vtotal; 625 uint32_t tv_vskew; 626 uint32_t tv_vsync_delay; 627 uint32_t tv_htotal; 628 uint32_t tv_hskew; 629 uint32_t tv_hsync_delay; 630 uint32_t tv_hsync_delay2; 631 uint32_t fp_horiz_regs[7]; 632 uint32_t fp_vert_regs[7]; 633 uint32_t dither; 634 uint32_t fp_control; 635 uint32_t dither_regs[6]; 636 uint32_t fp_debug_0; 637 uint32_t fp_debug_1; 638 uint32_t fp_debug_2; 639 uint32_t fp_margin_color; 640 uint32_t ramdac_8c0; 641 uint32_t ramdac_a20; 642 uint32_t ramdac_a24; 643 uint32_t ramdac_a34; 644 uint32_t ctv_regs[38]; 645}; 646 647struct nv04_output_reg { 648 uint32_t output; 649 int head; 650}; 651 652struct nv04_mode_state { 653 struct nv04_crtc_reg crtc_reg[2]; 654 uint32_t pllsel; 655 uint32_t sel_clk; 656}; 657 658enum nouveau_card_type { 659 NV_04 = 0x00, 660 NV_10 = 0x10, 661 NV_20 = 0x20, 662 NV_30 = 0x30, 663 NV_40 = 0x40, 664 NV_50 = 0x50, 665 NV_C0 = 0xc0, 666 NV_D0 = 0xd0 667}; 668 669struct drm_nouveau_private { 670 struct drm_device *dev; 671 bool noaccel; 672 673 /* the card type, takes NV_* as values */ 674 enum nouveau_card_type card_type; 675 /* exact chipset, derived from NV_PMC_BOOT_0 */ 676 int chipset; 677 int flags; 678 679 void __iomem *mmio; 680 681 spinlock_t ramin_lock; 682 void __iomem *ramin; 683 u32 ramin_size; 684 u32 ramin_base; 685 bool ramin_available; 686 struct drm_mm ramin_heap; 687 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 688 struct list_head gpuobj_list; 689 struct list_head classes; 690 691 struct nouveau_bo *vga_ram; 692 693 /* interrupt handling */ 694 void (*irq_handler[32])(struct drm_device *); 695 bool msi_enabled; 696 697 struct list_head vbl_waiting; 698 699 struct { 700 struct drm_global_reference mem_global_ref; 701 struct ttm_bo_global_ref bo_global_ref; 702 struct ttm_bo_device bdev; 703 atomic_t validate_sequence; 704 } ttm; 705 706 struct { 707 spinlock_t lock; 708 struct drm_mm heap; 709 struct nouveau_bo *bo; 710 } fence; 711 712 struct { 713 spinlock_t lock; 714 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 715 } channels; 716 717 struct nouveau_engine engine; 718 struct nouveau_channel *channel; 719 720 /* For PFIFO and PGRAPH. */ 721 spinlock_t context_switch_lock; 722 723 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 724 spinlock_t vm_lock; 725 726 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 727 struct nouveau_ramht *ramht; 728 struct nouveau_gpuobj *ramfc; 729 struct nouveau_gpuobj *ramro; 730 731 uint32_t ramin_rsvd_vram; 732 733 struct { 734 enum { 735 NOUVEAU_GART_NONE = 0, 736 NOUVEAU_GART_AGP, /* AGP */ 737 NOUVEAU_GART_PDMA, /* paged dma object */ 738 NOUVEAU_GART_HW /* on-chip gart/vm */ 739 } type; 740 uint64_t aper_base; 741 uint64_t aper_size; 742 uint64_t aper_free; 743 744 struct ttm_backend_func *func; 745 746 struct { 747 struct page *page; 748 dma_addr_t addr; 749 } dummy; 750 751 struct nouveau_gpuobj *sg_ctxdma; 752 } gart_info; 753 754 /* nv10-nv40 tiling regions */ 755 struct { 756 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 757 spinlock_t lock; 758 } tile; 759 760 /* VRAM/fb configuration */ 761 uint64_t vram_size; 762 uint64_t vram_sys_base; 763 764 uint64_t fb_available_size; 765 uint64_t fb_mappable_pages; 766 uint64_t fb_aper_free; 767 int fb_mtrr; 768 769 /* BAR control (NV50-) */ 770 struct nouveau_vm *bar1_vm; 771 struct nouveau_vm *bar3_vm; 772 773 /* G8x/G9x virtual address space */ 774 struct nouveau_vm *chan_vm; 775 776 struct nvbios vbios; 777 778 struct nv04_mode_state mode_reg; 779 struct nv04_mode_state saved_reg; 780 uint32_t saved_vga_font[4][16384]; 781 uint32_t crtc_owner; 782 uint32_t dac_users[4]; 783 784 struct backlight_device *backlight; 785 786 struct { 787 struct dentry *channel_root; 788 } debugfs; 789 790 struct nouveau_fbdev *nfbdev; 791 struct apertures_struct *apertures; 792}; 793 794static inline struct drm_nouveau_private * 795nouveau_private(struct drm_device *dev) 796{ 797 return dev->dev_private; 798} 799 800static inline struct drm_nouveau_private * 801nouveau_bdev(struct ttm_bo_device *bd) 802{ 803 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 804} 805 806static inline int 807nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 808{ 809 struct nouveau_bo *prev; 810 811 if (!pnvbo) 812 return -EINVAL; 813 prev = *pnvbo; 814 815 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 816 if (prev) { 817 struct ttm_buffer_object *bo = &prev->bo; 818 819 ttm_bo_unref(&bo); 820 } 821 822 return 0; 823} 824 825/* nouveau_drv.c */ 826extern int nouveau_modeset; 827extern int nouveau_agpmode; 828extern int nouveau_duallink; 829extern int nouveau_uscript_lvds; 830extern int nouveau_uscript_tmds; 831extern int nouveau_vram_pushbuf; 832extern int nouveau_vram_notify; 833extern int nouveau_fbpercrtc; 834extern int nouveau_tv_disable; 835extern char *nouveau_tv_norm; 836extern int nouveau_reg_debug; 837extern char *nouveau_vbios; 838extern int nouveau_ignorelid; 839extern int nouveau_nofbaccel; 840extern int nouveau_noaccel; 841extern int nouveau_force_post; 842extern int nouveau_override_conntype; 843extern char *nouveau_perflvl; 844extern int nouveau_perflvl_wr; 845extern int nouveau_msi; 846extern int nouveau_ctxfw; 847 848extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 849extern int nouveau_pci_resume(struct pci_dev *pdev); 850 851/* nouveau_state.c */ 852extern int nouveau_open(struct drm_device *, struct drm_file *); 853extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 854extern void nouveau_postclose(struct drm_device *, struct drm_file *); 855extern int nouveau_load(struct drm_device *, unsigned long flags); 856extern int nouveau_firstopen(struct drm_device *); 857extern void nouveau_lastclose(struct drm_device *); 858extern int nouveau_unload(struct drm_device *); 859extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 860 struct drm_file *); 861extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 862 struct drm_file *); 863extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 864 uint32_t reg, uint32_t mask, uint32_t val); 865extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 866 uint32_t reg, uint32_t mask, uint32_t val); 867extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 868 bool (*cond)(void *), void *); 869extern bool nouveau_wait_for_idle(struct drm_device *); 870extern int nouveau_card_init(struct drm_device *); 871 872/* nouveau_mem.c */ 873extern int nouveau_mem_vram_init(struct drm_device *); 874extern void nouveau_mem_vram_fini(struct drm_device *); 875extern int nouveau_mem_gart_init(struct drm_device *); 876extern void nouveau_mem_gart_fini(struct drm_device *); 877extern int nouveau_mem_init_agp(struct drm_device *); 878extern int nouveau_mem_reset_agp(struct drm_device *); 879extern void nouveau_mem_close(struct drm_device *); 880extern int nouveau_mem_detect(struct drm_device *); 881extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 882extern struct nouveau_tile_reg *nv10_mem_set_tiling( 883 struct drm_device *dev, uint32_t addr, uint32_t size, 884 uint32_t pitch, uint32_t flags); 885extern void nv10_mem_put_tile_region(struct drm_device *dev, 886 struct nouveau_tile_reg *tile, 887 struct nouveau_fence *fence); 888extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 889extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 890 891/* nouveau_notifier.c */ 892extern int nouveau_notifier_init_channel(struct nouveau_channel *); 893extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 894extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 895 int cout, uint32_t start, uint32_t end, 896 uint32_t *offset); 897extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 898extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 899 struct drm_file *); 900extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 901 struct drm_file *); 902 903/* nouveau_channel.c */ 904extern struct drm_ioctl_desc nouveau_ioctls[]; 905extern int nouveau_max_ioctl; 906extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 907extern int nouveau_channel_alloc(struct drm_device *dev, 908 struct nouveau_channel **chan, 909 struct drm_file *file_priv, 910 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 911extern struct nouveau_channel * 912nouveau_channel_get_unlocked(struct nouveau_channel *); 913extern struct nouveau_channel * 914nouveau_channel_get(struct drm_file *, int id); 915extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 916extern void nouveau_channel_put(struct nouveau_channel **); 917extern void nouveau_channel_ref(struct nouveau_channel *chan, 918 struct nouveau_channel **pchan); 919extern void nouveau_channel_idle(struct nouveau_channel *chan); 920 921/* nouveau_object.c */ 922#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 923 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 924 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 925} while (0) 926 927#define NVOBJ_ENGINE_DEL(d, e) do { \ 928 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 929 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 930} while (0) 931 932#define NVOBJ_CLASS(d, c, e) do { \ 933 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 934 if (ret) \ 935 return ret; \ 936} while (0) 937 938#define NVOBJ_MTHD(d, c, m, e) do { \ 939 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 940 if (ret) \ 941 return ret; \ 942} while (0) 943 944extern int nouveau_gpuobj_early_init(struct drm_device *); 945extern int nouveau_gpuobj_init(struct drm_device *); 946extern void nouveau_gpuobj_takedown(struct drm_device *); 947extern int nouveau_gpuobj_suspend(struct drm_device *dev); 948extern void nouveau_gpuobj_resume(struct drm_device *dev); 949extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 950extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 951 int (*exec)(struct nouveau_channel *, 952 u32 class, u32 mthd, u32 data)); 953extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 954extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 955extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 956 uint32_t vram_h, uint32_t tt_h); 957extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 958extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 959 uint32_t size, int align, uint32_t flags, 960 struct nouveau_gpuobj **); 961extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 962 struct nouveau_gpuobj **); 963extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 964 u32 size, u32 flags, 965 struct nouveau_gpuobj **); 966extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 967 uint64_t offset, uint64_t size, int access, 968 int target, struct nouveau_gpuobj **); 969extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 970extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 971 u64 size, int target, int access, u32 type, 972 u32 comp, struct nouveau_gpuobj **pobj); 973extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 974 int class, u64 base, u64 size, int target, 975 int access, u32 type, u32 comp); 976extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 977 struct drm_file *); 978extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 979 struct drm_file *); 980 981/* nouveau_irq.c */ 982extern int nouveau_irq_init(struct drm_device *); 983extern void nouveau_irq_fini(struct drm_device *); 984extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 985extern void nouveau_irq_register(struct drm_device *, int status_bit, 986 void (*)(struct drm_device *)); 987extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 988extern void nouveau_irq_preinstall(struct drm_device *); 989extern int nouveau_irq_postinstall(struct drm_device *); 990extern void nouveau_irq_uninstall(struct drm_device *); 991 992/* nouveau_sgdma.c */ 993extern int nouveau_sgdma_init(struct drm_device *); 994extern void nouveau_sgdma_takedown(struct drm_device *); 995extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 996 uint32_t offset); 997extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 998 999/* nouveau_debugfs.c */ 1000#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1001extern int nouveau_debugfs_init(struct drm_minor *); 1002extern void nouveau_debugfs_takedown(struct drm_minor *); 1003extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1004extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1005#else 1006static inline int 1007nouveau_debugfs_init(struct drm_minor *minor) 1008{ 1009 return 0; 1010} 1011 1012static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1013{ 1014} 1015 1016static inline int 1017nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1018{ 1019 return 0; 1020} 1021 1022static inline void 1023nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1024{ 1025} 1026#endif 1027 1028/* nouveau_dma.c */ 1029extern void nouveau_dma_pre_init(struct nouveau_channel *); 1030extern int nouveau_dma_init(struct nouveau_channel *); 1031extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1032 1033/* nouveau_acpi.c */ 1034#define ROM_BIOS_PAGE 4096 1035#if defined(CONFIG_ACPI) 1036void nouveau_register_dsm_handler(void); 1037void nouveau_unregister_dsm_handler(void); 1038int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1039bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1040int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1041#else 1042static inline void nouveau_register_dsm_handler(void) {} 1043static inline void nouveau_unregister_dsm_handler(void) {} 1044static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1045static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1046static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1047#endif 1048 1049/* nouveau_backlight.c */ 1050#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1051extern int nouveau_backlight_init(struct drm_connector *); 1052extern void nouveau_backlight_exit(struct drm_connector *); 1053#else 1054static inline int nouveau_backlight_init(struct drm_connector *dev) 1055{ 1056 return 0; 1057} 1058 1059static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1060#endif 1061 1062/* nouveau_bios.c */ 1063extern int nouveau_bios_init(struct drm_device *); 1064extern void nouveau_bios_takedown(struct drm_device *dev); 1065extern int nouveau_run_vbios_init(struct drm_device *); 1066extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1067 struct dcb_entry *, int crtc); 1068extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1069 enum dcb_gpio_tag); 1070extern struct dcb_connector_table_entry * 1071nouveau_bios_connector_entry(struct drm_device *, int index); 1072extern u32 get_pll_register(struct drm_device *, enum pll_types); 1073extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1074 struct pll_lims *); 1075extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1076 struct dcb_entry *, int crtc); 1077extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1078 int *length); 1079extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1080extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1081extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1082 bool *dl, bool *if_is_24bit); 1083extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1084 int head, int pxclk); 1085extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1086 enum LVDS_script, int pxclk); 1087 1088/* nouveau_ttm.c */ 1089int nouveau_ttm_global_init(struct drm_nouveau_private *); 1090void nouveau_ttm_global_release(struct drm_nouveau_private *); 1091int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1092 1093/* nouveau_dp.c */ 1094int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1095 uint8_t *data, int data_nr); 1096bool nouveau_dp_detect(struct drm_encoder *); 1097bool nouveau_dp_link_train(struct drm_encoder *); 1098 1099/* nv04_fb.c */ 1100extern int nv04_fb_init(struct drm_device *); 1101extern void nv04_fb_takedown(struct drm_device *); 1102 1103/* nv10_fb.c */ 1104extern int nv10_fb_init(struct drm_device *); 1105extern void nv10_fb_takedown(struct drm_device *); 1106extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1107 uint32_t addr, uint32_t size, 1108 uint32_t pitch, uint32_t flags); 1109extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1110extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1111 1112/* nv30_fb.c */ 1113extern int nv30_fb_init(struct drm_device *); 1114extern void nv30_fb_takedown(struct drm_device *); 1115extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1116 uint32_t addr, uint32_t size, 1117 uint32_t pitch, uint32_t flags); 1118extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1119 1120/* nv40_fb.c */ 1121extern int nv40_fb_init(struct drm_device *); 1122extern void nv40_fb_takedown(struct drm_device *); 1123extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1124 1125/* nv50_fb.c */ 1126extern int nv50_fb_init(struct drm_device *); 1127extern void nv50_fb_takedown(struct drm_device *); 1128extern void nv50_fb_vm_trap(struct drm_device *, int display); 1129 1130/* nvc0_fb.c */ 1131extern int nvc0_fb_init(struct drm_device *); 1132extern void nvc0_fb_takedown(struct drm_device *); 1133 1134/* nv04_fifo.c */ 1135extern int nv04_fifo_init(struct drm_device *); 1136extern void nv04_fifo_fini(struct drm_device *); 1137extern void nv04_fifo_disable(struct drm_device *); 1138extern void nv04_fifo_enable(struct drm_device *); 1139extern bool nv04_fifo_reassign(struct drm_device *, bool); 1140extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1141extern int nv04_fifo_channel_id(struct drm_device *); 1142extern int nv04_fifo_create_context(struct nouveau_channel *); 1143extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1144extern int nv04_fifo_load_context(struct nouveau_channel *); 1145extern int nv04_fifo_unload_context(struct drm_device *); 1146extern void nv04_fifo_isr(struct drm_device *); 1147 1148/* nv10_fifo.c */ 1149extern int nv10_fifo_init(struct drm_device *); 1150extern int nv10_fifo_channel_id(struct drm_device *); 1151extern int nv10_fifo_create_context(struct nouveau_channel *); 1152extern int nv10_fifo_load_context(struct nouveau_channel *); 1153extern int nv10_fifo_unload_context(struct drm_device *); 1154 1155/* nv40_fifo.c */ 1156extern int nv40_fifo_init(struct drm_device *); 1157extern int nv40_fifo_create_context(struct nouveau_channel *); 1158extern int nv40_fifo_load_context(struct nouveau_channel *); 1159extern int nv40_fifo_unload_context(struct drm_device *); 1160 1161/* nv50_fifo.c */ 1162extern int nv50_fifo_init(struct drm_device *); 1163extern void nv50_fifo_takedown(struct drm_device *); 1164extern int nv50_fifo_channel_id(struct drm_device *); 1165extern int nv50_fifo_create_context(struct nouveau_channel *); 1166extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1167extern int nv50_fifo_load_context(struct nouveau_channel *); 1168extern int nv50_fifo_unload_context(struct drm_device *); 1169extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1170 1171/* nvc0_fifo.c */ 1172extern int nvc0_fifo_init(struct drm_device *); 1173extern void nvc0_fifo_takedown(struct drm_device *); 1174extern void nvc0_fifo_disable(struct drm_device *); 1175extern void nvc0_fifo_enable(struct drm_device *); 1176extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1177extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1178extern int nvc0_fifo_channel_id(struct drm_device *); 1179extern int nvc0_fifo_create_context(struct nouveau_channel *); 1180extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1181extern int nvc0_fifo_load_context(struct nouveau_channel *); 1182extern int nvc0_fifo_unload_context(struct drm_device *); 1183 1184/* nv04_graph.c */ 1185extern int nv04_graph_create(struct drm_device *); 1186extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1187extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1188 u32 class, u32 mthd, u32 data); 1189extern struct nouveau_bitfield nv04_graph_nsource[]; 1190 1191/* nv10_graph.c */ 1192extern int nv10_graph_create(struct drm_device *); 1193extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1194extern struct nouveau_bitfield nv10_graph_intr[]; 1195extern struct nouveau_bitfield nv10_graph_nstatus[]; 1196 1197/* nv20_graph.c */ 1198extern int nv20_graph_create(struct drm_device *); 1199 1200/* nv40_graph.c */ 1201extern int nv40_graph_create(struct drm_device *); 1202extern void nv40_grctx_init(struct nouveau_grctx *); 1203 1204/* nv50_graph.c */ 1205extern int nv50_graph_create(struct drm_device *); 1206extern int nv50_grctx_init(struct nouveau_grctx *); 1207extern struct nouveau_enum nv50_data_error_names[]; 1208extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1209 1210/* nvc0_graph.c */ 1211extern int nvc0_graph_create(struct drm_device *); 1212extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1213 1214/* nv84_crypt.c */ 1215extern int nv84_crypt_create(struct drm_device *); 1216 1217/* nva3_copy.c */ 1218extern int nva3_copy_create(struct drm_device *dev); 1219 1220/* nvc0_copy.c */ 1221extern int nvc0_copy_create(struct drm_device *dev, int engine); 1222 1223/* nv31_mpeg.c */ 1224extern int nv31_mpeg_create(struct drm_device *dev); 1225 1226/* nv50_mpeg.c */ 1227extern int nv50_mpeg_create(struct drm_device *dev); 1228 1229/* nv04_instmem.c */ 1230extern int nv04_instmem_init(struct drm_device *); 1231extern void nv04_instmem_takedown(struct drm_device *); 1232extern int nv04_instmem_suspend(struct drm_device *); 1233extern void nv04_instmem_resume(struct drm_device *); 1234extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1235 u32 size, u32 align); 1236extern void nv04_instmem_put(struct nouveau_gpuobj *); 1237extern int nv04_instmem_map(struct nouveau_gpuobj *); 1238extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1239extern void nv04_instmem_flush(struct drm_device *); 1240 1241/* nv50_instmem.c */ 1242extern int nv50_instmem_init(struct drm_device *); 1243extern void nv50_instmem_takedown(struct drm_device *); 1244extern int nv50_instmem_suspend(struct drm_device *); 1245extern void nv50_instmem_resume(struct drm_device *); 1246extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1247 u32 size, u32 align); 1248extern void nv50_instmem_put(struct nouveau_gpuobj *); 1249extern int nv50_instmem_map(struct nouveau_gpuobj *); 1250extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1251extern void nv50_instmem_flush(struct drm_device *); 1252extern void nv84_instmem_flush(struct drm_device *); 1253 1254/* nvc0_instmem.c */ 1255extern int nvc0_instmem_init(struct drm_device *); 1256extern void nvc0_instmem_takedown(struct drm_device *); 1257extern int nvc0_instmem_suspend(struct drm_device *); 1258extern void nvc0_instmem_resume(struct drm_device *); 1259 1260/* nv04_mc.c */ 1261extern int nv04_mc_init(struct drm_device *); 1262extern void nv04_mc_takedown(struct drm_device *); 1263 1264/* nv40_mc.c */ 1265extern int nv40_mc_init(struct drm_device *); 1266extern void nv40_mc_takedown(struct drm_device *); 1267 1268/* nv50_mc.c */ 1269extern int nv50_mc_init(struct drm_device *); 1270extern void nv50_mc_takedown(struct drm_device *); 1271 1272/* nv04_timer.c */ 1273extern int nv04_timer_init(struct drm_device *); 1274extern uint64_t nv04_timer_read(struct drm_device *); 1275extern void nv04_timer_takedown(struct drm_device *); 1276 1277extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1278 unsigned long arg); 1279 1280/* nv04_dac.c */ 1281extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1282extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1283extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1284extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1285extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1286 1287/* nv04_dfp.c */ 1288extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1289extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1290extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1291 int head, bool dl); 1292extern void nv04_dfp_disable(struct drm_device *dev, int head); 1293extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1294 1295/* nv04_tv.c */ 1296extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1297extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1298 1299/* nv17_tv.c */ 1300extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1301 1302/* nv04_display.c */ 1303extern int nv04_display_early_init(struct drm_device *); 1304extern void nv04_display_late_takedown(struct drm_device *); 1305extern int nv04_display_create(struct drm_device *); 1306extern int nv04_display_init(struct drm_device *); 1307extern void nv04_display_destroy(struct drm_device *); 1308 1309/* nvd0_display.c */ 1310extern int nvd0_display_create(struct drm_device *); 1311extern int nvd0_display_init(struct drm_device *); 1312extern void nvd0_display_destroy(struct drm_device *); 1313 1314/* nv04_crtc.c */ 1315extern int nv04_crtc_create(struct drm_device *, int index); 1316 1317/* nouveau_bo.c */ 1318extern struct ttm_bo_driver nouveau_bo_driver; 1319extern int nouveau_bo_new(struct drm_device *, int size, int align, 1320 uint32_t flags, uint32_t tile_mode, 1321 uint32_t tile_flags, struct nouveau_bo **); 1322extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1323extern int nouveau_bo_unpin(struct nouveau_bo *); 1324extern int nouveau_bo_map(struct nouveau_bo *); 1325extern void nouveau_bo_unmap(struct nouveau_bo *); 1326extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1327 uint32_t busy); 1328extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1329extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1330extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1331extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1332extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1333extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1334 bool no_wait_reserve, bool no_wait_gpu); 1335 1336extern struct nouveau_vma * 1337nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1338extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1339 struct nouveau_vma *); 1340extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1341 1342/* nouveau_fence.c */ 1343struct nouveau_fence; 1344extern int nouveau_fence_init(struct drm_device *); 1345extern void nouveau_fence_fini(struct drm_device *); 1346extern int nouveau_fence_channel_init(struct nouveau_channel *); 1347extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1348extern void nouveau_fence_update(struct nouveau_channel *); 1349extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1350 bool emit); 1351extern int nouveau_fence_emit(struct nouveau_fence *); 1352extern void nouveau_fence_work(struct nouveau_fence *fence, 1353 void (*work)(void *priv, bool signalled), 1354 void *priv); 1355struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1356 1357extern bool __nouveau_fence_signalled(void *obj, void *arg); 1358extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1359extern int __nouveau_fence_flush(void *obj, void *arg); 1360extern void __nouveau_fence_unref(void **obj); 1361extern void *__nouveau_fence_ref(void *obj); 1362 1363static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1364{ 1365 return __nouveau_fence_signalled(obj, NULL); 1366} 1367static inline int 1368nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1369{ 1370 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1371} 1372extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1373static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1374{ 1375 return __nouveau_fence_flush(obj, NULL); 1376} 1377static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1378{ 1379 __nouveau_fence_unref((void **)obj); 1380} 1381static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1382{ 1383 return __nouveau_fence_ref(obj); 1384} 1385 1386/* nouveau_gem.c */ 1387extern int nouveau_gem_new(struct drm_device *, int size, int align, 1388 uint32_t domain, uint32_t tile_mode, 1389 uint32_t tile_flags, struct nouveau_bo **); 1390extern int nouveau_gem_object_new(struct drm_gem_object *); 1391extern void nouveau_gem_object_del(struct drm_gem_object *); 1392extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1393extern void nouveau_gem_object_close(struct drm_gem_object *, 1394 struct drm_file *); 1395extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1396 struct drm_file *); 1397extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1398 struct drm_file *); 1399extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1400 struct drm_file *); 1401extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1402 struct drm_file *); 1403extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1404 struct drm_file *); 1405 1406/* nouveau_display.c */ 1407int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1408void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1409int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1410 struct drm_pending_vblank_event *event); 1411int nouveau_finish_page_flip(struct nouveau_channel *, 1412 struct nouveau_page_flip_state *); 1413 1414/* nv10_gpio.c */ 1415int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1416int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1417 1418/* nv50_gpio.c */ 1419int nv50_gpio_init(struct drm_device *dev); 1420void nv50_gpio_fini(struct drm_device *dev); 1421int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1422int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1423int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1424int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1425int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1426 void (*)(void *, int), void *); 1427void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1428 void (*)(void *, int), void *); 1429bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1430 1431/* nv50_calc. */ 1432int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1433 int *N1, int *M1, int *N2, int *M2, int *P); 1434int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1435 int clk, int *N, int *fN, int *M, int *P); 1436 1437#ifndef ioread32_native 1438#ifdef __BIG_ENDIAN 1439#define ioread16_native ioread16be 1440#define iowrite16_native iowrite16be 1441#define ioread32_native ioread32be 1442#define iowrite32_native iowrite32be 1443#else /* def __BIG_ENDIAN */ 1444#define ioread16_native ioread16 1445#define iowrite16_native iowrite16 1446#define ioread32_native ioread32 1447#define iowrite32_native iowrite32 1448#endif /* def __BIG_ENDIAN else */ 1449#endif /* !ioread32_native */ 1450 1451/* channel control reg access */ 1452static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1453{ 1454 return ioread32_native(chan->user + reg); 1455} 1456 1457static inline void nvchan_wr32(struct nouveau_channel *chan, 1458 unsigned reg, u32 val) 1459{ 1460 iowrite32_native(val, chan->user + reg); 1461} 1462 1463/* register access */ 1464static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1465{ 1466 struct drm_nouveau_private *dev_priv = dev->dev_private; 1467 return ioread32_native(dev_priv->mmio + reg); 1468} 1469 1470static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1471{ 1472 struct drm_nouveau_private *dev_priv = dev->dev_private; 1473 iowrite32_native(val, dev_priv->mmio + reg); 1474} 1475 1476static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1477{ 1478 u32 tmp = nv_rd32(dev, reg); 1479 nv_wr32(dev, reg, (tmp & ~mask) | val); 1480 return tmp; 1481} 1482 1483static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1484{ 1485 struct drm_nouveau_private *dev_priv = dev->dev_private; 1486 return ioread8(dev_priv->mmio + reg); 1487} 1488 1489static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1490{ 1491 struct drm_nouveau_private *dev_priv = dev->dev_private; 1492 iowrite8(val, dev_priv->mmio + reg); 1493} 1494 1495#define nv_wait(dev, reg, mask, val) \ 1496 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1497#define nv_wait_ne(dev, reg, mask, val) \ 1498 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1499#define nv_wait_cb(dev, func, data) \ 1500 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1501 1502/* PRAMIN access */ 1503static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1504{ 1505 struct drm_nouveau_private *dev_priv = dev->dev_private; 1506 return ioread32_native(dev_priv->ramin + offset); 1507} 1508 1509static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1510{ 1511 struct drm_nouveau_private *dev_priv = dev->dev_private; 1512 iowrite32_native(val, dev_priv->ramin + offset); 1513} 1514 1515/* object access */ 1516extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1517extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1518 1519/* 1520 * Logging 1521 * Argument d is (struct drm_device *). 1522 */ 1523#define NV_PRINTK(level, d, fmt, arg...) \ 1524 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1525 pci_name(d->pdev), ##arg) 1526#ifndef NV_DEBUG_NOTRACE 1527#define NV_DEBUG(d, fmt, arg...) do { \ 1528 if (drm_debug & DRM_UT_DRIVER) { \ 1529 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1530 __LINE__, ##arg); \ 1531 } \ 1532} while (0) 1533#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1534 if (drm_debug & DRM_UT_KMS) { \ 1535 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1536 __LINE__, ##arg); \ 1537 } \ 1538} while (0) 1539#else 1540#define NV_DEBUG(d, fmt, arg...) do { \ 1541 if (drm_debug & DRM_UT_DRIVER) \ 1542 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1543} while (0) 1544#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1545 if (drm_debug & DRM_UT_KMS) \ 1546 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1547} while (0) 1548#endif 1549#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1550#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1551#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1552#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1553#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1554 1555/* nouveau_reg_debug bitmask */ 1556enum { 1557 NOUVEAU_REG_DEBUG_MC = 0x1, 1558 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1559 NOUVEAU_REG_DEBUG_FB = 0x4, 1560 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1561 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1562 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1563 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1564 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1565 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1566 NOUVEAU_REG_DEBUG_EVO = 0x200, 1567}; 1568 1569#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1570 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1571 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1572} while (0) 1573 1574static inline bool 1575nv_two_heads(struct drm_device *dev) 1576{ 1577 struct drm_nouveau_private *dev_priv = dev->dev_private; 1578 const int impl = dev->pci_device & 0x0ff0; 1579 1580 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1581 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1582 return true; 1583 1584 return false; 1585} 1586 1587static inline bool 1588nv_gf4_disp_arch(struct drm_device *dev) 1589{ 1590 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1591} 1592 1593static inline bool 1594nv_two_reg_pll(struct drm_device *dev) 1595{ 1596 struct drm_nouveau_private *dev_priv = dev->dev_private; 1597 const int impl = dev->pci_device & 0x0ff0; 1598 1599 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1600 return true; 1601 return false; 1602} 1603 1604static inline bool 1605nv_match_device(struct drm_device *dev, unsigned device, 1606 unsigned sub_vendor, unsigned sub_device) 1607{ 1608 return dev->pdev->device == device && 1609 dev->pdev->subsystem_vendor == sub_vendor && 1610 dev->pdev->subsystem_device == sub_device; 1611} 1612 1613static inline void * 1614nv_engine(struct drm_device *dev, int engine) 1615{ 1616 struct drm_nouveau_private *dev_priv = dev->dev_private; 1617 return (void *)dev_priv->eng[engine]; 1618} 1619 1620/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1621 * helpful to determine a number of other hardware features 1622 */ 1623static inline int 1624nv44_graph_class(struct drm_device *dev) 1625{ 1626 struct drm_nouveau_private *dev_priv = dev->dev_private; 1627 1628 if ((dev_priv->chipset & 0xf0) == 0x60) 1629 return 1; 1630 1631 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1632} 1633 1634/* memory type/access flags, do not match hardware values */ 1635#define NV_MEM_ACCESS_RO 1 1636#define NV_MEM_ACCESS_WO 2 1637#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1638#define NV_MEM_ACCESS_SYS 4 1639#define NV_MEM_ACCESS_VM 8 1640 1641#define NV_MEM_TARGET_VRAM 0 1642#define NV_MEM_TARGET_PCI 1 1643#define NV_MEM_TARGET_PCI_NOSNOOP 2 1644#define NV_MEM_TARGET_VM 3 1645#define NV_MEM_TARGET_GART 4 1646 1647#define NV_MEM_TYPE_VM 0x7f 1648#define NV_MEM_COMP_VM 0x03 1649 1650/* NV_SW object class */ 1651#define NV_SW 0x0000506e 1652#define NV_SW_DMA_SEMAPHORE 0x00000060 1653#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1654#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1655#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1656#define NV_SW_YIELD 0x00000080 1657#define NV_SW_DMA_VBLSEM 0x0000018c 1658#define NV_SW_VBLSEM_OFFSET 0x00000400 1659#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1660#define NV_SW_VBLSEM_RELEASE 0x00000408 1661#define NV_SW_PAGE_FLIP 0x00000500 1662 1663#endif /* __NOUVEAU_DRV_H__ */ 1664