nouveau_drv.h revision a0b25635515ef5049f93b032a1e37f18b16e0f6f
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 void (*destroy)(struct drm_device *); 400 int (*init)(struct drm_device *); 401 void (*fini)(struct drm_device *); 402 403 struct drm_property *dithering_mode; 404 struct drm_property *dithering_depth; 405 struct drm_property *underscan_property; 406 struct drm_property *underscan_hborder_property; 407 struct drm_property *underscan_vborder_property; 408}; 409 410struct nouveau_gpio_engine { 411 spinlock_t lock; 412 struct list_head isr; 413 int (*init)(struct drm_device *); 414 void (*fini)(struct drm_device *); 415 int (*drive)(struct drm_device *, int line, int dir, int out); 416 int (*sense)(struct drm_device *, int line); 417 void (*irq_enable)(struct drm_device *, int line, bool); 418}; 419 420struct nouveau_pm_voltage_level { 421 u32 voltage; /* microvolts */ 422 u8 vid; 423}; 424 425struct nouveau_pm_voltage { 426 bool supported; 427 u8 version; 428 u8 vid_mask; 429 430 struct nouveau_pm_voltage_level *level; 431 int nr_level; 432}; 433 434struct nouveau_pm_memtiming { 435 int id; 436 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 437 u32 reg_1; 438 u32 reg_2; 439 u32 reg_3; 440 u32 reg_4; 441 u32 reg_5; 442 u32 reg_6; 443 u32 reg_7; 444 u32 reg_8; 445 /* To be written to 0x1002c0 */ 446 u8 CL; 447 u8 WR; 448}; 449 450struct nouveau_pm_tbl_header{ 451 u8 version; 452 u8 header_len; 453 u8 entry_cnt; 454 u8 entry_len; 455}; 456 457struct nouveau_pm_tbl_entry{ 458 u8 tWR; 459 u8 tUNK_1; 460 u8 tCL; 461 u8 tRP; /* Byte 3 */ 462 u8 empty_4; 463 u8 tRAS; /* Byte 5 */ 464 u8 empty_6; 465 u8 tRFC; /* Byte 7 */ 466 u8 empty_8; 467 u8 tRC; /* Byte 9 */ 468 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 469 u8 empty_15,empty_16,empty_17; 470 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 471}; 472 473/* nouveau_mem.c */ 474void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 475 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 476 struct nouveau_pm_memtiming *timing); 477 478#define NOUVEAU_PM_MAX_LEVEL 8 479struct nouveau_pm_level { 480 struct device_attribute dev_attr; 481 char name[32]; 482 int id; 483 484 u32 core; 485 u32 memory; 486 u32 shader; 487 u32 rop; 488 u32 copy; 489 u32 daemon; 490 u32 vdec; 491 u32 dom6; 492 u32 unka0; /* nva3:nvc0 */ 493 u32 hub01; /* nvc0- */ 494 u32 hub06; /* nvc0- */ 495 u32 hub07; /* nvc0- */ 496 497 u32 volt_min; /* microvolts */ 498 u32 volt_max; 499 u8 fanspeed; 500 501 u16 memscript; 502 struct nouveau_pm_memtiming *timing; 503}; 504 505struct nouveau_pm_temp_sensor_constants { 506 u16 offset_constant; 507 s16 offset_mult; 508 s16 offset_div; 509 s16 slope_mult; 510 s16 slope_div; 511}; 512 513struct nouveau_pm_threshold_temp { 514 s16 critical; 515 s16 down_clock; 516 s16 fan_boost; 517}; 518 519struct nouveau_pm_memtimings { 520 bool supported; 521 struct nouveau_pm_memtiming *timing; 522 int nr_timing; 523}; 524 525struct nouveau_pm_fan { 526 u32 min_duty; 527 u32 max_duty; 528 u32 pwm_freq; 529}; 530 531struct nouveau_pm_engine { 532 struct nouveau_pm_voltage voltage; 533 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 534 int nr_perflvl; 535 struct nouveau_pm_memtimings memtimings; 536 struct nouveau_pm_temp_sensor_constants sensor_constants; 537 struct nouveau_pm_threshold_temp threshold_temp; 538 struct nouveau_pm_fan fan; 539 u32 pwm_divisor; 540 541 struct nouveau_pm_level boot; 542 struct nouveau_pm_level *cur; 543 544 struct device *hwmon; 545 struct notifier_block acpi_nb; 546 547 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 548 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 549 int (*clocks_set)(struct drm_device *, void *); 550 551 int (*voltage_get)(struct drm_device *); 552 int (*voltage_set)(struct drm_device *, int voltage); 553 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 554 int (*pwm_set)(struct drm_device *, int line, u32, u32); 555 int (*temp_get)(struct drm_device *); 556}; 557 558struct nouveau_vram_engine { 559 struct nouveau_mm mm; 560 561 int (*init)(struct drm_device *); 562 void (*takedown)(struct drm_device *dev); 563 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 564 u32 type, struct nouveau_mem **); 565 void (*put)(struct drm_device *, struct nouveau_mem **); 566 567 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 568}; 569 570struct nouveau_engine { 571 struct nouveau_instmem_engine instmem; 572 struct nouveau_mc_engine mc; 573 struct nouveau_timer_engine timer; 574 struct nouveau_fb_engine fb; 575 struct nouveau_fifo_engine fifo; 576 struct nouveau_display_engine display; 577 struct nouveau_gpio_engine gpio; 578 struct nouveau_pm_engine pm; 579 struct nouveau_vram_engine vram; 580}; 581 582struct nouveau_pll_vals { 583 union { 584 struct { 585#ifdef __BIG_ENDIAN 586 uint8_t N1, M1, N2, M2; 587#else 588 uint8_t M1, N1, M2, N2; 589#endif 590 }; 591 struct { 592 uint16_t NM1, NM2; 593 } __attribute__((packed)); 594 }; 595 int log2P; 596 597 int refclk; 598}; 599 600enum nv04_fp_display_regs { 601 FP_DISPLAY_END, 602 FP_TOTAL, 603 FP_CRTC, 604 FP_SYNC_START, 605 FP_SYNC_END, 606 FP_VALID_START, 607 FP_VALID_END 608}; 609 610struct nv04_crtc_reg { 611 unsigned char MiscOutReg; 612 uint8_t CRTC[0xa0]; 613 uint8_t CR58[0x10]; 614 uint8_t Sequencer[5]; 615 uint8_t Graphics[9]; 616 uint8_t Attribute[21]; 617 unsigned char DAC[768]; 618 619 /* PCRTC regs */ 620 uint32_t fb_start; 621 uint32_t crtc_cfg; 622 uint32_t cursor_cfg; 623 uint32_t gpio_ext; 624 uint32_t crtc_830; 625 uint32_t crtc_834; 626 uint32_t crtc_850; 627 uint32_t crtc_eng_ctrl; 628 629 /* PRAMDAC regs */ 630 uint32_t nv10_cursync; 631 struct nouveau_pll_vals pllvals; 632 uint32_t ramdac_gen_ctrl; 633 uint32_t ramdac_630; 634 uint32_t ramdac_634; 635 uint32_t tv_setup; 636 uint32_t tv_vtotal; 637 uint32_t tv_vskew; 638 uint32_t tv_vsync_delay; 639 uint32_t tv_htotal; 640 uint32_t tv_hskew; 641 uint32_t tv_hsync_delay; 642 uint32_t tv_hsync_delay2; 643 uint32_t fp_horiz_regs[7]; 644 uint32_t fp_vert_regs[7]; 645 uint32_t dither; 646 uint32_t fp_control; 647 uint32_t dither_regs[6]; 648 uint32_t fp_debug_0; 649 uint32_t fp_debug_1; 650 uint32_t fp_debug_2; 651 uint32_t fp_margin_color; 652 uint32_t ramdac_8c0; 653 uint32_t ramdac_a20; 654 uint32_t ramdac_a24; 655 uint32_t ramdac_a34; 656 uint32_t ctv_regs[38]; 657}; 658 659struct nv04_output_reg { 660 uint32_t output; 661 int head; 662}; 663 664struct nv04_mode_state { 665 struct nv04_crtc_reg crtc_reg[2]; 666 uint32_t pllsel; 667 uint32_t sel_clk; 668}; 669 670enum nouveau_card_type { 671 NV_04 = 0x00, 672 NV_10 = 0x10, 673 NV_20 = 0x20, 674 NV_30 = 0x30, 675 NV_40 = 0x40, 676 NV_50 = 0x50, 677 NV_C0 = 0xc0, 678 NV_D0 = 0xd0 679}; 680 681struct drm_nouveau_private { 682 struct drm_device *dev; 683 bool noaccel; 684 685 /* the card type, takes NV_* as values */ 686 enum nouveau_card_type card_type; 687 /* exact chipset, derived from NV_PMC_BOOT_0 */ 688 int chipset; 689 int flags; 690 u32 crystal; 691 692 void __iomem *mmio; 693 694 spinlock_t ramin_lock; 695 void __iomem *ramin; 696 u32 ramin_size; 697 u32 ramin_base; 698 bool ramin_available; 699 struct drm_mm ramin_heap; 700 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 701 struct list_head gpuobj_list; 702 struct list_head classes; 703 704 struct nouveau_bo *vga_ram; 705 706 /* interrupt handling */ 707 void (*irq_handler[32])(struct drm_device *); 708 bool msi_enabled; 709 710 struct list_head vbl_waiting; 711 712 struct { 713 struct drm_global_reference mem_global_ref; 714 struct ttm_bo_global_ref bo_global_ref; 715 struct ttm_bo_device bdev; 716 atomic_t validate_sequence; 717 } ttm; 718 719 struct { 720 spinlock_t lock; 721 struct drm_mm heap; 722 struct nouveau_bo *bo; 723 } fence; 724 725 struct { 726 spinlock_t lock; 727 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 728 } channels; 729 730 struct nouveau_engine engine; 731 struct nouveau_channel *channel; 732 733 /* For PFIFO and PGRAPH. */ 734 spinlock_t context_switch_lock; 735 736 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 737 spinlock_t vm_lock; 738 739 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 740 struct nouveau_ramht *ramht; 741 struct nouveau_gpuobj *ramfc; 742 struct nouveau_gpuobj *ramro; 743 744 uint32_t ramin_rsvd_vram; 745 746 struct { 747 enum { 748 NOUVEAU_GART_NONE = 0, 749 NOUVEAU_GART_AGP, /* AGP */ 750 NOUVEAU_GART_PDMA, /* paged dma object */ 751 NOUVEAU_GART_HW /* on-chip gart/vm */ 752 } type; 753 uint64_t aper_base; 754 uint64_t aper_size; 755 uint64_t aper_free; 756 757 struct ttm_backend_func *func; 758 759 struct { 760 struct page *page; 761 dma_addr_t addr; 762 } dummy; 763 764 struct nouveau_gpuobj *sg_ctxdma; 765 } gart_info; 766 767 /* nv10-nv40 tiling regions */ 768 struct { 769 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 770 spinlock_t lock; 771 } tile; 772 773 /* VRAM/fb configuration */ 774 uint64_t vram_size; 775 uint64_t vram_sys_base; 776 777 uint64_t fb_available_size; 778 uint64_t fb_mappable_pages; 779 uint64_t fb_aper_free; 780 int fb_mtrr; 781 782 /* BAR control (NV50-) */ 783 struct nouveau_vm *bar1_vm; 784 struct nouveau_vm *bar3_vm; 785 786 /* G8x/G9x virtual address space */ 787 struct nouveau_vm *chan_vm; 788 789 struct nvbios vbios; 790 u8 *mxms; 791 struct list_head i2c_ports; 792 793 struct nv04_mode_state mode_reg; 794 struct nv04_mode_state saved_reg; 795 uint32_t saved_vga_font[4][16384]; 796 uint32_t crtc_owner; 797 uint32_t dac_users[4]; 798 799 struct backlight_device *backlight; 800 801 struct { 802 struct dentry *channel_root; 803 } debugfs; 804 805 struct nouveau_fbdev *nfbdev; 806 struct apertures_struct *apertures; 807}; 808 809static inline struct drm_nouveau_private * 810nouveau_private(struct drm_device *dev) 811{ 812 return dev->dev_private; 813} 814 815static inline struct drm_nouveau_private * 816nouveau_bdev(struct ttm_bo_device *bd) 817{ 818 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 819} 820 821static inline int 822nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 823{ 824 struct nouveau_bo *prev; 825 826 if (!pnvbo) 827 return -EINVAL; 828 prev = *pnvbo; 829 830 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 831 if (prev) { 832 struct ttm_buffer_object *bo = &prev->bo; 833 834 ttm_bo_unref(&bo); 835 } 836 837 return 0; 838} 839 840/* nouveau_drv.c */ 841extern int nouveau_modeset; 842extern int nouveau_agpmode; 843extern int nouveau_duallink; 844extern int nouveau_uscript_lvds; 845extern int nouveau_uscript_tmds; 846extern int nouveau_vram_pushbuf; 847extern int nouveau_vram_notify; 848extern int nouveau_fbpercrtc; 849extern int nouveau_tv_disable; 850extern char *nouveau_tv_norm; 851extern int nouveau_reg_debug; 852extern char *nouveau_vbios; 853extern int nouveau_ignorelid; 854extern int nouveau_nofbaccel; 855extern int nouveau_noaccel; 856extern int nouveau_force_post; 857extern int nouveau_override_conntype; 858extern char *nouveau_perflvl; 859extern int nouveau_perflvl_wr; 860extern int nouveau_msi; 861extern int nouveau_ctxfw; 862extern int nouveau_mxmdcb; 863 864extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 865extern int nouveau_pci_resume(struct pci_dev *pdev); 866 867/* nouveau_state.c */ 868extern int nouveau_open(struct drm_device *, struct drm_file *); 869extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 870extern void nouveau_postclose(struct drm_device *, struct drm_file *); 871extern int nouveau_load(struct drm_device *, unsigned long flags); 872extern int nouveau_firstopen(struct drm_device *); 873extern void nouveau_lastclose(struct drm_device *); 874extern int nouveau_unload(struct drm_device *); 875extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 876 struct drm_file *); 877extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 878 struct drm_file *); 879extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 880 uint32_t reg, uint32_t mask, uint32_t val); 881extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 882 uint32_t reg, uint32_t mask, uint32_t val); 883extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 884 bool (*cond)(void *), void *); 885extern bool nouveau_wait_for_idle(struct drm_device *); 886extern int nouveau_card_init(struct drm_device *); 887 888/* nouveau_mem.c */ 889extern int nouveau_mem_vram_init(struct drm_device *); 890extern void nouveau_mem_vram_fini(struct drm_device *); 891extern int nouveau_mem_gart_init(struct drm_device *); 892extern void nouveau_mem_gart_fini(struct drm_device *); 893extern int nouveau_mem_init_agp(struct drm_device *); 894extern int nouveau_mem_reset_agp(struct drm_device *); 895extern void nouveau_mem_close(struct drm_device *); 896extern int nouveau_mem_detect(struct drm_device *); 897extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 898extern struct nouveau_tile_reg *nv10_mem_set_tiling( 899 struct drm_device *dev, uint32_t addr, uint32_t size, 900 uint32_t pitch, uint32_t flags); 901extern void nv10_mem_put_tile_region(struct drm_device *dev, 902 struct nouveau_tile_reg *tile, 903 struct nouveau_fence *fence); 904extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 905extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 906 907/* nouveau_notifier.c */ 908extern int nouveau_notifier_init_channel(struct nouveau_channel *); 909extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 910extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 911 int cout, uint32_t start, uint32_t end, 912 uint32_t *offset); 913extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 914extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 915 struct drm_file *); 916extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 917 struct drm_file *); 918 919/* nouveau_channel.c */ 920extern struct drm_ioctl_desc nouveau_ioctls[]; 921extern int nouveau_max_ioctl; 922extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 923extern int nouveau_channel_alloc(struct drm_device *dev, 924 struct nouveau_channel **chan, 925 struct drm_file *file_priv, 926 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 927extern struct nouveau_channel * 928nouveau_channel_get_unlocked(struct nouveau_channel *); 929extern struct nouveau_channel * 930nouveau_channel_get(struct drm_file *, int id); 931extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 932extern void nouveau_channel_put(struct nouveau_channel **); 933extern void nouveau_channel_ref(struct nouveau_channel *chan, 934 struct nouveau_channel **pchan); 935extern void nouveau_channel_idle(struct nouveau_channel *chan); 936 937/* nouveau_object.c */ 938#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 939 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 940 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 941} while (0) 942 943#define NVOBJ_ENGINE_DEL(d, e) do { \ 944 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 945 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 946} while (0) 947 948#define NVOBJ_CLASS(d, c, e) do { \ 949 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 950 if (ret) \ 951 return ret; \ 952} while (0) 953 954#define NVOBJ_MTHD(d, c, m, e) do { \ 955 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 956 if (ret) \ 957 return ret; \ 958} while (0) 959 960extern int nouveau_gpuobj_early_init(struct drm_device *); 961extern int nouveau_gpuobj_init(struct drm_device *); 962extern void nouveau_gpuobj_takedown(struct drm_device *); 963extern int nouveau_gpuobj_suspend(struct drm_device *dev); 964extern void nouveau_gpuobj_resume(struct drm_device *dev); 965extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 966extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 967 int (*exec)(struct nouveau_channel *, 968 u32 class, u32 mthd, u32 data)); 969extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 970extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 971extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 972 uint32_t vram_h, uint32_t tt_h); 973extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 974extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 975 uint32_t size, int align, uint32_t flags, 976 struct nouveau_gpuobj **); 977extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 978 struct nouveau_gpuobj **); 979extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 980 u32 size, u32 flags, 981 struct nouveau_gpuobj **); 982extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 983 uint64_t offset, uint64_t size, int access, 984 int target, struct nouveau_gpuobj **); 985extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 986extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 987 u64 size, int target, int access, u32 type, 988 u32 comp, struct nouveau_gpuobj **pobj); 989extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 990 int class, u64 base, u64 size, int target, 991 int access, u32 type, u32 comp); 992extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 993 struct drm_file *); 994extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 995 struct drm_file *); 996 997/* nouveau_irq.c */ 998extern int nouveau_irq_init(struct drm_device *); 999extern void nouveau_irq_fini(struct drm_device *); 1000extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1001extern void nouveau_irq_register(struct drm_device *, int status_bit, 1002 void (*)(struct drm_device *)); 1003extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1004extern void nouveau_irq_preinstall(struct drm_device *); 1005extern int nouveau_irq_postinstall(struct drm_device *); 1006extern void nouveau_irq_uninstall(struct drm_device *); 1007 1008/* nouveau_sgdma.c */ 1009extern int nouveau_sgdma_init(struct drm_device *); 1010extern void nouveau_sgdma_takedown(struct drm_device *); 1011extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1012 uint32_t offset); 1013extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1014 unsigned long size, 1015 uint32_t page_flags, 1016 struct page *dummy_read_page); 1017 1018/* nouveau_debugfs.c */ 1019#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1020extern int nouveau_debugfs_init(struct drm_minor *); 1021extern void nouveau_debugfs_takedown(struct drm_minor *); 1022extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1023extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1024#else 1025static inline int 1026nouveau_debugfs_init(struct drm_minor *minor) 1027{ 1028 return 0; 1029} 1030 1031static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1032{ 1033} 1034 1035static inline int 1036nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1037{ 1038 return 0; 1039} 1040 1041static inline void 1042nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1043{ 1044} 1045#endif 1046 1047/* nouveau_dma.c */ 1048extern void nouveau_dma_pre_init(struct nouveau_channel *); 1049extern int nouveau_dma_init(struct nouveau_channel *); 1050extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1051 1052/* nouveau_acpi.c */ 1053#define ROM_BIOS_PAGE 4096 1054#if defined(CONFIG_ACPI) 1055void nouveau_register_dsm_handler(void); 1056void nouveau_unregister_dsm_handler(void); 1057int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1058bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1059int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1060#else 1061static inline void nouveau_register_dsm_handler(void) {} 1062static inline void nouveau_unregister_dsm_handler(void) {} 1063static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1064static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1065static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1066#endif 1067 1068/* nouveau_backlight.c */ 1069#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1070extern int nouveau_backlight_init(struct drm_device *); 1071extern void nouveau_backlight_exit(struct drm_device *); 1072#else 1073static inline int nouveau_backlight_init(struct drm_device *dev) 1074{ 1075 return 0; 1076} 1077 1078static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1079#endif 1080 1081/* nouveau_bios.c */ 1082extern int nouveau_bios_init(struct drm_device *); 1083extern void nouveau_bios_takedown(struct drm_device *dev); 1084extern int nouveau_run_vbios_init(struct drm_device *); 1085extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1086 struct dcb_entry *, int crtc); 1087extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1088extern struct dcb_connector_table_entry * 1089nouveau_bios_connector_entry(struct drm_device *, int index); 1090extern u32 get_pll_register(struct drm_device *, enum pll_types); 1091extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1092 struct pll_lims *); 1093extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1094 struct dcb_entry *, int crtc); 1095extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1096extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1097extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1098 bool *dl, bool *if_is_24bit); 1099extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1100 int head, int pxclk); 1101extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1102 enum LVDS_script, int pxclk); 1103bool bios_encoder_match(struct dcb_entry *, u32 hash); 1104 1105/* nouveau_mxm.c */ 1106int nouveau_mxm_init(struct drm_device *dev); 1107void nouveau_mxm_fini(struct drm_device *dev); 1108 1109/* nouveau_ttm.c */ 1110int nouveau_ttm_global_init(struct drm_nouveau_private *); 1111void nouveau_ttm_global_release(struct drm_nouveau_private *); 1112int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1113 1114/* nouveau_hdmi.c */ 1115void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1116 1117/* nouveau_dp.c */ 1118int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1119 uint8_t *data, int data_nr); 1120bool nouveau_dp_detect(struct drm_encoder *); 1121bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1122void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1123u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1124 1125/* nv04_fb.c */ 1126extern int nv04_fb_init(struct drm_device *); 1127extern void nv04_fb_takedown(struct drm_device *); 1128 1129/* nv10_fb.c */ 1130extern int nv10_fb_init(struct drm_device *); 1131extern void nv10_fb_takedown(struct drm_device *); 1132extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1133 uint32_t addr, uint32_t size, 1134 uint32_t pitch, uint32_t flags); 1135extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1136extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1137 1138/* nv30_fb.c */ 1139extern int nv30_fb_init(struct drm_device *); 1140extern void nv30_fb_takedown(struct drm_device *); 1141extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1142 uint32_t addr, uint32_t size, 1143 uint32_t pitch, uint32_t flags); 1144extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1145 1146/* nv40_fb.c */ 1147extern int nv40_fb_init(struct drm_device *); 1148extern void nv40_fb_takedown(struct drm_device *); 1149extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1150 1151/* nv50_fb.c */ 1152extern int nv50_fb_init(struct drm_device *); 1153extern void nv50_fb_takedown(struct drm_device *); 1154extern void nv50_fb_vm_trap(struct drm_device *, int display); 1155 1156/* nvc0_fb.c */ 1157extern int nvc0_fb_init(struct drm_device *); 1158extern void nvc0_fb_takedown(struct drm_device *); 1159 1160/* nv04_fifo.c */ 1161extern int nv04_fifo_init(struct drm_device *); 1162extern void nv04_fifo_fini(struct drm_device *); 1163extern void nv04_fifo_disable(struct drm_device *); 1164extern void nv04_fifo_enable(struct drm_device *); 1165extern bool nv04_fifo_reassign(struct drm_device *, bool); 1166extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1167extern int nv04_fifo_channel_id(struct drm_device *); 1168extern int nv04_fifo_create_context(struct nouveau_channel *); 1169extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1170extern int nv04_fifo_load_context(struct nouveau_channel *); 1171extern int nv04_fifo_unload_context(struct drm_device *); 1172extern void nv04_fifo_isr(struct drm_device *); 1173 1174/* nv10_fifo.c */ 1175extern int nv10_fifo_init(struct drm_device *); 1176extern int nv10_fifo_channel_id(struct drm_device *); 1177extern int nv10_fifo_create_context(struct nouveau_channel *); 1178extern int nv10_fifo_load_context(struct nouveau_channel *); 1179extern int nv10_fifo_unload_context(struct drm_device *); 1180 1181/* nv40_fifo.c */ 1182extern int nv40_fifo_init(struct drm_device *); 1183extern int nv40_fifo_create_context(struct nouveau_channel *); 1184extern int nv40_fifo_load_context(struct nouveau_channel *); 1185extern int nv40_fifo_unload_context(struct drm_device *); 1186 1187/* nv50_fifo.c */ 1188extern int nv50_fifo_init(struct drm_device *); 1189extern void nv50_fifo_takedown(struct drm_device *); 1190extern int nv50_fifo_channel_id(struct drm_device *); 1191extern int nv50_fifo_create_context(struct nouveau_channel *); 1192extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1193extern int nv50_fifo_load_context(struct nouveau_channel *); 1194extern int nv50_fifo_unload_context(struct drm_device *); 1195extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1196 1197/* nvc0_fifo.c */ 1198extern int nvc0_fifo_init(struct drm_device *); 1199extern void nvc0_fifo_takedown(struct drm_device *); 1200extern void nvc0_fifo_disable(struct drm_device *); 1201extern void nvc0_fifo_enable(struct drm_device *); 1202extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1203extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1204extern int nvc0_fifo_channel_id(struct drm_device *); 1205extern int nvc0_fifo_create_context(struct nouveau_channel *); 1206extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1207extern int nvc0_fifo_load_context(struct nouveau_channel *); 1208extern int nvc0_fifo_unload_context(struct drm_device *); 1209 1210/* nv04_graph.c */ 1211extern int nv04_graph_create(struct drm_device *); 1212extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1213extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1214 u32 class, u32 mthd, u32 data); 1215extern struct nouveau_bitfield nv04_graph_nsource[]; 1216 1217/* nv10_graph.c */ 1218extern int nv10_graph_create(struct drm_device *); 1219extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1220extern struct nouveau_bitfield nv10_graph_intr[]; 1221extern struct nouveau_bitfield nv10_graph_nstatus[]; 1222 1223/* nv20_graph.c */ 1224extern int nv20_graph_create(struct drm_device *); 1225 1226/* nv40_graph.c */ 1227extern int nv40_graph_create(struct drm_device *); 1228extern void nv40_grctx_init(struct nouveau_grctx *); 1229 1230/* nv50_graph.c */ 1231extern int nv50_graph_create(struct drm_device *); 1232extern int nv50_grctx_init(struct nouveau_grctx *); 1233extern struct nouveau_enum nv50_data_error_names[]; 1234extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1235 1236/* nvc0_graph.c */ 1237extern int nvc0_graph_create(struct drm_device *); 1238extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1239 1240/* nv84_crypt.c */ 1241extern int nv84_crypt_create(struct drm_device *); 1242 1243/* nv98_crypt.c */ 1244extern int nv98_crypt_create(struct drm_device *dev); 1245 1246/* nva3_copy.c */ 1247extern int nva3_copy_create(struct drm_device *dev); 1248 1249/* nvc0_copy.c */ 1250extern int nvc0_copy_create(struct drm_device *dev, int engine); 1251 1252/* nv31_mpeg.c */ 1253extern int nv31_mpeg_create(struct drm_device *dev); 1254 1255/* nv50_mpeg.c */ 1256extern int nv50_mpeg_create(struct drm_device *dev); 1257 1258/* nv84_bsp.c */ 1259/* nv98_bsp.c */ 1260extern int nv84_bsp_create(struct drm_device *dev); 1261 1262/* nv84_vp.c */ 1263/* nv98_vp.c */ 1264extern int nv84_vp_create(struct drm_device *dev); 1265 1266/* nv98_ppp.c */ 1267extern int nv98_ppp_create(struct drm_device *dev); 1268 1269/* nv04_instmem.c */ 1270extern int nv04_instmem_init(struct drm_device *); 1271extern void nv04_instmem_takedown(struct drm_device *); 1272extern int nv04_instmem_suspend(struct drm_device *); 1273extern void nv04_instmem_resume(struct drm_device *); 1274extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1275 u32 size, u32 align); 1276extern void nv04_instmem_put(struct nouveau_gpuobj *); 1277extern int nv04_instmem_map(struct nouveau_gpuobj *); 1278extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1279extern void nv04_instmem_flush(struct drm_device *); 1280 1281/* nv50_instmem.c */ 1282extern int nv50_instmem_init(struct drm_device *); 1283extern void nv50_instmem_takedown(struct drm_device *); 1284extern int nv50_instmem_suspend(struct drm_device *); 1285extern void nv50_instmem_resume(struct drm_device *); 1286extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1287 u32 size, u32 align); 1288extern void nv50_instmem_put(struct nouveau_gpuobj *); 1289extern int nv50_instmem_map(struct nouveau_gpuobj *); 1290extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1291extern void nv50_instmem_flush(struct drm_device *); 1292extern void nv84_instmem_flush(struct drm_device *); 1293 1294/* nvc0_instmem.c */ 1295extern int nvc0_instmem_init(struct drm_device *); 1296extern void nvc0_instmem_takedown(struct drm_device *); 1297extern int nvc0_instmem_suspend(struct drm_device *); 1298extern void nvc0_instmem_resume(struct drm_device *); 1299 1300/* nv04_mc.c */ 1301extern int nv04_mc_init(struct drm_device *); 1302extern void nv04_mc_takedown(struct drm_device *); 1303 1304/* nv40_mc.c */ 1305extern int nv40_mc_init(struct drm_device *); 1306extern void nv40_mc_takedown(struct drm_device *); 1307 1308/* nv50_mc.c */ 1309extern int nv50_mc_init(struct drm_device *); 1310extern void nv50_mc_takedown(struct drm_device *); 1311 1312/* nv04_timer.c */ 1313extern int nv04_timer_init(struct drm_device *); 1314extern uint64_t nv04_timer_read(struct drm_device *); 1315extern void nv04_timer_takedown(struct drm_device *); 1316 1317extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1318 unsigned long arg); 1319 1320/* nv04_dac.c */ 1321extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1322extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1323extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1324extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1325extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1326 1327/* nv04_dfp.c */ 1328extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1329extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1330extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1331 int head, bool dl); 1332extern void nv04_dfp_disable(struct drm_device *dev, int head); 1333extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1334 1335/* nv04_tv.c */ 1336extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1337extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1338 1339/* nv17_tv.c */ 1340extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1341 1342/* nv04_display.c */ 1343extern int nv04_display_early_init(struct drm_device *); 1344extern void nv04_display_late_takedown(struct drm_device *); 1345extern int nv04_display_create(struct drm_device *); 1346extern void nv04_display_destroy(struct drm_device *); 1347extern int nv04_display_init(struct drm_device *); 1348extern void nv04_display_fini(struct drm_device *); 1349 1350/* nvd0_display.c */ 1351extern int nvd0_display_create(struct drm_device *); 1352extern void nvd0_display_destroy(struct drm_device *); 1353extern int nvd0_display_init(struct drm_device *); 1354extern void nvd0_display_fini(struct drm_device *); 1355struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1356void nvd0_display_flip_stop(struct drm_crtc *); 1357int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1358 struct nouveau_channel *, u32 swap_interval); 1359 1360/* nv04_crtc.c */ 1361extern int nv04_crtc_create(struct drm_device *, int index); 1362 1363/* nouveau_bo.c */ 1364extern struct ttm_bo_driver nouveau_bo_driver; 1365extern int nouveau_bo_new(struct drm_device *, int size, int align, 1366 uint32_t flags, uint32_t tile_mode, 1367 uint32_t tile_flags, struct nouveau_bo **); 1368extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1369extern int nouveau_bo_unpin(struct nouveau_bo *); 1370extern int nouveau_bo_map(struct nouveau_bo *); 1371extern void nouveau_bo_unmap(struct nouveau_bo *); 1372extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1373 uint32_t busy); 1374extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1375extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1376extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1377extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1378extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1379extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1380 bool no_wait_reserve, bool no_wait_gpu); 1381 1382extern struct nouveau_vma * 1383nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1384extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1385 struct nouveau_vma *); 1386extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1387 1388/* nouveau_fence.c */ 1389struct nouveau_fence; 1390extern int nouveau_fence_init(struct drm_device *); 1391extern void nouveau_fence_fini(struct drm_device *); 1392extern int nouveau_fence_channel_init(struct nouveau_channel *); 1393extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1394extern void nouveau_fence_update(struct nouveau_channel *); 1395extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1396 bool emit); 1397extern int nouveau_fence_emit(struct nouveau_fence *); 1398extern void nouveau_fence_work(struct nouveau_fence *fence, 1399 void (*work)(void *priv, bool signalled), 1400 void *priv); 1401struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1402 1403extern bool __nouveau_fence_signalled(void *obj, void *arg); 1404extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1405extern int __nouveau_fence_flush(void *obj, void *arg); 1406extern void __nouveau_fence_unref(void **obj); 1407extern void *__nouveau_fence_ref(void *obj); 1408 1409static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1410{ 1411 return __nouveau_fence_signalled(obj, NULL); 1412} 1413static inline int 1414nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1415{ 1416 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1417} 1418extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1419static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1420{ 1421 return __nouveau_fence_flush(obj, NULL); 1422} 1423static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1424{ 1425 __nouveau_fence_unref((void **)obj); 1426} 1427static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1428{ 1429 return __nouveau_fence_ref(obj); 1430} 1431 1432/* nouveau_gem.c */ 1433extern int nouveau_gem_new(struct drm_device *, int size, int align, 1434 uint32_t domain, uint32_t tile_mode, 1435 uint32_t tile_flags, struct nouveau_bo **); 1436extern int nouveau_gem_object_new(struct drm_gem_object *); 1437extern void nouveau_gem_object_del(struct drm_gem_object *); 1438extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1439extern void nouveau_gem_object_close(struct drm_gem_object *, 1440 struct drm_file *); 1441extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1442 struct drm_file *); 1443extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1444 struct drm_file *); 1445extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1446 struct drm_file *); 1447extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1448 struct drm_file *); 1449extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1450 struct drm_file *); 1451 1452/* nouveau_display.c */ 1453int nouveau_display_create(struct drm_device *dev); 1454void nouveau_display_destroy(struct drm_device *dev); 1455int nouveau_display_init(struct drm_device *dev); 1456void nouveau_display_fini(struct drm_device *dev); 1457int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1458void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1459int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1460 struct drm_pending_vblank_event *event); 1461int nouveau_finish_page_flip(struct nouveau_channel *, 1462 struct nouveau_page_flip_state *); 1463int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1464 struct drm_mode_create_dumb *args); 1465int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1466 uint32_t handle, uint64_t *offset); 1467int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1468 uint32_t handle); 1469 1470/* nv10_gpio.c */ 1471int nv10_gpio_init(struct drm_device *dev); 1472void nv10_gpio_fini(struct drm_device *dev); 1473int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1474int nv10_gpio_sense(struct drm_device *dev, int line); 1475void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1476 1477/* nv50_gpio.c */ 1478int nv50_gpio_init(struct drm_device *dev); 1479void nv50_gpio_fini(struct drm_device *dev); 1480int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1481int nv50_gpio_sense(struct drm_device *dev, int line); 1482void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1483int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1484int nvd0_gpio_sense(struct drm_device *dev, int line); 1485 1486/* nv50_calc.c */ 1487int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1488 int *N1, int *M1, int *N2, int *M2, int *P); 1489int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1490 int clk, int *N, int *fN, int *M, int *P); 1491 1492#ifndef ioread32_native 1493#ifdef __BIG_ENDIAN 1494#define ioread16_native ioread16be 1495#define iowrite16_native iowrite16be 1496#define ioread32_native ioread32be 1497#define iowrite32_native iowrite32be 1498#else /* def __BIG_ENDIAN */ 1499#define ioread16_native ioread16 1500#define iowrite16_native iowrite16 1501#define ioread32_native ioread32 1502#define iowrite32_native iowrite32 1503#endif /* def __BIG_ENDIAN else */ 1504#endif /* !ioread32_native */ 1505 1506/* channel control reg access */ 1507static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1508{ 1509 return ioread32_native(chan->user + reg); 1510} 1511 1512static inline void nvchan_wr32(struct nouveau_channel *chan, 1513 unsigned reg, u32 val) 1514{ 1515 iowrite32_native(val, chan->user + reg); 1516} 1517 1518/* register access */ 1519static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1520{ 1521 struct drm_nouveau_private *dev_priv = dev->dev_private; 1522 return ioread32_native(dev_priv->mmio + reg); 1523} 1524 1525static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1526{ 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 iowrite32_native(val, dev_priv->mmio + reg); 1529} 1530 1531static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1532{ 1533 u32 tmp = nv_rd32(dev, reg); 1534 nv_wr32(dev, reg, (tmp & ~mask) | val); 1535 return tmp; 1536} 1537 1538static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1539{ 1540 struct drm_nouveau_private *dev_priv = dev->dev_private; 1541 return ioread8(dev_priv->mmio + reg); 1542} 1543 1544static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 iowrite8(val, dev_priv->mmio + reg); 1548} 1549 1550#define nv_wait(dev, reg, mask, val) \ 1551 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1552#define nv_wait_ne(dev, reg, mask, val) \ 1553 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1554#define nv_wait_cb(dev, func, data) \ 1555 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1556 1557/* PRAMIN access */ 1558static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1559{ 1560 struct drm_nouveau_private *dev_priv = dev->dev_private; 1561 return ioread32_native(dev_priv->ramin + offset); 1562} 1563 1564static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1565{ 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 iowrite32_native(val, dev_priv->ramin + offset); 1568} 1569 1570/* object access */ 1571extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1572extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1573 1574/* 1575 * Logging 1576 * Argument d is (struct drm_device *). 1577 */ 1578#define NV_PRINTK(level, d, fmt, arg...) \ 1579 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1580 pci_name(d->pdev), ##arg) 1581#ifndef NV_DEBUG_NOTRACE 1582#define NV_DEBUG(d, fmt, arg...) do { \ 1583 if (drm_debug & DRM_UT_DRIVER) { \ 1584 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1585 __LINE__, ##arg); \ 1586 } \ 1587} while (0) 1588#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1589 if (drm_debug & DRM_UT_KMS) { \ 1590 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1591 __LINE__, ##arg); \ 1592 } \ 1593} while (0) 1594#else 1595#define NV_DEBUG(d, fmt, arg...) do { \ 1596 if (drm_debug & DRM_UT_DRIVER) \ 1597 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1598} while (0) 1599#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1600 if (drm_debug & DRM_UT_KMS) \ 1601 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1602} while (0) 1603#endif 1604#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1605#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1606#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1607#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1608#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1609#define NV_WARNONCE(d, fmt, arg...) do { \ 1610 static int _warned = 0; \ 1611 if (!_warned) { \ 1612 NV_WARN(d, fmt, ##arg); \ 1613 _warned = 1; \ 1614 } \ 1615} while(0) 1616 1617/* nouveau_reg_debug bitmask */ 1618enum { 1619 NOUVEAU_REG_DEBUG_MC = 0x1, 1620 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1621 NOUVEAU_REG_DEBUG_FB = 0x4, 1622 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1623 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1624 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1625 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1626 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1627 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1628 NOUVEAU_REG_DEBUG_EVO = 0x200, 1629 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1630}; 1631 1632#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1633 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1634 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1635} while (0) 1636 1637static inline bool 1638nv_two_heads(struct drm_device *dev) 1639{ 1640 struct drm_nouveau_private *dev_priv = dev->dev_private; 1641 const int impl = dev->pci_device & 0x0ff0; 1642 1643 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1644 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1645 return true; 1646 1647 return false; 1648} 1649 1650static inline bool 1651nv_gf4_disp_arch(struct drm_device *dev) 1652{ 1653 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1654} 1655 1656static inline bool 1657nv_two_reg_pll(struct drm_device *dev) 1658{ 1659 struct drm_nouveau_private *dev_priv = dev->dev_private; 1660 const int impl = dev->pci_device & 0x0ff0; 1661 1662 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1663 return true; 1664 return false; 1665} 1666 1667static inline bool 1668nv_match_device(struct drm_device *dev, unsigned device, 1669 unsigned sub_vendor, unsigned sub_device) 1670{ 1671 return dev->pdev->device == device && 1672 dev->pdev->subsystem_vendor == sub_vendor && 1673 dev->pdev->subsystem_device == sub_device; 1674} 1675 1676static inline void * 1677nv_engine(struct drm_device *dev, int engine) 1678{ 1679 struct drm_nouveau_private *dev_priv = dev->dev_private; 1680 return (void *)dev_priv->eng[engine]; 1681} 1682 1683/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1684 * helpful to determine a number of other hardware features 1685 */ 1686static inline int 1687nv44_graph_class(struct drm_device *dev) 1688{ 1689 struct drm_nouveau_private *dev_priv = dev->dev_private; 1690 1691 if ((dev_priv->chipset & 0xf0) == 0x60) 1692 return 1; 1693 1694 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1695} 1696 1697/* memory type/access flags, do not match hardware values */ 1698#define NV_MEM_ACCESS_RO 1 1699#define NV_MEM_ACCESS_WO 2 1700#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1701#define NV_MEM_ACCESS_SYS 4 1702#define NV_MEM_ACCESS_VM 8 1703 1704#define NV_MEM_TARGET_VRAM 0 1705#define NV_MEM_TARGET_PCI 1 1706#define NV_MEM_TARGET_PCI_NOSNOOP 2 1707#define NV_MEM_TARGET_VM 3 1708#define NV_MEM_TARGET_GART 4 1709 1710#define NV_MEM_TYPE_VM 0x7f 1711#define NV_MEM_COMP_VM 0x03 1712 1713/* NV_SW object class */ 1714#define NV_SW 0x0000506e 1715#define NV_SW_DMA_SEMAPHORE 0x00000060 1716#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1717#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1718#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1719#define NV_SW_YIELD 0x00000080 1720#define NV_SW_DMA_VBLSEM 0x0000018c 1721#define NV_SW_VBLSEM_OFFSET 0x00000400 1722#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1723#define NV_SW_VBLSEM_RELEASE 0x00000408 1724#define NV_SW_PAGE_FLIP 0x00000500 1725 1726#endif /* __NOUVEAU_DRV_H__ */ 1727