nouveau_drv.h revision a11c3198c9ba38d81e25b65e3908d531feba1372
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58struct nouveau_grctx; 59 60#define MAX_NUM_DCB_ENTRIES 16 61 62#define NOUVEAU_MAX_CHANNEL_NR 128 63#define NOUVEAU_MAX_TILE_NR 15 64 65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 66#define NV50_VM_BLOCK (512*1024*1024ULL) 67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 68 69struct nouveau_vram { 70 struct drm_device *dev; 71 72 struct list_head regions; 73 u32 memtype; 74 u64 offset; 75 u64 size; 76}; 77 78struct nouveau_tile_reg { 79 bool used; 80 uint32_t addr; 81 uint32_t limit; 82 uint32_t pitch; 83 uint32_t zcomp; 84 struct drm_mm_node *tag_mem; 85 struct nouveau_fence *fence; 86}; 87 88struct nouveau_bo { 89 struct ttm_buffer_object bo; 90 struct ttm_placement placement; 91 u32 placements[3]; 92 u32 busy_placements[3]; 93 struct ttm_bo_kmap_obj kmap; 94 struct list_head head; 95 96 /* protected by ttm_bo_reserve() */ 97 struct drm_file *reserved_by; 98 struct list_head entry; 99 int pbbo_index; 100 bool validate_mapped; 101 102 struct nouveau_channel *channel; 103 104 bool mappable; 105 bool no_vm; 106 107 uint32_t tile_mode; 108 uint32_t tile_flags; 109 struct nouveau_tile_reg *tile; 110 111 struct drm_gem_object *gem; 112 int pin_refcnt; 113}; 114 115#define nouveau_bo_tile_layout(nvbo) \ 116 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 117 118static inline struct nouveau_bo * 119nouveau_bo(struct ttm_buffer_object *bo) 120{ 121 return container_of(bo, struct nouveau_bo, bo); 122} 123 124static inline struct nouveau_bo * 125nouveau_gem_object(struct drm_gem_object *gem) 126{ 127 return gem ? gem->driver_private : NULL; 128} 129 130/* TODO: submit equivalent to TTM generic API upstream? */ 131static inline void __iomem * 132nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 133{ 134 bool is_iomem; 135 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 136 &nvbo->kmap, &is_iomem); 137 WARN_ON_ONCE(ioptr && !is_iomem); 138 return ioptr; 139} 140 141enum nouveau_flags { 142 NV_NFORCE = 0x10000000, 143 NV_NFORCE2 = 0x20000000 144}; 145 146#define NVOBJ_ENGINE_SW 0 147#define NVOBJ_ENGINE_GR 1 148#define NVOBJ_ENGINE_PPP 2 149#define NVOBJ_ENGINE_COPY 3 150#define NVOBJ_ENGINE_VP 4 151#define NVOBJ_ENGINE_CRYPT 5 152#define NVOBJ_ENGINE_BSP 6 153#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 154#define NVOBJ_ENGINE_INT 0xdeadbeef 155 156#define NVOBJ_FLAG_DONT_MAP (1 << 0) 157#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 158#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 159 160#define NVOBJ_CINST_GLOBAL 0xdeadbeef 161 162struct nouveau_gpuobj { 163 struct drm_device *dev; 164 struct kref refcount; 165 struct list_head list; 166 167 void *node; 168 u32 *suspend; 169 170 uint32_t flags; 171 172 u32 size; 173 u32 pinst; 174 u32 cinst; 175 u64 vinst; 176 177 uint32_t engine; 178 uint32_t class; 179 180 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 181 void *priv; 182}; 183 184struct nouveau_page_flip_state { 185 struct list_head head; 186 struct drm_pending_vblank_event *event; 187 int crtc, bpp, pitch, x, y; 188 uint64_t offset; 189}; 190 191enum nouveau_channel_mutex_class { 192 NOUVEAU_UCHANNEL_MUTEX, 193 NOUVEAU_KCHANNEL_MUTEX 194}; 195 196struct nouveau_channel { 197 struct drm_device *dev; 198 int id; 199 200 /* references to the channel data structure */ 201 struct kref ref; 202 /* users of the hardware channel resources, the hardware 203 * context will be kicked off when it reaches zero. */ 204 atomic_t users; 205 struct mutex mutex; 206 207 /* owner of this fifo */ 208 struct drm_file *file_priv; 209 /* mapping of the fifo itself */ 210 struct drm_local_map *map; 211 212 /* mapping of the regs controling the fifo */ 213 void __iomem *user; 214 uint32_t user_get; 215 uint32_t user_put; 216 217 /* Fencing */ 218 struct { 219 /* lock protects the pending list only */ 220 spinlock_t lock; 221 struct list_head pending; 222 uint32_t sequence; 223 uint32_t sequence_ack; 224 atomic_t last_sequence_irq; 225 } fence; 226 227 /* DMA push buffer */ 228 struct nouveau_gpuobj *pushbuf; 229 struct nouveau_bo *pushbuf_bo; 230 uint32_t pushbuf_base; 231 232 /* Notifier memory */ 233 struct nouveau_bo *notifier_bo; 234 struct drm_mm notifier_heap; 235 236 /* PFIFO context */ 237 struct nouveau_gpuobj *ramfc; 238 struct nouveau_gpuobj *cache; 239 240 /* PGRAPH context */ 241 /* XXX may be merge 2 pointers as private data ??? */ 242 struct nouveau_gpuobj *ramin_grctx; 243 struct nouveau_gpuobj *crypt_ctx; 244 void *pgraph_ctx; 245 246 /* NV50 VM */ 247 struct nouveau_gpuobj *vm_pd; 248 struct nouveau_gpuobj *vm_gart_pt; 249 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 250 251 /* Objects */ 252 struct nouveau_gpuobj *ramin; /* Private instmem */ 253 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 254 struct nouveau_ramht *ramht; /* Hash table */ 255 256 /* GPU object info for stuff used in-kernel (mm_enabled) */ 257 uint32_t m2mf_ntfy; 258 uint32_t vram_handle; 259 uint32_t gart_handle; 260 bool accel_done; 261 262 /* Push buffer state (only for drm's channel on !mm_enabled) */ 263 struct { 264 int max; 265 int free; 266 int cur; 267 int put; 268 /* access via pushbuf_bo */ 269 270 int ib_base; 271 int ib_max; 272 int ib_free; 273 int ib_put; 274 } dma; 275 276 uint32_t sw_subchannel[8]; 277 278 struct { 279 struct nouveau_gpuobj *vblsem; 280 uint32_t vblsem_head; 281 uint32_t vblsem_offset; 282 uint32_t vblsem_rval; 283 struct list_head vbl_wait; 284 struct list_head flip; 285 } nvsw; 286 287 struct { 288 bool active; 289 char name[32]; 290 struct drm_info_list info; 291 } debugfs; 292}; 293 294struct nouveau_instmem_engine { 295 void *priv; 296 297 int (*init)(struct drm_device *dev); 298 void (*takedown)(struct drm_device *dev); 299 int (*suspend)(struct drm_device *dev); 300 void (*resume)(struct drm_device *dev); 301 302 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 303 void (*put)(struct nouveau_gpuobj *); 304 int (*map)(struct nouveau_gpuobj *); 305 void (*unmap)(struct nouveau_gpuobj *); 306 307 void (*flush)(struct drm_device *); 308}; 309 310struct nouveau_mc_engine { 311 int (*init)(struct drm_device *dev); 312 void (*takedown)(struct drm_device *dev); 313}; 314 315struct nouveau_timer_engine { 316 int (*init)(struct drm_device *dev); 317 void (*takedown)(struct drm_device *dev); 318 uint64_t (*read)(struct drm_device *dev); 319}; 320 321struct nouveau_fb_engine { 322 int num_tiles; 323 struct drm_mm tag_heap; 324 void *priv; 325 326 int (*init)(struct drm_device *dev); 327 void (*takedown)(struct drm_device *dev); 328 329 void (*init_tile_region)(struct drm_device *dev, int i, 330 uint32_t addr, uint32_t size, 331 uint32_t pitch, uint32_t flags); 332 void (*set_tile_region)(struct drm_device *dev, int i); 333 void (*free_tile_region)(struct drm_device *dev, int i); 334}; 335 336struct nouveau_fifo_engine { 337 int channels; 338 339 struct nouveau_gpuobj *playlist[2]; 340 int cur_playlist; 341 342 int (*init)(struct drm_device *); 343 void (*takedown)(struct drm_device *); 344 345 void (*disable)(struct drm_device *); 346 void (*enable)(struct drm_device *); 347 bool (*reassign)(struct drm_device *, bool enable); 348 bool (*cache_pull)(struct drm_device *dev, bool enable); 349 350 int (*channel_id)(struct drm_device *); 351 352 int (*create_context)(struct nouveau_channel *); 353 void (*destroy_context)(struct nouveau_channel *); 354 int (*load_context)(struct nouveau_channel *); 355 int (*unload_context)(struct drm_device *); 356 void (*tlb_flush)(struct drm_device *dev); 357}; 358 359struct nouveau_pgraph_engine { 360 bool accel_blocked; 361 bool registered; 362 int grctx_size; 363 364 /* NV2x/NV3x context table (0x400780) */ 365 struct nouveau_gpuobj *ctx_table; 366 367 int (*init)(struct drm_device *); 368 void (*takedown)(struct drm_device *); 369 370 void (*fifo_access)(struct drm_device *, bool); 371 372 struct nouveau_channel *(*channel)(struct drm_device *); 373 int (*create_context)(struct nouveau_channel *); 374 void (*destroy_context)(struct nouveau_channel *); 375 int (*load_context)(struct nouveau_channel *); 376 int (*unload_context)(struct drm_device *); 377 void (*tlb_flush)(struct drm_device *dev); 378 379 void (*set_tile_region)(struct drm_device *dev, int i); 380}; 381 382struct nouveau_display_engine { 383 int (*early_init)(struct drm_device *); 384 void (*late_takedown)(struct drm_device *); 385 int (*create)(struct drm_device *); 386 int (*init)(struct drm_device *); 387 void (*destroy)(struct drm_device *); 388}; 389 390struct nouveau_gpio_engine { 391 void *priv; 392 393 int (*init)(struct drm_device *); 394 void (*takedown)(struct drm_device *); 395 396 int (*get)(struct drm_device *, enum dcb_gpio_tag); 397 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 398 399 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 400 void (*)(void *, int), void *); 401 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 402 void (*)(void *, int), void *); 403 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 404}; 405 406struct nouveau_pm_voltage_level { 407 u8 voltage; 408 u8 vid; 409}; 410 411struct nouveau_pm_voltage { 412 bool supported; 413 u8 vid_mask; 414 415 struct nouveau_pm_voltage_level *level; 416 int nr_level; 417}; 418 419#define NOUVEAU_PM_MAX_LEVEL 8 420struct nouveau_pm_level { 421 struct device_attribute dev_attr; 422 char name[32]; 423 int id; 424 425 u32 core; 426 u32 memory; 427 u32 shader; 428 u32 unk05; 429 430 u8 voltage; 431 u8 fanspeed; 432 433 u16 memscript; 434}; 435 436struct nouveau_pm_temp_sensor_constants { 437 u16 offset_constant; 438 s16 offset_mult; 439 u16 offset_div; 440 u16 slope_mult; 441 u16 slope_div; 442}; 443 444struct nouveau_pm_threshold_temp { 445 s16 critical; 446 s16 down_clock; 447 s16 fan_boost; 448}; 449 450struct nouveau_pm_memtiming { 451 u32 reg_100220; 452 u32 reg_100224; 453 u32 reg_100228; 454 u32 reg_10022c; 455 u32 reg_100230; 456 u32 reg_100234; 457 u32 reg_100238; 458 u32 reg_10023c; 459}; 460 461struct nouveau_pm_memtimings { 462 bool supported; 463 struct nouveau_pm_memtiming *timing; 464 int nr_timing; 465}; 466 467struct nouveau_pm_engine { 468 struct nouveau_pm_voltage voltage; 469 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 470 int nr_perflvl; 471 struct nouveau_pm_memtimings memtimings; 472 struct nouveau_pm_temp_sensor_constants sensor_constants; 473 struct nouveau_pm_threshold_temp threshold_temp; 474 475 struct nouveau_pm_level boot; 476 struct nouveau_pm_level *cur; 477 478 struct device *hwmon; 479 struct notifier_block acpi_nb; 480 481 int (*clock_get)(struct drm_device *, u32 id); 482 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 483 u32 id, int khz); 484 void (*clock_set)(struct drm_device *, void *); 485 int (*voltage_get)(struct drm_device *); 486 int (*voltage_set)(struct drm_device *, int voltage); 487 int (*fanspeed_get)(struct drm_device *); 488 int (*fanspeed_set)(struct drm_device *, int fanspeed); 489 int (*temp_get)(struct drm_device *); 490}; 491 492struct nouveau_crypt_engine { 493 bool registered; 494 495 int (*init)(struct drm_device *); 496 void (*takedown)(struct drm_device *); 497 int (*create_context)(struct nouveau_channel *); 498 void (*destroy_context)(struct nouveau_channel *); 499 void (*tlb_flush)(struct drm_device *dev); 500}; 501 502struct nouveau_engine { 503 struct nouveau_instmem_engine instmem; 504 struct nouveau_mc_engine mc; 505 struct nouveau_timer_engine timer; 506 struct nouveau_fb_engine fb; 507 struct nouveau_pgraph_engine graph; 508 struct nouveau_fifo_engine fifo; 509 struct nouveau_display_engine display; 510 struct nouveau_gpio_engine gpio; 511 struct nouveau_pm_engine pm; 512 struct nouveau_crypt_engine crypt; 513}; 514 515struct nouveau_pll_vals { 516 union { 517 struct { 518#ifdef __BIG_ENDIAN 519 uint8_t N1, M1, N2, M2; 520#else 521 uint8_t M1, N1, M2, N2; 522#endif 523 }; 524 struct { 525 uint16_t NM1, NM2; 526 } __attribute__((packed)); 527 }; 528 int log2P; 529 530 int refclk; 531}; 532 533enum nv04_fp_display_regs { 534 FP_DISPLAY_END, 535 FP_TOTAL, 536 FP_CRTC, 537 FP_SYNC_START, 538 FP_SYNC_END, 539 FP_VALID_START, 540 FP_VALID_END 541}; 542 543struct nv04_crtc_reg { 544 unsigned char MiscOutReg; 545 uint8_t CRTC[0xa0]; 546 uint8_t CR58[0x10]; 547 uint8_t Sequencer[5]; 548 uint8_t Graphics[9]; 549 uint8_t Attribute[21]; 550 unsigned char DAC[768]; 551 552 /* PCRTC regs */ 553 uint32_t fb_start; 554 uint32_t crtc_cfg; 555 uint32_t cursor_cfg; 556 uint32_t gpio_ext; 557 uint32_t crtc_830; 558 uint32_t crtc_834; 559 uint32_t crtc_850; 560 uint32_t crtc_eng_ctrl; 561 562 /* PRAMDAC regs */ 563 uint32_t nv10_cursync; 564 struct nouveau_pll_vals pllvals; 565 uint32_t ramdac_gen_ctrl; 566 uint32_t ramdac_630; 567 uint32_t ramdac_634; 568 uint32_t tv_setup; 569 uint32_t tv_vtotal; 570 uint32_t tv_vskew; 571 uint32_t tv_vsync_delay; 572 uint32_t tv_htotal; 573 uint32_t tv_hskew; 574 uint32_t tv_hsync_delay; 575 uint32_t tv_hsync_delay2; 576 uint32_t fp_horiz_regs[7]; 577 uint32_t fp_vert_regs[7]; 578 uint32_t dither; 579 uint32_t fp_control; 580 uint32_t dither_regs[6]; 581 uint32_t fp_debug_0; 582 uint32_t fp_debug_1; 583 uint32_t fp_debug_2; 584 uint32_t fp_margin_color; 585 uint32_t ramdac_8c0; 586 uint32_t ramdac_a20; 587 uint32_t ramdac_a24; 588 uint32_t ramdac_a34; 589 uint32_t ctv_regs[38]; 590}; 591 592struct nv04_output_reg { 593 uint32_t output; 594 int head; 595}; 596 597struct nv04_mode_state { 598 struct nv04_crtc_reg crtc_reg[2]; 599 uint32_t pllsel; 600 uint32_t sel_clk; 601}; 602 603enum nouveau_card_type { 604 NV_04 = 0x00, 605 NV_10 = 0x10, 606 NV_20 = 0x20, 607 NV_30 = 0x30, 608 NV_40 = 0x40, 609 NV_50 = 0x50, 610 NV_C0 = 0xc0, 611}; 612 613struct drm_nouveau_private { 614 struct drm_device *dev; 615 616 /* the card type, takes NV_* as values */ 617 enum nouveau_card_type card_type; 618 /* exact chipset, derived from NV_PMC_BOOT_0 */ 619 int chipset; 620 int flags; 621 622 void __iomem *mmio; 623 624 spinlock_t ramin_lock; 625 void __iomem *ramin; 626 u32 ramin_size; 627 u32 ramin_base; 628 bool ramin_available; 629 struct drm_mm ramin_heap; 630 struct list_head gpuobj_list; 631 struct list_head classes; 632 633 struct nouveau_bo *vga_ram; 634 635 /* interrupt handling */ 636 void (*irq_handler[32])(struct drm_device *); 637 bool msi_enabled; 638 struct workqueue_struct *wq; 639 struct work_struct irq_work; 640 641 struct list_head vbl_waiting; 642 643 struct { 644 struct drm_global_reference mem_global_ref; 645 struct ttm_bo_global_ref bo_global_ref; 646 struct ttm_bo_device bdev; 647 atomic_t validate_sequence; 648 } ttm; 649 650 struct { 651 spinlock_t lock; 652 struct drm_mm heap; 653 struct nouveau_bo *bo; 654 } fence; 655 656 struct { 657 spinlock_t lock; 658 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 659 } channels; 660 661 struct nouveau_engine engine; 662 struct nouveau_channel *channel; 663 664 /* For PFIFO and PGRAPH. */ 665 spinlock_t context_switch_lock; 666 667 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 668 struct nouveau_ramht *ramht; 669 struct nouveau_gpuobj *ramfc; 670 struct nouveau_gpuobj *ramro; 671 672 uint32_t ramin_rsvd_vram; 673 674 struct { 675 enum { 676 NOUVEAU_GART_NONE = 0, 677 NOUVEAU_GART_AGP, 678 NOUVEAU_GART_SGDMA 679 } type; 680 uint64_t aper_base; 681 uint64_t aper_size; 682 uint64_t aper_free; 683 684 struct nouveau_gpuobj *sg_ctxdma; 685 } gart_info; 686 687 /* nv10-nv40 tiling regions */ 688 struct { 689 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 690 spinlock_t lock; 691 } tile; 692 693 /* VRAM/fb configuration */ 694 uint64_t vram_size; 695 uint64_t vram_sys_base; 696 u32 vram_rblock_size; 697 698 uint64_t fb_phys; 699 uint64_t fb_available_size; 700 uint64_t fb_mappable_pages; 701 uint64_t fb_aper_free; 702 int fb_mtrr; 703 704 /* G8x/G9x virtual address space */ 705 uint64_t vm_gart_base; 706 uint64_t vm_gart_size; 707 uint64_t vm_vram_base; 708 uint64_t vm_vram_size; 709 uint64_t vm_end; 710 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 711 int vm_vram_pt_nr; 712 713 struct nvbios vbios; 714 715 struct nv04_mode_state mode_reg; 716 struct nv04_mode_state saved_reg; 717 uint32_t saved_vga_font[4][16384]; 718 uint32_t crtc_owner; 719 uint32_t dac_users[4]; 720 721 struct nouveau_suspend_resume { 722 uint32_t *ramin_copy; 723 } susres; 724 725 struct backlight_device *backlight; 726 727 struct nouveau_channel *evo; 728 u32 evo_alloc; 729 struct { 730 struct dcb_entry *dcb; 731 u16 script; 732 u32 pclk; 733 } evo_irq; 734 735 struct { 736 struct dentry *channel_root; 737 } debugfs; 738 739 struct nouveau_fbdev *nfbdev; 740 struct apertures_struct *apertures; 741}; 742 743static inline struct drm_nouveau_private * 744nouveau_private(struct drm_device *dev) 745{ 746 return dev->dev_private; 747} 748 749static inline struct drm_nouveau_private * 750nouveau_bdev(struct ttm_bo_device *bd) 751{ 752 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 753} 754 755static inline int 756nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 757{ 758 struct nouveau_bo *prev; 759 760 if (!pnvbo) 761 return -EINVAL; 762 prev = *pnvbo; 763 764 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 765 if (prev) { 766 struct ttm_buffer_object *bo = &prev->bo; 767 768 ttm_bo_unref(&bo); 769 } 770 771 return 0; 772} 773 774/* nouveau_drv.c */ 775extern int nouveau_agpmode; 776extern int nouveau_duallink; 777extern int nouveau_uscript_lvds; 778extern int nouveau_uscript_tmds; 779extern int nouveau_vram_pushbuf; 780extern int nouveau_vram_notify; 781extern int nouveau_fbpercrtc; 782extern int nouveau_tv_disable; 783extern char *nouveau_tv_norm; 784extern int nouveau_reg_debug; 785extern char *nouveau_vbios; 786extern int nouveau_ignorelid; 787extern int nouveau_nofbaccel; 788extern int nouveau_noaccel; 789extern int nouveau_force_post; 790extern int nouveau_override_conntype; 791extern char *nouveau_perflvl; 792extern int nouveau_perflvl_wr; 793extern int nouveau_msi; 794 795extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 796extern int nouveau_pci_resume(struct pci_dev *pdev); 797 798/* nouveau_state.c */ 799extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 800extern int nouveau_load(struct drm_device *, unsigned long flags); 801extern int nouveau_firstopen(struct drm_device *); 802extern void nouveau_lastclose(struct drm_device *); 803extern int nouveau_unload(struct drm_device *); 804extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 805 struct drm_file *); 806extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 807 struct drm_file *); 808extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 809 uint32_t reg, uint32_t mask, uint32_t val); 810extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 811 uint32_t reg, uint32_t mask, uint32_t val); 812extern bool nouveau_wait_for_idle(struct drm_device *); 813extern int nouveau_card_init(struct drm_device *); 814 815/* nouveau_mem.c */ 816extern int nouveau_mem_vram_init(struct drm_device *); 817extern void nouveau_mem_vram_fini(struct drm_device *); 818extern int nouveau_mem_gart_init(struct drm_device *); 819extern void nouveau_mem_gart_fini(struct drm_device *); 820extern int nouveau_mem_init_agp(struct drm_device *); 821extern int nouveau_mem_reset_agp(struct drm_device *); 822extern void nouveau_mem_close(struct drm_device *); 823extern struct nouveau_tile_reg *nv10_mem_set_tiling( 824 struct drm_device *dev, uint32_t addr, uint32_t size, 825 uint32_t pitch, uint32_t flags); 826extern void nv10_mem_put_tile_region(struct drm_device *dev, 827 struct nouveau_tile_reg *tile, 828 struct nouveau_fence *fence); 829extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 830 uint32_t size, uint32_t flags, 831 uint64_t phys); 832extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 833 uint32_t size); 834extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 835 836/* nouveau_notifier.c */ 837extern int nouveau_notifier_init_channel(struct nouveau_channel *); 838extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 839extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 840 int cout, uint32_t *offset); 841extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 842extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 843 struct drm_file *); 844extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 845 struct drm_file *); 846 847/* nouveau_channel.c */ 848extern struct drm_ioctl_desc nouveau_ioctls[]; 849extern int nouveau_max_ioctl; 850extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 851extern int nouveau_channel_alloc(struct drm_device *dev, 852 struct nouveau_channel **chan, 853 struct drm_file *file_priv, 854 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 855extern struct nouveau_channel * 856nouveau_channel_get_unlocked(struct nouveau_channel *); 857extern struct nouveau_channel * 858nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 859extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 860extern void nouveau_channel_put(struct nouveau_channel **); 861extern void nouveau_channel_ref(struct nouveau_channel *chan, 862 struct nouveau_channel **pchan); 863extern void nouveau_channel_idle(struct nouveau_channel *chan); 864 865/* nouveau_object.c */ 866#define NVOBJ_CLASS(d,c,e) do { \ 867 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 868 if (ret) \ 869 return ret; \ 870} while(0) 871 872#define NVOBJ_MTHD(d,c,m,e) do { \ 873 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 874 if (ret) \ 875 return ret; \ 876} while(0) 877 878extern int nouveau_gpuobj_early_init(struct drm_device *); 879extern int nouveau_gpuobj_init(struct drm_device *); 880extern void nouveau_gpuobj_takedown(struct drm_device *); 881extern int nouveau_gpuobj_suspend(struct drm_device *dev); 882extern void nouveau_gpuobj_resume(struct drm_device *dev); 883extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 884extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 885 int (*exec)(struct nouveau_channel *, 886 u32 class, u32 mthd, u32 data)); 887extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 888extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 889extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 890 uint32_t vram_h, uint32_t tt_h); 891extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 892extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 893 uint32_t size, int align, uint32_t flags, 894 struct nouveau_gpuobj **); 895extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 896 struct nouveau_gpuobj **); 897extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 898 u32 size, u32 flags, 899 struct nouveau_gpuobj **); 900extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 901 uint64_t offset, uint64_t size, int access, 902 int target, struct nouveau_gpuobj **); 903extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 904extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 905 u64 size, int target, int access, u32 type, 906 u32 comp, struct nouveau_gpuobj **pobj); 907extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 908 int class, u64 base, u64 size, int target, 909 int access, u32 type, u32 comp); 910extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 911 struct drm_file *); 912extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 913 struct drm_file *); 914 915/* nouveau_irq.c */ 916extern int nouveau_irq_init(struct drm_device *); 917extern void nouveau_irq_fini(struct drm_device *); 918extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 919extern void nouveau_irq_register(struct drm_device *, int status_bit, 920 void (*)(struct drm_device *)); 921extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 922extern void nouveau_irq_preinstall(struct drm_device *); 923extern int nouveau_irq_postinstall(struct drm_device *); 924extern void nouveau_irq_uninstall(struct drm_device *); 925 926/* nouveau_sgdma.c */ 927extern int nouveau_sgdma_init(struct drm_device *); 928extern void nouveau_sgdma_takedown(struct drm_device *); 929extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 930 uint32_t *page); 931extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 932 933/* nouveau_debugfs.c */ 934#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 935extern int nouveau_debugfs_init(struct drm_minor *); 936extern void nouveau_debugfs_takedown(struct drm_minor *); 937extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 938extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 939#else 940static inline int 941nouveau_debugfs_init(struct drm_minor *minor) 942{ 943 return 0; 944} 945 946static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 947{ 948} 949 950static inline int 951nouveau_debugfs_channel_init(struct nouveau_channel *chan) 952{ 953 return 0; 954} 955 956static inline void 957nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 958{ 959} 960#endif 961 962/* nouveau_dma.c */ 963extern void nouveau_dma_pre_init(struct nouveau_channel *); 964extern int nouveau_dma_init(struct nouveau_channel *); 965extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 966 967/* nouveau_acpi.c */ 968#define ROM_BIOS_PAGE 4096 969#if defined(CONFIG_ACPI) 970void nouveau_register_dsm_handler(void); 971void nouveau_unregister_dsm_handler(void); 972int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 973bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 974int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 975#else 976static inline void nouveau_register_dsm_handler(void) {} 977static inline void nouveau_unregister_dsm_handler(void) {} 978static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 979static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 980static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 981#endif 982 983/* nouveau_backlight.c */ 984#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 985extern int nouveau_backlight_init(struct drm_device *); 986extern void nouveau_backlight_exit(struct drm_device *); 987#else 988static inline int nouveau_backlight_init(struct drm_device *dev) 989{ 990 return 0; 991} 992 993static inline void nouveau_backlight_exit(struct drm_device *dev) { } 994#endif 995 996/* nouveau_bios.c */ 997extern int nouveau_bios_init(struct drm_device *); 998extern void nouveau_bios_takedown(struct drm_device *dev); 999extern int nouveau_run_vbios_init(struct drm_device *); 1000extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1001 struct dcb_entry *); 1002extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1003 enum dcb_gpio_tag); 1004extern struct dcb_connector_table_entry * 1005nouveau_bios_connector_entry(struct drm_device *, int index); 1006extern u32 get_pll_register(struct drm_device *, enum pll_types); 1007extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1008 struct pll_lims *); 1009extern int nouveau_bios_run_display_table(struct drm_device *, 1010 struct dcb_entry *, 1011 uint32_t script, int pxclk); 1012extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1013 int *length); 1014extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1015extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1016extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1017 bool *dl, bool *if_is_24bit); 1018extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1019 int head, int pxclk); 1020extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1021 enum LVDS_script, int pxclk); 1022 1023/* nouveau_ttm.c */ 1024int nouveau_ttm_global_init(struct drm_nouveau_private *); 1025void nouveau_ttm_global_release(struct drm_nouveau_private *); 1026int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1027 1028/* nouveau_dp.c */ 1029int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1030 uint8_t *data, int data_nr); 1031bool nouveau_dp_detect(struct drm_encoder *); 1032bool nouveau_dp_link_train(struct drm_encoder *); 1033 1034/* nv04_fb.c */ 1035extern int nv04_fb_init(struct drm_device *); 1036extern void nv04_fb_takedown(struct drm_device *); 1037 1038/* nv10_fb.c */ 1039extern int nv10_fb_init(struct drm_device *); 1040extern void nv10_fb_takedown(struct drm_device *); 1041extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1042 uint32_t addr, uint32_t size, 1043 uint32_t pitch, uint32_t flags); 1044extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1045extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1046 1047/* nv30_fb.c */ 1048extern int nv30_fb_init(struct drm_device *); 1049extern void nv30_fb_takedown(struct drm_device *); 1050extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1051 uint32_t addr, uint32_t size, 1052 uint32_t pitch, uint32_t flags); 1053extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1054 1055/* nv40_fb.c */ 1056extern int nv40_fb_init(struct drm_device *); 1057extern void nv40_fb_takedown(struct drm_device *); 1058extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1059 1060/* nv50_fb.c */ 1061extern int nv50_fb_init(struct drm_device *); 1062extern void nv50_fb_takedown(struct drm_device *); 1063extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1064 1065/* nvc0_fb.c */ 1066extern int nvc0_fb_init(struct drm_device *); 1067extern void nvc0_fb_takedown(struct drm_device *); 1068 1069/* nv04_fifo.c */ 1070extern int nv04_fifo_init(struct drm_device *); 1071extern void nv04_fifo_fini(struct drm_device *); 1072extern void nv04_fifo_disable(struct drm_device *); 1073extern void nv04_fifo_enable(struct drm_device *); 1074extern bool nv04_fifo_reassign(struct drm_device *, bool); 1075extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1076extern int nv04_fifo_channel_id(struct drm_device *); 1077extern int nv04_fifo_create_context(struct nouveau_channel *); 1078extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1079extern int nv04_fifo_load_context(struct nouveau_channel *); 1080extern int nv04_fifo_unload_context(struct drm_device *); 1081extern void nv04_fifo_isr(struct drm_device *); 1082 1083/* nv10_fifo.c */ 1084extern int nv10_fifo_init(struct drm_device *); 1085extern int nv10_fifo_channel_id(struct drm_device *); 1086extern int nv10_fifo_create_context(struct nouveau_channel *); 1087extern int nv10_fifo_load_context(struct nouveau_channel *); 1088extern int nv10_fifo_unload_context(struct drm_device *); 1089 1090/* nv40_fifo.c */ 1091extern int nv40_fifo_init(struct drm_device *); 1092extern int nv40_fifo_create_context(struct nouveau_channel *); 1093extern int nv40_fifo_load_context(struct nouveau_channel *); 1094extern int nv40_fifo_unload_context(struct drm_device *); 1095 1096/* nv50_fifo.c */ 1097extern int nv50_fifo_init(struct drm_device *); 1098extern void nv50_fifo_takedown(struct drm_device *); 1099extern int nv50_fifo_channel_id(struct drm_device *); 1100extern int nv50_fifo_create_context(struct nouveau_channel *); 1101extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1102extern int nv50_fifo_load_context(struct nouveau_channel *); 1103extern int nv50_fifo_unload_context(struct drm_device *); 1104extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1105 1106/* nvc0_fifo.c */ 1107extern int nvc0_fifo_init(struct drm_device *); 1108extern void nvc0_fifo_takedown(struct drm_device *); 1109extern void nvc0_fifo_disable(struct drm_device *); 1110extern void nvc0_fifo_enable(struct drm_device *); 1111extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1112extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1113extern int nvc0_fifo_channel_id(struct drm_device *); 1114extern int nvc0_fifo_create_context(struct nouveau_channel *); 1115extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1116extern int nvc0_fifo_load_context(struct nouveau_channel *); 1117extern int nvc0_fifo_unload_context(struct drm_device *); 1118 1119/* nv04_graph.c */ 1120extern int nv04_graph_init(struct drm_device *); 1121extern void nv04_graph_takedown(struct drm_device *); 1122extern void nv04_graph_fifo_access(struct drm_device *, bool); 1123extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1124extern int nv04_graph_create_context(struct nouveau_channel *); 1125extern void nv04_graph_destroy_context(struct nouveau_channel *); 1126extern int nv04_graph_load_context(struct nouveau_channel *); 1127extern int nv04_graph_unload_context(struct drm_device *); 1128extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1129 u32 class, u32 mthd, u32 data); 1130extern struct nouveau_bitfield nv04_graph_nsource[]; 1131 1132/* nv10_graph.c */ 1133extern int nv10_graph_init(struct drm_device *); 1134extern void nv10_graph_takedown(struct drm_device *); 1135extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1136extern int nv10_graph_create_context(struct nouveau_channel *); 1137extern void nv10_graph_destroy_context(struct nouveau_channel *); 1138extern int nv10_graph_load_context(struct nouveau_channel *); 1139extern int nv10_graph_unload_context(struct drm_device *); 1140extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1141extern struct nouveau_bitfield nv10_graph_intr[]; 1142extern struct nouveau_bitfield nv10_graph_nstatus[]; 1143 1144/* nv20_graph.c */ 1145extern int nv20_graph_create_context(struct nouveau_channel *); 1146extern void nv20_graph_destroy_context(struct nouveau_channel *); 1147extern int nv20_graph_load_context(struct nouveau_channel *); 1148extern int nv20_graph_unload_context(struct drm_device *); 1149extern int nv20_graph_init(struct drm_device *); 1150extern void nv20_graph_takedown(struct drm_device *); 1151extern int nv30_graph_init(struct drm_device *); 1152extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1153 1154/* nv40_graph.c */ 1155extern int nv40_graph_init(struct drm_device *); 1156extern void nv40_graph_takedown(struct drm_device *); 1157extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1158extern int nv40_graph_create_context(struct nouveau_channel *); 1159extern void nv40_graph_destroy_context(struct nouveau_channel *); 1160extern int nv40_graph_load_context(struct nouveau_channel *); 1161extern int nv40_graph_unload_context(struct drm_device *); 1162extern void nv40_grctx_init(struct nouveau_grctx *); 1163extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1164 1165/* nv50_graph.c */ 1166extern int nv50_graph_init(struct drm_device *); 1167extern void nv50_graph_takedown(struct drm_device *); 1168extern void nv50_graph_fifo_access(struct drm_device *, bool); 1169extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1170extern int nv50_graph_create_context(struct nouveau_channel *); 1171extern void nv50_graph_destroy_context(struct nouveau_channel *); 1172extern int nv50_graph_load_context(struct nouveau_channel *); 1173extern int nv50_graph_unload_context(struct drm_device *); 1174extern int nv50_grctx_init(struct nouveau_grctx *); 1175extern void nv50_graph_tlb_flush(struct drm_device *dev); 1176extern void nv86_graph_tlb_flush(struct drm_device *dev); 1177 1178/* nvc0_graph.c */ 1179extern int nvc0_graph_init(struct drm_device *); 1180extern void nvc0_graph_takedown(struct drm_device *); 1181extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1182extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1183extern int nvc0_graph_create_context(struct nouveau_channel *); 1184extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1185extern int nvc0_graph_load_context(struct nouveau_channel *); 1186extern int nvc0_graph_unload_context(struct drm_device *); 1187 1188/* nv84_crypt.c */ 1189extern int nv84_crypt_init(struct drm_device *dev); 1190extern void nv84_crypt_fini(struct drm_device *dev); 1191extern int nv84_crypt_create_context(struct nouveau_channel *); 1192extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1193extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1194 1195/* nv04_instmem.c */ 1196extern int nv04_instmem_init(struct drm_device *); 1197extern void nv04_instmem_takedown(struct drm_device *); 1198extern int nv04_instmem_suspend(struct drm_device *); 1199extern void nv04_instmem_resume(struct drm_device *); 1200extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1201extern void nv04_instmem_put(struct nouveau_gpuobj *); 1202extern int nv04_instmem_map(struct nouveau_gpuobj *); 1203extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1204extern void nv04_instmem_flush(struct drm_device *); 1205 1206/* nv50_instmem.c */ 1207extern int nv50_instmem_init(struct drm_device *); 1208extern void nv50_instmem_takedown(struct drm_device *); 1209extern int nv50_instmem_suspend(struct drm_device *); 1210extern void nv50_instmem_resume(struct drm_device *); 1211extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1212extern void nv50_instmem_put(struct nouveau_gpuobj *); 1213extern int nv50_instmem_map(struct nouveau_gpuobj *); 1214extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1215extern void nv50_instmem_flush(struct drm_device *); 1216extern void nv84_instmem_flush(struct drm_device *); 1217 1218/* nvc0_instmem.c */ 1219extern int nvc0_instmem_init(struct drm_device *); 1220extern void nvc0_instmem_takedown(struct drm_device *); 1221extern int nvc0_instmem_suspend(struct drm_device *); 1222extern void nvc0_instmem_resume(struct drm_device *); 1223extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1224extern void nvc0_instmem_put(struct nouveau_gpuobj *); 1225extern int nvc0_instmem_map(struct nouveau_gpuobj *); 1226extern void nvc0_instmem_unmap(struct nouveau_gpuobj *); 1227extern void nvc0_instmem_flush(struct drm_device *); 1228 1229/* nv04_mc.c */ 1230extern int nv04_mc_init(struct drm_device *); 1231extern void nv04_mc_takedown(struct drm_device *); 1232 1233/* nv40_mc.c */ 1234extern int nv40_mc_init(struct drm_device *); 1235extern void nv40_mc_takedown(struct drm_device *); 1236 1237/* nv50_mc.c */ 1238extern int nv50_mc_init(struct drm_device *); 1239extern void nv50_mc_takedown(struct drm_device *); 1240 1241/* nv04_timer.c */ 1242extern int nv04_timer_init(struct drm_device *); 1243extern uint64_t nv04_timer_read(struct drm_device *); 1244extern void nv04_timer_takedown(struct drm_device *); 1245 1246extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1247 unsigned long arg); 1248 1249/* nv04_dac.c */ 1250extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1251extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1252extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1253extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1254extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1255 1256/* nv04_dfp.c */ 1257extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1258extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1259extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1260 int head, bool dl); 1261extern void nv04_dfp_disable(struct drm_device *dev, int head); 1262extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1263 1264/* nv04_tv.c */ 1265extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1266extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1267 1268/* nv17_tv.c */ 1269extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1270 1271/* nv04_display.c */ 1272extern int nv04_display_early_init(struct drm_device *); 1273extern void nv04_display_late_takedown(struct drm_device *); 1274extern int nv04_display_create(struct drm_device *); 1275extern int nv04_display_init(struct drm_device *); 1276extern void nv04_display_destroy(struct drm_device *); 1277 1278/* nv04_crtc.c */ 1279extern int nv04_crtc_create(struct drm_device *, int index); 1280 1281/* nouveau_bo.c */ 1282extern struct ttm_bo_driver nouveau_bo_driver; 1283extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1284 int size, int align, uint32_t flags, 1285 uint32_t tile_mode, uint32_t tile_flags, 1286 bool no_vm, bool mappable, struct nouveau_bo **); 1287extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1288extern int nouveau_bo_unpin(struct nouveau_bo *); 1289extern int nouveau_bo_map(struct nouveau_bo *); 1290extern void nouveau_bo_unmap(struct nouveau_bo *); 1291extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1292 uint32_t busy); 1293extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1294extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1295extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1296extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1297extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1298extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1299 bool no_wait_reserve, bool no_wait_gpu); 1300 1301/* nouveau_fence.c */ 1302struct nouveau_fence; 1303extern int nouveau_fence_init(struct drm_device *); 1304extern void nouveau_fence_fini(struct drm_device *); 1305extern int nouveau_fence_channel_init(struct nouveau_channel *); 1306extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1307extern void nouveau_fence_update(struct nouveau_channel *); 1308extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1309 bool emit); 1310extern int nouveau_fence_emit(struct nouveau_fence *); 1311extern void nouveau_fence_work(struct nouveau_fence *fence, 1312 void (*work)(void *priv, bool signalled), 1313 void *priv); 1314struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1315 1316extern bool __nouveau_fence_signalled(void *obj, void *arg); 1317extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1318extern int __nouveau_fence_flush(void *obj, void *arg); 1319extern void __nouveau_fence_unref(void **obj); 1320extern void *__nouveau_fence_ref(void *obj); 1321 1322static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1323{ 1324 return __nouveau_fence_signalled(obj, NULL); 1325} 1326static inline int 1327nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1328{ 1329 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1330} 1331extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1332static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1333{ 1334 return __nouveau_fence_flush(obj, NULL); 1335} 1336static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1337{ 1338 __nouveau_fence_unref((void **)obj); 1339} 1340static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1341{ 1342 return __nouveau_fence_ref(obj); 1343} 1344 1345/* nouveau_gem.c */ 1346extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1347 int size, int align, uint32_t flags, 1348 uint32_t tile_mode, uint32_t tile_flags, 1349 bool no_vm, bool mappable, struct nouveau_bo **); 1350extern int nouveau_gem_object_new(struct drm_gem_object *); 1351extern void nouveau_gem_object_del(struct drm_gem_object *); 1352extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1353 struct drm_file *); 1354extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1355 struct drm_file *); 1356extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1357 struct drm_file *); 1358extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1359 struct drm_file *); 1360extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1361 struct drm_file *); 1362 1363/* nouveau_display.c */ 1364int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1365void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1366int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1367 struct drm_pending_vblank_event *event); 1368int nouveau_finish_page_flip(struct nouveau_channel *, 1369 struct nouveau_page_flip_state *); 1370 1371/* nv10_gpio.c */ 1372int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1373int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1374 1375/* nv50_gpio.c */ 1376int nv50_gpio_init(struct drm_device *dev); 1377void nv50_gpio_fini(struct drm_device *dev); 1378int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1379int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1380int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1381 void (*)(void *, int), void *); 1382void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1383 void (*)(void *, int), void *); 1384bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1385 1386/* nv50_calc. */ 1387int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1388 int *N1, int *M1, int *N2, int *M2, int *P); 1389int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1390 int clk, int *N, int *fN, int *M, int *P); 1391 1392#ifndef ioread32_native 1393#ifdef __BIG_ENDIAN 1394#define ioread16_native ioread16be 1395#define iowrite16_native iowrite16be 1396#define ioread32_native ioread32be 1397#define iowrite32_native iowrite32be 1398#else /* def __BIG_ENDIAN */ 1399#define ioread16_native ioread16 1400#define iowrite16_native iowrite16 1401#define ioread32_native ioread32 1402#define iowrite32_native iowrite32 1403#endif /* def __BIG_ENDIAN else */ 1404#endif /* !ioread32_native */ 1405 1406/* channel control reg access */ 1407static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1408{ 1409 return ioread32_native(chan->user + reg); 1410} 1411 1412static inline void nvchan_wr32(struct nouveau_channel *chan, 1413 unsigned reg, u32 val) 1414{ 1415 iowrite32_native(val, chan->user + reg); 1416} 1417 1418/* register access */ 1419static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1420{ 1421 struct drm_nouveau_private *dev_priv = dev->dev_private; 1422 return ioread32_native(dev_priv->mmio + reg); 1423} 1424 1425static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1426{ 1427 struct drm_nouveau_private *dev_priv = dev->dev_private; 1428 iowrite32_native(val, dev_priv->mmio + reg); 1429} 1430 1431static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1432{ 1433 u32 tmp = nv_rd32(dev, reg); 1434 nv_wr32(dev, reg, (tmp & ~mask) | val); 1435 return tmp; 1436} 1437 1438static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 return ioread8(dev_priv->mmio + reg); 1442} 1443 1444static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1445{ 1446 struct drm_nouveau_private *dev_priv = dev->dev_private; 1447 iowrite8(val, dev_priv->mmio + reg); 1448} 1449 1450#define nv_wait(dev, reg, mask, val) \ 1451 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1452#define nv_wait_ne(dev, reg, mask, val) \ 1453 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1454 1455/* PRAMIN access */ 1456static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1457{ 1458 struct drm_nouveau_private *dev_priv = dev->dev_private; 1459 return ioread32_native(dev_priv->ramin + offset); 1460} 1461 1462static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1463{ 1464 struct drm_nouveau_private *dev_priv = dev->dev_private; 1465 iowrite32_native(val, dev_priv->ramin + offset); 1466} 1467 1468/* object access */ 1469extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1470extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1471 1472/* 1473 * Logging 1474 * Argument d is (struct drm_device *). 1475 */ 1476#define NV_PRINTK(level, d, fmt, arg...) \ 1477 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1478 pci_name(d->pdev), ##arg) 1479#ifndef NV_DEBUG_NOTRACE 1480#define NV_DEBUG(d, fmt, arg...) do { \ 1481 if (drm_debug & DRM_UT_DRIVER) { \ 1482 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1483 __LINE__, ##arg); \ 1484 } \ 1485} while (0) 1486#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1487 if (drm_debug & DRM_UT_KMS) { \ 1488 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1489 __LINE__, ##arg); \ 1490 } \ 1491} while (0) 1492#else 1493#define NV_DEBUG(d, fmt, arg...) do { \ 1494 if (drm_debug & DRM_UT_DRIVER) \ 1495 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1496} while (0) 1497#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1498 if (drm_debug & DRM_UT_KMS) \ 1499 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1500} while (0) 1501#endif 1502#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1503#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1504#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1505#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1506#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1507 1508/* nouveau_reg_debug bitmask */ 1509enum { 1510 NOUVEAU_REG_DEBUG_MC = 0x1, 1511 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1512 NOUVEAU_REG_DEBUG_FB = 0x4, 1513 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1514 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1515 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1516 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1517 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1518 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1519 NOUVEAU_REG_DEBUG_EVO = 0x200, 1520}; 1521 1522#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1523 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1524 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1525} while (0) 1526 1527static inline bool 1528nv_two_heads(struct drm_device *dev) 1529{ 1530 struct drm_nouveau_private *dev_priv = dev->dev_private; 1531 const int impl = dev->pci_device & 0x0ff0; 1532 1533 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1534 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1535 return true; 1536 1537 return false; 1538} 1539 1540static inline bool 1541nv_gf4_disp_arch(struct drm_device *dev) 1542{ 1543 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1544} 1545 1546static inline bool 1547nv_two_reg_pll(struct drm_device *dev) 1548{ 1549 struct drm_nouveau_private *dev_priv = dev->dev_private; 1550 const int impl = dev->pci_device & 0x0ff0; 1551 1552 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1553 return true; 1554 return false; 1555} 1556 1557static inline bool 1558nv_match_device(struct drm_device *dev, unsigned device, 1559 unsigned sub_vendor, unsigned sub_device) 1560{ 1561 return dev->pdev->device == device && 1562 dev->pdev->subsystem_vendor == sub_vendor && 1563 dev->pdev->subsystem_device == sub_device; 1564} 1565 1566/* memory type/access flags, do not match hardware values */ 1567#define NV_MEM_ACCESS_RO 1 1568#define NV_MEM_ACCESS_WO 2 1569#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1570#define NV_MEM_ACCESS_SYS 4 1571#define NV_MEM_ACCESS_VM 8 1572 1573#define NV_MEM_TARGET_VRAM 0 1574#define NV_MEM_TARGET_PCI 1 1575#define NV_MEM_TARGET_PCI_NOSNOOP 2 1576#define NV_MEM_TARGET_VM 3 1577#define NV_MEM_TARGET_GART 4 1578 1579#define NV_MEM_TYPE_VM 0x7f 1580#define NV_MEM_COMP_VM 0x03 1581 1582/* NV_SW object class */ 1583#define NV_SW 0x0000506e 1584#define NV_SW_DMA_SEMAPHORE 0x00000060 1585#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1586#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1587#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1588#define NV_SW_YIELD 0x00000080 1589#define NV_SW_DMA_VBLSEM 0x0000018c 1590#define NV_SW_VBLSEM_OFFSET 0x00000400 1591#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1592#define NV_SW_VBLSEM_RELEASE 0x00000408 1593#define NV_SW_PAGE_FLIP 0x00000500 1594 1595#endif /* __NOUVEAU_DRV_H__ */ 1596