nouveau_drv.h revision a76fb4e8ffe42144529e21fe1e609b762e8eb5cc
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126struct mem_block { 127 struct mem_block *next; 128 struct mem_block *prev; 129 uint64_t start; 130 uint64_t size; 131 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 132}; 133 134enum nouveau_flags { 135 NV_NFORCE = 0x10000000, 136 NV_NFORCE2 = 0x20000000 137}; 138 139#define NVOBJ_ENGINE_SW 0 140#define NVOBJ_ENGINE_GR 1 141#define NVOBJ_ENGINE_DISPLAY 2 142#define NVOBJ_ENGINE_INT 0xdeadbeef 143 144#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 145#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 146#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 147#define NVOBJ_FLAG_FAKE (1 << 3) 148struct nouveau_gpuobj { 149 struct list_head list; 150 151 struct nouveau_channel *im_channel; 152 struct mem_block *im_pramin; 153 struct nouveau_bo *im_backing; 154 uint32_t im_backing_start; 155 uint32_t *im_backing_suspend; 156 int im_bound; 157 158 uint32_t flags; 159 int refcount; 160 161 uint32_t engine; 162 uint32_t class; 163 164 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 165 void *priv; 166}; 167 168struct nouveau_gpuobj_ref { 169 struct list_head list; 170 171 struct nouveau_gpuobj *gpuobj; 172 uint32_t instance; 173 174 struct nouveau_channel *channel; 175 int handle; 176}; 177 178struct nouveau_channel { 179 struct drm_device *dev; 180 int id; 181 182 /* owner of this fifo */ 183 struct drm_file *file_priv; 184 /* mapping of the fifo itself */ 185 struct drm_local_map *map; 186 187 /* mapping of the regs controling the fifo */ 188 void __iomem *user; 189 uint32_t user_get; 190 uint32_t user_put; 191 192 /* Fencing */ 193 struct { 194 /* lock protects the pending list only */ 195 spinlock_t lock; 196 struct list_head pending; 197 uint32_t sequence; 198 uint32_t sequence_ack; 199 uint32_t last_sequence_irq; 200 } fence; 201 202 /* DMA push buffer */ 203 struct nouveau_gpuobj_ref *pushbuf; 204 struct nouveau_bo *pushbuf_bo; 205 uint32_t pushbuf_base; 206 207 /* Notifier memory */ 208 struct nouveau_bo *notifier_bo; 209 struct mem_block *notifier_heap; 210 211 /* PFIFO context */ 212 struct nouveau_gpuobj_ref *ramfc; 213 struct nouveau_gpuobj_ref *cache; 214 215 /* PGRAPH context */ 216 /* XXX may be merge 2 pointers as private data ??? */ 217 struct nouveau_gpuobj_ref *ramin_grctx; 218 void *pgraph_ctx; 219 220 /* NV50 VM */ 221 struct nouveau_gpuobj *vm_pd; 222 struct nouveau_gpuobj_ref *vm_gart_pt; 223 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 224 225 /* Objects */ 226 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 227 struct mem_block *ramin_heap; /* Private PRAMIN heap */ 228 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 229 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 230 231 /* GPU object info for stuff used in-kernel (mm_enabled) */ 232 uint32_t m2mf_ntfy; 233 uint32_t vram_handle; 234 uint32_t gart_handle; 235 bool accel_done; 236 237 /* Push buffer state (only for drm's channel on !mm_enabled) */ 238 struct { 239 int max; 240 int free; 241 int cur; 242 int put; 243 /* access via pushbuf_bo */ 244 245 int ib_base; 246 int ib_max; 247 int ib_free; 248 int ib_put; 249 } dma; 250 251 uint32_t sw_subchannel[8]; 252 253 struct { 254 struct nouveau_gpuobj *vblsem; 255 uint32_t vblsem_offset; 256 uint32_t vblsem_rval; 257 struct list_head vbl_wait; 258 } nvsw; 259 260 struct { 261 bool active; 262 char name[32]; 263 struct drm_info_list info; 264 } debugfs; 265}; 266 267struct nouveau_instmem_engine { 268 void *priv; 269 270 int (*init)(struct drm_device *dev); 271 void (*takedown)(struct drm_device *dev); 272 int (*suspend)(struct drm_device *dev); 273 void (*resume)(struct drm_device *dev); 274 275 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 276 uint32_t *size); 277 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 278 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 279 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 280 void (*prepare_access)(struct drm_device *, bool write); 281 void (*finish_access)(struct drm_device *); 282}; 283 284struct nouveau_mc_engine { 285 int (*init)(struct drm_device *dev); 286 void (*takedown)(struct drm_device *dev); 287}; 288 289struct nouveau_timer_engine { 290 int (*init)(struct drm_device *dev); 291 void (*takedown)(struct drm_device *dev); 292 uint64_t (*read)(struct drm_device *dev); 293}; 294 295struct nouveau_fb_engine { 296 int num_tiles; 297 298 int (*init)(struct drm_device *dev); 299 void (*takedown)(struct drm_device *dev); 300 301 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 302 uint32_t size, uint32_t pitch); 303}; 304 305struct nouveau_fifo_engine { 306 void *priv; 307 308 int channels; 309 310 int (*init)(struct drm_device *); 311 void (*takedown)(struct drm_device *); 312 313 void (*disable)(struct drm_device *); 314 void (*enable)(struct drm_device *); 315 bool (*reassign)(struct drm_device *, bool enable); 316 bool (*cache_flush)(struct drm_device *dev); 317 bool (*cache_pull)(struct drm_device *dev, bool enable); 318 319 int (*channel_id)(struct drm_device *); 320 321 int (*create_context)(struct nouveau_channel *); 322 void (*destroy_context)(struct nouveau_channel *); 323 int (*load_context)(struct nouveau_channel *); 324 int (*unload_context)(struct drm_device *); 325}; 326 327struct nouveau_pgraph_object_method { 328 int id; 329 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 330 uint32_t data); 331}; 332 333struct nouveau_pgraph_object_class { 334 int id; 335 bool software; 336 struct nouveau_pgraph_object_method *methods; 337}; 338 339struct nouveau_pgraph_engine { 340 struct nouveau_pgraph_object_class *grclass; 341 bool accel_blocked; 342 void *ctxprog; 343 void *ctxvals; 344 int grctx_size; 345 346 int (*init)(struct drm_device *); 347 void (*takedown)(struct drm_device *); 348 349 void (*fifo_access)(struct drm_device *, bool); 350 351 struct nouveau_channel *(*channel)(struct drm_device *); 352 int (*create_context)(struct nouveau_channel *); 353 void (*destroy_context)(struct nouveau_channel *); 354 int (*load_context)(struct nouveau_channel *); 355 int (*unload_context)(struct drm_device *); 356 357 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 358 uint32_t size, uint32_t pitch); 359}; 360 361struct nouveau_engine { 362 struct nouveau_instmem_engine instmem; 363 struct nouveau_mc_engine mc; 364 struct nouveau_timer_engine timer; 365 struct nouveau_fb_engine fb; 366 struct nouveau_pgraph_engine graph; 367 struct nouveau_fifo_engine fifo; 368}; 369 370struct nouveau_pll_vals { 371 union { 372 struct { 373#ifdef __BIG_ENDIAN 374 uint8_t N1, M1, N2, M2; 375#else 376 uint8_t M1, N1, M2, N2; 377#endif 378 }; 379 struct { 380 uint16_t NM1, NM2; 381 } __attribute__((packed)); 382 }; 383 int log2P; 384 385 int refclk; 386}; 387 388enum nv04_fp_display_regs { 389 FP_DISPLAY_END, 390 FP_TOTAL, 391 FP_CRTC, 392 FP_SYNC_START, 393 FP_SYNC_END, 394 FP_VALID_START, 395 FP_VALID_END 396}; 397 398struct nv04_crtc_reg { 399 unsigned char MiscOutReg; /* */ 400 uint8_t CRTC[0x9f]; 401 uint8_t CR58[0x10]; 402 uint8_t Sequencer[5]; 403 uint8_t Graphics[9]; 404 uint8_t Attribute[21]; 405 unsigned char DAC[768]; /* Internal Colorlookuptable */ 406 407 /* PCRTC regs */ 408 uint32_t fb_start; 409 uint32_t crtc_cfg; 410 uint32_t cursor_cfg; 411 uint32_t gpio_ext; 412 uint32_t crtc_830; 413 uint32_t crtc_834; 414 uint32_t crtc_850; 415 uint32_t crtc_eng_ctrl; 416 417 /* PRAMDAC regs */ 418 uint32_t nv10_cursync; 419 struct nouveau_pll_vals pllvals; 420 uint32_t ramdac_gen_ctrl; 421 uint32_t ramdac_630; 422 uint32_t ramdac_634; 423 uint32_t tv_setup; 424 uint32_t tv_vtotal; 425 uint32_t tv_vskew; 426 uint32_t tv_vsync_delay; 427 uint32_t tv_htotal; 428 uint32_t tv_hskew; 429 uint32_t tv_hsync_delay; 430 uint32_t tv_hsync_delay2; 431 uint32_t fp_horiz_regs[7]; 432 uint32_t fp_vert_regs[7]; 433 uint32_t dither; 434 uint32_t fp_control; 435 uint32_t dither_regs[6]; 436 uint32_t fp_debug_0; 437 uint32_t fp_debug_1; 438 uint32_t fp_debug_2; 439 uint32_t fp_margin_color; 440 uint32_t ramdac_8c0; 441 uint32_t ramdac_a20; 442 uint32_t ramdac_a24; 443 uint32_t ramdac_a34; 444 uint32_t ctv_regs[38]; 445}; 446 447struct nv04_output_reg { 448 uint32_t output; 449 int head; 450}; 451 452struct nv04_mode_state { 453 uint32_t bpp; 454 uint32_t width; 455 uint32_t height; 456 uint32_t interlace; 457 uint32_t repaint0; 458 uint32_t repaint1; 459 uint32_t screen; 460 uint32_t scale; 461 uint32_t dither; 462 uint32_t extra; 463 uint32_t fifo; 464 uint32_t pixel; 465 uint32_t horiz; 466 int arbitration0; 467 int arbitration1; 468 uint32_t pll; 469 uint32_t pllB; 470 uint32_t vpll; 471 uint32_t vpll2; 472 uint32_t vpllB; 473 uint32_t vpll2B; 474 uint32_t pllsel; 475 uint32_t sel_clk; 476 uint32_t general; 477 uint32_t crtcOwner; 478 uint32_t head; 479 uint32_t head2; 480 uint32_t cursorConfig; 481 uint32_t cursor0; 482 uint32_t cursor1; 483 uint32_t cursor2; 484 uint32_t timingH; 485 uint32_t timingV; 486 uint32_t displayV; 487 uint32_t crtcSync; 488 489 struct nv04_crtc_reg crtc_reg[2]; 490}; 491 492enum nouveau_card_type { 493 NV_04 = 0x00, 494 NV_10 = 0x10, 495 NV_20 = 0x20, 496 NV_30 = 0x30, 497 NV_40 = 0x40, 498 NV_50 = 0x50, 499}; 500 501struct drm_nouveau_private { 502 struct drm_device *dev; 503 enum { 504 NOUVEAU_CARD_INIT_DOWN, 505 NOUVEAU_CARD_INIT_DONE, 506 NOUVEAU_CARD_INIT_FAILED 507 } init_state; 508 509 /* the card type, takes NV_* as values */ 510 enum nouveau_card_type card_type; 511 /* exact chipset, derived from NV_PMC_BOOT_0 */ 512 int chipset; 513 int flags; 514 515 void __iomem *mmio; 516 void __iomem *ramin; 517 uint32_t ramin_size; 518 519 struct nouveau_bo *vga_ram; 520 521 struct workqueue_struct *wq; 522 struct work_struct irq_work; 523 524 struct list_head vbl_waiting; 525 526 struct { 527 struct ttm_global_reference mem_global_ref; 528 struct ttm_bo_global_ref bo_global_ref; 529 struct ttm_bo_device bdev; 530 spinlock_t bo_list_lock; 531 struct list_head bo_list; 532 atomic_t validate_sequence; 533 } ttm; 534 535 struct fb_info *fbdev_info; 536 537 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 538 539 struct nouveau_engine engine; 540 struct nouveau_channel *channel; 541 542 /* For PFIFO and PGRAPH. */ 543 spinlock_t context_switch_lock; 544 545 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 546 struct nouveau_gpuobj *ramht; 547 uint32_t ramin_rsvd_vram; 548 uint32_t ramht_offset; 549 uint32_t ramht_size; 550 uint32_t ramht_bits; 551 uint32_t ramfc_offset; 552 uint32_t ramfc_size; 553 uint32_t ramro_offset; 554 uint32_t ramro_size; 555 556 struct { 557 enum { 558 NOUVEAU_GART_NONE = 0, 559 NOUVEAU_GART_AGP, 560 NOUVEAU_GART_SGDMA 561 } type; 562 uint64_t aper_base; 563 uint64_t aper_size; 564 uint64_t aper_free; 565 566 struct nouveau_gpuobj *sg_ctxdma; 567 struct page *sg_dummy_page; 568 dma_addr_t sg_dummy_bus; 569 } gart_info; 570 571 /* nv10-nv40 tiling regions */ 572 struct { 573 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 574 spinlock_t lock; 575 } tile; 576 577 /* VRAM/fb configuration */ 578 uint64_t vram_size; 579 uint64_t vram_sys_base; 580 581 uint64_t fb_phys; 582 uint64_t fb_available_size; 583 uint64_t fb_mappable_pages; 584 uint64_t fb_aper_free; 585 int fb_mtrr; 586 587 /* G8x/G9x virtual address space */ 588 uint64_t vm_gart_base; 589 uint64_t vm_gart_size; 590 uint64_t vm_vram_base; 591 uint64_t vm_vram_size; 592 uint64_t vm_end; 593 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 594 int vm_vram_pt_nr; 595 596 struct mem_block *ramin_heap; 597 598 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ 599 uint32_t ctx_table_size; 600 struct nouveau_gpuobj_ref *ctx_table; 601 602 struct list_head gpuobj_list; 603 604 struct nvbios vbios; 605 606 struct nv04_mode_state mode_reg; 607 struct nv04_mode_state saved_reg; 608 uint32_t saved_vga_font[4][16384]; 609 uint32_t crtc_owner; 610 uint32_t dac_users[4]; 611 612 struct nouveau_suspend_resume { 613 uint32_t *ramin_copy; 614 } susres; 615 616 struct backlight_device *backlight; 617 618 struct nouveau_channel *evo; 619 620 struct { 621 struct dentry *channel_root; 622 } debugfs; 623}; 624 625static inline struct drm_nouveau_private * 626nouveau_bdev(struct ttm_bo_device *bd) 627{ 628 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 629} 630 631static inline int 632nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 633{ 634 struct nouveau_bo *prev; 635 636 if (!pnvbo) 637 return -EINVAL; 638 prev = *pnvbo; 639 640 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 641 if (prev) { 642 struct ttm_buffer_object *bo = &prev->bo; 643 644 ttm_bo_unref(&bo); 645 } 646 647 return 0; 648} 649 650#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \ 651 struct drm_nouveau_private *nv = dev->dev_private; \ 652 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \ 653 NV_ERROR(dev, "called without init\n"); \ 654 return -EINVAL; \ 655 } \ 656} while (0) 657 658#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 659 struct drm_nouveau_private *nv = dev->dev_private; \ 660 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 661 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 662 DRM_CURRENTPID, (id)); \ 663 return -EPERM; \ 664 } \ 665 (ch) = nv->fifos[(id)]; \ 666} while (0) 667 668/* nouveau_drv.c */ 669extern int nouveau_noagp; 670extern int nouveau_duallink; 671extern int nouveau_uscript_lvds; 672extern int nouveau_uscript_tmds; 673extern int nouveau_vram_pushbuf; 674extern int nouveau_vram_notify; 675extern int nouveau_fbpercrtc; 676extern int nouveau_tv_disable; 677extern char *nouveau_tv_norm; 678extern int nouveau_reg_debug; 679extern char *nouveau_vbios; 680extern int nouveau_ctxfw; 681extern int nouveau_ignorelid; 682extern int nouveau_nofbaccel; 683extern int nouveau_noaccel; 684extern int nouveau_override_conntype; 685 686extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 687extern int nouveau_pci_resume(struct pci_dev *pdev); 688 689/* nouveau_state.c */ 690extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 691extern int nouveau_load(struct drm_device *, unsigned long flags); 692extern int nouveau_firstopen(struct drm_device *); 693extern void nouveau_lastclose(struct drm_device *); 694extern int nouveau_unload(struct drm_device *); 695extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 696 struct drm_file *); 697extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 698 struct drm_file *); 699extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 700 uint32_t reg, uint32_t mask, uint32_t val); 701extern bool nouveau_wait_for_idle(struct drm_device *); 702extern int nouveau_card_init(struct drm_device *); 703 704/* nouveau_mem.c */ 705extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start, 706 uint64_t size); 707extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, 708 uint64_t size, int align2, 709 struct drm_file *, int tail); 710extern void nouveau_mem_takedown(struct mem_block **heap); 711extern void nouveau_mem_free_block(struct mem_block *); 712extern int nouveau_mem_detect(struct drm_device *dev); 713extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); 714extern int nouveau_mem_init(struct drm_device *); 715extern int nouveau_mem_init_agp(struct drm_device *); 716extern void nouveau_mem_close(struct drm_device *); 717extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 718 uint32_t addr, 719 uint32_t size, 720 uint32_t pitch); 721extern void nv10_mem_expire_tiling(struct drm_device *dev, 722 struct nouveau_tile_reg *tile, 723 struct nouveau_fence *fence); 724extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 725 uint32_t size, uint32_t flags, 726 uint64_t phys); 727extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 728 uint32_t size); 729 730/* nouveau_notifier.c */ 731extern int nouveau_notifier_init_channel(struct nouveau_channel *); 732extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 733extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 734 int cout, uint32_t *offset); 735extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 736extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 737 struct drm_file *); 738extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 739 struct drm_file *); 740 741/* nouveau_channel.c */ 742extern struct drm_ioctl_desc nouveau_ioctls[]; 743extern int nouveau_max_ioctl; 744extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 745extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 746 int channel); 747extern int nouveau_channel_alloc(struct drm_device *dev, 748 struct nouveau_channel **chan, 749 struct drm_file *file_priv, 750 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 751extern void nouveau_channel_free(struct nouveau_channel *); 752 753/* nouveau_object.c */ 754extern int nouveau_gpuobj_early_init(struct drm_device *); 755extern int nouveau_gpuobj_init(struct drm_device *); 756extern void nouveau_gpuobj_takedown(struct drm_device *); 757extern void nouveau_gpuobj_late_takedown(struct drm_device *); 758extern int nouveau_gpuobj_suspend(struct drm_device *dev); 759extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 760extern void nouveau_gpuobj_resume(struct drm_device *dev); 761extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 762 uint32_t vram_h, uint32_t tt_h); 763extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 764extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 765 uint32_t size, int align, uint32_t flags, 766 struct nouveau_gpuobj **); 767extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 768extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 769 uint32_t handle, struct nouveau_gpuobj *, 770 struct nouveau_gpuobj_ref **); 771extern int nouveau_gpuobj_ref_del(struct drm_device *, 772 struct nouveau_gpuobj_ref **); 773extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 774 struct nouveau_gpuobj_ref **ref_ret); 775extern int nouveau_gpuobj_new_ref(struct drm_device *, 776 struct nouveau_channel *alloc_chan, 777 struct nouveau_channel *ref_chan, 778 uint32_t handle, uint32_t size, int align, 779 uint32_t flags, struct nouveau_gpuobj_ref **); 780extern int nouveau_gpuobj_new_fake(struct drm_device *, 781 uint32_t p_offset, uint32_t b_offset, 782 uint32_t size, uint32_t flags, 783 struct nouveau_gpuobj **, 784 struct nouveau_gpuobj_ref**); 785extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 786 uint64_t offset, uint64_t size, int access, 787 int target, struct nouveau_gpuobj **); 788extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 789 uint64_t offset, uint64_t size, 790 int access, struct nouveau_gpuobj **, 791 uint32_t *o_ret); 792extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 793 struct nouveau_gpuobj **); 794extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 795 struct nouveau_gpuobj **); 796extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 797 struct drm_file *); 798extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 799 struct drm_file *); 800 801/* nouveau_irq.c */ 802extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 803extern void nouveau_irq_preinstall(struct drm_device *); 804extern int nouveau_irq_postinstall(struct drm_device *); 805extern void nouveau_irq_uninstall(struct drm_device *); 806 807/* nouveau_sgdma.c */ 808extern int nouveau_sgdma_init(struct drm_device *); 809extern void nouveau_sgdma_takedown(struct drm_device *); 810extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 811 uint32_t *page); 812extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 813 814/* nouveau_debugfs.c */ 815#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 816extern int nouveau_debugfs_init(struct drm_minor *); 817extern void nouveau_debugfs_takedown(struct drm_minor *); 818extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 819extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 820#else 821static inline int 822nouveau_debugfs_init(struct drm_minor *minor) 823{ 824 return 0; 825} 826 827static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 828{ 829} 830 831static inline int 832nouveau_debugfs_channel_init(struct nouveau_channel *chan) 833{ 834 return 0; 835} 836 837static inline void 838nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 839{ 840} 841#endif 842 843/* nouveau_dma.c */ 844extern void nouveau_dma_pre_init(struct nouveau_channel *); 845extern int nouveau_dma_init(struct nouveau_channel *); 846extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 847 848/* nouveau_acpi.c */ 849#if defined(CONFIG_ACPI) 850void nouveau_register_dsm_handler(void); 851void nouveau_unregister_dsm_handler(void); 852#else 853static inline void nouveau_register_dsm_handler(void) {} 854static inline void nouveau_unregister_dsm_handler(void) {} 855#endif 856 857/* nouveau_backlight.c */ 858#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 859extern int nouveau_backlight_init(struct drm_device *); 860extern void nouveau_backlight_exit(struct drm_device *); 861#else 862static inline int nouveau_backlight_init(struct drm_device *dev) 863{ 864 return 0; 865} 866 867static inline void nouveau_backlight_exit(struct drm_device *dev) { } 868#endif 869 870/* nouveau_bios.c */ 871extern int nouveau_bios_init(struct drm_device *); 872extern void nouveau_bios_takedown(struct drm_device *dev); 873extern int nouveau_run_vbios_init(struct drm_device *); 874extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 875 struct dcb_entry *); 876extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 877 enum dcb_gpio_tag); 878extern struct dcb_connector_table_entry * 879nouveau_bios_connector_entry(struct drm_device *, int index); 880extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 881 struct pll_lims *); 882extern int nouveau_bios_run_display_table(struct drm_device *, 883 struct dcb_entry *, 884 uint32_t script, int pxclk); 885extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 886 int *length); 887extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 888extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 889extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 890 bool *dl, bool *if_is_24bit); 891extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 892 int head, int pxclk); 893extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 894 enum LVDS_script, int pxclk); 895 896/* nouveau_ttm.c */ 897int nouveau_ttm_global_init(struct drm_nouveau_private *); 898void nouveau_ttm_global_release(struct drm_nouveau_private *); 899int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 900 901/* nouveau_dp.c */ 902int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 903 uint8_t *data, int data_nr); 904bool nouveau_dp_detect(struct drm_encoder *); 905bool nouveau_dp_link_train(struct drm_encoder *); 906 907/* nv04_fb.c */ 908extern int nv04_fb_init(struct drm_device *); 909extern void nv04_fb_takedown(struct drm_device *); 910 911/* nv10_fb.c */ 912extern int nv10_fb_init(struct drm_device *); 913extern void nv10_fb_takedown(struct drm_device *); 914extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 915 uint32_t, uint32_t); 916 917/* nv40_fb.c */ 918extern int nv40_fb_init(struct drm_device *); 919extern void nv40_fb_takedown(struct drm_device *); 920extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 921 uint32_t, uint32_t); 922 923/* nv50_fb.c */ 924extern int nv50_fb_init(struct drm_device *); 925extern void nv50_fb_takedown(struct drm_device *); 926 927/* nv04_fifo.c */ 928extern int nv04_fifo_init(struct drm_device *); 929extern void nv04_fifo_disable(struct drm_device *); 930extern void nv04_fifo_enable(struct drm_device *); 931extern bool nv04_fifo_reassign(struct drm_device *, bool); 932extern bool nv04_fifo_cache_flush(struct drm_device *); 933extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 934extern int nv04_fifo_channel_id(struct drm_device *); 935extern int nv04_fifo_create_context(struct nouveau_channel *); 936extern void nv04_fifo_destroy_context(struct nouveau_channel *); 937extern int nv04_fifo_load_context(struct nouveau_channel *); 938extern int nv04_fifo_unload_context(struct drm_device *); 939 940/* nv10_fifo.c */ 941extern int nv10_fifo_init(struct drm_device *); 942extern int nv10_fifo_channel_id(struct drm_device *); 943extern int nv10_fifo_create_context(struct nouveau_channel *); 944extern void nv10_fifo_destroy_context(struct nouveau_channel *); 945extern int nv10_fifo_load_context(struct nouveau_channel *); 946extern int nv10_fifo_unload_context(struct drm_device *); 947 948/* nv40_fifo.c */ 949extern int nv40_fifo_init(struct drm_device *); 950extern int nv40_fifo_create_context(struct nouveau_channel *); 951extern void nv40_fifo_destroy_context(struct nouveau_channel *); 952extern int nv40_fifo_load_context(struct nouveau_channel *); 953extern int nv40_fifo_unload_context(struct drm_device *); 954 955/* nv50_fifo.c */ 956extern int nv50_fifo_init(struct drm_device *); 957extern void nv50_fifo_takedown(struct drm_device *); 958extern int nv50_fifo_channel_id(struct drm_device *); 959extern int nv50_fifo_create_context(struct nouveau_channel *); 960extern void nv50_fifo_destroy_context(struct nouveau_channel *); 961extern int nv50_fifo_load_context(struct nouveau_channel *); 962extern int nv50_fifo_unload_context(struct drm_device *); 963 964/* nv04_graph.c */ 965extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 966extern int nv04_graph_init(struct drm_device *); 967extern void nv04_graph_takedown(struct drm_device *); 968extern void nv04_graph_fifo_access(struct drm_device *, bool); 969extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 970extern int nv04_graph_create_context(struct nouveau_channel *); 971extern void nv04_graph_destroy_context(struct nouveau_channel *); 972extern int nv04_graph_load_context(struct nouveau_channel *); 973extern int nv04_graph_unload_context(struct drm_device *); 974extern void nv04_graph_context_switch(struct drm_device *); 975 976/* nv10_graph.c */ 977extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 978extern int nv10_graph_init(struct drm_device *); 979extern void nv10_graph_takedown(struct drm_device *); 980extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 981extern int nv10_graph_create_context(struct nouveau_channel *); 982extern void nv10_graph_destroy_context(struct nouveau_channel *); 983extern int nv10_graph_load_context(struct nouveau_channel *); 984extern int nv10_graph_unload_context(struct drm_device *); 985extern void nv10_graph_context_switch(struct drm_device *); 986extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 987 uint32_t, uint32_t); 988 989/* nv20_graph.c */ 990extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 991extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 992extern int nv20_graph_create_context(struct nouveau_channel *); 993extern void nv20_graph_destroy_context(struct nouveau_channel *); 994extern int nv20_graph_load_context(struct nouveau_channel *); 995extern int nv20_graph_unload_context(struct drm_device *); 996extern int nv20_graph_init(struct drm_device *); 997extern void nv20_graph_takedown(struct drm_device *); 998extern int nv30_graph_init(struct drm_device *); 999extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1000 uint32_t, uint32_t); 1001 1002/* nv40_graph.c */ 1003extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1004extern int nv40_graph_init(struct drm_device *); 1005extern void nv40_graph_takedown(struct drm_device *); 1006extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1007extern int nv40_graph_create_context(struct nouveau_channel *); 1008extern void nv40_graph_destroy_context(struct nouveau_channel *); 1009extern int nv40_graph_load_context(struct nouveau_channel *); 1010extern int nv40_graph_unload_context(struct drm_device *); 1011extern void nv40_grctx_init(struct nouveau_grctx *); 1012extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1013 uint32_t, uint32_t); 1014 1015/* nv50_graph.c */ 1016extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1017extern int nv50_graph_init(struct drm_device *); 1018extern void nv50_graph_takedown(struct drm_device *); 1019extern void nv50_graph_fifo_access(struct drm_device *, bool); 1020extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1021extern int nv50_graph_create_context(struct nouveau_channel *); 1022extern void nv50_graph_destroy_context(struct nouveau_channel *); 1023extern int nv50_graph_load_context(struct nouveau_channel *); 1024extern int nv50_graph_unload_context(struct drm_device *); 1025extern void nv50_graph_context_switch(struct drm_device *); 1026extern int nv50_grctx_init(struct nouveau_grctx *); 1027 1028/* nouveau_grctx.c */ 1029extern int nouveau_grctx_prog_load(struct drm_device *); 1030extern void nouveau_grctx_vals_load(struct drm_device *, 1031 struct nouveau_gpuobj *); 1032extern void nouveau_grctx_fini(struct drm_device *); 1033 1034/* nv04_instmem.c */ 1035extern int nv04_instmem_init(struct drm_device *); 1036extern void nv04_instmem_takedown(struct drm_device *); 1037extern int nv04_instmem_suspend(struct drm_device *); 1038extern void nv04_instmem_resume(struct drm_device *); 1039extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1040 uint32_t *size); 1041extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1042extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1043extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1044extern void nv04_instmem_prepare_access(struct drm_device *, bool write); 1045extern void nv04_instmem_finish_access(struct drm_device *); 1046 1047/* nv50_instmem.c */ 1048extern int nv50_instmem_init(struct drm_device *); 1049extern void nv50_instmem_takedown(struct drm_device *); 1050extern int nv50_instmem_suspend(struct drm_device *); 1051extern void nv50_instmem_resume(struct drm_device *); 1052extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1053 uint32_t *size); 1054extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1055extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1056extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1057extern void nv50_instmem_prepare_access(struct drm_device *, bool write); 1058extern void nv50_instmem_finish_access(struct drm_device *); 1059 1060/* nv04_mc.c */ 1061extern int nv04_mc_init(struct drm_device *); 1062extern void nv04_mc_takedown(struct drm_device *); 1063 1064/* nv40_mc.c */ 1065extern int nv40_mc_init(struct drm_device *); 1066extern void nv40_mc_takedown(struct drm_device *); 1067 1068/* nv50_mc.c */ 1069extern int nv50_mc_init(struct drm_device *); 1070extern void nv50_mc_takedown(struct drm_device *); 1071 1072/* nv04_timer.c */ 1073extern int nv04_timer_init(struct drm_device *); 1074extern uint64_t nv04_timer_read(struct drm_device *); 1075extern void nv04_timer_takedown(struct drm_device *); 1076 1077extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1078 unsigned long arg); 1079 1080/* nv04_dac.c */ 1081extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); 1082extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1083extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1084extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1085 1086/* nv04_dfp.c */ 1087extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry); 1088extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1089extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1090 int head, bool dl); 1091extern void nv04_dfp_disable(struct drm_device *dev, int head); 1092extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1093 1094/* nv04_tv.c */ 1095extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1096extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1097 1098/* nv17_tv.c */ 1099extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); 1100 1101/* nv04_display.c */ 1102extern int nv04_display_create(struct drm_device *); 1103extern void nv04_display_destroy(struct drm_device *); 1104extern void nv04_display_restore(struct drm_device *); 1105 1106/* nv04_crtc.c */ 1107extern int nv04_crtc_create(struct drm_device *, int index); 1108 1109/* nouveau_bo.c */ 1110extern struct ttm_bo_driver nouveau_bo_driver; 1111extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1112 int size, int align, uint32_t flags, 1113 uint32_t tile_mode, uint32_t tile_flags, 1114 bool no_vm, bool mappable, struct nouveau_bo **); 1115extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1116extern int nouveau_bo_unpin(struct nouveau_bo *); 1117extern int nouveau_bo_map(struct nouveau_bo *); 1118extern void nouveau_bo_unmap(struct nouveau_bo *); 1119extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1120 uint32_t busy); 1121extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1122extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1123extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1124extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1125 1126/* nouveau_fence.c */ 1127struct nouveau_fence; 1128extern int nouveau_fence_init(struct nouveau_channel *); 1129extern void nouveau_fence_fini(struct nouveau_channel *); 1130extern void nouveau_fence_update(struct nouveau_channel *); 1131extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1132 bool emit); 1133extern int nouveau_fence_emit(struct nouveau_fence *); 1134struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1135extern bool nouveau_fence_signalled(void *obj, void *arg); 1136extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1137extern int nouveau_fence_flush(void *obj, void *arg); 1138extern void nouveau_fence_unref(void **obj); 1139extern void *nouveau_fence_ref(void *obj); 1140extern void nouveau_fence_handler(struct drm_device *dev, int channel); 1141 1142/* nouveau_gem.c */ 1143extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1144 int size, int align, uint32_t flags, 1145 uint32_t tile_mode, uint32_t tile_flags, 1146 bool no_vm, bool mappable, struct nouveau_bo **); 1147extern int nouveau_gem_object_new(struct drm_gem_object *); 1148extern void nouveau_gem_object_del(struct drm_gem_object *); 1149extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1150 struct drm_file *); 1151extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1152 struct drm_file *); 1153extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1154 struct drm_file *); 1155extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1156 struct drm_file *); 1157extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1158 struct drm_file *); 1159 1160/* nv17_gpio.c */ 1161int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1162int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1163 1164#ifndef ioread32_native 1165#ifdef __BIG_ENDIAN 1166#define ioread16_native ioread16be 1167#define iowrite16_native iowrite16be 1168#define ioread32_native ioread32be 1169#define iowrite32_native iowrite32be 1170#else /* def __BIG_ENDIAN */ 1171#define ioread16_native ioread16 1172#define iowrite16_native iowrite16 1173#define ioread32_native ioread32 1174#define iowrite32_native iowrite32 1175#endif /* def __BIG_ENDIAN else */ 1176#endif /* !ioread32_native */ 1177 1178/* channel control reg access */ 1179static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1180{ 1181 return ioread32_native(chan->user + reg); 1182} 1183 1184static inline void nvchan_wr32(struct nouveau_channel *chan, 1185 unsigned reg, u32 val) 1186{ 1187 iowrite32_native(val, chan->user + reg); 1188} 1189 1190/* register access */ 1191static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1192{ 1193 struct drm_nouveau_private *dev_priv = dev->dev_private; 1194 return ioread32_native(dev_priv->mmio + reg); 1195} 1196 1197static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1198{ 1199 struct drm_nouveau_private *dev_priv = dev->dev_private; 1200 iowrite32_native(val, dev_priv->mmio + reg); 1201} 1202 1203static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1204{ 1205 struct drm_nouveau_private *dev_priv = dev->dev_private; 1206 return ioread8(dev_priv->mmio + reg); 1207} 1208 1209static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1210{ 1211 struct drm_nouveau_private *dev_priv = dev->dev_private; 1212 iowrite8(val, dev_priv->mmio + reg); 1213} 1214 1215#define nv_wait(reg, mask, val) \ 1216 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1217 1218/* PRAMIN access */ 1219static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1220{ 1221 struct drm_nouveau_private *dev_priv = dev->dev_private; 1222 return ioread32_native(dev_priv->ramin + offset); 1223} 1224 1225static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1226{ 1227 struct drm_nouveau_private *dev_priv = dev->dev_private; 1228 iowrite32_native(val, dev_priv->ramin + offset); 1229} 1230 1231/* object access */ 1232static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1233 unsigned index) 1234{ 1235 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1236} 1237 1238static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1239 unsigned index, u32 val) 1240{ 1241 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1242} 1243 1244/* 1245 * Logging 1246 * Argument d is (struct drm_device *). 1247 */ 1248#define NV_PRINTK(level, d, fmt, arg...) \ 1249 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1250 pci_name(d->pdev), ##arg) 1251#ifndef NV_DEBUG_NOTRACE 1252#define NV_DEBUG(d, fmt, arg...) do { \ 1253 if (drm_debug & DRM_UT_DRIVER) { \ 1254 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1255 __LINE__, ##arg); \ 1256 } \ 1257} while (0) 1258#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1259 if (drm_debug & DRM_UT_KMS) { \ 1260 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1261 __LINE__, ##arg); \ 1262 } \ 1263} while (0) 1264#else 1265#define NV_DEBUG(d, fmt, arg...) do { \ 1266 if (drm_debug & DRM_UT_DRIVER) \ 1267 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1268} while (0) 1269#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1270 if (drm_debug & DRM_UT_KMS) \ 1271 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1272} while (0) 1273#endif 1274#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1275#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1276#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1277#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1278#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1279 1280/* nouveau_reg_debug bitmask */ 1281enum { 1282 NOUVEAU_REG_DEBUG_MC = 0x1, 1283 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1284 NOUVEAU_REG_DEBUG_FB = 0x4, 1285 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1286 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1287 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1288 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1289 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1290 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1291 NOUVEAU_REG_DEBUG_EVO = 0x200, 1292}; 1293 1294#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1295 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1296 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1297} while (0) 1298 1299static inline bool 1300nv_two_heads(struct drm_device *dev) 1301{ 1302 struct drm_nouveau_private *dev_priv = dev->dev_private; 1303 const int impl = dev->pci_device & 0x0ff0; 1304 1305 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1306 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1307 return true; 1308 1309 return false; 1310} 1311 1312static inline bool 1313nv_gf4_disp_arch(struct drm_device *dev) 1314{ 1315 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1316} 1317 1318static inline bool 1319nv_two_reg_pll(struct drm_device *dev) 1320{ 1321 struct drm_nouveau_private *dev_priv = dev->dev_private; 1322 const int impl = dev->pci_device & 0x0ff0; 1323 1324 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1325 return true; 1326 return false; 1327} 1328 1329#define NV_SW 0x0000506e 1330#define NV_SW_DMA_SEMAPHORE 0x00000060 1331#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1332#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1333#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1334#define NV_SW_DMA_VBLSEM 0x0000018c 1335#define NV_SW_VBLSEM_OFFSET 0x00000400 1336#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1337#define NV_SW_VBLSEM_RELEASE 0x00000408 1338 1339#endif /* __NOUVEAU_DRV_H__ */ 1340