nouveau_drv.h revision a82dd49f14742e2529f79feb6360e0993277e788
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_CRYPT 2 154#define NVOBJ_ENGINE_DISPLAY 15 155#define NVOBJ_ENGINE_NR 16 156 157#define NVOBJ_FLAG_DONT_MAP (1 << 0) 158#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 159#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 160#define NVOBJ_FLAG_VM (1 << 3) 161#define NVOBJ_FLAG_VM_USER (1 << 4) 162 163#define NVOBJ_CINST_GLOBAL 0xdeadbeef 164 165struct nouveau_gpuobj { 166 struct drm_device *dev; 167 struct kref refcount; 168 struct list_head list; 169 170 void *node; 171 u32 *suspend; 172 173 uint32_t flags; 174 175 u32 size; 176 u32 pinst; 177 u32 cinst; 178 u64 vinst; 179 180 uint32_t engine; 181 uint32_t class; 182 183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 184 void *priv; 185}; 186 187struct nouveau_page_flip_state { 188 struct list_head head; 189 struct drm_pending_vblank_event *event; 190 int crtc, bpp, pitch, x, y; 191 uint64_t offset; 192}; 193 194enum nouveau_channel_mutex_class { 195 NOUVEAU_UCHANNEL_MUTEX, 196 NOUVEAU_KCHANNEL_MUTEX 197}; 198 199struct nouveau_channel { 200 struct drm_device *dev; 201 int id; 202 203 /* references to the channel data structure */ 204 struct kref ref; 205 /* users of the hardware channel resources, the hardware 206 * context will be kicked off when it reaches zero. */ 207 atomic_t users; 208 struct mutex mutex; 209 210 /* owner of this fifo */ 211 struct drm_file *file_priv; 212 /* mapping of the fifo itself */ 213 struct drm_local_map *map; 214 215 /* mapping of the regs controlling the fifo */ 216 void __iomem *user; 217 uint32_t user_get; 218 uint32_t user_put; 219 220 /* Fencing */ 221 struct { 222 /* lock protects the pending list only */ 223 spinlock_t lock; 224 struct list_head pending; 225 uint32_t sequence; 226 uint32_t sequence_ack; 227 atomic_t last_sequence_irq; 228 } fence; 229 230 /* DMA push buffer */ 231 struct nouveau_gpuobj *pushbuf; 232 struct nouveau_bo *pushbuf_bo; 233 uint32_t pushbuf_base; 234 235 /* Notifier memory */ 236 struct nouveau_bo *notifier_bo; 237 struct drm_mm notifier_heap; 238 239 /* PFIFO context */ 240 struct nouveau_gpuobj *ramfc; 241 struct nouveau_gpuobj *cache; 242 void *fifo_priv; 243 244 /* Execution engine contexts */ 245 void *engctx[NVOBJ_ENGINE_NR]; 246 247 /* NV50 VM */ 248 struct nouveau_vm *vm; 249 struct nouveau_gpuobj *vm_pd; 250 251 /* Objects */ 252 struct nouveau_gpuobj *ramin; /* Private instmem */ 253 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 254 struct nouveau_ramht *ramht; /* Hash table */ 255 256 /* GPU object info for stuff used in-kernel (mm_enabled) */ 257 uint32_t m2mf_ntfy; 258 uint32_t vram_handle; 259 uint32_t gart_handle; 260 bool accel_done; 261 262 /* Push buffer state (only for drm's channel on !mm_enabled) */ 263 struct { 264 int max; 265 int free; 266 int cur; 267 int put; 268 /* access via pushbuf_bo */ 269 270 int ib_base; 271 int ib_max; 272 int ib_free; 273 int ib_put; 274 } dma; 275 276 uint32_t sw_subchannel[8]; 277 278 struct { 279 struct nouveau_gpuobj *vblsem; 280 uint32_t vblsem_head; 281 uint32_t vblsem_offset; 282 uint32_t vblsem_rval; 283 struct list_head vbl_wait; 284 struct list_head flip; 285 } nvsw; 286 287 struct { 288 bool active; 289 char name[32]; 290 struct drm_info_list info; 291 } debugfs; 292}; 293 294struct nouveau_exec_engine { 295 void (*destroy)(struct drm_device *, int engine); 296 int (*init)(struct drm_device *, int engine); 297 int (*fini)(struct drm_device *, int engine); 298 int (*context_new)(struct nouveau_channel *, int engine); 299 void (*context_del)(struct nouveau_channel *, int engine); 300 int (*object_new)(struct nouveau_channel *, int engine, 301 u32 handle, u16 class); 302 void (*set_tile_region)(struct drm_device *dev, int i); 303 void (*tlb_flush)(struct drm_device *, int engine); 304}; 305 306struct nouveau_instmem_engine { 307 void *priv; 308 309 int (*init)(struct drm_device *dev); 310 void (*takedown)(struct drm_device *dev); 311 int (*suspend)(struct drm_device *dev); 312 void (*resume)(struct drm_device *dev); 313 314 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 315 void (*put)(struct nouveau_gpuobj *); 316 int (*map)(struct nouveau_gpuobj *); 317 void (*unmap)(struct nouveau_gpuobj *); 318 319 void (*flush)(struct drm_device *); 320}; 321 322struct nouveau_mc_engine { 323 int (*init)(struct drm_device *dev); 324 void (*takedown)(struct drm_device *dev); 325}; 326 327struct nouveau_timer_engine { 328 int (*init)(struct drm_device *dev); 329 void (*takedown)(struct drm_device *dev); 330 uint64_t (*read)(struct drm_device *dev); 331}; 332 333struct nouveau_fb_engine { 334 int num_tiles; 335 struct drm_mm tag_heap; 336 void *priv; 337 338 int (*init)(struct drm_device *dev); 339 void (*takedown)(struct drm_device *dev); 340 341 void (*init_tile_region)(struct drm_device *dev, int i, 342 uint32_t addr, uint32_t size, 343 uint32_t pitch, uint32_t flags); 344 void (*set_tile_region)(struct drm_device *dev, int i); 345 void (*free_tile_region)(struct drm_device *dev, int i); 346}; 347 348struct nouveau_fifo_engine { 349 void *priv; 350 int channels; 351 352 struct nouveau_gpuobj *playlist[2]; 353 int cur_playlist; 354 355 int (*init)(struct drm_device *); 356 void (*takedown)(struct drm_device *); 357 358 void (*disable)(struct drm_device *); 359 void (*enable)(struct drm_device *); 360 bool (*reassign)(struct drm_device *, bool enable); 361 bool (*cache_pull)(struct drm_device *dev, bool enable); 362 363 int (*channel_id)(struct drm_device *); 364 365 int (*create_context)(struct nouveau_channel *); 366 void (*destroy_context)(struct nouveau_channel *); 367 int (*load_context)(struct nouveau_channel *); 368 int (*unload_context)(struct drm_device *); 369 void (*tlb_flush)(struct drm_device *dev); 370}; 371 372struct nouveau_display_engine { 373 void *priv; 374 int (*early_init)(struct drm_device *); 375 void (*late_takedown)(struct drm_device *); 376 int (*create)(struct drm_device *); 377 int (*init)(struct drm_device *); 378 void (*destroy)(struct drm_device *); 379}; 380 381struct nouveau_gpio_engine { 382 void *priv; 383 384 int (*init)(struct drm_device *); 385 void (*takedown)(struct drm_device *); 386 387 int (*get)(struct drm_device *, enum dcb_gpio_tag); 388 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 389 390 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 391 void (*)(void *, int), void *); 392 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 393 void (*)(void *, int), void *); 394 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 395}; 396 397struct nouveau_pm_voltage_level { 398 u8 voltage; 399 u8 vid; 400}; 401 402struct nouveau_pm_voltage { 403 bool supported; 404 u8 vid_mask; 405 406 struct nouveau_pm_voltage_level *level; 407 int nr_level; 408}; 409 410#define NOUVEAU_PM_MAX_LEVEL 8 411struct nouveau_pm_level { 412 struct device_attribute dev_attr; 413 char name[32]; 414 int id; 415 416 u32 core; 417 u32 memory; 418 u32 shader; 419 u32 unk05; 420 421 u8 voltage; 422 u8 fanspeed; 423 424 u16 memscript; 425}; 426 427struct nouveau_pm_temp_sensor_constants { 428 u16 offset_constant; 429 s16 offset_mult; 430 u16 offset_div; 431 u16 slope_mult; 432 u16 slope_div; 433}; 434 435struct nouveau_pm_threshold_temp { 436 s16 critical; 437 s16 down_clock; 438 s16 fan_boost; 439}; 440 441struct nouveau_pm_memtiming { 442 u32 reg_100220; 443 u32 reg_100224; 444 u32 reg_100228; 445 u32 reg_10022c; 446 u32 reg_100230; 447 u32 reg_100234; 448 u32 reg_100238; 449 u32 reg_10023c; 450 u32 reg_100240; 451}; 452 453struct nouveau_pm_memtimings { 454 bool supported; 455 struct nouveau_pm_memtiming *timing; 456 int nr_timing; 457}; 458 459struct nouveau_pm_engine { 460 struct nouveau_pm_voltage voltage; 461 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 462 int nr_perflvl; 463 struct nouveau_pm_memtimings memtimings; 464 struct nouveau_pm_temp_sensor_constants sensor_constants; 465 struct nouveau_pm_threshold_temp threshold_temp; 466 467 struct nouveau_pm_level boot; 468 struct nouveau_pm_level *cur; 469 470 struct device *hwmon; 471 struct notifier_block acpi_nb; 472 473 int (*clock_get)(struct drm_device *, u32 id); 474 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 475 u32 id, int khz); 476 void (*clock_set)(struct drm_device *, void *); 477 int (*voltage_get)(struct drm_device *); 478 int (*voltage_set)(struct drm_device *, int voltage); 479 int (*fanspeed_get)(struct drm_device *); 480 int (*fanspeed_set)(struct drm_device *, int fanspeed); 481 int (*temp_get)(struct drm_device *); 482}; 483 484struct nouveau_vram_engine { 485 int (*init)(struct drm_device *); 486 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 487 u32 type, struct nouveau_mem **); 488 void (*put)(struct drm_device *, struct nouveau_mem **); 489 490 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 491}; 492 493struct nouveau_engine { 494 struct nouveau_instmem_engine instmem; 495 struct nouveau_mc_engine mc; 496 struct nouveau_timer_engine timer; 497 struct nouveau_fb_engine fb; 498 struct nouveau_fifo_engine fifo; 499 struct nouveau_display_engine display; 500 struct nouveau_gpio_engine gpio; 501 struct nouveau_pm_engine pm; 502 struct nouveau_vram_engine vram; 503}; 504 505struct nouveau_pll_vals { 506 union { 507 struct { 508#ifdef __BIG_ENDIAN 509 uint8_t N1, M1, N2, M2; 510#else 511 uint8_t M1, N1, M2, N2; 512#endif 513 }; 514 struct { 515 uint16_t NM1, NM2; 516 } __attribute__((packed)); 517 }; 518 int log2P; 519 520 int refclk; 521}; 522 523enum nv04_fp_display_regs { 524 FP_DISPLAY_END, 525 FP_TOTAL, 526 FP_CRTC, 527 FP_SYNC_START, 528 FP_SYNC_END, 529 FP_VALID_START, 530 FP_VALID_END 531}; 532 533struct nv04_crtc_reg { 534 unsigned char MiscOutReg; 535 uint8_t CRTC[0xa0]; 536 uint8_t CR58[0x10]; 537 uint8_t Sequencer[5]; 538 uint8_t Graphics[9]; 539 uint8_t Attribute[21]; 540 unsigned char DAC[768]; 541 542 /* PCRTC regs */ 543 uint32_t fb_start; 544 uint32_t crtc_cfg; 545 uint32_t cursor_cfg; 546 uint32_t gpio_ext; 547 uint32_t crtc_830; 548 uint32_t crtc_834; 549 uint32_t crtc_850; 550 uint32_t crtc_eng_ctrl; 551 552 /* PRAMDAC regs */ 553 uint32_t nv10_cursync; 554 struct nouveau_pll_vals pllvals; 555 uint32_t ramdac_gen_ctrl; 556 uint32_t ramdac_630; 557 uint32_t ramdac_634; 558 uint32_t tv_setup; 559 uint32_t tv_vtotal; 560 uint32_t tv_vskew; 561 uint32_t tv_vsync_delay; 562 uint32_t tv_htotal; 563 uint32_t tv_hskew; 564 uint32_t tv_hsync_delay; 565 uint32_t tv_hsync_delay2; 566 uint32_t fp_horiz_regs[7]; 567 uint32_t fp_vert_regs[7]; 568 uint32_t dither; 569 uint32_t fp_control; 570 uint32_t dither_regs[6]; 571 uint32_t fp_debug_0; 572 uint32_t fp_debug_1; 573 uint32_t fp_debug_2; 574 uint32_t fp_margin_color; 575 uint32_t ramdac_8c0; 576 uint32_t ramdac_a20; 577 uint32_t ramdac_a24; 578 uint32_t ramdac_a34; 579 uint32_t ctv_regs[38]; 580}; 581 582struct nv04_output_reg { 583 uint32_t output; 584 int head; 585}; 586 587struct nv04_mode_state { 588 struct nv04_crtc_reg crtc_reg[2]; 589 uint32_t pllsel; 590 uint32_t sel_clk; 591}; 592 593enum nouveau_card_type { 594 NV_04 = 0x00, 595 NV_10 = 0x10, 596 NV_20 = 0x20, 597 NV_30 = 0x30, 598 NV_40 = 0x40, 599 NV_50 = 0x50, 600 NV_C0 = 0xc0, 601}; 602 603struct drm_nouveau_private { 604 struct drm_device *dev; 605 606 /* the card type, takes NV_* as values */ 607 enum nouveau_card_type card_type; 608 /* exact chipset, derived from NV_PMC_BOOT_0 */ 609 int chipset; 610 int stepping; 611 int flags; 612 613 void __iomem *mmio; 614 615 spinlock_t ramin_lock; 616 void __iomem *ramin; 617 u32 ramin_size; 618 u32 ramin_base; 619 bool ramin_available; 620 struct drm_mm ramin_heap; 621 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 622 struct list_head gpuobj_list; 623 struct list_head classes; 624 625 struct nouveau_bo *vga_ram; 626 627 /* interrupt handling */ 628 void (*irq_handler[32])(struct drm_device *); 629 bool msi_enabled; 630 631 struct list_head vbl_waiting; 632 633 struct { 634 struct drm_global_reference mem_global_ref; 635 struct ttm_bo_global_ref bo_global_ref; 636 struct ttm_bo_device bdev; 637 atomic_t validate_sequence; 638 } ttm; 639 640 struct { 641 spinlock_t lock; 642 struct drm_mm heap; 643 struct nouveau_bo *bo; 644 } fence; 645 646 struct { 647 spinlock_t lock; 648 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 649 } channels; 650 651 struct nouveau_engine engine; 652 struct nouveau_channel *channel; 653 654 /* For PFIFO and PGRAPH. */ 655 spinlock_t context_switch_lock; 656 657 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 658 spinlock_t vm_lock; 659 660 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 661 struct nouveau_ramht *ramht; 662 struct nouveau_gpuobj *ramfc; 663 struct nouveau_gpuobj *ramro; 664 665 uint32_t ramin_rsvd_vram; 666 667 struct { 668 enum { 669 NOUVEAU_GART_NONE = 0, 670 NOUVEAU_GART_AGP, /* AGP */ 671 NOUVEAU_GART_PDMA, /* paged dma object */ 672 NOUVEAU_GART_HW /* on-chip gart/vm */ 673 } type; 674 uint64_t aper_base; 675 uint64_t aper_size; 676 uint64_t aper_free; 677 678 struct ttm_backend_func *func; 679 680 struct { 681 struct page *page; 682 dma_addr_t addr; 683 } dummy; 684 685 struct nouveau_gpuobj *sg_ctxdma; 686 } gart_info; 687 688 /* nv10-nv40 tiling regions */ 689 struct { 690 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 691 spinlock_t lock; 692 } tile; 693 694 /* VRAM/fb configuration */ 695 uint64_t vram_size; 696 uint64_t vram_sys_base; 697 u32 vram_rblock_size; 698 699 uint64_t fb_phys; 700 uint64_t fb_available_size; 701 uint64_t fb_mappable_pages; 702 uint64_t fb_aper_free; 703 int fb_mtrr; 704 705 /* BAR control (NV50-) */ 706 struct nouveau_vm *bar1_vm; 707 struct nouveau_vm *bar3_vm; 708 709 /* G8x/G9x virtual address space */ 710 struct nouveau_vm *chan_vm; 711 712 struct nvbios vbios; 713 714 struct nv04_mode_state mode_reg; 715 struct nv04_mode_state saved_reg; 716 uint32_t saved_vga_font[4][16384]; 717 uint32_t crtc_owner; 718 uint32_t dac_users[4]; 719 720 struct backlight_device *backlight; 721 722 struct { 723 struct dentry *channel_root; 724 } debugfs; 725 726 struct nouveau_fbdev *nfbdev; 727 struct apertures_struct *apertures; 728}; 729 730static inline struct drm_nouveau_private * 731nouveau_private(struct drm_device *dev) 732{ 733 return dev->dev_private; 734} 735 736static inline struct drm_nouveau_private * 737nouveau_bdev(struct ttm_bo_device *bd) 738{ 739 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 740} 741 742static inline int 743nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 744{ 745 struct nouveau_bo *prev; 746 747 if (!pnvbo) 748 return -EINVAL; 749 prev = *pnvbo; 750 751 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 752 if (prev) { 753 struct ttm_buffer_object *bo = &prev->bo; 754 755 ttm_bo_unref(&bo); 756 } 757 758 return 0; 759} 760 761/* nouveau_drv.c */ 762extern int nouveau_agpmode; 763extern int nouveau_duallink; 764extern int nouveau_uscript_lvds; 765extern int nouveau_uscript_tmds; 766extern int nouveau_vram_pushbuf; 767extern int nouveau_vram_notify; 768extern int nouveau_fbpercrtc; 769extern int nouveau_tv_disable; 770extern char *nouveau_tv_norm; 771extern int nouveau_reg_debug; 772extern char *nouveau_vbios; 773extern int nouveau_ignorelid; 774extern int nouveau_nofbaccel; 775extern int nouveau_noaccel; 776extern int nouveau_force_post; 777extern int nouveau_override_conntype; 778extern char *nouveau_perflvl; 779extern int nouveau_perflvl_wr; 780extern int nouveau_msi; 781 782extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 783extern int nouveau_pci_resume(struct pci_dev *pdev); 784 785/* nouveau_state.c */ 786extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 787extern int nouveau_load(struct drm_device *, unsigned long flags); 788extern int nouveau_firstopen(struct drm_device *); 789extern void nouveau_lastclose(struct drm_device *); 790extern int nouveau_unload(struct drm_device *); 791extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 792 struct drm_file *); 793extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 794 struct drm_file *); 795extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 796 uint32_t reg, uint32_t mask, uint32_t val); 797extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 798 uint32_t reg, uint32_t mask, uint32_t val); 799extern bool nouveau_wait_for_idle(struct drm_device *); 800extern int nouveau_card_init(struct drm_device *); 801 802/* nouveau_mem.c */ 803extern int nouveau_mem_vram_init(struct drm_device *); 804extern void nouveau_mem_vram_fini(struct drm_device *); 805extern int nouveau_mem_gart_init(struct drm_device *); 806extern void nouveau_mem_gart_fini(struct drm_device *); 807extern int nouveau_mem_init_agp(struct drm_device *); 808extern int nouveau_mem_reset_agp(struct drm_device *); 809extern void nouveau_mem_close(struct drm_device *); 810extern int nouveau_mem_detect(struct drm_device *); 811extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 812extern struct nouveau_tile_reg *nv10_mem_set_tiling( 813 struct drm_device *dev, uint32_t addr, uint32_t size, 814 uint32_t pitch, uint32_t flags); 815extern void nv10_mem_put_tile_region(struct drm_device *dev, 816 struct nouveau_tile_reg *tile, 817 struct nouveau_fence *fence); 818extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 819extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 820 821/* nouveau_notifier.c */ 822extern int nouveau_notifier_init_channel(struct nouveau_channel *); 823extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 824extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 825 int cout, uint32_t start, uint32_t end, 826 uint32_t *offset); 827extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 828extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 829 struct drm_file *); 830extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 831 struct drm_file *); 832 833/* nouveau_channel.c */ 834extern struct drm_ioctl_desc nouveau_ioctls[]; 835extern int nouveau_max_ioctl; 836extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 837extern int nouveau_channel_alloc(struct drm_device *dev, 838 struct nouveau_channel **chan, 839 struct drm_file *file_priv, 840 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 841extern struct nouveau_channel * 842nouveau_channel_get_unlocked(struct nouveau_channel *); 843extern struct nouveau_channel * 844nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 845extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 846extern void nouveau_channel_put(struct nouveau_channel **); 847extern void nouveau_channel_ref(struct nouveau_channel *chan, 848 struct nouveau_channel **pchan); 849extern void nouveau_channel_idle(struct nouveau_channel *chan); 850 851/* nouveau_object.c */ 852#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 853 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 854 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 855} while (0) 856 857#define NVOBJ_ENGINE_DEL(d, e) do { \ 858 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 859 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 860} while (0) 861 862#define NVOBJ_CLASS(d, c, e) do { \ 863 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 864 if (ret) \ 865 return ret; \ 866} while (0) 867 868#define NVOBJ_MTHD(d, c, m, e) do { \ 869 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 870 if (ret) \ 871 return ret; \ 872} while (0) 873 874extern int nouveau_gpuobj_early_init(struct drm_device *); 875extern int nouveau_gpuobj_init(struct drm_device *); 876extern void nouveau_gpuobj_takedown(struct drm_device *); 877extern int nouveau_gpuobj_suspend(struct drm_device *dev); 878extern void nouveau_gpuobj_resume(struct drm_device *dev); 879extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 880extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 881 int (*exec)(struct nouveau_channel *, 882 u32 class, u32 mthd, u32 data)); 883extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 884extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 885extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 886 uint32_t vram_h, uint32_t tt_h); 887extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 888extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 889 uint32_t size, int align, uint32_t flags, 890 struct nouveau_gpuobj **); 891extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 892 struct nouveau_gpuobj **); 893extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 894 u32 size, u32 flags, 895 struct nouveau_gpuobj **); 896extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 897 uint64_t offset, uint64_t size, int access, 898 int target, struct nouveau_gpuobj **); 899extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 900extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 901 u64 size, int target, int access, u32 type, 902 u32 comp, struct nouveau_gpuobj **pobj); 903extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 904 int class, u64 base, u64 size, int target, 905 int access, u32 type, u32 comp); 906extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 907 struct drm_file *); 908extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 909 struct drm_file *); 910 911/* nouveau_irq.c */ 912extern int nouveau_irq_init(struct drm_device *); 913extern void nouveau_irq_fini(struct drm_device *); 914extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 915extern void nouveau_irq_register(struct drm_device *, int status_bit, 916 void (*)(struct drm_device *)); 917extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 918extern void nouveau_irq_preinstall(struct drm_device *); 919extern int nouveau_irq_postinstall(struct drm_device *); 920extern void nouveau_irq_uninstall(struct drm_device *); 921 922/* nouveau_sgdma.c */ 923extern int nouveau_sgdma_init(struct drm_device *); 924extern void nouveau_sgdma_takedown(struct drm_device *); 925extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 926 uint32_t offset); 927extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 928 929/* nouveau_debugfs.c */ 930#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 931extern int nouveau_debugfs_init(struct drm_minor *); 932extern void nouveau_debugfs_takedown(struct drm_minor *); 933extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 934extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 935#else 936static inline int 937nouveau_debugfs_init(struct drm_minor *minor) 938{ 939 return 0; 940} 941 942static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 943{ 944} 945 946static inline int 947nouveau_debugfs_channel_init(struct nouveau_channel *chan) 948{ 949 return 0; 950} 951 952static inline void 953nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 954{ 955} 956#endif 957 958/* nouveau_dma.c */ 959extern void nouveau_dma_pre_init(struct nouveau_channel *); 960extern int nouveau_dma_init(struct nouveau_channel *); 961extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 962 963/* nouveau_acpi.c */ 964#define ROM_BIOS_PAGE 4096 965#if defined(CONFIG_ACPI) 966void nouveau_register_dsm_handler(void); 967void nouveau_unregister_dsm_handler(void); 968int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 969bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 970int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 971#else 972static inline void nouveau_register_dsm_handler(void) {} 973static inline void nouveau_unregister_dsm_handler(void) {} 974static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 975static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 976static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 977#endif 978 979/* nouveau_backlight.c */ 980#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 981extern int nouveau_backlight_init(struct drm_connector *); 982extern void nouveau_backlight_exit(struct drm_connector *); 983#else 984static inline int nouveau_backlight_init(struct drm_connector *dev) 985{ 986 return 0; 987} 988 989static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 990#endif 991 992/* nouveau_bios.c */ 993extern int nouveau_bios_init(struct drm_device *); 994extern void nouveau_bios_takedown(struct drm_device *dev); 995extern int nouveau_run_vbios_init(struct drm_device *); 996extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 997 struct dcb_entry *); 998extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 999 enum dcb_gpio_tag); 1000extern struct dcb_connector_table_entry * 1001nouveau_bios_connector_entry(struct drm_device *, int index); 1002extern u32 get_pll_register(struct drm_device *, enum pll_types); 1003extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1004 struct pll_lims *); 1005extern int nouveau_bios_run_display_table(struct drm_device *, 1006 struct dcb_entry *, 1007 uint32_t script, int pxclk); 1008extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1009 int *length); 1010extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1011extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1012extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1013 bool *dl, bool *if_is_24bit); 1014extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1015 int head, int pxclk); 1016extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1017 enum LVDS_script, int pxclk); 1018 1019/* nouveau_ttm.c */ 1020int nouveau_ttm_global_init(struct drm_nouveau_private *); 1021void nouveau_ttm_global_release(struct drm_nouveau_private *); 1022int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1023 1024/* nouveau_dp.c */ 1025int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1026 uint8_t *data, int data_nr); 1027bool nouveau_dp_detect(struct drm_encoder *); 1028bool nouveau_dp_link_train(struct drm_encoder *); 1029 1030/* nv04_fb.c */ 1031extern int nv04_fb_init(struct drm_device *); 1032extern void nv04_fb_takedown(struct drm_device *); 1033 1034/* nv10_fb.c */ 1035extern int nv10_fb_init(struct drm_device *); 1036extern void nv10_fb_takedown(struct drm_device *); 1037extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1038 uint32_t addr, uint32_t size, 1039 uint32_t pitch, uint32_t flags); 1040extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1041extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1042 1043/* nv30_fb.c */ 1044extern int nv30_fb_init(struct drm_device *); 1045extern void nv30_fb_takedown(struct drm_device *); 1046extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1047 uint32_t addr, uint32_t size, 1048 uint32_t pitch, uint32_t flags); 1049extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1050 1051/* nv40_fb.c */ 1052extern int nv40_fb_init(struct drm_device *); 1053extern void nv40_fb_takedown(struct drm_device *); 1054extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1055 1056/* nv50_fb.c */ 1057extern int nv50_fb_init(struct drm_device *); 1058extern void nv50_fb_takedown(struct drm_device *); 1059extern void nv50_fb_vm_trap(struct drm_device *, int display); 1060 1061/* nvc0_fb.c */ 1062extern int nvc0_fb_init(struct drm_device *); 1063extern void nvc0_fb_takedown(struct drm_device *); 1064 1065/* nv04_fifo.c */ 1066extern int nv04_fifo_init(struct drm_device *); 1067extern void nv04_fifo_fini(struct drm_device *); 1068extern void nv04_fifo_disable(struct drm_device *); 1069extern void nv04_fifo_enable(struct drm_device *); 1070extern bool nv04_fifo_reassign(struct drm_device *, bool); 1071extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1072extern int nv04_fifo_channel_id(struct drm_device *); 1073extern int nv04_fifo_create_context(struct nouveau_channel *); 1074extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1075extern int nv04_fifo_load_context(struct nouveau_channel *); 1076extern int nv04_fifo_unload_context(struct drm_device *); 1077extern void nv04_fifo_isr(struct drm_device *); 1078 1079/* nv10_fifo.c */ 1080extern int nv10_fifo_init(struct drm_device *); 1081extern int nv10_fifo_channel_id(struct drm_device *); 1082extern int nv10_fifo_create_context(struct nouveau_channel *); 1083extern int nv10_fifo_load_context(struct nouveau_channel *); 1084extern int nv10_fifo_unload_context(struct drm_device *); 1085 1086/* nv40_fifo.c */ 1087extern int nv40_fifo_init(struct drm_device *); 1088extern int nv40_fifo_create_context(struct nouveau_channel *); 1089extern int nv40_fifo_load_context(struct nouveau_channel *); 1090extern int nv40_fifo_unload_context(struct drm_device *); 1091 1092/* nv50_fifo.c */ 1093extern int nv50_fifo_init(struct drm_device *); 1094extern void nv50_fifo_takedown(struct drm_device *); 1095extern int nv50_fifo_channel_id(struct drm_device *); 1096extern int nv50_fifo_create_context(struct nouveau_channel *); 1097extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1098extern int nv50_fifo_load_context(struct nouveau_channel *); 1099extern int nv50_fifo_unload_context(struct drm_device *); 1100extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1101 1102/* nvc0_fifo.c */ 1103extern int nvc0_fifo_init(struct drm_device *); 1104extern void nvc0_fifo_takedown(struct drm_device *); 1105extern void nvc0_fifo_disable(struct drm_device *); 1106extern void nvc0_fifo_enable(struct drm_device *); 1107extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1108extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1109extern int nvc0_fifo_channel_id(struct drm_device *); 1110extern int nvc0_fifo_create_context(struct nouveau_channel *); 1111extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1112extern int nvc0_fifo_load_context(struct nouveau_channel *); 1113extern int nvc0_fifo_unload_context(struct drm_device *); 1114 1115/* nv04_graph.c */ 1116extern int nv04_graph_create(struct drm_device *); 1117extern void nv04_graph_fifo_access(struct drm_device *, bool); 1118extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1119extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1120 u32 class, u32 mthd, u32 data); 1121extern struct nouveau_bitfield nv04_graph_nsource[]; 1122 1123/* nv10_graph.c */ 1124extern int nv10_graph_create(struct drm_device *); 1125extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1126extern struct nouveau_bitfield nv10_graph_intr[]; 1127extern struct nouveau_bitfield nv10_graph_nstatus[]; 1128 1129/* nv20_graph.c */ 1130extern int nv20_graph_create(struct drm_device *); 1131 1132/* nv40_graph.c */ 1133extern int nv40_graph_create(struct drm_device *); 1134extern void nv40_grctx_init(struct nouveau_grctx *); 1135 1136/* nv50_graph.c */ 1137extern int nv50_graph_create(struct drm_device *); 1138extern int nv50_grctx_init(struct nouveau_grctx *); 1139extern struct nouveau_enum nv50_data_error_names[]; 1140 1141/* nvc0_graph.c */ 1142extern int nvc0_graph_create(struct drm_device *); 1143 1144/* nv84_crypt.c */ 1145extern int nv84_crypt_create(struct drm_device *); 1146 1147/* nv04_instmem.c */ 1148extern int nv04_instmem_init(struct drm_device *); 1149extern void nv04_instmem_takedown(struct drm_device *); 1150extern int nv04_instmem_suspend(struct drm_device *); 1151extern void nv04_instmem_resume(struct drm_device *); 1152extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1153extern void nv04_instmem_put(struct nouveau_gpuobj *); 1154extern int nv04_instmem_map(struct nouveau_gpuobj *); 1155extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1156extern void nv04_instmem_flush(struct drm_device *); 1157 1158/* nv50_instmem.c */ 1159extern int nv50_instmem_init(struct drm_device *); 1160extern void nv50_instmem_takedown(struct drm_device *); 1161extern int nv50_instmem_suspend(struct drm_device *); 1162extern void nv50_instmem_resume(struct drm_device *); 1163extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1164extern void nv50_instmem_put(struct nouveau_gpuobj *); 1165extern int nv50_instmem_map(struct nouveau_gpuobj *); 1166extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1167extern void nv50_instmem_flush(struct drm_device *); 1168extern void nv84_instmem_flush(struct drm_device *); 1169 1170/* nvc0_instmem.c */ 1171extern int nvc0_instmem_init(struct drm_device *); 1172extern void nvc0_instmem_takedown(struct drm_device *); 1173extern int nvc0_instmem_suspend(struct drm_device *); 1174extern void nvc0_instmem_resume(struct drm_device *); 1175 1176/* nv04_mc.c */ 1177extern int nv04_mc_init(struct drm_device *); 1178extern void nv04_mc_takedown(struct drm_device *); 1179 1180/* nv40_mc.c */ 1181extern int nv40_mc_init(struct drm_device *); 1182extern void nv40_mc_takedown(struct drm_device *); 1183 1184/* nv50_mc.c */ 1185extern int nv50_mc_init(struct drm_device *); 1186extern void nv50_mc_takedown(struct drm_device *); 1187 1188/* nv04_timer.c */ 1189extern int nv04_timer_init(struct drm_device *); 1190extern uint64_t nv04_timer_read(struct drm_device *); 1191extern void nv04_timer_takedown(struct drm_device *); 1192 1193extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1194 unsigned long arg); 1195 1196/* nv04_dac.c */ 1197extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1198extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1199extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1200extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1201extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1202 1203/* nv04_dfp.c */ 1204extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1205extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1206extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1207 int head, bool dl); 1208extern void nv04_dfp_disable(struct drm_device *dev, int head); 1209extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1210 1211/* nv04_tv.c */ 1212extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1213extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1214 1215/* nv17_tv.c */ 1216extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1217 1218/* nv04_display.c */ 1219extern int nv04_display_early_init(struct drm_device *); 1220extern void nv04_display_late_takedown(struct drm_device *); 1221extern int nv04_display_create(struct drm_device *); 1222extern int nv04_display_init(struct drm_device *); 1223extern void nv04_display_destroy(struct drm_device *); 1224 1225/* nv04_crtc.c */ 1226extern int nv04_crtc_create(struct drm_device *, int index); 1227 1228/* nouveau_bo.c */ 1229extern struct ttm_bo_driver nouveau_bo_driver; 1230extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1231 int size, int align, uint32_t flags, 1232 uint32_t tile_mode, uint32_t tile_flags, 1233 struct nouveau_bo **); 1234extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1235extern int nouveau_bo_unpin(struct nouveau_bo *); 1236extern int nouveau_bo_map(struct nouveau_bo *); 1237extern void nouveau_bo_unmap(struct nouveau_bo *); 1238extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1239 uint32_t busy); 1240extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1241extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1242extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1243extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1244extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1245extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1246 bool no_wait_reserve, bool no_wait_gpu); 1247 1248/* nouveau_fence.c */ 1249struct nouveau_fence; 1250extern int nouveau_fence_init(struct drm_device *); 1251extern void nouveau_fence_fini(struct drm_device *); 1252extern int nouveau_fence_channel_init(struct nouveau_channel *); 1253extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1254extern void nouveau_fence_update(struct nouveau_channel *); 1255extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1256 bool emit); 1257extern int nouveau_fence_emit(struct nouveau_fence *); 1258extern void nouveau_fence_work(struct nouveau_fence *fence, 1259 void (*work)(void *priv, bool signalled), 1260 void *priv); 1261struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1262 1263extern bool __nouveau_fence_signalled(void *obj, void *arg); 1264extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1265extern int __nouveau_fence_flush(void *obj, void *arg); 1266extern void __nouveau_fence_unref(void **obj); 1267extern void *__nouveau_fence_ref(void *obj); 1268 1269static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1270{ 1271 return __nouveau_fence_signalled(obj, NULL); 1272} 1273static inline int 1274nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1275{ 1276 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1277} 1278extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1279static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1280{ 1281 return __nouveau_fence_flush(obj, NULL); 1282} 1283static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1284{ 1285 __nouveau_fence_unref((void **)obj); 1286} 1287static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1288{ 1289 return __nouveau_fence_ref(obj); 1290} 1291 1292/* nouveau_gem.c */ 1293extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1294 int size, int align, uint32_t domain, 1295 uint32_t tile_mode, uint32_t tile_flags, 1296 struct nouveau_bo **); 1297extern int nouveau_gem_object_new(struct drm_gem_object *); 1298extern void nouveau_gem_object_del(struct drm_gem_object *); 1299extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1300 struct drm_file *); 1301extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1302 struct drm_file *); 1303extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1304 struct drm_file *); 1305extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1306 struct drm_file *); 1307extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1308 struct drm_file *); 1309 1310/* nouveau_display.c */ 1311int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1312void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1313int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1314 struct drm_pending_vblank_event *event); 1315int nouveau_finish_page_flip(struct nouveau_channel *, 1316 struct nouveau_page_flip_state *); 1317 1318/* nv10_gpio.c */ 1319int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1320int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1321 1322/* nv50_gpio.c */ 1323int nv50_gpio_init(struct drm_device *dev); 1324void nv50_gpio_fini(struct drm_device *dev); 1325int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1326int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1327int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1328 void (*)(void *, int), void *); 1329void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1330 void (*)(void *, int), void *); 1331bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1332 1333/* nv50_calc. */ 1334int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1335 int *N1, int *M1, int *N2, int *M2, int *P); 1336int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1337 int clk, int *N, int *fN, int *M, int *P); 1338 1339#ifndef ioread32_native 1340#ifdef __BIG_ENDIAN 1341#define ioread16_native ioread16be 1342#define iowrite16_native iowrite16be 1343#define ioread32_native ioread32be 1344#define iowrite32_native iowrite32be 1345#else /* def __BIG_ENDIAN */ 1346#define ioread16_native ioread16 1347#define iowrite16_native iowrite16 1348#define ioread32_native ioread32 1349#define iowrite32_native iowrite32 1350#endif /* def __BIG_ENDIAN else */ 1351#endif /* !ioread32_native */ 1352 1353/* channel control reg access */ 1354static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1355{ 1356 return ioread32_native(chan->user + reg); 1357} 1358 1359static inline void nvchan_wr32(struct nouveau_channel *chan, 1360 unsigned reg, u32 val) 1361{ 1362 iowrite32_native(val, chan->user + reg); 1363} 1364 1365/* register access */ 1366static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1367{ 1368 struct drm_nouveau_private *dev_priv = dev->dev_private; 1369 return ioread32_native(dev_priv->mmio + reg); 1370} 1371 1372static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1373{ 1374 struct drm_nouveau_private *dev_priv = dev->dev_private; 1375 iowrite32_native(val, dev_priv->mmio + reg); 1376} 1377 1378static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1379{ 1380 u32 tmp = nv_rd32(dev, reg); 1381 nv_wr32(dev, reg, (tmp & ~mask) | val); 1382 return tmp; 1383} 1384 1385static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1386{ 1387 struct drm_nouveau_private *dev_priv = dev->dev_private; 1388 return ioread8(dev_priv->mmio + reg); 1389} 1390 1391static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1392{ 1393 struct drm_nouveau_private *dev_priv = dev->dev_private; 1394 iowrite8(val, dev_priv->mmio + reg); 1395} 1396 1397#define nv_wait(dev, reg, mask, val) \ 1398 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1399#define nv_wait_ne(dev, reg, mask, val) \ 1400 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1401 1402/* PRAMIN access */ 1403static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1404{ 1405 struct drm_nouveau_private *dev_priv = dev->dev_private; 1406 return ioread32_native(dev_priv->ramin + offset); 1407} 1408 1409static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1410{ 1411 struct drm_nouveau_private *dev_priv = dev->dev_private; 1412 iowrite32_native(val, dev_priv->ramin + offset); 1413} 1414 1415/* object access */ 1416extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1417extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1418 1419/* 1420 * Logging 1421 * Argument d is (struct drm_device *). 1422 */ 1423#define NV_PRINTK(level, d, fmt, arg...) \ 1424 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1425 pci_name(d->pdev), ##arg) 1426#ifndef NV_DEBUG_NOTRACE 1427#define NV_DEBUG(d, fmt, arg...) do { \ 1428 if (drm_debug & DRM_UT_DRIVER) { \ 1429 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1430 __LINE__, ##arg); \ 1431 } \ 1432} while (0) 1433#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1434 if (drm_debug & DRM_UT_KMS) { \ 1435 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1436 __LINE__, ##arg); \ 1437 } \ 1438} while (0) 1439#else 1440#define NV_DEBUG(d, fmt, arg...) do { \ 1441 if (drm_debug & DRM_UT_DRIVER) \ 1442 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1443} while (0) 1444#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1445 if (drm_debug & DRM_UT_KMS) \ 1446 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1447} while (0) 1448#endif 1449#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1450#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1451#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1452#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1453#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1454 1455/* nouveau_reg_debug bitmask */ 1456enum { 1457 NOUVEAU_REG_DEBUG_MC = 0x1, 1458 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1459 NOUVEAU_REG_DEBUG_FB = 0x4, 1460 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1461 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1462 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1463 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1464 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1465 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1466 NOUVEAU_REG_DEBUG_EVO = 0x200, 1467}; 1468 1469#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1470 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1471 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1472} while (0) 1473 1474static inline bool 1475nv_two_heads(struct drm_device *dev) 1476{ 1477 struct drm_nouveau_private *dev_priv = dev->dev_private; 1478 const int impl = dev->pci_device & 0x0ff0; 1479 1480 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1481 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1482 return true; 1483 1484 return false; 1485} 1486 1487static inline bool 1488nv_gf4_disp_arch(struct drm_device *dev) 1489{ 1490 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1491} 1492 1493static inline bool 1494nv_two_reg_pll(struct drm_device *dev) 1495{ 1496 struct drm_nouveau_private *dev_priv = dev->dev_private; 1497 const int impl = dev->pci_device & 0x0ff0; 1498 1499 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1500 return true; 1501 return false; 1502} 1503 1504static inline bool 1505nv_match_device(struct drm_device *dev, unsigned device, 1506 unsigned sub_vendor, unsigned sub_device) 1507{ 1508 return dev->pdev->device == device && 1509 dev->pdev->subsystem_vendor == sub_vendor && 1510 dev->pdev->subsystem_device == sub_device; 1511} 1512 1513static inline void * 1514nv_engine(struct drm_device *dev, int engine) 1515{ 1516 struct drm_nouveau_private *dev_priv = dev->dev_private; 1517 return (void *)dev_priv->eng[engine]; 1518} 1519 1520/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1521 * helpful to determine a number of other hardware features 1522 */ 1523static inline int 1524nv44_graph_class(struct drm_device *dev) 1525{ 1526 struct drm_nouveau_private *dev_priv = dev->dev_private; 1527 1528 if ((dev_priv->chipset & 0xf0) == 0x60) 1529 return 1; 1530 1531 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1532} 1533 1534/* memory type/access flags, do not match hardware values */ 1535#define NV_MEM_ACCESS_RO 1 1536#define NV_MEM_ACCESS_WO 2 1537#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1538#define NV_MEM_ACCESS_SYS 4 1539#define NV_MEM_ACCESS_VM 8 1540 1541#define NV_MEM_TARGET_VRAM 0 1542#define NV_MEM_TARGET_PCI 1 1543#define NV_MEM_TARGET_PCI_NOSNOOP 2 1544#define NV_MEM_TARGET_VM 3 1545#define NV_MEM_TARGET_GART 4 1546 1547#define NV_MEM_TYPE_VM 0x7f 1548#define NV_MEM_COMP_VM 0x03 1549 1550/* NV_SW object class */ 1551#define NV_SW 0x0000506e 1552#define NV_SW_DMA_SEMAPHORE 0x00000060 1553#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1554#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1555#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1556#define NV_SW_YIELD 0x00000080 1557#define NV_SW_DMA_VBLSEM 0x0000018c 1558#define NV_SW_VBLSEM_OFFSET 0x00000400 1559#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1560#define NV_SW_VBLSEM_RELEASE 0x00000408 1561#define NV_SW_PAGE_FLIP 0x00000500 1562 1563#endif /* __NOUVEAU_DRV_H__ */ 1564