nouveau_drv.h revision aba99a8400e0b1ca9e6306e3a71013cc7a25bc29
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_CRYPT 2 154#define NVOBJ_ENGINE_COPY0 3 155#define NVOBJ_ENGINE_COPY1 4 156#define NVOBJ_ENGINE_MPEG 5 157#define NVOBJ_ENGINE_DISPLAY 15 158#define NVOBJ_ENGINE_NR 16 159 160#define NVOBJ_FLAG_DONT_MAP (1 << 0) 161#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 162#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 163#define NVOBJ_FLAG_VM (1 << 3) 164#define NVOBJ_FLAG_VM_USER (1 << 4) 165 166#define NVOBJ_CINST_GLOBAL 0xdeadbeef 167 168struct nouveau_gpuobj { 169 struct drm_device *dev; 170 struct kref refcount; 171 struct list_head list; 172 173 void *node; 174 u32 *suspend; 175 176 uint32_t flags; 177 178 u32 size; 179 u32 pinst; 180 u32 cinst; 181 u64 vinst; 182 183 uint32_t engine; 184 uint32_t class; 185 186 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 187 void *priv; 188}; 189 190struct nouveau_page_flip_state { 191 struct list_head head; 192 struct drm_pending_vblank_event *event; 193 int crtc, bpp, pitch, x, y; 194 uint64_t offset; 195}; 196 197enum nouveau_channel_mutex_class { 198 NOUVEAU_UCHANNEL_MUTEX, 199 NOUVEAU_KCHANNEL_MUTEX 200}; 201 202struct nouveau_channel { 203 struct drm_device *dev; 204 int id; 205 206 /* references to the channel data structure */ 207 struct kref ref; 208 /* users of the hardware channel resources, the hardware 209 * context will be kicked off when it reaches zero. */ 210 atomic_t users; 211 struct mutex mutex; 212 213 /* owner of this fifo */ 214 struct drm_file *file_priv; 215 /* mapping of the fifo itself */ 216 struct drm_local_map *map; 217 218 /* mapping of the regs controlling the fifo */ 219 void __iomem *user; 220 uint32_t user_get; 221 uint32_t user_put; 222 223 /* Fencing */ 224 struct { 225 /* lock protects the pending list only */ 226 spinlock_t lock; 227 struct list_head pending; 228 uint32_t sequence; 229 uint32_t sequence_ack; 230 atomic_t last_sequence_irq; 231 } fence; 232 233 /* DMA push buffer */ 234 struct nouveau_gpuobj *pushbuf; 235 struct nouveau_bo *pushbuf_bo; 236 uint32_t pushbuf_base; 237 238 /* Notifier memory */ 239 struct nouveau_bo *notifier_bo; 240 struct drm_mm notifier_heap; 241 242 /* PFIFO context */ 243 struct nouveau_gpuobj *ramfc; 244 struct nouveau_gpuobj *cache; 245 void *fifo_priv; 246 247 /* Execution engine contexts */ 248 void *engctx[NVOBJ_ENGINE_NR]; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295}; 296 297struct nouveau_exec_engine { 298 void (*destroy)(struct drm_device *, int engine); 299 int (*init)(struct drm_device *, int engine); 300 int (*fini)(struct drm_device *, int engine); 301 int (*context_new)(struct nouveau_channel *, int engine); 302 void (*context_del)(struct nouveau_channel *, int engine); 303 int (*object_new)(struct nouveau_channel *, int engine, 304 u32 handle, u16 class); 305 void (*set_tile_region)(struct drm_device *dev, int i); 306 void (*tlb_flush)(struct drm_device *, int engine); 307}; 308 309struct nouveau_instmem_engine { 310 void *priv; 311 312 int (*init)(struct drm_device *dev); 313 void (*takedown)(struct drm_device *dev); 314 int (*suspend)(struct drm_device *dev); 315 void (*resume)(struct drm_device *dev); 316 317 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 318 void (*put)(struct nouveau_gpuobj *); 319 int (*map)(struct nouveau_gpuobj *); 320 void (*unmap)(struct nouveau_gpuobj *); 321 322 void (*flush)(struct drm_device *); 323}; 324 325struct nouveau_mc_engine { 326 int (*init)(struct drm_device *dev); 327 void (*takedown)(struct drm_device *dev); 328}; 329 330struct nouveau_timer_engine { 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 uint64_t (*read)(struct drm_device *dev); 334}; 335 336struct nouveau_fb_engine { 337 int num_tiles; 338 struct drm_mm tag_heap; 339 void *priv; 340 341 int (*init)(struct drm_device *dev); 342 void (*takedown)(struct drm_device *dev); 343 344 void (*init_tile_region)(struct drm_device *dev, int i, 345 uint32_t addr, uint32_t size, 346 uint32_t pitch, uint32_t flags); 347 void (*set_tile_region)(struct drm_device *dev, int i); 348 void (*free_tile_region)(struct drm_device *dev, int i); 349}; 350 351struct nouveau_fifo_engine { 352 void *priv; 353 int channels; 354 355 struct nouveau_gpuobj *playlist[2]; 356 int cur_playlist; 357 358 int (*init)(struct drm_device *); 359 void (*takedown)(struct drm_device *); 360 361 void (*disable)(struct drm_device *); 362 void (*enable)(struct drm_device *); 363 bool (*reassign)(struct drm_device *, bool enable); 364 bool (*cache_pull)(struct drm_device *dev, bool enable); 365 366 int (*channel_id)(struct drm_device *); 367 368 int (*create_context)(struct nouveau_channel *); 369 void (*destroy_context)(struct nouveau_channel *); 370 int (*load_context)(struct nouveau_channel *); 371 int (*unload_context)(struct drm_device *); 372 void (*tlb_flush)(struct drm_device *dev); 373}; 374 375struct nouveau_display_engine { 376 void *priv; 377 int (*early_init)(struct drm_device *); 378 void (*late_takedown)(struct drm_device *); 379 int (*create)(struct drm_device *); 380 int (*init)(struct drm_device *); 381 void (*destroy)(struct drm_device *); 382}; 383 384struct nouveau_gpio_engine { 385 void *priv; 386 387 int (*init)(struct drm_device *); 388 void (*takedown)(struct drm_device *); 389 390 int (*get)(struct drm_device *, enum dcb_gpio_tag); 391 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 392 393 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 394 void (*)(void *, int), void *); 395 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 396 void (*)(void *, int), void *); 397 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 398}; 399 400struct nouveau_pm_voltage_level { 401 u8 voltage; 402 u8 vid; 403}; 404 405struct nouveau_pm_voltage { 406 bool supported; 407 u8 vid_mask; 408 409 struct nouveau_pm_voltage_level *level; 410 int nr_level; 411}; 412 413struct nouveau_pm_memtiming { 414 int id; 415 u32 reg_100220; 416 u32 reg_100224; 417 u32 reg_100228; 418 u32 reg_10022c; 419 u32 reg_100230; 420 u32 reg_100234; 421 u32 reg_100238; 422 u32 reg_10023c; 423 u32 reg_100240; 424}; 425 426#define NOUVEAU_PM_MAX_LEVEL 8 427struct nouveau_pm_level { 428 struct device_attribute dev_attr; 429 char name[32]; 430 int id; 431 432 u32 core; 433 u32 memory; 434 u32 shader; 435 u32 unk05; 436 u32 unk0a; 437 438 u8 voltage; 439 u8 fanspeed; 440 441 u16 memscript; 442 struct nouveau_pm_memtiming *timing; 443}; 444 445struct nouveau_pm_temp_sensor_constants { 446 u16 offset_constant; 447 s16 offset_mult; 448 u16 offset_div; 449 u16 slope_mult; 450 u16 slope_div; 451}; 452 453struct nouveau_pm_threshold_temp { 454 s16 critical; 455 s16 down_clock; 456 s16 fan_boost; 457}; 458 459struct nouveau_pm_memtimings { 460 bool supported; 461 struct nouveau_pm_memtiming *timing; 462 int nr_timing; 463}; 464 465struct nouveau_pm_engine { 466 struct nouveau_pm_voltage voltage; 467 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 468 int nr_perflvl; 469 struct nouveau_pm_memtimings memtimings; 470 struct nouveau_pm_temp_sensor_constants sensor_constants; 471 struct nouveau_pm_threshold_temp threshold_temp; 472 473 struct nouveau_pm_level boot; 474 struct nouveau_pm_level *cur; 475 476 struct device *hwmon; 477 struct notifier_block acpi_nb; 478 479 int (*clock_get)(struct drm_device *, u32 id); 480 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 481 u32 id, int khz); 482 void (*clock_set)(struct drm_device *, void *); 483 int (*voltage_get)(struct drm_device *); 484 int (*voltage_set)(struct drm_device *, int voltage); 485 int (*fanspeed_get)(struct drm_device *); 486 int (*fanspeed_set)(struct drm_device *, int fanspeed); 487 int (*temp_get)(struct drm_device *); 488}; 489 490struct nouveau_vram_engine { 491 int (*init)(struct drm_device *); 492 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 493 u32 type, struct nouveau_mem **); 494 void (*put)(struct drm_device *, struct nouveau_mem **); 495 496 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 497}; 498 499struct nouveau_engine { 500 struct nouveau_instmem_engine instmem; 501 struct nouveau_mc_engine mc; 502 struct nouveau_timer_engine timer; 503 struct nouveau_fb_engine fb; 504 struct nouveau_fifo_engine fifo; 505 struct nouveau_display_engine display; 506 struct nouveau_gpio_engine gpio; 507 struct nouveau_pm_engine pm; 508 struct nouveau_vram_engine vram; 509}; 510 511struct nouveau_pll_vals { 512 union { 513 struct { 514#ifdef __BIG_ENDIAN 515 uint8_t N1, M1, N2, M2; 516#else 517 uint8_t M1, N1, M2, N2; 518#endif 519 }; 520 struct { 521 uint16_t NM1, NM2; 522 } __attribute__((packed)); 523 }; 524 int log2P; 525 526 int refclk; 527}; 528 529enum nv04_fp_display_regs { 530 FP_DISPLAY_END, 531 FP_TOTAL, 532 FP_CRTC, 533 FP_SYNC_START, 534 FP_SYNC_END, 535 FP_VALID_START, 536 FP_VALID_END 537}; 538 539struct nv04_crtc_reg { 540 unsigned char MiscOutReg; 541 uint8_t CRTC[0xa0]; 542 uint8_t CR58[0x10]; 543 uint8_t Sequencer[5]; 544 uint8_t Graphics[9]; 545 uint8_t Attribute[21]; 546 unsigned char DAC[768]; 547 548 /* PCRTC regs */ 549 uint32_t fb_start; 550 uint32_t crtc_cfg; 551 uint32_t cursor_cfg; 552 uint32_t gpio_ext; 553 uint32_t crtc_830; 554 uint32_t crtc_834; 555 uint32_t crtc_850; 556 uint32_t crtc_eng_ctrl; 557 558 /* PRAMDAC regs */ 559 uint32_t nv10_cursync; 560 struct nouveau_pll_vals pllvals; 561 uint32_t ramdac_gen_ctrl; 562 uint32_t ramdac_630; 563 uint32_t ramdac_634; 564 uint32_t tv_setup; 565 uint32_t tv_vtotal; 566 uint32_t tv_vskew; 567 uint32_t tv_vsync_delay; 568 uint32_t tv_htotal; 569 uint32_t tv_hskew; 570 uint32_t tv_hsync_delay; 571 uint32_t tv_hsync_delay2; 572 uint32_t fp_horiz_regs[7]; 573 uint32_t fp_vert_regs[7]; 574 uint32_t dither; 575 uint32_t fp_control; 576 uint32_t dither_regs[6]; 577 uint32_t fp_debug_0; 578 uint32_t fp_debug_1; 579 uint32_t fp_debug_2; 580 uint32_t fp_margin_color; 581 uint32_t ramdac_8c0; 582 uint32_t ramdac_a20; 583 uint32_t ramdac_a24; 584 uint32_t ramdac_a34; 585 uint32_t ctv_regs[38]; 586}; 587 588struct nv04_output_reg { 589 uint32_t output; 590 int head; 591}; 592 593struct nv04_mode_state { 594 struct nv04_crtc_reg crtc_reg[2]; 595 uint32_t pllsel; 596 uint32_t sel_clk; 597}; 598 599enum nouveau_card_type { 600 NV_04 = 0x00, 601 NV_10 = 0x10, 602 NV_20 = 0x20, 603 NV_30 = 0x30, 604 NV_40 = 0x40, 605 NV_50 = 0x50, 606 NV_C0 = 0xc0, 607}; 608 609struct drm_nouveau_private { 610 struct drm_device *dev; 611 bool noaccel; 612 613 /* the card type, takes NV_* as values */ 614 enum nouveau_card_type card_type; 615 /* exact chipset, derived from NV_PMC_BOOT_0 */ 616 int chipset; 617 int stepping; 618 int flags; 619 620 void __iomem *mmio; 621 622 spinlock_t ramin_lock; 623 void __iomem *ramin; 624 u32 ramin_size; 625 u32 ramin_base; 626 bool ramin_available; 627 struct drm_mm ramin_heap; 628 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 629 struct list_head gpuobj_list; 630 struct list_head classes; 631 632 struct nouveau_bo *vga_ram; 633 634 /* interrupt handling */ 635 void (*irq_handler[32])(struct drm_device *); 636 bool msi_enabled; 637 638 struct list_head vbl_waiting; 639 640 struct { 641 struct drm_global_reference mem_global_ref; 642 struct ttm_bo_global_ref bo_global_ref; 643 struct ttm_bo_device bdev; 644 atomic_t validate_sequence; 645 } ttm; 646 647 struct { 648 spinlock_t lock; 649 struct drm_mm heap; 650 struct nouveau_bo *bo; 651 } fence; 652 653 struct { 654 spinlock_t lock; 655 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 656 } channels; 657 658 struct nouveau_engine engine; 659 struct nouveau_channel *channel; 660 661 /* For PFIFO and PGRAPH. */ 662 spinlock_t context_switch_lock; 663 664 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 665 spinlock_t vm_lock; 666 667 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 668 struct nouveau_ramht *ramht; 669 struct nouveau_gpuobj *ramfc; 670 struct nouveau_gpuobj *ramro; 671 672 uint32_t ramin_rsvd_vram; 673 674 struct { 675 enum { 676 NOUVEAU_GART_NONE = 0, 677 NOUVEAU_GART_AGP, /* AGP */ 678 NOUVEAU_GART_PDMA, /* paged dma object */ 679 NOUVEAU_GART_HW /* on-chip gart/vm */ 680 } type; 681 uint64_t aper_base; 682 uint64_t aper_size; 683 uint64_t aper_free; 684 685 struct ttm_backend_func *func; 686 687 struct { 688 struct page *page; 689 dma_addr_t addr; 690 } dummy; 691 692 struct nouveau_gpuobj *sg_ctxdma; 693 } gart_info; 694 695 /* nv10-nv40 tiling regions */ 696 struct { 697 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 698 spinlock_t lock; 699 } tile; 700 701 /* VRAM/fb configuration */ 702 uint64_t vram_size; 703 uint64_t vram_sys_base; 704 u32 vram_rblock_size; 705 706 uint64_t fb_phys; 707 uint64_t fb_available_size; 708 uint64_t fb_mappable_pages; 709 uint64_t fb_aper_free; 710 int fb_mtrr; 711 712 /* BAR control (NV50-) */ 713 struct nouveau_vm *bar1_vm; 714 struct nouveau_vm *bar3_vm; 715 716 /* G8x/G9x virtual address space */ 717 struct nouveau_vm *chan_vm; 718 719 struct nvbios vbios; 720 721 struct nv04_mode_state mode_reg; 722 struct nv04_mode_state saved_reg; 723 uint32_t saved_vga_font[4][16384]; 724 uint32_t crtc_owner; 725 uint32_t dac_users[4]; 726 727 struct backlight_device *backlight; 728 729 struct { 730 struct dentry *channel_root; 731 } debugfs; 732 733 struct nouveau_fbdev *nfbdev; 734 struct apertures_struct *apertures; 735}; 736 737static inline struct drm_nouveau_private * 738nouveau_private(struct drm_device *dev) 739{ 740 return dev->dev_private; 741} 742 743static inline struct drm_nouveau_private * 744nouveau_bdev(struct ttm_bo_device *bd) 745{ 746 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 747} 748 749static inline int 750nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 751{ 752 struct nouveau_bo *prev; 753 754 if (!pnvbo) 755 return -EINVAL; 756 prev = *pnvbo; 757 758 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 759 if (prev) { 760 struct ttm_buffer_object *bo = &prev->bo; 761 762 ttm_bo_unref(&bo); 763 } 764 765 return 0; 766} 767 768/* nouveau_drv.c */ 769extern int nouveau_agpmode; 770extern int nouveau_duallink; 771extern int nouveau_uscript_lvds; 772extern int nouveau_uscript_tmds; 773extern int nouveau_vram_pushbuf; 774extern int nouveau_vram_notify; 775extern int nouveau_fbpercrtc; 776extern int nouveau_tv_disable; 777extern char *nouveau_tv_norm; 778extern int nouveau_reg_debug; 779extern char *nouveau_vbios; 780extern int nouveau_ignorelid; 781extern int nouveau_nofbaccel; 782extern int nouveau_noaccel; 783extern int nouveau_force_post; 784extern int nouveau_override_conntype; 785extern char *nouveau_perflvl; 786extern int nouveau_perflvl_wr; 787extern int nouveau_msi; 788 789extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 790extern int nouveau_pci_resume(struct pci_dev *pdev); 791 792/* nouveau_state.c */ 793extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 794extern int nouveau_load(struct drm_device *, unsigned long flags); 795extern int nouveau_firstopen(struct drm_device *); 796extern void nouveau_lastclose(struct drm_device *); 797extern int nouveau_unload(struct drm_device *); 798extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 799 struct drm_file *); 800extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 801 struct drm_file *); 802extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 803 uint32_t reg, uint32_t mask, uint32_t val); 804extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 805 uint32_t reg, uint32_t mask, uint32_t val); 806extern bool nouveau_wait_for_idle(struct drm_device *); 807extern int nouveau_card_init(struct drm_device *); 808 809/* nouveau_mem.c */ 810extern int nouveau_mem_vram_init(struct drm_device *); 811extern void nouveau_mem_vram_fini(struct drm_device *); 812extern int nouveau_mem_gart_init(struct drm_device *); 813extern void nouveau_mem_gart_fini(struct drm_device *); 814extern int nouveau_mem_init_agp(struct drm_device *); 815extern int nouveau_mem_reset_agp(struct drm_device *); 816extern void nouveau_mem_close(struct drm_device *); 817extern int nouveau_mem_detect(struct drm_device *); 818extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 819extern struct nouveau_tile_reg *nv10_mem_set_tiling( 820 struct drm_device *dev, uint32_t addr, uint32_t size, 821 uint32_t pitch, uint32_t flags); 822extern void nv10_mem_put_tile_region(struct drm_device *dev, 823 struct nouveau_tile_reg *tile, 824 struct nouveau_fence *fence); 825extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 826extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 827 828/* nouveau_notifier.c */ 829extern int nouveau_notifier_init_channel(struct nouveau_channel *); 830extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 831extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 832 int cout, uint32_t start, uint32_t end, 833 uint32_t *offset); 834extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 835extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 836 struct drm_file *); 837extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 838 struct drm_file *); 839 840/* nouveau_channel.c */ 841extern struct drm_ioctl_desc nouveau_ioctls[]; 842extern int nouveau_max_ioctl; 843extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 844extern int nouveau_channel_alloc(struct drm_device *dev, 845 struct nouveau_channel **chan, 846 struct drm_file *file_priv, 847 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 848extern struct nouveau_channel * 849nouveau_channel_get_unlocked(struct nouveau_channel *); 850extern struct nouveau_channel * 851nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 852extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 853extern void nouveau_channel_put(struct nouveau_channel **); 854extern void nouveau_channel_ref(struct nouveau_channel *chan, 855 struct nouveau_channel **pchan); 856extern void nouveau_channel_idle(struct nouveau_channel *chan); 857 858/* nouveau_object.c */ 859#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 860 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 861 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 862} while (0) 863 864#define NVOBJ_ENGINE_DEL(d, e) do { \ 865 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 866 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 867} while (0) 868 869#define NVOBJ_CLASS(d, c, e) do { \ 870 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 871 if (ret) \ 872 return ret; \ 873} while (0) 874 875#define NVOBJ_MTHD(d, c, m, e) do { \ 876 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 877 if (ret) \ 878 return ret; \ 879} while (0) 880 881extern int nouveau_gpuobj_early_init(struct drm_device *); 882extern int nouveau_gpuobj_init(struct drm_device *); 883extern void nouveau_gpuobj_takedown(struct drm_device *); 884extern int nouveau_gpuobj_suspend(struct drm_device *dev); 885extern void nouveau_gpuobj_resume(struct drm_device *dev); 886extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 887extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 888 int (*exec)(struct nouveau_channel *, 889 u32 class, u32 mthd, u32 data)); 890extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 891extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 892extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 893 uint32_t vram_h, uint32_t tt_h); 894extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 895extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 896 uint32_t size, int align, uint32_t flags, 897 struct nouveau_gpuobj **); 898extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 899 struct nouveau_gpuobj **); 900extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 901 u32 size, u32 flags, 902 struct nouveau_gpuobj **); 903extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 904 uint64_t offset, uint64_t size, int access, 905 int target, struct nouveau_gpuobj **); 906extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 907extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 908 u64 size, int target, int access, u32 type, 909 u32 comp, struct nouveau_gpuobj **pobj); 910extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 911 int class, u64 base, u64 size, int target, 912 int access, u32 type, u32 comp); 913extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 914 struct drm_file *); 915extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 916 struct drm_file *); 917 918/* nouveau_irq.c */ 919extern int nouveau_irq_init(struct drm_device *); 920extern void nouveau_irq_fini(struct drm_device *); 921extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 922extern void nouveau_irq_register(struct drm_device *, int status_bit, 923 void (*)(struct drm_device *)); 924extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 925extern void nouveau_irq_preinstall(struct drm_device *); 926extern int nouveau_irq_postinstall(struct drm_device *); 927extern void nouveau_irq_uninstall(struct drm_device *); 928 929/* nouveau_sgdma.c */ 930extern int nouveau_sgdma_init(struct drm_device *); 931extern void nouveau_sgdma_takedown(struct drm_device *); 932extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 933 uint32_t offset); 934extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 935 936/* nouveau_debugfs.c */ 937#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 938extern int nouveau_debugfs_init(struct drm_minor *); 939extern void nouveau_debugfs_takedown(struct drm_minor *); 940extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 941extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 942#else 943static inline int 944nouveau_debugfs_init(struct drm_minor *minor) 945{ 946 return 0; 947} 948 949static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 950{ 951} 952 953static inline int 954nouveau_debugfs_channel_init(struct nouveau_channel *chan) 955{ 956 return 0; 957} 958 959static inline void 960nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 961{ 962} 963#endif 964 965/* nouveau_dma.c */ 966extern void nouveau_dma_pre_init(struct nouveau_channel *); 967extern int nouveau_dma_init(struct nouveau_channel *); 968extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 969 970/* nouveau_acpi.c */ 971#define ROM_BIOS_PAGE 4096 972#if defined(CONFIG_ACPI) 973void nouveau_register_dsm_handler(void); 974void nouveau_unregister_dsm_handler(void); 975int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 976bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 977int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 978#else 979static inline void nouveau_register_dsm_handler(void) {} 980static inline void nouveau_unregister_dsm_handler(void) {} 981static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 982static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 983static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 984#endif 985 986/* nouveau_backlight.c */ 987#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 988extern int nouveau_backlight_init(struct drm_connector *); 989extern void nouveau_backlight_exit(struct drm_connector *); 990#else 991static inline int nouveau_backlight_init(struct drm_connector *dev) 992{ 993 return 0; 994} 995 996static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 997#endif 998 999/* nouveau_bios.c */ 1000extern int nouveau_bios_init(struct drm_device *); 1001extern void nouveau_bios_takedown(struct drm_device *dev); 1002extern int nouveau_run_vbios_init(struct drm_device *); 1003extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1004 struct dcb_entry *); 1005extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1006 enum dcb_gpio_tag); 1007extern struct dcb_connector_table_entry * 1008nouveau_bios_connector_entry(struct drm_device *, int index); 1009extern u32 get_pll_register(struct drm_device *, enum pll_types); 1010extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1011 struct pll_lims *); 1012extern int nouveau_bios_run_display_table(struct drm_device *, 1013 struct dcb_entry *, 1014 uint32_t script, int pxclk); 1015extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1016 int *length); 1017extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1018extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1019extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1020 bool *dl, bool *if_is_24bit); 1021extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1022 int head, int pxclk); 1023extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1024 enum LVDS_script, int pxclk); 1025 1026/* nouveau_ttm.c */ 1027int nouveau_ttm_global_init(struct drm_nouveau_private *); 1028void nouveau_ttm_global_release(struct drm_nouveau_private *); 1029int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1030 1031/* nouveau_dp.c */ 1032int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1033 uint8_t *data, int data_nr); 1034bool nouveau_dp_detect(struct drm_encoder *); 1035bool nouveau_dp_link_train(struct drm_encoder *); 1036 1037/* nv04_fb.c */ 1038extern int nv04_fb_init(struct drm_device *); 1039extern void nv04_fb_takedown(struct drm_device *); 1040 1041/* nv10_fb.c */ 1042extern int nv10_fb_init(struct drm_device *); 1043extern void nv10_fb_takedown(struct drm_device *); 1044extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1045 uint32_t addr, uint32_t size, 1046 uint32_t pitch, uint32_t flags); 1047extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1048extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1049 1050/* nv30_fb.c */ 1051extern int nv30_fb_init(struct drm_device *); 1052extern void nv30_fb_takedown(struct drm_device *); 1053extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1054 uint32_t addr, uint32_t size, 1055 uint32_t pitch, uint32_t flags); 1056extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1057 1058/* nv40_fb.c */ 1059extern int nv40_fb_init(struct drm_device *); 1060extern void nv40_fb_takedown(struct drm_device *); 1061extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1062 1063/* nv50_fb.c */ 1064extern int nv50_fb_init(struct drm_device *); 1065extern void nv50_fb_takedown(struct drm_device *); 1066extern void nv50_fb_vm_trap(struct drm_device *, int display); 1067 1068/* nvc0_fb.c */ 1069extern int nvc0_fb_init(struct drm_device *); 1070extern void nvc0_fb_takedown(struct drm_device *); 1071 1072/* nv04_fifo.c */ 1073extern int nv04_fifo_init(struct drm_device *); 1074extern void nv04_fifo_fini(struct drm_device *); 1075extern void nv04_fifo_disable(struct drm_device *); 1076extern void nv04_fifo_enable(struct drm_device *); 1077extern bool nv04_fifo_reassign(struct drm_device *, bool); 1078extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1079extern int nv04_fifo_channel_id(struct drm_device *); 1080extern int nv04_fifo_create_context(struct nouveau_channel *); 1081extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1082extern int nv04_fifo_load_context(struct nouveau_channel *); 1083extern int nv04_fifo_unload_context(struct drm_device *); 1084extern void nv04_fifo_isr(struct drm_device *); 1085 1086/* nv10_fifo.c */ 1087extern int nv10_fifo_init(struct drm_device *); 1088extern int nv10_fifo_channel_id(struct drm_device *); 1089extern int nv10_fifo_create_context(struct nouveau_channel *); 1090extern int nv10_fifo_load_context(struct nouveau_channel *); 1091extern int nv10_fifo_unload_context(struct drm_device *); 1092 1093/* nv40_fifo.c */ 1094extern int nv40_fifo_init(struct drm_device *); 1095extern int nv40_fifo_create_context(struct nouveau_channel *); 1096extern int nv40_fifo_load_context(struct nouveau_channel *); 1097extern int nv40_fifo_unload_context(struct drm_device *); 1098 1099/* nv50_fifo.c */ 1100extern int nv50_fifo_init(struct drm_device *); 1101extern void nv50_fifo_takedown(struct drm_device *); 1102extern int nv50_fifo_channel_id(struct drm_device *); 1103extern int nv50_fifo_create_context(struct nouveau_channel *); 1104extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1105extern int nv50_fifo_load_context(struct nouveau_channel *); 1106extern int nv50_fifo_unload_context(struct drm_device *); 1107extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1108 1109/* nvc0_fifo.c */ 1110extern int nvc0_fifo_init(struct drm_device *); 1111extern void nvc0_fifo_takedown(struct drm_device *); 1112extern void nvc0_fifo_disable(struct drm_device *); 1113extern void nvc0_fifo_enable(struct drm_device *); 1114extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1115extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1116extern int nvc0_fifo_channel_id(struct drm_device *); 1117extern int nvc0_fifo_create_context(struct nouveau_channel *); 1118extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1119extern int nvc0_fifo_load_context(struct nouveau_channel *); 1120extern int nvc0_fifo_unload_context(struct drm_device *); 1121 1122/* nv04_graph.c */ 1123extern int nv04_graph_create(struct drm_device *); 1124extern void nv04_graph_fifo_access(struct drm_device *, bool); 1125extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1126extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1127 u32 class, u32 mthd, u32 data); 1128extern struct nouveau_bitfield nv04_graph_nsource[]; 1129 1130/* nv10_graph.c */ 1131extern int nv10_graph_create(struct drm_device *); 1132extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1133extern struct nouveau_bitfield nv10_graph_intr[]; 1134extern struct nouveau_bitfield nv10_graph_nstatus[]; 1135 1136/* nv20_graph.c */ 1137extern int nv20_graph_create(struct drm_device *); 1138 1139/* nv40_graph.c */ 1140extern int nv40_graph_create(struct drm_device *); 1141extern void nv40_grctx_init(struct nouveau_grctx *); 1142 1143/* nv50_graph.c */ 1144extern int nv50_graph_create(struct drm_device *); 1145extern int nv50_grctx_init(struct nouveau_grctx *); 1146extern struct nouveau_enum nv50_data_error_names[]; 1147extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1148 1149/* nvc0_graph.c */ 1150extern int nvc0_graph_create(struct drm_device *); 1151extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1152 1153/* nv84_crypt.c */ 1154extern int nv84_crypt_create(struct drm_device *); 1155 1156/* nva3_copy.c */ 1157extern int nva3_copy_create(struct drm_device *dev); 1158 1159/* nvc0_copy.c */ 1160extern int nvc0_copy_create(struct drm_device *dev, int engine); 1161 1162/* nv40_mpeg.c */ 1163extern int nv40_mpeg_create(struct drm_device *dev); 1164 1165/* nv50_mpeg.c */ 1166extern int nv50_mpeg_create(struct drm_device *dev); 1167 1168/* nv04_instmem.c */ 1169extern int nv04_instmem_init(struct drm_device *); 1170extern void nv04_instmem_takedown(struct drm_device *); 1171extern int nv04_instmem_suspend(struct drm_device *); 1172extern void nv04_instmem_resume(struct drm_device *); 1173extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1174extern void nv04_instmem_put(struct nouveau_gpuobj *); 1175extern int nv04_instmem_map(struct nouveau_gpuobj *); 1176extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1177extern void nv04_instmem_flush(struct drm_device *); 1178 1179/* nv50_instmem.c */ 1180extern int nv50_instmem_init(struct drm_device *); 1181extern void nv50_instmem_takedown(struct drm_device *); 1182extern int nv50_instmem_suspend(struct drm_device *); 1183extern void nv50_instmem_resume(struct drm_device *); 1184extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1185extern void nv50_instmem_put(struct nouveau_gpuobj *); 1186extern int nv50_instmem_map(struct nouveau_gpuobj *); 1187extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1188extern void nv50_instmem_flush(struct drm_device *); 1189extern void nv84_instmem_flush(struct drm_device *); 1190 1191/* nvc0_instmem.c */ 1192extern int nvc0_instmem_init(struct drm_device *); 1193extern void nvc0_instmem_takedown(struct drm_device *); 1194extern int nvc0_instmem_suspend(struct drm_device *); 1195extern void nvc0_instmem_resume(struct drm_device *); 1196 1197/* nv04_mc.c */ 1198extern int nv04_mc_init(struct drm_device *); 1199extern void nv04_mc_takedown(struct drm_device *); 1200 1201/* nv40_mc.c */ 1202extern int nv40_mc_init(struct drm_device *); 1203extern void nv40_mc_takedown(struct drm_device *); 1204 1205/* nv50_mc.c */ 1206extern int nv50_mc_init(struct drm_device *); 1207extern void nv50_mc_takedown(struct drm_device *); 1208 1209/* nv04_timer.c */ 1210extern int nv04_timer_init(struct drm_device *); 1211extern uint64_t nv04_timer_read(struct drm_device *); 1212extern void nv04_timer_takedown(struct drm_device *); 1213 1214extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1215 unsigned long arg); 1216 1217/* nv04_dac.c */ 1218extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1219extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1220extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1221extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1222extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1223 1224/* nv04_dfp.c */ 1225extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1226extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1227extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1228 int head, bool dl); 1229extern void nv04_dfp_disable(struct drm_device *dev, int head); 1230extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1231 1232/* nv04_tv.c */ 1233extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1234extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1235 1236/* nv17_tv.c */ 1237extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1238 1239/* nv04_display.c */ 1240extern int nv04_display_early_init(struct drm_device *); 1241extern void nv04_display_late_takedown(struct drm_device *); 1242extern int nv04_display_create(struct drm_device *); 1243extern int nv04_display_init(struct drm_device *); 1244extern void nv04_display_destroy(struct drm_device *); 1245 1246/* nv04_crtc.c */ 1247extern int nv04_crtc_create(struct drm_device *, int index); 1248 1249/* nouveau_bo.c */ 1250extern struct ttm_bo_driver nouveau_bo_driver; 1251extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1252 int size, int align, uint32_t flags, 1253 uint32_t tile_mode, uint32_t tile_flags, 1254 struct nouveau_bo **); 1255extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1256extern int nouveau_bo_unpin(struct nouveau_bo *); 1257extern int nouveau_bo_map(struct nouveau_bo *); 1258extern void nouveau_bo_unmap(struct nouveau_bo *); 1259extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1260 uint32_t busy); 1261extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1262extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1263extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1264extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1265extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1266extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1267 bool no_wait_reserve, bool no_wait_gpu); 1268 1269/* nouveau_fence.c */ 1270struct nouveau_fence; 1271extern int nouveau_fence_init(struct drm_device *); 1272extern void nouveau_fence_fini(struct drm_device *); 1273extern int nouveau_fence_channel_init(struct nouveau_channel *); 1274extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1275extern void nouveau_fence_update(struct nouveau_channel *); 1276extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1277 bool emit); 1278extern int nouveau_fence_emit(struct nouveau_fence *); 1279extern void nouveau_fence_work(struct nouveau_fence *fence, 1280 void (*work)(void *priv, bool signalled), 1281 void *priv); 1282struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1283 1284extern bool __nouveau_fence_signalled(void *obj, void *arg); 1285extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1286extern int __nouveau_fence_flush(void *obj, void *arg); 1287extern void __nouveau_fence_unref(void **obj); 1288extern void *__nouveau_fence_ref(void *obj); 1289 1290static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1291{ 1292 return __nouveau_fence_signalled(obj, NULL); 1293} 1294static inline int 1295nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1296{ 1297 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1298} 1299extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1300static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1301{ 1302 return __nouveau_fence_flush(obj, NULL); 1303} 1304static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1305{ 1306 __nouveau_fence_unref((void **)obj); 1307} 1308static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1309{ 1310 return __nouveau_fence_ref(obj); 1311} 1312 1313/* nouveau_gem.c */ 1314extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1315 int size, int align, uint32_t domain, 1316 uint32_t tile_mode, uint32_t tile_flags, 1317 struct nouveau_bo **); 1318extern int nouveau_gem_object_new(struct drm_gem_object *); 1319extern void nouveau_gem_object_del(struct drm_gem_object *); 1320extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1321 struct drm_file *); 1322extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1323 struct drm_file *); 1324extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1325 struct drm_file *); 1326extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1327 struct drm_file *); 1328extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1329 struct drm_file *); 1330 1331/* nouveau_display.c */ 1332int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1333void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1334int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1335 struct drm_pending_vblank_event *event); 1336int nouveau_finish_page_flip(struct nouveau_channel *, 1337 struct nouveau_page_flip_state *); 1338 1339/* nv10_gpio.c */ 1340int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1341int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1342 1343/* nv50_gpio.c */ 1344int nv50_gpio_init(struct drm_device *dev); 1345void nv50_gpio_fini(struct drm_device *dev); 1346int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1347int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1348int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1349 void (*)(void *, int), void *); 1350void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1351 void (*)(void *, int), void *); 1352bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1353 1354/* nv50_calc. */ 1355int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1356 int *N1, int *M1, int *N2, int *M2, int *P); 1357int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1358 int clk, int *N, int *fN, int *M, int *P); 1359 1360#ifndef ioread32_native 1361#ifdef __BIG_ENDIAN 1362#define ioread16_native ioread16be 1363#define iowrite16_native iowrite16be 1364#define ioread32_native ioread32be 1365#define iowrite32_native iowrite32be 1366#else /* def __BIG_ENDIAN */ 1367#define ioread16_native ioread16 1368#define iowrite16_native iowrite16 1369#define ioread32_native ioread32 1370#define iowrite32_native iowrite32 1371#endif /* def __BIG_ENDIAN else */ 1372#endif /* !ioread32_native */ 1373 1374/* channel control reg access */ 1375static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1376{ 1377 return ioread32_native(chan->user + reg); 1378} 1379 1380static inline void nvchan_wr32(struct nouveau_channel *chan, 1381 unsigned reg, u32 val) 1382{ 1383 iowrite32_native(val, chan->user + reg); 1384} 1385 1386/* register access */ 1387static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1388{ 1389 struct drm_nouveau_private *dev_priv = dev->dev_private; 1390 return ioread32_native(dev_priv->mmio + reg); 1391} 1392 1393static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1394{ 1395 struct drm_nouveau_private *dev_priv = dev->dev_private; 1396 iowrite32_native(val, dev_priv->mmio + reg); 1397} 1398 1399static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1400{ 1401 u32 tmp = nv_rd32(dev, reg); 1402 nv_wr32(dev, reg, (tmp & ~mask) | val); 1403 return tmp; 1404} 1405 1406static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1407{ 1408 struct drm_nouveau_private *dev_priv = dev->dev_private; 1409 return ioread8(dev_priv->mmio + reg); 1410} 1411 1412static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1413{ 1414 struct drm_nouveau_private *dev_priv = dev->dev_private; 1415 iowrite8(val, dev_priv->mmio + reg); 1416} 1417 1418#define nv_wait(dev, reg, mask, val) \ 1419 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1420#define nv_wait_ne(dev, reg, mask, val) \ 1421 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1422 1423/* PRAMIN access */ 1424static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1425{ 1426 struct drm_nouveau_private *dev_priv = dev->dev_private; 1427 return ioread32_native(dev_priv->ramin + offset); 1428} 1429 1430static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1431{ 1432 struct drm_nouveau_private *dev_priv = dev->dev_private; 1433 iowrite32_native(val, dev_priv->ramin + offset); 1434} 1435 1436/* object access */ 1437extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1438extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1439 1440/* 1441 * Logging 1442 * Argument d is (struct drm_device *). 1443 */ 1444#define NV_PRINTK(level, d, fmt, arg...) \ 1445 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1446 pci_name(d->pdev), ##arg) 1447#ifndef NV_DEBUG_NOTRACE 1448#define NV_DEBUG(d, fmt, arg...) do { \ 1449 if (drm_debug & DRM_UT_DRIVER) { \ 1450 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1451 __LINE__, ##arg); \ 1452 } \ 1453} while (0) 1454#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1455 if (drm_debug & DRM_UT_KMS) { \ 1456 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1457 __LINE__, ##arg); \ 1458 } \ 1459} while (0) 1460#else 1461#define NV_DEBUG(d, fmt, arg...) do { \ 1462 if (drm_debug & DRM_UT_DRIVER) \ 1463 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1464} while (0) 1465#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1466 if (drm_debug & DRM_UT_KMS) \ 1467 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1468} while (0) 1469#endif 1470#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1471#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1472#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1473#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1474#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1475 1476/* nouveau_reg_debug bitmask */ 1477enum { 1478 NOUVEAU_REG_DEBUG_MC = 0x1, 1479 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1480 NOUVEAU_REG_DEBUG_FB = 0x4, 1481 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1482 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1483 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1484 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1485 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1486 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1487 NOUVEAU_REG_DEBUG_EVO = 0x200, 1488}; 1489 1490#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1491 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1492 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1493} while (0) 1494 1495static inline bool 1496nv_two_heads(struct drm_device *dev) 1497{ 1498 struct drm_nouveau_private *dev_priv = dev->dev_private; 1499 const int impl = dev->pci_device & 0x0ff0; 1500 1501 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1502 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1503 return true; 1504 1505 return false; 1506} 1507 1508static inline bool 1509nv_gf4_disp_arch(struct drm_device *dev) 1510{ 1511 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1512} 1513 1514static inline bool 1515nv_two_reg_pll(struct drm_device *dev) 1516{ 1517 struct drm_nouveau_private *dev_priv = dev->dev_private; 1518 const int impl = dev->pci_device & 0x0ff0; 1519 1520 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1521 return true; 1522 return false; 1523} 1524 1525static inline bool 1526nv_match_device(struct drm_device *dev, unsigned device, 1527 unsigned sub_vendor, unsigned sub_device) 1528{ 1529 return dev->pdev->device == device && 1530 dev->pdev->subsystem_vendor == sub_vendor && 1531 dev->pdev->subsystem_device == sub_device; 1532} 1533 1534static inline void * 1535nv_engine(struct drm_device *dev, int engine) 1536{ 1537 struct drm_nouveau_private *dev_priv = dev->dev_private; 1538 return (void *)dev_priv->eng[engine]; 1539} 1540 1541/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1542 * helpful to determine a number of other hardware features 1543 */ 1544static inline int 1545nv44_graph_class(struct drm_device *dev) 1546{ 1547 struct drm_nouveau_private *dev_priv = dev->dev_private; 1548 1549 if ((dev_priv->chipset & 0xf0) == 0x60) 1550 return 1; 1551 1552 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1553} 1554 1555/* memory type/access flags, do not match hardware values */ 1556#define NV_MEM_ACCESS_RO 1 1557#define NV_MEM_ACCESS_WO 2 1558#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1559#define NV_MEM_ACCESS_SYS 4 1560#define NV_MEM_ACCESS_VM 8 1561 1562#define NV_MEM_TARGET_VRAM 0 1563#define NV_MEM_TARGET_PCI 1 1564#define NV_MEM_TARGET_PCI_NOSNOOP 2 1565#define NV_MEM_TARGET_VM 3 1566#define NV_MEM_TARGET_GART 4 1567 1568#define NV_MEM_TYPE_VM 0x7f 1569#define NV_MEM_COMP_VM 0x03 1570 1571/* NV_SW object class */ 1572#define NV_SW 0x0000506e 1573#define NV_SW_DMA_SEMAPHORE 0x00000060 1574#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1575#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1576#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1577#define NV_SW_YIELD 0x00000080 1578#define NV_SW_DMA_VBLSEM 0x0000018c 1579#define NV_SW_VBLSEM_OFFSET 0x00000400 1580#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1581#define NV_SW_VBLSEM_RELEASE 0x00000408 1582#define NV_SW_PAGE_FLIP 0x00000500 1583 1584#endif /* __NOUVEAU_DRV_H__ */ 1585