nouveau_drv.h revision b2b099388fa76f0be25431794d369d251a4002dd
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78}; 79 80struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88}; 89 90struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 bool mappable; 108 bool no_vm; 109 110 uint32_t tile_mode; 111 uint32_t tile_flags; 112 struct nouveau_tile_reg *tile; 113 114 struct drm_gem_object *gem; 115 int pin_refcnt; 116}; 117 118#define nouveau_bo_tile_layout(nvbo) \ 119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 120 121static inline struct nouveau_bo * 122nouveau_bo(struct ttm_buffer_object *bo) 123{ 124 return container_of(bo, struct nouveau_bo, bo); 125} 126 127static inline struct nouveau_bo * 128nouveau_gem_object(struct drm_gem_object *gem) 129{ 130 return gem ? gem->driver_private : NULL; 131} 132 133/* TODO: submit equivalent to TTM generic API upstream? */ 134static inline void __iomem * 135nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 136{ 137 bool is_iomem; 138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 139 &nvbo->kmap, &is_iomem); 140 WARN_ON_ONCE(ioptr && !is_iomem); 141 return ioptr; 142} 143 144enum nouveau_flags { 145 NV_NFORCE = 0x10000000, 146 NV_NFORCE2 = 0x20000000 147}; 148 149#define NVOBJ_ENGINE_SW 0 150#define NVOBJ_ENGINE_GR 1 151#define NVOBJ_ENGINE_PPP 2 152#define NVOBJ_ENGINE_COPY 3 153#define NVOBJ_ENGINE_VP 4 154#define NVOBJ_ENGINE_CRYPT 5 155#define NVOBJ_ENGINE_BSP 6 156#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 157#define NVOBJ_ENGINE_INT 0xdeadbeef 158 159#define NVOBJ_FLAG_DONT_MAP (1 << 0) 160#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 161#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 162#define NVOBJ_FLAG_VM (1 << 3) 163 164#define NVOBJ_CINST_GLOBAL 0xdeadbeef 165 166struct nouveau_gpuobj { 167 struct drm_device *dev; 168 struct kref refcount; 169 struct list_head list; 170 171 void *node; 172 u32 *suspend; 173 174 uint32_t flags; 175 176 u32 size; 177 u32 pinst; 178 u32 cinst; 179 u64 vinst; 180 181 uint32_t engine; 182 uint32_t class; 183 184 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 185 void *priv; 186}; 187 188struct nouveau_page_flip_state { 189 struct list_head head; 190 struct drm_pending_vblank_event *event; 191 int crtc, bpp, pitch, x, y; 192 uint64_t offset; 193}; 194 195enum nouveau_channel_mutex_class { 196 NOUVEAU_UCHANNEL_MUTEX, 197 NOUVEAU_KCHANNEL_MUTEX 198}; 199 200struct nouveau_channel { 201 struct drm_device *dev; 202 int id; 203 204 /* references to the channel data structure */ 205 struct kref ref; 206 /* users of the hardware channel resources, the hardware 207 * context will be kicked off when it reaches zero. */ 208 atomic_t users; 209 struct mutex mutex; 210 211 /* owner of this fifo */ 212 struct drm_file *file_priv; 213 /* mapping of the fifo itself */ 214 struct drm_local_map *map; 215 216 /* mapping of the regs controling the fifo */ 217 void __iomem *user; 218 uint32_t user_get; 219 uint32_t user_put; 220 221 /* Fencing */ 222 struct { 223 /* lock protects the pending list only */ 224 spinlock_t lock; 225 struct list_head pending; 226 uint32_t sequence; 227 uint32_t sequence_ack; 228 atomic_t last_sequence_irq; 229 } fence; 230 231 /* DMA push buffer */ 232 struct nouveau_gpuobj *pushbuf; 233 struct nouveau_bo *pushbuf_bo; 234 uint32_t pushbuf_base; 235 236 /* Notifier memory */ 237 struct nouveau_bo *notifier_bo; 238 struct drm_mm notifier_heap; 239 240 /* PFIFO context */ 241 struct nouveau_gpuobj *ramfc; 242 struct nouveau_gpuobj *cache; 243 void *fifo_priv; 244 245 /* PGRAPH context */ 246 /* XXX may be merge 2 pointers as private data ??? */ 247 struct nouveau_gpuobj *ramin_grctx; 248 struct nouveau_gpuobj *crypt_ctx; 249 void *pgraph_ctx; 250 251 /* NV50 VM */ 252 struct nouveau_vm *vm; 253 struct nouveau_gpuobj *vm_pd; 254 255 /* Objects */ 256 struct nouveau_gpuobj *ramin; /* Private instmem */ 257 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 258 struct nouveau_ramht *ramht; /* Hash table */ 259 260 /* GPU object info for stuff used in-kernel (mm_enabled) */ 261 uint32_t m2mf_ntfy; 262 uint32_t vram_handle; 263 uint32_t gart_handle; 264 bool accel_done; 265 266 /* Push buffer state (only for drm's channel on !mm_enabled) */ 267 struct { 268 int max; 269 int free; 270 int cur; 271 int put; 272 /* access via pushbuf_bo */ 273 274 int ib_base; 275 int ib_max; 276 int ib_free; 277 int ib_put; 278 } dma; 279 280 uint32_t sw_subchannel[8]; 281 282 struct { 283 struct nouveau_gpuobj *vblsem; 284 uint32_t vblsem_head; 285 uint32_t vblsem_offset; 286 uint32_t vblsem_rval; 287 struct list_head vbl_wait; 288 struct list_head flip; 289 } nvsw; 290 291 struct { 292 bool active; 293 char name[32]; 294 struct drm_info_list info; 295 } debugfs; 296}; 297 298struct nouveau_instmem_engine { 299 void *priv; 300 301 int (*init)(struct drm_device *dev); 302 void (*takedown)(struct drm_device *dev); 303 int (*suspend)(struct drm_device *dev); 304 void (*resume)(struct drm_device *dev); 305 306 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 307 void (*put)(struct nouveau_gpuobj *); 308 int (*map)(struct nouveau_gpuobj *); 309 void (*unmap)(struct nouveau_gpuobj *); 310 311 void (*flush)(struct drm_device *); 312}; 313 314struct nouveau_mc_engine { 315 int (*init)(struct drm_device *dev); 316 void (*takedown)(struct drm_device *dev); 317}; 318 319struct nouveau_timer_engine { 320 int (*init)(struct drm_device *dev); 321 void (*takedown)(struct drm_device *dev); 322 uint64_t (*read)(struct drm_device *dev); 323}; 324 325struct nouveau_fb_engine { 326 int num_tiles; 327 struct drm_mm tag_heap; 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 333 void (*init_tile_region)(struct drm_device *dev, int i, 334 uint32_t addr, uint32_t size, 335 uint32_t pitch, uint32_t flags); 336 void (*set_tile_region)(struct drm_device *dev, int i); 337 void (*free_tile_region)(struct drm_device *dev, int i); 338}; 339 340struct nouveau_fifo_engine { 341 void *priv; 342 int channels; 343 344 struct nouveau_gpuobj *playlist[2]; 345 int cur_playlist; 346 347 int (*init)(struct drm_device *); 348 void (*takedown)(struct drm_device *); 349 350 void (*disable)(struct drm_device *); 351 void (*enable)(struct drm_device *); 352 bool (*reassign)(struct drm_device *, bool enable); 353 bool (*cache_pull)(struct drm_device *dev, bool enable); 354 355 int (*channel_id)(struct drm_device *); 356 357 int (*create_context)(struct nouveau_channel *); 358 void (*destroy_context)(struct nouveau_channel *); 359 int (*load_context)(struct nouveau_channel *); 360 int (*unload_context)(struct drm_device *); 361 void (*tlb_flush)(struct drm_device *dev); 362}; 363 364struct nouveau_pgraph_engine { 365 bool accel_blocked; 366 bool registered; 367 int grctx_size; 368 369 /* NV2x/NV3x context table (0x400780) */ 370 struct nouveau_gpuobj *ctx_table; 371 372 int (*init)(struct drm_device *); 373 void (*takedown)(struct drm_device *); 374 375 void (*fifo_access)(struct drm_device *, bool); 376 377 struct nouveau_channel *(*channel)(struct drm_device *); 378 int (*create_context)(struct nouveau_channel *); 379 void (*destroy_context)(struct nouveau_channel *); 380 int (*load_context)(struct nouveau_channel *); 381 int (*unload_context)(struct drm_device *); 382 void (*tlb_flush)(struct drm_device *dev); 383 384 void (*set_tile_region)(struct drm_device *dev, int i); 385}; 386 387struct nouveau_display_engine { 388 int (*early_init)(struct drm_device *); 389 void (*late_takedown)(struct drm_device *); 390 int (*create)(struct drm_device *); 391 int (*init)(struct drm_device *); 392 void (*destroy)(struct drm_device *); 393}; 394 395struct nouveau_gpio_engine { 396 void *priv; 397 398 int (*init)(struct drm_device *); 399 void (*takedown)(struct drm_device *); 400 401 int (*get)(struct drm_device *, enum dcb_gpio_tag); 402 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 403 404 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 405 void (*)(void *, int), void *); 406 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 407 void (*)(void *, int), void *); 408 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 409}; 410 411struct nouveau_pm_voltage_level { 412 u8 voltage; 413 u8 vid; 414}; 415 416struct nouveau_pm_voltage { 417 bool supported; 418 u8 vid_mask; 419 420 struct nouveau_pm_voltage_level *level; 421 int nr_level; 422}; 423 424#define NOUVEAU_PM_MAX_LEVEL 8 425struct nouveau_pm_level { 426 struct device_attribute dev_attr; 427 char name[32]; 428 int id; 429 430 u32 core; 431 u32 memory; 432 u32 shader; 433 u32 unk05; 434 435 u8 voltage; 436 u8 fanspeed; 437 438 u16 memscript; 439}; 440 441struct nouveau_pm_temp_sensor_constants { 442 u16 offset_constant; 443 s16 offset_mult; 444 u16 offset_div; 445 u16 slope_mult; 446 u16 slope_div; 447}; 448 449struct nouveau_pm_threshold_temp { 450 s16 critical; 451 s16 down_clock; 452 s16 fan_boost; 453}; 454 455struct nouveau_pm_memtiming { 456 u32 reg_100220; 457 u32 reg_100224; 458 u32 reg_100228; 459 u32 reg_10022c; 460 u32 reg_100230; 461 u32 reg_100234; 462 u32 reg_100238; 463 u32 reg_10023c; 464}; 465 466struct nouveau_pm_memtimings { 467 bool supported; 468 struct nouveau_pm_memtiming *timing; 469 int nr_timing; 470}; 471 472struct nouveau_pm_engine { 473 struct nouveau_pm_voltage voltage; 474 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 475 int nr_perflvl; 476 struct nouveau_pm_memtimings memtimings; 477 struct nouveau_pm_temp_sensor_constants sensor_constants; 478 struct nouveau_pm_threshold_temp threshold_temp; 479 480 struct nouveau_pm_level boot; 481 struct nouveau_pm_level *cur; 482 483 struct device *hwmon; 484 struct notifier_block acpi_nb; 485 486 int (*clock_get)(struct drm_device *, u32 id); 487 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 488 u32 id, int khz); 489 void (*clock_set)(struct drm_device *, void *); 490 int (*voltage_get)(struct drm_device *); 491 int (*voltage_set)(struct drm_device *, int voltage); 492 int (*fanspeed_get)(struct drm_device *); 493 int (*fanspeed_set)(struct drm_device *, int fanspeed); 494 int (*temp_get)(struct drm_device *); 495}; 496 497struct nouveau_crypt_engine { 498 bool registered; 499 500 int (*init)(struct drm_device *); 501 void (*takedown)(struct drm_device *); 502 int (*create_context)(struct nouveau_channel *); 503 void (*destroy_context)(struct nouveau_channel *); 504 void (*tlb_flush)(struct drm_device *dev); 505}; 506 507struct nouveau_vram_engine { 508 int (*init)(struct drm_device *); 509 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 510 u32 type, struct nouveau_vram **); 511 void (*put)(struct drm_device *, struct nouveau_vram **); 512 513 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 514}; 515 516struct nouveau_engine { 517 struct nouveau_instmem_engine instmem; 518 struct nouveau_mc_engine mc; 519 struct nouveau_timer_engine timer; 520 struct nouveau_fb_engine fb; 521 struct nouveau_pgraph_engine graph; 522 struct nouveau_fifo_engine fifo; 523 struct nouveau_display_engine display; 524 struct nouveau_gpio_engine gpio; 525 struct nouveau_pm_engine pm; 526 struct nouveau_crypt_engine crypt; 527 struct nouveau_vram_engine vram; 528}; 529 530struct nouveau_pll_vals { 531 union { 532 struct { 533#ifdef __BIG_ENDIAN 534 uint8_t N1, M1, N2, M2; 535#else 536 uint8_t M1, N1, M2, N2; 537#endif 538 }; 539 struct { 540 uint16_t NM1, NM2; 541 } __attribute__((packed)); 542 }; 543 int log2P; 544 545 int refclk; 546}; 547 548enum nv04_fp_display_regs { 549 FP_DISPLAY_END, 550 FP_TOTAL, 551 FP_CRTC, 552 FP_SYNC_START, 553 FP_SYNC_END, 554 FP_VALID_START, 555 FP_VALID_END 556}; 557 558struct nv04_crtc_reg { 559 unsigned char MiscOutReg; 560 uint8_t CRTC[0xa0]; 561 uint8_t CR58[0x10]; 562 uint8_t Sequencer[5]; 563 uint8_t Graphics[9]; 564 uint8_t Attribute[21]; 565 unsigned char DAC[768]; 566 567 /* PCRTC regs */ 568 uint32_t fb_start; 569 uint32_t crtc_cfg; 570 uint32_t cursor_cfg; 571 uint32_t gpio_ext; 572 uint32_t crtc_830; 573 uint32_t crtc_834; 574 uint32_t crtc_850; 575 uint32_t crtc_eng_ctrl; 576 577 /* PRAMDAC regs */ 578 uint32_t nv10_cursync; 579 struct nouveau_pll_vals pllvals; 580 uint32_t ramdac_gen_ctrl; 581 uint32_t ramdac_630; 582 uint32_t ramdac_634; 583 uint32_t tv_setup; 584 uint32_t tv_vtotal; 585 uint32_t tv_vskew; 586 uint32_t tv_vsync_delay; 587 uint32_t tv_htotal; 588 uint32_t tv_hskew; 589 uint32_t tv_hsync_delay; 590 uint32_t tv_hsync_delay2; 591 uint32_t fp_horiz_regs[7]; 592 uint32_t fp_vert_regs[7]; 593 uint32_t dither; 594 uint32_t fp_control; 595 uint32_t dither_regs[6]; 596 uint32_t fp_debug_0; 597 uint32_t fp_debug_1; 598 uint32_t fp_debug_2; 599 uint32_t fp_margin_color; 600 uint32_t ramdac_8c0; 601 uint32_t ramdac_a20; 602 uint32_t ramdac_a24; 603 uint32_t ramdac_a34; 604 uint32_t ctv_regs[38]; 605}; 606 607struct nv04_output_reg { 608 uint32_t output; 609 int head; 610}; 611 612struct nv04_mode_state { 613 struct nv04_crtc_reg crtc_reg[2]; 614 uint32_t pllsel; 615 uint32_t sel_clk; 616}; 617 618enum nouveau_card_type { 619 NV_04 = 0x00, 620 NV_10 = 0x10, 621 NV_20 = 0x20, 622 NV_30 = 0x30, 623 NV_40 = 0x40, 624 NV_50 = 0x50, 625 NV_C0 = 0xc0, 626}; 627 628struct drm_nouveau_private { 629 struct drm_device *dev; 630 631 /* the card type, takes NV_* as values */ 632 enum nouveau_card_type card_type; 633 /* exact chipset, derived from NV_PMC_BOOT_0 */ 634 int chipset; 635 int flags; 636 637 void __iomem *mmio; 638 639 spinlock_t ramin_lock; 640 void __iomem *ramin; 641 u32 ramin_size; 642 u32 ramin_base; 643 bool ramin_available; 644 struct drm_mm ramin_heap; 645 struct list_head gpuobj_list; 646 struct list_head classes; 647 648 struct nouveau_bo *vga_ram; 649 650 /* interrupt handling */ 651 void (*irq_handler[32])(struct drm_device *); 652 bool msi_enabled; 653 struct workqueue_struct *wq; 654 struct work_struct irq_work; 655 656 struct list_head vbl_waiting; 657 658 struct { 659 struct drm_global_reference mem_global_ref; 660 struct ttm_bo_global_ref bo_global_ref; 661 struct ttm_bo_device bdev; 662 atomic_t validate_sequence; 663 } ttm; 664 665 struct { 666 spinlock_t lock; 667 struct drm_mm heap; 668 struct nouveau_bo *bo; 669 } fence; 670 671 struct { 672 spinlock_t lock; 673 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 674 } channels; 675 676 struct nouveau_engine engine; 677 struct nouveau_channel *channel; 678 679 /* For PFIFO and PGRAPH. */ 680 spinlock_t context_switch_lock; 681 682 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 683 struct nouveau_ramht *ramht; 684 struct nouveau_gpuobj *ramfc; 685 struct nouveau_gpuobj *ramro; 686 687 uint32_t ramin_rsvd_vram; 688 689 struct { 690 enum { 691 NOUVEAU_GART_NONE = 0, 692 NOUVEAU_GART_AGP, 693 NOUVEAU_GART_SGDMA 694 } type; 695 uint64_t aper_base; 696 uint64_t aper_size; 697 uint64_t aper_free; 698 699 struct nouveau_gpuobj *sg_ctxdma; 700 struct nouveau_vma vma; 701 } gart_info; 702 703 /* nv10-nv40 tiling regions */ 704 struct { 705 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 706 spinlock_t lock; 707 } tile; 708 709 /* VRAM/fb configuration */ 710 uint64_t vram_size; 711 uint64_t vram_sys_base; 712 u32 vram_rblock_size; 713 714 uint64_t fb_phys; 715 uint64_t fb_available_size; 716 uint64_t fb_mappable_pages; 717 uint64_t fb_aper_free; 718 int fb_mtrr; 719 720 /* BAR control (NV50-) */ 721 struct nouveau_vm *bar1_vm; 722 struct nouveau_vm *bar3_vm; 723 724 /* G8x/G9x virtual address space */ 725 struct nouveau_vm *chan_vm; 726 727 struct nvbios vbios; 728 729 struct nv04_mode_state mode_reg; 730 struct nv04_mode_state saved_reg; 731 uint32_t saved_vga_font[4][16384]; 732 uint32_t crtc_owner; 733 uint32_t dac_users[4]; 734 735 struct nouveau_suspend_resume { 736 uint32_t *ramin_copy; 737 } susres; 738 739 struct backlight_device *backlight; 740 741 struct nouveau_channel *evo; 742 u32 evo_alloc; 743 struct { 744 struct dcb_entry *dcb; 745 u16 script; 746 u32 pclk; 747 } evo_irq; 748 749 struct { 750 struct dentry *channel_root; 751 } debugfs; 752 753 struct nouveau_fbdev *nfbdev; 754 struct apertures_struct *apertures; 755}; 756 757static inline struct drm_nouveau_private * 758nouveau_private(struct drm_device *dev) 759{ 760 return dev->dev_private; 761} 762 763static inline struct drm_nouveau_private * 764nouveau_bdev(struct ttm_bo_device *bd) 765{ 766 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 767} 768 769static inline int 770nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 771{ 772 struct nouveau_bo *prev; 773 774 if (!pnvbo) 775 return -EINVAL; 776 prev = *pnvbo; 777 778 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 779 if (prev) { 780 struct ttm_buffer_object *bo = &prev->bo; 781 782 ttm_bo_unref(&bo); 783 } 784 785 return 0; 786} 787 788/* nouveau_drv.c */ 789extern int nouveau_agpmode; 790extern int nouveau_duallink; 791extern int nouveau_uscript_lvds; 792extern int nouveau_uscript_tmds; 793extern int nouveau_vram_pushbuf; 794extern int nouveau_vram_notify; 795extern int nouveau_fbpercrtc; 796extern int nouveau_tv_disable; 797extern char *nouveau_tv_norm; 798extern int nouveau_reg_debug; 799extern char *nouveau_vbios; 800extern int nouveau_ignorelid; 801extern int nouveau_nofbaccel; 802extern int nouveau_noaccel; 803extern int nouveau_force_post; 804extern int nouveau_override_conntype; 805extern char *nouveau_perflvl; 806extern int nouveau_perflvl_wr; 807extern int nouveau_msi; 808 809extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 810extern int nouveau_pci_resume(struct pci_dev *pdev); 811 812/* nouveau_state.c */ 813extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 814extern int nouveau_load(struct drm_device *, unsigned long flags); 815extern int nouveau_firstopen(struct drm_device *); 816extern void nouveau_lastclose(struct drm_device *); 817extern int nouveau_unload(struct drm_device *); 818extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 819 struct drm_file *); 820extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 821 struct drm_file *); 822extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 823 uint32_t reg, uint32_t mask, uint32_t val); 824extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 825 uint32_t reg, uint32_t mask, uint32_t val); 826extern bool nouveau_wait_for_idle(struct drm_device *); 827extern int nouveau_card_init(struct drm_device *); 828 829/* nouveau_mem.c */ 830extern int nouveau_mem_vram_init(struct drm_device *); 831extern void nouveau_mem_vram_fini(struct drm_device *); 832extern int nouveau_mem_gart_init(struct drm_device *); 833extern void nouveau_mem_gart_fini(struct drm_device *); 834extern int nouveau_mem_init_agp(struct drm_device *); 835extern int nouveau_mem_reset_agp(struct drm_device *); 836extern void nouveau_mem_close(struct drm_device *); 837extern int nouveau_mem_detect(struct drm_device *); 838extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 839extern struct nouveau_tile_reg *nv10_mem_set_tiling( 840 struct drm_device *dev, uint32_t addr, uint32_t size, 841 uint32_t pitch, uint32_t flags); 842extern void nv10_mem_put_tile_region(struct drm_device *dev, 843 struct nouveau_tile_reg *tile, 844 struct nouveau_fence *fence); 845extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 846 847/* nvc0_vram.c */ 848extern const struct ttm_mem_type_manager_func nvc0_vram_manager; 849 850/* nouveau_notifier.c */ 851extern int nouveau_notifier_init_channel(struct nouveau_channel *); 852extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 853extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 854 int cout, uint32_t *offset); 855extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 856extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 857 struct drm_file *); 858extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 859 struct drm_file *); 860 861/* nouveau_channel.c */ 862extern struct drm_ioctl_desc nouveau_ioctls[]; 863extern int nouveau_max_ioctl; 864extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 865extern int nouveau_channel_alloc(struct drm_device *dev, 866 struct nouveau_channel **chan, 867 struct drm_file *file_priv, 868 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 869extern struct nouveau_channel * 870nouveau_channel_get_unlocked(struct nouveau_channel *); 871extern struct nouveau_channel * 872nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 873extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 874extern void nouveau_channel_put(struct nouveau_channel **); 875extern void nouveau_channel_ref(struct nouveau_channel *chan, 876 struct nouveau_channel **pchan); 877extern void nouveau_channel_idle(struct nouveau_channel *chan); 878 879/* nouveau_object.c */ 880#define NVOBJ_CLASS(d,c,e) do { \ 881 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 882 if (ret) \ 883 return ret; \ 884} while(0) 885 886#define NVOBJ_MTHD(d,c,m,e) do { \ 887 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 888 if (ret) \ 889 return ret; \ 890} while(0) 891 892extern int nouveau_gpuobj_early_init(struct drm_device *); 893extern int nouveau_gpuobj_init(struct drm_device *); 894extern void nouveau_gpuobj_takedown(struct drm_device *); 895extern int nouveau_gpuobj_suspend(struct drm_device *dev); 896extern void nouveau_gpuobj_resume(struct drm_device *dev); 897extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 898extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 899 int (*exec)(struct nouveau_channel *, 900 u32 class, u32 mthd, u32 data)); 901extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 902extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 903extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 904 uint32_t vram_h, uint32_t tt_h); 905extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 906extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 907 uint32_t size, int align, uint32_t flags, 908 struct nouveau_gpuobj **); 909extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 910 struct nouveau_gpuobj **); 911extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 912 u32 size, u32 flags, 913 struct nouveau_gpuobj **); 914extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 915 uint64_t offset, uint64_t size, int access, 916 int target, struct nouveau_gpuobj **); 917extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 918extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 919 u64 size, int target, int access, u32 type, 920 u32 comp, struct nouveau_gpuobj **pobj); 921extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 922 int class, u64 base, u64 size, int target, 923 int access, u32 type, u32 comp); 924extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 925 struct drm_file *); 926extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 927 struct drm_file *); 928 929/* nouveau_irq.c */ 930extern int nouveau_irq_init(struct drm_device *); 931extern void nouveau_irq_fini(struct drm_device *); 932extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 933extern void nouveau_irq_register(struct drm_device *, int status_bit, 934 void (*)(struct drm_device *)); 935extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 936extern void nouveau_irq_preinstall(struct drm_device *); 937extern int nouveau_irq_postinstall(struct drm_device *); 938extern void nouveau_irq_uninstall(struct drm_device *); 939 940/* nouveau_sgdma.c */ 941extern int nouveau_sgdma_init(struct drm_device *); 942extern void nouveau_sgdma_takedown(struct drm_device *); 943extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 944 uint32_t offset); 945extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 946 947/* nouveau_debugfs.c */ 948#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 949extern int nouveau_debugfs_init(struct drm_minor *); 950extern void nouveau_debugfs_takedown(struct drm_minor *); 951extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 952extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 953#else 954static inline int 955nouveau_debugfs_init(struct drm_minor *minor) 956{ 957 return 0; 958} 959 960static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 961{ 962} 963 964static inline int 965nouveau_debugfs_channel_init(struct nouveau_channel *chan) 966{ 967 return 0; 968} 969 970static inline void 971nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 972{ 973} 974#endif 975 976/* nouveau_dma.c */ 977extern void nouveau_dma_pre_init(struct nouveau_channel *); 978extern int nouveau_dma_init(struct nouveau_channel *); 979extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 980 981/* nouveau_acpi.c */ 982#define ROM_BIOS_PAGE 4096 983#if defined(CONFIG_ACPI) 984void nouveau_register_dsm_handler(void); 985void nouveau_unregister_dsm_handler(void); 986int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 987bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 988int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 989#else 990static inline void nouveau_register_dsm_handler(void) {} 991static inline void nouveau_unregister_dsm_handler(void) {} 992static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 993static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 994static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 995#endif 996 997/* nouveau_backlight.c */ 998#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 999extern int nouveau_backlight_init(struct drm_device *); 1000extern void nouveau_backlight_exit(struct drm_device *); 1001#else 1002static inline int nouveau_backlight_init(struct drm_device *dev) 1003{ 1004 return 0; 1005} 1006 1007static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1008#endif 1009 1010/* nouveau_bios.c */ 1011extern int nouveau_bios_init(struct drm_device *); 1012extern void nouveau_bios_takedown(struct drm_device *dev); 1013extern int nouveau_run_vbios_init(struct drm_device *); 1014extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1015 struct dcb_entry *); 1016extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1017 enum dcb_gpio_tag); 1018extern struct dcb_connector_table_entry * 1019nouveau_bios_connector_entry(struct drm_device *, int index); 1020extern u32 get_pll_register(struct drm_device *, enum pll_types); 1021extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1022 struct pll_lims *); 1023extern int nouveau_bios_run_display_table(struct drm_device *, 1024 struct dcb_entry *, 1025 uint32_t script, int pxclk); 1026extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1027 int *length); 1028extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1029extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1030extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1031 bool *dl, bool *if_is_24bit); 1032extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1033 int head, int pxclk); 1034extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1035 enum LVDS_script, int pxclk); 1036 1037/* nouveau_ttm.c */ 1038int nouveau_ttm_global_init(struct drm_nouveau_private *); 1039void nouveau_ttm_global_release(struct drm_nouveau_private *); 1040int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1041 1042/* nouveau_dp.c */ 1043int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1044 uint8_t *data, int data_nr); 1045bool nouveau_dp_detect(struct drm_encoder *); 1046bool nouveau_dp_link_train(struct drm_encoder *); 1047 1048/* nv04_fb.c */ 1049extern int nv04_fb_init(struct drm_device *); 1050extern void nv04_fb_takedown(struct drm_device *); 1051 1052/* nv10_fb.c */ 1053extern int nv10_fb_init(struct drm_device *); 1054extern void nv10_fb_takedown(struct drm_device *); 1055extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1056 uint32_t addr, uint32_t size, 1057 uint32_t pitch, uint32_t flags); 1058extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1059extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1060 1061/* nv30_fb.c */ 1062extern int nv30_fb_init(struct drm_device *); 1063extern void nv30_fb_takedown(struct drm_device *); 1064extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1065 uint32_t addr, uint32_t size, 1066 uint32_t pitch, uint32_t flags); 1067extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1068 1069/* nv40_fb.c */ 1070extern int nv40_fb_init(struct drm_device *); 1071extern void nv40_fb_takedown(struct drm_device *); 1072extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1073 1074/* nv50_fb.c */ 1075extern int nv50_fb_init(struct drm_device *); 1076extern void nv50_fb_takedown(struct drm_device *); 1077extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1078 1079/* nvc0_fb.c */ 1080extern int nvc0_fb_init(struct drm_device *); 1081extern void nvc0_fb_takedown(struct drm_device *); 1082 1083/* nv04_fifo.c */ 1084extern int nv04_fifo_init(struct drm_device *); 1085extern void nv04_fifo_fini(struct drm_device *); 1086extern void nv04_fifo_disable(struct drm_device *); 1087extern void nv04_fifo_enable(struct drm_device *); 1088extern bool nv04_fifo_reassign(struct drm_device *, bool); 1089extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1090extern int nv04_fifo_channel_id(struct drm_device *); 1091extern int nv04_fifo_create_context(struct nouveau_channel *); 1092extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1093extern int nv04_fifo_load_context(struct nouveau_channel *); 1094extern int nv04_fifo_unload_context(struct drm_device *); 1095extern void nv04_fifo_isr(struct drm_device *); 1096 1097/* nv10_fifo.c */ 1098extern int nv10_fifo_init(struct drm_device *); 1099extern int nv10_fifo_channel_id(struct drm_device *); 1100extern int nv10_fifo_create_context(struct nouveau_channel *); 1101extern int nv10_fifo_load_context(struct nouveau_channel *); 1102extern int nv10_fifo_unload_context(struct drm_device *); 1103 1104/* nv40_fifo.c */ 1105extern int nv40_fifo_init(struct drm_device *); 1106extern int nv40_fifo_create_context(struct nouveau_channel *); 1107extern int nv40_fifo_load_context(struct nouveau_channel *); 1108extern int nv40_fifo_unload_context(struct drm_device *); 1109 1110/* nv50_fifo.c */ 1111extern int nv50_fifo_init(struct drm_device *); 1112extern void nv50_fifo_takedown(struct drm_device *); 1113extern int nv50_fifo_channel_id(struct drm_device *); 1114extern int nv50_fifo_create_context(struct nouveau_channel *); 1115extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1116extern int nv50_fifo_load_context(struct nouveau_channel *); 1117extern int nv50_fifo_unload_context(struct drm_device *); 1118extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1119 1120/* nvc0_fifo.c */ 1121extern int nvc0_fifo_init(struct drm_device *); 1122extern void nvc0_fifo_takedown(struct drm_device *); 1123extern void nvc0_fifo_disable(struct drm_device *); 1124extern void nvc0_fifo_enable(struct drm_device *); 1125extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1126extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1127extern int nvc0_fifo_channel_id(struct drm_device *); 1128extern int nvc0_fifo_create_context(struct nouveau_channel *); 1129extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1130extern int nvc0_fifo_load_context(struct nouveau_channel *); 1131extern int nvc0_fifo_unload_context(struct drm_device *); 1132 1133/* nv04_graph.c */ 1134extern int nv04_graph_init(struct drm_device *); 1135extern void nv04_graph_takedown(struct drm_device *); 1136extern void nv04_graph_fifo_access(struct drm_device *, bool); 1137extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1138extern int nv04_graph_create_context(struct nouveau_channel *); 1139extern void nv04_graph_destroy_context(struct nouveau_channel *); 1140extern int nv04_graph_load_context(struct nouveau_channel *); 1141extern int nv04_graph_unload_context(struct drm_device *); 1142extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1143 u32 class, u32 mthd, u32 data); 1144extern struct nouveau_bitfield nv04_graph_nsource[]; 1145 1146/* nv10_graph.c */ 1147extern int nv10_graph_init(struct drm_device *); 1148extern void nv10_graph_takedown(struct drm_device *); 1149extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1150extern int nv10_graph_create_context(struct nouveau_channel *); 1151extern void nv10_graph_destroy_context(struct nouveau_channel *); 1152extern int nv10_graph_load_context(struct nouveau_channel *); 1153extern int nv10_graph_unload_context(struct drm_device *); 1154extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1155extern struct nouveau_bitfield nv10_graph_intr[]; 1156extern struct nouveau_bitfield nv10_graph_nstatus[]; 1157 1158/* nv20_graph.c */ 1159extern int nv20_graph_create_context(struct nouveau_channel *); 1160extern void nv20_graph_destroy_context(struct nouveau_channel *); 1161extern int nv20_graph_load_context(struct nouveau_channel *); 1162extern int nv20_graph_unload_context(struct drm_device *); 1163extern int nv20_graph_init(struct drm_device *); 1164extern void nv20_graph_takedown(struct drm_device *); 1165extern int nv30_graph_init(struct drm_device *); 1166extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1167 1168/* nv40_graph.c */ 1169extern int nv40_graph_init(struct drm_device *); 1170extern void nv40_graph_takedown(struct drm_device *); 1171extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1172extern int nv40_graph_create_context(struct nouveau_channel *); 1173extern void nv40_graph_destroy_context(struct nouveau_channel *); 1174extern int nv40_graph_load_context(struct nouveau_channel *); 1175extern int nv40_graph_unload_context(struct drm_device *); 1176extern void nv40_grctx_init(struct nouveau_grctx *); 1177extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1178 1179/* nv50_graph.c */ 1180extern int nv50_graph_init(struct drm_device *); 1181extern void nv50_graph_takedown(struct drm_device *); 1182extern void nv50_graph_fifo_access(struct drm_device *, bool); 1183extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1184extern int nv50_graph_create_context(struct nouveau_channel *); 1185extern void nv50_graph_destroy_context(struct nouveau_channel *); 1186extern int nv50_graph_load_context(struct nouveau_channel *); 1187extern int nv50_graph_unload_context(struct drm_device *); 1188extern int nv50_grctx_init(struct nouveau_grctx *); 1189extern void nv50_graph_tlb_flush(struct drm_device *dev); 1190extern void nv86_graph_tlb_flush(struct drm_device *dev); 1191 1192/* nvc0_graph.c */ 1193extern int nvc0_graph_init(struct drm_device *); 1194extern void nvc0_graph_takedown(struct drm_device *); 1195extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1196extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1197extern int nvc0_graph_create_context(struct nouveau_channel *); 1198extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1199extern int nvc0_graph_load_context(struct nouveau_channel *); 1200extern int nvc0_graph_unload_context(struct drm_device *); 1201 1202/* nv84_crypt.c */ 1203extern int nv84_crypt_init(struct drm_device *dev); 1204extern void nv84_crypt_fini(struct drm_device *dev); 1205extern int nv84_crypt_create_context(struct nouveau_channel *); 1206extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1207extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1208 1209/* nv04_instmem.c */ 1210extern int nv04_instmem_init(struct drm_device *); 1211extern void nv04_instmem_takedown(struct drm_device *); 1212extern int nv04_instmem_suspend(struct drm_device *); 1213extern void nv04_instmem_resume(struct drm_device *); 1214extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1215extern void nv04_instmem_put(struct nouveau_gpuobj *); 1216extern int nv04_instmem_map(struct nouveau_gpuobj *); 1217extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1218extern void nv04_instmem_flush(struct drm_device *); 1219 1220/* nv50_instmem.c */ 1221extern int nv50_instmem_init(struct drm_device *); 1222extern void nv50_instmem_takedown(struct drm_device *); 1223extern int nv50_instmem_suspend(struct drm_device *); 1224extern void nv50_instmem_resume(struct drm_device *); 1225extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1226extern void nv50_instmem_put(struct nouveau_gpuobj *); 1227extern int nv50_instmem_map(struct nouveau_gpuobj *); 1228extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1229extern void nv50_instmem_flush(struct drm_device *); 1230extern void nv84_instmem_flush(struct drm_device *); 1231 1232/* nvc0_instmem.c */ 1233extern int nvc0_instmem_init(struct drm_device *); 1234extern void nvc0_instmem_takedown(struct drm_device *); 1235extern int nvc0_instmem_suspend(struct drm_device *); 1236extern void nvc0_instmem_resume(struct drm_device *); 1237 1238/* nv04_mc.c */ 1239extern int nv04_mc_init(struct drm_device *); 1240extern void nv04_mc_takedown(struct drm_device *); 1241 1242/* nv40_mc.c */ 1243extern int nv40_mc_init(struct drm_device *); 1244extern void nv40_mc_takedown(struct drm_device *); 1245 1246/* nv50_mc.c */ 1247extern int nv50_mc_init(struct drm_device *); 1248extern void nv50_mc_takedown(struct drm_device *); 1249 1250/* nv04_timer.c */ 1251extern int nv04_timer_init(struct drm_device *); 1252extern uint64_t nv04_timer_read(struct drm_device *); 1253extern void nv04_timer_takedown(struct drm_device *); 1254 1255extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1256 unsigned long arg); 1257 1258/* nv04_dac.c */ 1259extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1260extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1261extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1262extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1263extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1264 1265/* nv04_dfp.c */ 1266extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1267extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1268extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1269 int head, bool dl); 1270extern void nv04_dfp_disable(struct drm_device *dev, int head); 1271extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1272 1273/* nv04_tv.c */ 1274extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1275extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1276 1277/* nv17_tv.c */ 1278extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1279 1280/* nv04_display.c */ 1281extern int nv04_display_early_init(struct drm_device *); 1282extern void nv04_display_late_takedown(struct drm_device *); 1283extern int nv04_display_create(struct drm_device *); 1284extern int nv04_display_init(struct drm_device *); 1285extern void nv04_display_destroy(struct drm_device *); 1286 1287/* nv04_crtc.c */ 1288extern int nv04_crtc_create(struct drm_device *, int index); 1289 1290/* nouveau_bo.c */ 1291extern struct ttm_bo_driver nouveau_bo_driver; 1292extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1293 int size, int align, uint32_t flags, 1294 uint32_t tile_mode, uint32_t tile_flags, 1295 bool no_vm, bool mappable, struct nouveau_bo **); 1296extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1297extern int nouveau_bo_unpin(struct nouveau_bo *); 1298extern int nouveau_bo_map(struct nouveau_bo *); 1299extern void nouveau_bo_unmap(struct nouveau_bo *); 1300extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1301 uint32_t busy); 1302extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1303extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1304extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1305extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1306extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1307extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1308 bool no_wait_reserve, bool no_wait_gpu); 1309 1310/* nouveau_fence.c */ 1311struct nouveau_fence; 1312extern int nouveau_fence_init(struct drm_device *); 1313extern void nouveau_fence_fini(struct drm_device *); 1314extern int nouveau_fence_channel_init(struct nouveau_channel *); 1315extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1316extern void nouveau_fence_update(struct nouveau_channel *); 1317extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1318 bool emit); 1319extern int nouveau_fence_emit(struct nouveau_fence *); 1320extern void nouveau_fence_work(struct nouveau_fence *fence, 1321 void (*work)(void *priv, bool signalled), 1322 void *priv); 1323struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1324 1325extern bool __nouveau_fence_signalled(void *obj, void *arg); 1326extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1327extern int __nouveau_fence_flush(void *obj, void *arg); 1328extern void __nouveau_fence_unref(void **obj); 1329extern void *__nouveau_fence_ref(void *obj); 1330 1331static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1332{ 1333 return __nouveau_fence_signalled(obj, NULL); 1334} 1335static inline int 1336nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1337{ 1338 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1339} 1340extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1341static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1342{ 1343 return __nouveau_fence_flush(obj, NULL); 1344} 1345static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1346{ 1347 __nouveau_fence_unref((void **)obj); 1348} 1349static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1350{ 1351 return __nouveau_fence_ref(obj); 1352} 1353 1354/* nouveau_gem.c */ 1355extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1356 int size, int align, uint32_t flags, 1357 uint32_t tile_mode, uint32_t tile_flags, 1358 bool no_vm, bool mappable, struct nouveau_bo **); 1359extern int nouveau_gem_object_new(struct drm_gem_object *); 1360extern void nouveau_gem_object_del(struct drm_gem_object *); 1361extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1362 struct drm_file *); 1363extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1364 struct drm_file *); 1365extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1366 struct drm_file *); 1367extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1368 struct drm_file *); 1369extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1370 struct drm_file *); 1371 1372/* nouveau_display.c */ 1373int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1374void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1375int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1376 struct drm_pending_vblank_event *event); 1377int nouveau_finish_page_flip(struct nouveau_channel *, 1378 struct nouveau_page_flip_state *); 1379 1380/* nv10_gpio.c */ 1381int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1382int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1383 1384/* nv50_gpio.c */ 1385int nv50_gpio_init(struct drm_device *dev); 1386void nv50_gpio_fini(struct drm_device *dev); 1387int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1388int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1389int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1390 void (*)(void *, int), void *); 1391void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1392 void (*)(void *, int), void *); 1393bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1394 1395/* nv50_calc. */ 1396int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1397 int *N1, int *M1, int *N2, int *M2, int *P); 1398int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1399 int clk, int *N, int *fN, int *M, int *P); 1400 1401#ifndef ioread32_native 1402#ifdef __BIG_ENDIAN 1403#define ioread16_native ioread16be 1404#define iowrite16_native iowrite16be 1405#define ioread32_native ioread32be 1406#define iowrite32_native iowrite32be 1407#else /* def __BIG_ENDIAN */ 1408#define ioread16_native ioread16 1409#define iowrite16_native iowrite16 1410#define ioread32_native ioread32 1411#define iowrite32_native iowrite32 1412#endif /* def __BIG_ENDIAN else */ 1413#endif /* !ioread32_native */ 1414 1415/* channel control reg access */ 1416static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1417{ 1418 return ioread32_native(chan->user + reg); 1419} 1420 1421static inline void nvchan_wr32(struct nouveau_channel *chan, 1422 unsigned reg, u32 val) 1423{ 1424 iowrite32_native(val, chan->user + reg); 1425} 1426 1427/* register access */ 1428static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1429{ 1430 struct drm_nouveau_private *dev_priv = dev->dev_private; 1431 return ioread32_native(dev_priv->mmio + reg); 1432} 1433 1434static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1435{ 1436 struct drm_nouveau_private *dev_priv = dev->dev_private; 1437 iowrite32_native(val, dev_priv->mmio + reg); 1438} 1439 1440static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1441{ 1442 u32 tmp = nv_rd32(dev, reg); 1443 nv_wr32(dev, reg, (tmp & ~mask) | val); 1444 return tmp; 1445} 1446 1447static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1448{ 1449 struct drm_nouveau_private *dev_priv = dev->dev_private; 1450 return ioread8(dev_priv->mmio + reg); 1451} 1452 1453static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1454{ 1455 struct drm_nouveau_private *dev_priv = dev->dev_private; 1456 iowrite8(val, dev_priv->mmio + reg); 1457} 1458 1459#define nv_wait(dev, reg, mask, val) \ 1460 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1461#define nv_wait_ne(dev, reg, mask, val) \ 1462 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1463 1464/* PRAMIN access */ 1465static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1466{ 1467 struct drm_nouveau_private *dev_priv = dev->dev_private; 1468 return ioread32_native(dev_priv->ramin + offset); 1469} 1470 1471static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1472{ 1473 struct drm_nouveau_private *dev_priv = dev->dev_private; 1474 iowrite32_native(val, dev_priv->ramin + offset); 1475} 1476 1477/* object access */ 1478extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1479extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1480 1481/* 1482 * Logging 1483 * Argument d is (struct drm_device *). 1484 */ 1485#define NV_PRINTK(level, d, fmt, arg...) \ 1486 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1487 pci_name(d->pdev), ##arg) 1488#ifndef NV_DEBUG_NOTRACE 1489#define NV_DEBUG(d, fmt, arg...) do { \ 1490 if (drm_debug & DRM_UT_DRIVER) { \ 1491 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1492 __LINE__, ##arg); \ 1493 } \ 1494} while (0) 1495#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1496 if (drm_debug & DRM_UT_KMS) { \ 1497 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1498 __LINE__, ##arg); \ 1499 } \ 1500} while (0) 1501#else 1502#define NV_DEBUG(d, fmt, arg...) do { \ 1503 if (drm_debug & DRM_UT_DRIVER) \ 1504 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1505} while (0) 1506#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1507 if (drm_debug & DRM_UT_KMS) \ 1508 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1509} while (0) 1510#endif 1511#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1512#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1513#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1514#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1515#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1516 1517/* nouveau_reg_debug bitmask */ 1518enum { 1519 NOUVEAU_REG_DEBUG_MC = 0x1, 1520 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1521 NOUVEAU_REG_DEBUG_FB = 0x4, 1522 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1523 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1524 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1525 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1526 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1527 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1528 NOUVEAU_REG_DEBUG_EVO = 0x200, 1529}; 1530 1531#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1532 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1533 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1534} while (0) 1535 1536static inline bool 1537nv_two_heads(struct drm_device *dev) 1538{ 1539 struct drm_nouveau_private *dev_priv = dev->dev_private; 1540 const int impl = dev->pci_device & 0x0ff0; 1541 1542 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1543 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1544 return true; 1545 1546 return false; 1547} 1548 1549static inline bool 1550nv_gf4_disp_arch(struct drm_device *dev) 1551{ 1552 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1553} 1554 1555static inline bool 1556nv_two_reg_pll(struct drm_device *dev) 1557{ 1558 struct drm_nouveau_private *dev_priv = dev->dev_private; 1559 const int impl = dev->pci_device & 0x0ff0; 1560 1561 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1562 return true; 1563 return false; 1564} 1565 1566static inline bool 1567nv_match_device(struct drm_device *dev, unsigned device, 1568 unsigned sub_vendor, unsigned sub_device) 1569{ 1570 return dev->pdev->device == device && 1571 dev->pdev->subsystem_vendor == sub_vendor && 1572 dev->pdev->subsystem_device == sub_device; 1573} 1574 1575/* memory type/access flags, do not match hardware values */ 1576#define NV_MEM_ACCESS_RO 1 1577#define NV_MEM_ACCESS_WO 2 1578#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1579#define NV_MEM_ACCESS_SYS 4 1580#define NV_MEM_ACCESS_VM 8 1581 1582#define NV_MEM_TARGET_VRAM 0 1583#define NV_MEM_TARGET_PCI 1 1584#define NV_MEM_TARGET_PCI_NOSNOOP 2 1585#define NV_MEM_TARGET_VM 3 1586#define NV_MEM_TARGET_GART 4 1587 1588#define NV_MEM_TYPE_VM 0x7f 1589#define NV_MEM_COMP_VM 0x03 1590 1591/* NV_SW object class */ 1592#define NV_SW 0x0000506e 1593#define NV_SW_DMA_SEMAPHORE 0x00000060 1594#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1595#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1596#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1597#define NV_SW_YIELD 0x00000080 1598#define NV_SW_DMA_VBLSEM 0x0000018c 1599#define NV_SW_VBLSEM_OFFSET 0x00000400 1600#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1601#define NV_SW_VBLSEM_RELEASE 0x00000408 1602#define NV_SW_PAGE_FLIP 0x00000500 1603 1604#endif /* __NOUVEAU_DRV_H__ */ 1605