nouveau_drv.h revision ba4420c224c2808f2661cf8428f43ceef7a73a4a
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 138#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 139#define NVOBJ_FLAG_FAKE (1 << 3) 140struct nouveau_gpuobj { 141 struct list_head list; 142 143 struct nouveau_channel *im_channel; 144 struct drm_mm_node *im_pramin; 145 struct nouveau_bo *im_backing; 146 uint32_t im_backing_start; 147 uint32_t *im_backing_suspend; 148 int im_bound; 149 150 uint32_t flags; 151 int refcount; 152 153 uint32_t engine; 154 uint32_t class; 155 156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 157 void *priv; 158}; 159 160struct nouveau_gpuobj_ref { 161 struct list_head list; 162 163 struct nouveau_gpuobj *gpuobj; 164 uint32_t instance; 165 166 struct nouveau_channel *channel; 167 int handle; 168}; 169 170struct nouveau_channel { 171 struct drm_device *dev; 172 int id; 173 174 /* owner of this fifo */ 175 struct drm_file *file_priv; 176 /* mapping of the fifo itself */ 177 struct drm_local_map *map; 178 179 /* mapping of the regs controling the fifo */ 180 void __iomem *user; 181 uint32_t user_get; 182 uint32_t user_put; 183 184 /* Fencing */ 185 struct { 186 /* lock protects the pending list only */ 187 spinlock_t lock; 188 struct list_head pending; 189 uint32_t sequence; 190 uint32_t sequence_ack; 191 atomic_t last_sequence_irq; 192 } fence; 193 194 /* DMA push buffer */ 195 struct nouveau_gpuobj_ref *pushbuf; 196 struct nouveau_bo *pushbuf_bo; 197 uint32_t pushbuf_base; 198 199 /* Notifier memory */ 200 struct nouveau_bo *notifier_bo; 201 struct drm_mm notifier_heap; 202 203 /* PFIFO context */ 204 struct nouveau_gpuobj_ref *ramfc; 205 struct nouveau_gpuobj_ref *cache; 206 207 /* PGRAPH context */ 208 /* XXX may be merge 2 pointers as private data ??? */ 209 struct nouveau_gpuobj_ref *ramin_grctx; 210 void *pgraph_ctx; 211 212 /* NV50 VM */ 213 struct nouveau_gpuobj *vm_pd; 214 struct nouveau_gpuobj_ref *vm_gart_pt; 215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 216 217 /* Objects */ 218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 221 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 222 223 /* GPU object info for stuff used in-kernel (mm_enabled) */ 224 uint32_t m2mf_ntfy; 225 uint32_t vram_handle; 226 uint32_t gart_handle; 227 bool accel_done; 228 229 /* Push buffer state (only for drm's channel on !mm_enabled) */ 230 struct { 231 int max; 232 int free; 233 int cur; 234 int put; 235 /* access via pushbuf_bo */ 236 237 int ib_base; 238 int ib_max; 239 int ib_free; 240 int ib_put; 241 } dma; 242 243 uint32_t sw_subchannel[8]; 244 245 struct { 246 struct nouveau_gpuobj *vblsem; 247 uint32_t vblsem_offset; 248 uint32_t vblsem_rval; 249 struct list_head vbl_wait; 250 } nvsw; 251 252 struct { 253 bool active; 254 char name[32]; 255 struct drm_info_list info; 256 } debugfs; 257}; 258 259struct nouveau_instmem_engine { 260 void *priv; 261 262 int (*init)(struct drm_device *dev); 263 void (*takedown)(struct drm_device *dev); 264 int (*suspend)(struct drm_device *dev); 265 void (*resume)(struct drm_device *dev); 266 267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 268 uint32_t *size); 269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 272 void (*flush)(struct drm_device *); 273}; 274 275struct nouveau_mc_engine { 276 int (*init)(struct drm_device *dev); 277 void (*takedown)(struct drm_device *dev); 278}; 279 280struct nouveau_timer_engine { 281 int (*init)(struct drm_device *dev); 282 void (*takedown)(struct drm_device *dev); 283 uint64_t (*read)(struct drm_device *dev); 284}; 285 286struct nouveau_fb_engine { 287 int num_tiles; 288 289 int (*init)(struct drm_device *dev); 290 void (*takedown)(struct drm_device *dev); 291 292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 293 uint32_t size, uint32_t pitch); 294}; 295 296struct nouveau_fifo_engine { 297 int channels; 298 299 struct nouveau_gpuobj_ref *playlist[2]; 300 int cur_playlist; 301 302 int (*init)(struct drm_device *); 303 void (*takedown)(struct drm_device *); 304 305 void (*disable)(struct drm_device *); 306 void (*enable)(struct drm_device *); 307 bool (*reassign)(struct drm_device *, bool enable); 308 bool (*cache_flush)(struct drm_device *dev); 309 bool (*cache_pull)(struct drm_device *dev, bool enable); 310 311 int (*channel_id)(struct drm_device *); 312 313 int (*create_context)(struct nouveau_channel *); 314 void (*destroy_context)(struct nouveau_channel *); 315 int (*load_context)(struct nouveau_channel *); 316 int (*unload_context)(struct drm_device *); 317}; 318 319struct nouveau_pgraph_object_method { 320 int id; 321 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 322 uint32_t data); 323}; 324 325struct nouveau_pgraph_object_class { 326 int id; 327 bool software; 328 struct nouveau_pgraph_object_method *methods; 329}; 330 331struct nouveau_pgraph_engine { 332 struct nouveau_pgraph_object_class *grclass; 333 bool accel_blocked; 334 int grctx_size; 335 336 /* NV2x/NV3x context table (0x400780) */ 337 struct nouveau_gpuobj_ref *ctx_table; 338 339 int (*init)(struct drm_device *); 340 void (*takedown)(struct drm_device *); 341 342 void (*fifo_access)(struct drm_device *, bool); 343 344 struct nouveau_channel *(*channel)(struct drm_device *); 345 int (*create_context)(struct nouveau_channel *); 346 void (*destroy_context)(struct nouveau_channel *); 347 int (*load_context)(struct nouveau_channel *); 348 int (*unload_context)(struct drm_device *); 349 350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 351 uint32_t size, uint32_t pitch); 352}; 353 354struct nouveau_display_engine { 355 int (*early_init)(struct drm_device *); 356 void (*late_takedown)(struct drm_device *); 357 int (*create)(struct drm_device *); 358 int (*init)(struct drm_device *); 359 void (*destroy)(struct drm_device *); 360}; 361 362struct nouveau_gpio_engine { 363 int (*init)(struct drm_device *); 364 void (*takedown)(struct drm_device *); 365 366 int (*get)(struct drm_device *, enum dcb_gpio_tag); 367 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 368 369 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 370}; 371 372struct nouveau_engine { 373 struct nouveau_instmem_engine instmem; 374 struct nouveau_mc_engine mc; 375 struct nouveau_timer_engine timer; 376 struct nouveau_fb_engine fb; 377 struct nouveau_pgraph_engine graph; 378 struct nouveau_fifo_engine fifo; 379 struct nouveau_display_engine display; 380 struct nouveau_gpio_engine gpio; 381}; 382 383struct nouveau_pll_vals { 384 union { 385 struct { 386#ifdef __BIG_ENDIAN 387 uint8_t N1, M1, N2, M2; 388#else 389 uint8_t M1, N1, M2, N2; 390#endif 391 }; 392 struct { 393 uint16_t NM1, NM2; 394 } __attribute__((packed)); 395 }; 396 int log2P; 397 398 int refclk; 399}; 400 401enum nv04_fp_display_regs { 402 FP_DISPLAY_END, 403 FP_TOTAL, 404 FP_CRTC, 405 FP_SYNC_START, 406 FP_SYNC_END, 407 FP_VALID_START, 408 FP_VALID_END 409}; 410 411struct nv04_crtc_reg { 412 unsigned char MiscOutReg; /* */ 413 uint8_t CRTC[0x9f]; 414 uint8_t CR58[0x10]; 415 uint8_t Sequencer[5]; 416 uint8_t Graphics[9]; 417 uint8_t Attribute[21]; 418 unsigned char DAC[768]; /* Internal Colorlookuptable */ 419 420 /* PCRTC regs */ 421 uint32_t fb_start; 422 uint32_t crtc_cfg; 423 uint32_t cursor_cfg; 424 uint32_t gpio_ext; 425 uint32_t crtc_830; 426 uint32_t crtc_834; 427 uint32_t crtc_850; 428 uint32_t crtc_eng_ctrl; 429 430 /* PRAMDAC regs */ 431 uint32_t nv10_cursync; 432 struct nouveau_pll_vals pllvals; 433 uint32_t ramdac_gen_ctrl; 434 uint32_t ramdac_630; 435 uint32_t ramdac_634; 436 uint32_t tv_setup; 437 uint32_t tv_vtotal; 438 uint32_t tv_vskew; 439 uint32_t tv_vsync_delay; 440 uint32_t tv_htotal; 441 uint32_t tv_hskew; 442 uint32_t tv_hsync_delay; 443 uint32_t tv_hsync_delay2; 444 uint32_t fp_horiz_regs[7]; 445 uint32_t fp_vert_regs[7]; 446 uint32_t dither; 447 uint32_t fp_control; 448 uint32_t dither_regs[6]; 449 uint32_t fp_debug_0; 450 uint32_t fp_debug_1; 451 uint32_t fp_debug_2; 452 uint32_t fp_margin_color; 453 uint32_t ramdac_8c0; 454 uint32_t ramdac_a20; 455 uint32_t ramdac_a24; 456 uint32_t ramdac_a34; 457 uint32_t ctv_regs[38]; 458}; 459 460struct nv04_output_reg { 461 uint32_t output; 462 int head; 463}; 464 465struct nv04_mode_state { 466 uint32_t bpp; 467 uint32_t width; 468 uint32_t height; 469 uint32_t interlace; 470 uint32_t repaint0; 471 uint32_t repaint1; 472 uint32_t screen; 473 uint32_t scale; 474 uint32_t dither; 475 uint32_t extra; 476 uint32_t fifo; 477 uint32_t pixel; 478 uint32_t horiz; 479 int arbitration0; 480 int arbitration1; 481 uint32_t pll; 482 uint32_t pllB; 483 uint32_t vpll; 484 uint32_t vpll2; 485 uint32_t vpllB; 486 uint32_t vpll2B; 487 uint32_t pllsel; 488 uint32_t sel_clk; 489 uint32_t general; 490 uint32_t crtcOwner; 491 uint32_t head; 492 uint32_t head2; 493 uint32_t cursorConfig; 494 uint32_t cursor0; 495 uint32_t cursor1; 496 uint32_t cursor2; 497 uint32_t timingH; 498 uint32_t timingV; 499 uint32_t displayV; 500 uint32_t crtcSync; 501 502 struct nv04_crtc_reg crtc_reg[2]; 503}; 504 505enum nouveau_card_type { 506 NV_04 = 0x00, 507 NV_10 = 0x10, 508 NV_20 = 0x20, 509 NV_30 = 0x30, 510 NV_40 = 0x40, 511 NV_50 = 0x50, 512}; 513 514struct drm_nouveau_private { 515 struct drm_device *dev; 516 517 /* the card type, takes NV_* as values */ 518 enum nouveau_card_type card_type; 519 /* exact chipset, derived from NV_PMC_BOOT_0 */ 520 int chipset; 521 int flags; 522 523 void __iomem *mmio; 524 void __iomem *ramin; 525 uint32_t ramin_size; 526 527 struct nouveau_bo *vga_ram; 528 529 struct workqueue_struct *wq; 530 struct work_struct irq_work; 531 struct work_struct hpd_work; 532 533 struct list_head vbl_waiting; 534 535 struct { 536 struct drm_global_reference mem_global_ref; 537 struct ttm_bo_global_ref bo_global_ref; 538 struct ttm_bo_device bdev; 539 spinlock_t bo_list_lock; 540 struct list_head bo_list; 541 atomic_t validate_sequence; 542 } ttm; 543 544 int fifo_alloc_count; 545 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 546 547 struct nouveau_engine engine; 548 struct nouveau_channel *channel; 549 550 /* For PFIFO and PGRAPH. */ 551 spinlock_t context_switch_lock; 552 553 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 554 struct nouveau_gpuobj *ramht; 555 uint32_t ramin_rsvd_vram; 556 uint32_t ramht_offset; 557 uint32_t ramht_size; 558 uint32_t ramht_bits; 559 uint32_t ramfc_offset; 560 uint32_t ramfc_size; 561 uint32_t ramro_offset; 562 uint32_t ramro_size; 563 564 struct { 565 enum { 566 NOUVEAU_GART_NONE = 0, 567 NOUVEAU_GART_AGP, 568 NOUVEAU_GART_SGDMA 569 } type; 570 uint64_t aper_base; 571 uint64_t aper_size; 572 uint64_t aper_free; 573 574 struct nouveau_gpuobj *sg_ctxdma; 575 struct page *sg_dummy_page; 576 dma_addr_t sg_dummy_bus; 577 } gart_info; 578 579 /* nv10-nv40 tiling regions */ 580 struct { 581 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 582 spinlock_t lock; 583 } tile; 584 585 /* VRAM/fb configuration */ 586 uint64_t vram_size; 587 uint64_t vram_sys_base; 588 589 uint64_t fb_phys; 590 uint64_t fb_available_size; 591 uint64_t fb_mappable_pages; 592 uint64_t fb_aper_free; 593 int fb_mtrr; 594 595 /* G8x/G9x virtual address space */ 596 uint64_t vm_gart_base; 597 uint64_t vm_gart_size; 598 uint64_t vm_vram_base; 599 uint64_t vm_vram_size; 600 uint64_t vm_end; 601 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 602 int vm_vram_pt_nr; 603 604 struct drm_mm ramin_heap; 605 606 struct list_head gpuobj_list; 607 608 struct nvbios vbios; 609 610 struct nv04_mode_state mode_reg; 611 struct nv04_mode_state saved_reg; 612 uint32_t saved_vga_font[4][16384]; 613 uint32_t crtc_owner; 614 uint32_t dac_users[4]; 615 616 struct nouveau_suspend_resume { 617 uint32_t *ramin_copy; 618 } susres; 619 620 struct backlight_device *backlight; 621 622 struct nouveau_channel *evo; 623 struct { 624 struct dcb_entry *dcb; 625 u16 script; 626 u32 pclk; 627 } evo_irq; 628 629 struct { 630 struct dentry *channel_root; 631 } debugfs; 632 633 struct nouveau_fbdev *nfbdev; 634 struct apertures_struct *apertures; 635}; 636 637static inline struct drm_nouveau_private * 638nouveau_bdev(struct ttm_bo_device *bd) 639{ 640 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 641} 642 643static inline int 644nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 645{ 646 struct nouveau_bo *prev; 647 648 if (!pnvbo) 649 return -EINVAL; 650 prev = *pnvbo; 651 652 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 653 if (prev) { 654 struct ttm_buffer_object *bo = &prev->bo; 655 656 ttm_bo_unref(&bo); 657 } 658 659 return 0; 660} 661 662#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 663 struct drm_nouveau_private *nv = dev->dev_private; \ 664 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 665 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 666 DRM_CURRENTPID, (id)); \ 667 return -EPERM; \ 668 } \ 669 (ch) = nv->fifos[(id)]; \ 670} while (0) 671 672/* nouveau_drv.c */ 673extern int nouveau_noagp; 674extern int nouveau_duallink; 675extern int nouveau_uscript_lvds; 676extern int nouveau_uscript_tmds; 677extern int nouveau_vram_pushbuf; 678extern int nouveau_vram_notify; 679extern int nouveau_fbpercrtc; 680extern int nouveau_tv_disable; 681extern char *nouveau_tv_norm; 682extern int nouveau_reg_debug; 683extern char *nouveau_vbios; 684extern int nouveau_ignorelid; 685extern int nouveau_nofbaccel; 686extern int nouveau_noaccel; 687extern int nouveau_override_conntype; 688 689extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 690extern int nouveau_pci_resume(struct pci_dev *pdev); 691 692/* nouveau_state.c */ 693extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 694extern int nouveau_load(struct drm_device *, unsigned long flags); 695extern int nouveau_firstopen(struct drm_device *); 696extern void nouveau_lastclose(struct drm_device *); 697extern int nouveau_unload(struct drm_device *); 698extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 699 struct drm_file *); 700extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 701 struct drm_file *); 702extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 703 uint32_t reg, uint32_t mask, uint32_t val); 704extern bool nouveau_wait_for_idle(struct drm_device *); 705extern int nouveau_card_init(struct drm_device *); 706 707/* nouveau_mem.c */ 708extern int nouveau_mem_detect(struct drm_device *dev); 709extern int nouveau_mem_init(struct drm_device *); 710extern int nouveau_mem_init_agp(struct drm_device *); 711extern int nouveau_mem_reset_agp(struct drm_device *); 712extern void nouveau_mem_close(struct drm_device *); 713extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 714 uint32_t addr, 715 uint32_t size, 716 uint32_t pitch); 717extern void nv10_mem_expire_tiling(struct drm_device *dev, 718 struct nouveau_tile_reg *tile, 719 struct nouveau_fence *fence); 720extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 721 uint32_t size, uint32_t flags, 722 uint64_t phys); 723extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 724 uint32_t size); 725 726/* nouveau_notifier.c */ 727extern int nouveau_notifier_init_channel(struct nouveau_channel *); 728extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 729extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 730 int cout, uint32_t *offset); 731extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 732extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 733 struct drm_file *); 734extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 735 struct drm_file *); 736 737/* nouveau_channel.c */ 738extern struct drm_ioctl_desc nouveau_ioctls[]; 739extern int nouveau_max_ioctl; 740extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 741extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 742 int channel); 743extern int nouveau_channel_alloc(struct drm_device *dev, 744 struct nouveau_channel **chan, 745 struct drm_file *file_priv, 746 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 747extern void nouveau_channel_free(struct nouveau_channel *); 748 749/* nouveau_object.c */ 750extern int nouveau_gpuobj_early_init(struct drm_device *); 751extern int nouveau_gpuobj_init(struct drm_device *); 752extern void nouveau_gpuobj_takedown(struct drm_device *); 753extern void nouveau_gpuobj_late_takedown(struct drm_device *); 754extern int nouveau_gpuobj_suspend(struct drm_device *dev); 755extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 756extern void nouveau_gpuobj_resume(struct drm_device *dev); 757extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 758 uint32_t vram_h, uint32_t tt_h); 759extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 760extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 761 uint32_t size, int align, uint32_t flags, 762 struct nouveau_gpuobj **); 763extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 764extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 765 uint32_t handle, struct nouveau_gpuobj *, 766 struct nouveau_gpuobj_ref **); 767extern int nouveau_gpuobj_ref_del(struct drm_device *, 768 struct nouveau_gpuobj_ref **); 769extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 770 struct nouveau_gpuobj_ref **ref_ret); 771extern int nouveau_gpuobj_new_ref(struct drm_device *, 772 struct nouveau_channel *alloc_chan, 773 struct nouveau_channel *ref_chan, 774 uint32_t handle, uint32_t size, int align, 775 uint32_t flags, struct nouveau_gpuobj_ref **); 776extern int nouveau_gpuobj_new_fake(struct drm_device *, 777 uint32_t p_offset, uint32_t b_offset, 778 uint32_t size, uint32_t flags, 779 struct nouveau_gpuobj **, 780 struct nouveau_gpuobj_ref**); 781extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 782 uint64_t offset, uint64_t size, int access, 783 int target, struct nouveau_gpuobj **); 784extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 785 uint64_t offset, uint64_t size, 786 int access, struct nouveau_gpuobj **, 787 uint32_t *o_ret); 788extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 789 struct nouveau_gpuobj **); 790extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 791 struct nouveau_gpuobj **); 792extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 793 struct drm_file *); 794extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 795 struct drm_file *); 796 797/* nouveau_irq.c */ 798extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 799extern void nouveau_irq_preinstall(struct drm_device *); 800extern int nouveau_irq_postinstall(struct drm_device *); 801extern void nouveau_irq_uninstall(struct drm_device *); 802 803/* nouveau_sgdma.c */ 804extern int nouveau_sgdma_init(struct drm_device *); 805extern void nouveau_sgdma_takedown(struct drm_device *); 806extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 807 uint32_t *page); 808extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 809 810/* nouveau_debugfs.c */ 811#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 812extern int nouveau_debugfs_init(struct drm_minor *); 813extern void nouveau_debugfs_takedown(struct drm_minor *); 814extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 815extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 816#else 817static inline int 818nouveau_debugfs_init(struct drm_minor *minor) 819{ 820 return 0; 821} 822 823static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 824{ 825} 826 827static inline int 828nouveau_debugfs_channel_init(struct nouveau_channel *chan) 829{ 830 return 0; 831} 832 833static inline void 834nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 835{ 836} 837#endif 838 839/* nouveau_dma.c */ 840extern void nouveau_dma_pre_init(struct nouveau_channel *); 841extern int nouveau_dma_init(struct nouveau_channel *); 842extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 843 844/* nouveau_acpi.c */ 845#define ROM_BIOS_PAGE 4096 846#if defined(CONFIG_ACPI) 847void nouveau_register_dsm_handler(void); 848void nouveau_unregister_dsm_handler(void); 849int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 850bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 851int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 852#else 853static inline void nouveau_register_dsm_handler(void) {} 854static inline void nouveau_unregister_dsm_handler(void) {} 855static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 856static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 857static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 858#endif 859 860/* nouveau_backlight.c */ 861#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 862extern int nouveau_backlight_init(struct drm_device *); 863extern void nouveau_backlight_exit(struct drm_device *); 864#else 865static inline int nouveau_backlight_init(struct drm_device *dev) 866{ 867 return 0; 868} 869 870static inline void nouveau_backlight_exit(struct drm_device *dev) { } 871#endif 872 873/* nouveau_bios.c */ 874extern int nouveau_bios_init(struct drm_device *); 875extern void nouveau_bios_takedown(struct drm_device *dev); 876extern int nouveau_run_vbios_init(struct drm_device *); 877extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 878 struct dcb_entry *); 879extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 880 enum dcb_gpio_tag); 881extern struct dcb_connector_table_entry * 882nouveau_bios_connector_entry(struct drm_device *, int index); 883extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 884 struct pll_lims *); 885extern int nouveau_bios_run_display_table(struct drm_device *, 886 struct dcb_entry *, 887 uint32_t script, int pxclk); 888extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 889 int *length); 890extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 891extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 892extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 893 bool *dl, bool *if_is_24bit); 894extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 895 int head, int pxclk); 896extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 897 enum LVDS_script, int pxclk); 898 899/* nouveau_ttm.c */ 900int nouveau_ttm_global_init(struct drm_nouveau_private *); 901void nouveau_ttm_global_release(struct drm_nouveau_private *); 902int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 903 904/* nouveau_dp.c */ 905int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 906 uint8_t *data, int data_nr); 907bool nouveau_dp_detect(struct drm_encoder *); 908bool nouveau_dp_link_train(struct drm_encoder *); 909 910/* nv04_fb.c */ 911extern int nv04_fb_init(struct drm_device *); 912extern void nv04_fb_takedown(struct drm_device *); 913 914/* nv10_fb.c */ 915extern int nv10_fb_init(struct drm_device *); 916extern void nv10_fb_takedown(struct drm_device *); 917extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 918 uint32_t, uint32_t); 919 920/* nv30_fb.c */ 921extern int nv30_fb_init(struct drm_device *); 922extern void nv30_fb_takedown(struct drm_device *); 923 924/* nv40_fb.c */ 925extern int nv40_fb_init(struct drm_device *); 926extern void nv40_fb_takedown(struct drm_device *); 927extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 928 uint32_t, uint32_t); 929 930/* nv50_fb.c */ 931extern int nv50_fb_init(struct drm_device *); 932extern void nv50_fb_takedown(struct drm_device *); 933 934/* nv04_fifo.c */ 935extern int nv04_fifo_init(struct drm_device *); 936extern void nv04_fifo_disable(struct drm_device *); 937extern void nv04_fifo_enable(struct drm_device *); 938extern bool nv04_fifo_reassign(struct drm_device *, bool); 939extern bool nv04_fifo_cache_flush(struct drm_device *); 940extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 941extern int nv04_fifo_channel_id(struct drm_device *); 942extern int nv04_fifo_create_context(struct nouveau_channel *); 943extern void nv04_fifo_destroy_context(struct nouveau_channel *); 944extern int nv04_fifo_load_context(struct nouveau_channel *); 945extern int nv04_fifo_unload_context(struct drm_device *); 946 947/* nv10_fifo.c */ 948extern int nv10_fifo_init(struct drm_device *); 949extern int nv10_fifo_channel_id(struct drm_device *); 950extern int nv10_fifo_create_context(struct nouveau_channel *); 951extern void nv10_fifo_destroy_context(struct nouveau_channel *); 952extern int nv10_fifo_load_context(struct nouveau_channel *); 953extern int nv10_fifo_unload_context(struct drm_device *); 954 955/* nv40_fifo.c */ 956extern int nv40_fifo_init(struct drm_device *); 957extern int nv40_fifo_create_context(struct nouveau_channel *); 958extern void nv40_fifo_destroy_context(struct nouveau_channel *); 959extern int nv40_fifo_load_context(struct nouveau_channel *); 960extern int nv40_fifo_unload_context(struct drm_device *); 961 962/* nv50_fifo.c */ 963extern int nv50_fifo_init(struct drm_device *); 964extern void nv50_fifo_takedown(struct drm_device *); 965extern int nv50_fifo_channel_id(struct drm_device *); 966extern int nv50_fifo_create_context(struct nouveau_channel *); 967extern void nv50_fifo_destroy_context(struct nouveau_channel *); 968extern int nv50_fifo_load_context(struct nouveau_channel *); 969extern int nv50_fifo_unload_context(struct drm_device *); 970 971/* nv04_graph.c */ 972extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 973extern int nv04_graph_init(struct drm_device *); 974extern void nv04_graph_takedown(struct drm_device *); 975extern void nv04_graph_fifo_access(struct drm_device *, bool); 976extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 977extern int nv04_graph_create_context(struct nouveau_channel *); 978extern void nv04_graph_destroy_context(struct nouveau_channel *); 979extern int nv04_graph_load_context(struct nouveau_channel *); 980extern int nv04_graph_unload_context(struct drm_device *); 981extern void nv04_graph_context_switch(struct drm_device *); 982 983/* nv10_graph.c */ 984extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 985extern int nv10_graph_init(struct drm_device *); 986extern void nv10_graph_takedown(struct drm_device *); 987extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 988extern int nv10_graph_create_context(struct nouveau_channel *); 989extern void nv10_graph_destroy_context(struct nouveau_channel *); 990extern int nv10_graph_load_context(struct nouveau_channel *); 991extern int nv10_graph_unload_context(struct drm_device *); 992extern void nv10_graph_context_switch(struct drm_device *); 993extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 994 uint32_t, uint32_t); 995 996/* nv20_graph.c */ 997extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 998extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 999extern int nv20_graph_create_context(struct nouveau_channel *); 1000extern void nv20_graph_destroy_context(struct nouveau_channel *); 1001extern int nv20_graph_load_context(struct nouveau_channel *); 1002extern int nv20_graph_unload_context(struct drm_device *); 1003extern int nv20_graph_init(struct drm_device *); 1004extern void nv20_graph_takedown(struct drm_device *); 1005extern int nv30_graph_init(struct drm_device *); 1006extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1007 uint32_t, uint32_t); 1008 1009/* nv40_graph.c */ 1010extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1011extern int nv40_graph_init(struct drm_device *); 1012extern void nv40_graph_takedown(struct drm_device *); 1013extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1014extern int nv40_graph_create_context(struct nouveau_channel *); 1015extern void nv40_graph_destroy_context(struct nouveau_channel *); 1016extern int nv40_graph_load_context(struct nouveau_channel *); 1017extern int nv40_graph_unload_context(struct drm_device *); 1018extern void nv40_grctx_init(struct nouveau_grctx *); 1019extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1020 uint32_t, uint32_t); 1021 1022/* nv50_graph.c */ 1023extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1024extern int nv50_graph_init(struct drm_device *); 1025extern void nv50_graph_takedown(struct drm_device *); 1026extern void nv50_graph_fifo_access(struct drm_device *, bool); 1027extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1028extern int nv50_graph_create_context(struct nouveau_channel *); 1029extern void nv50_graph_destroy_context(struct nouveau_channel *); 1030extern int nv50_graph_load_context(struct nouveau_channel *); 1031extern int nv50_graph_unload_context(struct drm_device *); 1032extern void nv50_graph_context_switch(struct drm_device *); 1033extern int nv50_grctx_init(struct nouveau_grctx *); 1034 1035/* nv04_instmem.c */ 1036extern int nv04_instmem_init(struct drm_device *); 1037extern void nv04_instmem_takedown(struct drm_device *); 1038extern int nv04_instmem_suspend(struct drm_device *); 1039extern void nv04_instmem_resume(struct drm_device *); 1040extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1041 uint32_t *size); 1042extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1043extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1044extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1045extern void nv04_instmem_flush(struct drm_device *); 1046 1047/* nv50_instmem.c */ 1048extern int nv50_instmem_init(struct drm_device *); 1049extern void nv50_instmem_takedown(struct drm_device *); 1050extern int nv50_instmem_suspend(struct drm_device *); 1051extern void nv50_instmem_resume(struct drm_device *); 1052extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1053 uint32_t *size); 1054extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1055extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1056extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1057extern void nv50_instmem_flush(struct drm_device *); 1058extern void nv84_instmem_flush(struct drm_device *); 1059extern void nv50_vm_flush(struct drm_device *, int engine); 1060 1061/* nv04_mc.c */ 1062extern int nv04_mc_init(struct drm_device *); 1063extern void nv04_mc_takedown(struct drm_device *); 1064 1065/* nv40_mc.c */ 1066extern int nv40_mc_init(struct drm_device *); 1067extern void nv40_mc_takedown(struct drm_device *); 1068 1069/* nv50_mc.c */ 1070extern int nv50_mc_init(struct drm_device *); 1071extern void nv50_mc_takedown(struct drm_device *); 1072 1073/* nv04_timer.c */ 1074extern int nv04_timer_init(struct drm_device *); 1075extern uint64_t nv04_timer_read(struct drm_device *); 1076extern void nv04_timer_takedown(struct drm_device *); 1077 1078extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1079 unsigned long arg); 1080 1081/* nv04_dac.c */ 1082extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1083extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1084extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1085extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1086extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1087 1088/* nv04_dfp.c */ 1089extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1090extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1091extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1092 int head, bool dl); 1093extern void nv04_dfp_disable(struct drm_device *dev, int head); 1094extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1095 1096/* nv04_tv.c */ 1097extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1098extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1099 1100/* nv17_tv.c */ 1101extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1102 1103/* nv04_display.c */ 1104extern int nv04_display_early_init(struct drm_device *); 1105extern void nv04_display_late_takedown(struct drm_device *); 1106extern int nv04_display_create(struct drm_device *); 1107extern int nv04_display_init(struct drm_device *); 1108extern void nv04_display_destroy(struct drm_device *); 1109 1110/* nv04_crtc.c */ 1111extern int nv04_crtc_create(struct drm_device *, int index); 1112 1113/* nouveau_bo.c */ 1114extern struct ttm_bo_driver nouveau_bo_driver; 1115extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1116 int size, int align, uint32_t flags, 1117 uint32_t tile_mode, uint32_t tile_flags, 1118 bool no_vm, bool mappable, struct nouveau_bo **); 1119extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1120extern int nouveau_bo_unpin(struct nouveau_bo *); 1121extern int nouveau_bo_map(struct nouveau_bo *); 1122extern void nouveau_bo_unmap(struct nouveau_bo *); 1123extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1124 uint32_t busy); 1125extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1126extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1127extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1128extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1129 1130/* nouveau_fence.c */ 1131struct nouveau_fence; 1132extern int nouveau_fence_init(struct nouveau_channel *); 1133extern void nouveau_fence_fini(struct nouveau_channel *); 1134extern void nouveau_fence_update(struct nouveau_channel *); 1135extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1136 bool emit); 1137extern int nouveau_fence_emit(struct nouveau_fence *); 1138struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1139extern bool nouveau_fence_signalled(void *obj, void *arg); 1140extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1141extern int nouveau_fence_flush(void *obj, void *arg); 1142extern void nouveau_fence_unref(void **obj); 1143extern void *nouveau_fence_ref(void *obj); 1144 1145/* nouveau_gem.c */ 1146extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1147 int size, int align, uint32_t flags, 1148 uint32_t tile_mode, uint32_t tile_flags, 1149 bool no_vm, bool mappable, struct nouveau_bo **); 1150extern int nouveau_gem_object_new(struct drm_gem_object *); 1151extern void nouveau_gem_object_del(struct drm_gem_object *); 1152extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1153 struct drm_file *); 1154extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1155 struct drm_file *); 1156extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1157 struct drm_file *); 1158extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1159 struct drm_file *); 1160extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1161 struct drm_file *); 1162 1163/* nv10_gpio.c */ 1164int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1165int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1166 1167/* nv50_gpio.c */ 1168int nv50_gpio_init(struct drm_device *dev); 1169int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1170int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1171void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1172 1173/* nv50_calc. */ 1174int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1175 int *N1, int *M1, int *N2, int *M2, int *P); 1176int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1177 int clk, int *N, int *fN, int *M, int *P); 1178 1179#ifndef ioread32_native 1180#ifdef __BIG_ENDIAN 1181#define ioread16_native ioread16be 1182#define iowrite16_native iowrite16be 1183#define ioread32_native ioread32be 1184#define iowrite32_native iowrite32be 1185#else /* def __BIG_ENDIAN */ 1186#define ioread16_native ioread16 1187#define iowrite16_native iowrite16 1188#define ioread32_native ioread32 1189#define iowrite32_native iowrite32 1190#endif /* def __BIG_ENDIAN else */ 1191#endif /* !ioread32_native */ 1192 1193/* channel control reg access */ 1194static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1195{ 1196 return ioread32_native(chan->user + reg); 1197} 1198 1199static inline void nvchan_wr32(struct nouveau_channel *chan, 1200 unsigned reg, u32 val) 1201{ 1202 iowrite32_native(val, chan->user + reg); 1203} 1204 1205/* register access */ 1206static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1207{ 1208 struct drm_nouveau_private *dev_priv = dev->dev_private; 1209 return ioread32_native(dev_priv->mmio + reg); 1210} 1211 1212static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1213{ 1214 struct drm_nouveau_private *dev_priv = dev->dev_private; 1215 iowrite32_native(val, dev_priv->mmio + reg); 1216} 1217 1218static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1219{ 1220 u32 tmp = nv_rd32(dev, reg); 1221 tmp &= ~mask; 1222 tmp |= val; 1223 nv_wr32(dev, reg, tmp); 1224} 1225 1226static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1227{ 1228 struct drm_nouveau_private *dev_priv = dev->dev_private; 1229 return ioread8(dev_priv->mmio + reg); 1230} 1231 1232static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1233{ 1234 struct drm_nouveau_private *dev_priv = dev->dev_private; 1235 iowrite8(val, dev_priv->mmio + reg); 1236} 1237 1238#define nv_wait(reg, mask, val) \ 1239 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1240 1241/* PRAMIN access */ 1242static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1243{ 1244 struct drm_nouveau_private *dev_priv = dev->dev_private; 1245 return ioread32_native(dev_priv->ramin + offset); 1246} 1247 1248static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1249{ 1250 struct drm_nouveau_private *dev_priv = dev->dev_private; 1251 iowrite32_native(val, dev_priv->ramin + offset); 1252} 1253 1254/* object access */ 1255static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1256 unsigned index) 1257{ 1258 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1259} 1260 1261static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1262 unsigned index, u32 val) 1263{ 1264 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1265} 1266 1267/* 1268 * Logging 1269 * Argument d is (struct drm_device *). 1270 */ 1271#define NV_PRINTK(level, d, fmt, arg...) \ 1272 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1273 pci_name(d->pdev), ##arg) 1274#ifndef NV_DEBUG_NOTRACE 1275#define NV_DEBUG(d, fmt, arg...) do { \ 1276 if (drm_debug & DRM_UT_DRIVER) { \ 1277 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1278 __LINE__, ##arg); \ 1279 } \ 1280} while (0) 1281#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1282 if (drm_debug & DRM_UT_KMS) { \ 1283 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1284 __LINE__, ##arg); \ 1285 } \ 1286} while (0) 1287#else 1288#define NV_DEBUG(d, fmt, arg...) do { \ 1289 if (drm_debug & DRM_UT_DRIVER) \ 1290 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1291} while (0) 1292#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1293 if (drm_debug & DRM_UT_KMS) \ 1294 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1295} while (0) 1296#endif 1297#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1298#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1299#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1300#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1301#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1302 1303/* nouveau_reg_debug bitmask */ 1304enum { 1305 NOUVEAU_REG_DEBUG_MC = 0x1, 1306 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1307 NOUVEAU_REG_DEBUG_FB = 0x4, 1308 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1309 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1310 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1311 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1312 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1313 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1314 NOUVEAU_REG_DEBUG_EVO = 0x200, 1315}; 1316 1317#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1318 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1319 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1320} while (0) 1321 1322static inline bool 1323nv_two_heads(struct drm_device *dev) 1324{ 1325 struct drm_nouveau_private *dev_priv = dev->dev_private; 1326 const int impl = dev->pci_device & 0x0ff0; 1327 1328 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1329 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1330 return true; 1331 1332 return false; 1333} 1334 1335static inline bool 1336nv_gf4_disp_arch(struct drm_device *dev) 1337{ 1338 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1339} 1340 1341static inline bool 1342nv_two_reg_pll(struct drm_device *dev) 1343{ 1344 struct drm_nouveau_private *dev_priv = dev->dev_private; 1345 const int impl = dev->pci_device & 0x0ff0; 1346 1347 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1348 return true; 1349 return false; 1350} 1351 1352#define NV_SW 0x0000506e 1353#define NV_SW_DMA_SEMAPHORE 0x00000060 1354#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1355#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1356#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1357#define NV_SW_DMA_VBLSEM 0x0000018c 1358#define NV_SW_VBLSEM_OFFSET 0x00000400 1359#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1360#define NV_SW_VBLSEM_RELEASE 0x00000408 1361 1362#endif /* __NOUVEAU_DRV_H__ */ 1363