nouveau_drv.h revision bc6389e4fa1a6535021ffc4d3b37d48f9a0542e2
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435struct nouveau_pm_memtiming { 436 int id; 437 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 438 u32 reg_1; 439 u32 reg_2; 440 u32 reg_3; 441 u32 reg_4; 442 u32 reg_5; 443 u32 reg_6; 444 u32 reg_7; 445 u32 reg_8; 446 /* To be written to 0x1002c0 */ 447 u8 CL; 448 u8 WR; 449}; 450 451struct nouveau_pm_tbl_header { 452 u8 version; 453 u8 header_len; 454 u8 entry_cnt; 455 u8 entry_len; 456}; 457 458struct nouveau_pm_tbl_entry { 459 u8 tWR; 460 u8 tUNK_1; 461 u8 tCL; 462 u8 tRP; /* Byte 3 */ 463 u8 empty_4; 464 u8 tRAS; /* Byte 5 */ 465 u8 empty_6; 466 u8 tRFC; /* Byte 7 */ 467 u8 empty_8; 468 u8 tRC; /* Byte 9 */ 469 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 470 u8 empty_15,empty_16,empty_17; 471 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 472}; 473 474#define NOUVEAU_PM_MAX_LEVEL 8 475struct nouveau_pm_level { 476 struct device_attribute dev_attr; 477 char name[32]; 478 int id; 479 480 u32 core; 481 u32 memory; 482 u32 shader; 483 u32 rop; 484 u32 copy; 485 u32 daemon; 486 u32 vdec; 487 u32 dom6; 488 u32 unka0; /* nva3:nvc0 */ 489 u32 hub01; /* nvc0- */ 490 u32 hub06; /* nvc0- */ 491 u32 hub07; /* nvc0- */ 492 493 u32 volt_min; /* microvolts */ 494 u32 volt_max; 495 u8 fanspeed; 496 497 u16 memscript; 498 struct nouveau_pm_memtiming *timing; 499}; 500 501struct nouveau_pm_temp_sensor_constants { 502 u16 offset_constant; 503 s16 offset_mult; 504 s16 offset_div; 505 s16 slope_mult; 506 s16 slope_div; 507}; 508 509struct nouveau_pm_threshold_temp { 510 s16 critical; 511 s16 down_clock; 512 s16 fan_boost; 513}; 514 515struct nouveau_pm_memtimings { 516 bool supported; 517 struct nouveau_pm_memtiming *timing; 518 int nr_timing; 519}; 520 521struct nouveau_pm_fan { 522 u32 percent; 523 u32 min_duty; 524 u32 max_duty; 525 u32 pwm_freq; 526}; 527 528struct nouveau_pm_engine { 529 struct nouveau_pm_voltage voltage; 530 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 531 int nr_perflvl; 532 struct nouveau_pm_memtimings memtimings; 533 struct nouveau_pm_temp_sensor_constants sensor_constants; 534 struct nouveau_pm_threshold_temp threshold_temp; 535 struct nouveau_pm_fan fan; 536 u32 pwm_divisor; 537 538 struct nouveau_pm_level boot; 539 struct nouveau_pm_level *cur; 540 541 struct device *hwmon; 542 struct notifier_block acpi_nb; 543 544 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 545 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 546 int (*clocks_set)(struct drm_device *, void *); 547 548 int (*voltage_get)(struct drm_device *); 549 int (*voltage_set)(struct drm_device *, int voltage); 550 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 551 int (*pwm_set)(struct drm_device *, int line, u32, u32); 552 int (*temp_get)(struct drm_device *); 553}; 554 555struct nouveau_vram_engine { 556 struct nouveau_mm mm; 557 558 int (*init)(struct drm_device *); 559 void (*takedown)(struct drm_device *dev); 560 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 561 u32 type, struct nouveau_mem **); 562 void (*put)(struct drm_device *, struct nouveau_mem **); 563 564 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 565}; 566 567struct nouveau_engine { 568 struct nouveau_instmem_engine instmem; 569 struct nouveau_mc_engine mc; 570 struct nouveau_timer_engine timer; 571 struct nouveau_fb_engine fb; 572 struct nouveau_fifo_engine fifo; 573 struct nouveau_display_engine display; 574 struct nouveau_gpio_engine gpio; 575 struct nouveau_pm_engine pm; 576 struct nouveau_vram_engine vram; 577}; 578 579struct nouveau_pll_vals { 580 union { 581 struct { 582#ifdef __BIG_ENDIAN 583 uint8_t N1, M1, N2, M2; 584#else 585 uint8_t M1, N1, M2, N2; 586#endif 587 }; 588 struct { 589 uint16_t NM1, NM2; 590 } __attribute__((packed)); 591 }; 592 int log2P; 593 594 int refclk; 595}; 596 597enum nv04_fp_display_regs { 598 FP_DISPLAY_END, 599 FP_TOTAL, 600 FP_CRTC, 601 FP_SYNC_START, 602 FP_SYNC_END, 603 FP_VALID_START, 604 FP_VALID_END 605}; 606 607struct nv04_crtc_reg { 608 unsigned char MiscOutReg; 609 uint8_t CRTC[0xa0]; 610 uint8_t CR58[0x10]; 611 uint8_t Sequencer[5]; 612 uint8_t Graphics[9]; 613 uint8_t Attribute[21]; 614 unsigned char DAC[768]; 615 616 /* PCRTC regs */ 617 uint32_t fb_start; 618 uint32_t crtc_cfg; 619 uint32_t cursor_cfg; 620 uint32_t gpio_ext; 621 uint32_t crtc_830; 622 uint32_t crtc_834; 623 uint32_t crtc_850; 624 uint32_t crtc_eng_ctrl; 625 626 /* PRAMDAC regs */ 627 uint32_t nv10_cursync; 628 struct nouveau_pll_vals pllvals; 629 uint32_t ramdac_gen_ctrl; 630 uint32_t ramdac_630; 631 uint32_t ramdac_634; 632 uint32_t tv_setup; 633 uint32_t tv_vtotal; 634 uint32_t tv_vskew; 635 uint32_t tv_vsync_delay; 636 uint32_t tv_htotal; 637 uint32_t tv_hskew; 638 uint32_t tv_hsync_delay; 639 uint32_t tv_hsync_delay2; 640 uint32_t fp_horiz_regs[7]; 641 uint32_t fp_vert_regs[7]; 642 uint32_t dither; 643 uint32_t fp_control; 644 uint32_t dither_regs[6]; 645 uint32_t fp_debug_0; 646 uint32_t fp_debug_1; 647 uint32_t fp_debug_2; 648 uint32_t fp_margin_color; 649 uint32_t ramdac_8c0; 650 uint32_t ramdac_a20; 651 uint32_t ramdac_a24; 652 uint32_t ramdac_a34; 653 uint32_t ctv_regs[38]; 654}; 655 656struct nv04_output_reg { 657 uint32_t output; 658 int head; 659}; 660 661struct nv04_mode_state { 662 struct nv04_crtc_reg crtc_reg[2]; 663 uint32_t pllsel; 664 uint32_t sel_clk; 665}; 666 667enum nouveau_card_type { 668 NV_04 = 0x00, 669 NV_10 = 0x10, 670 NV_20 = 0x20, 671 NV_30 = 0x30, 672 NV_40 = 0x40, 673 NV_50 = 0x50, 674 NV_C0 = 0xc0, 675 NV_D0 = 0xd0 676}; 677 678struct drm_nouveau_private { 679 struct drm_device *dev; 680 bool noaccel; 681 682 /* the card type, takes NV_* as values */ 683 enum nouveau_card_type card_type; 684 /* exact chipset, derived from NV_PMC_BOOT_0 */ 685 int chipset; 686 int flags; 687 u32 crystal; 688 689 void __iomem *mmio; 690 691 spinlock_t ramin_lock; 692 void __iomem *ramin; 693 u32 ramin_size; 694 u32 ramin_base; 695 bool ramin_available; 696 struct drm_mm ramin_heap; 697 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 698 struct list_head gpuobj_list; 699 struct list_head classes; 700 701 struct nouveau_bo *vga_ram; 702 703 /* interrupt handling */ 704 void (*irq_handler[32])(struct drm_device *); 705 bool msi_enabled; 706 707 struct list_head vbl_waiting; 708 709 struct { 710 struct drm_global_reference mem_global_ref; 711 struct ttm_bo_global_ref bo_global_ref; 712 struct ttm_bo_device bdev; 713 atomic_t validate_sequence; 714 } ttm; 715 716 struct { 717 spinlock_t lock; 718 struct drm_mm heap; 719 struct nouveau_bo *bo; 720 } fence; 721 722 struct { 723 spinlock_t lock; 724 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 725 } channels; 726 727 struct nouveau_engine engine; 728 struct nouveau_channel *channel; 729 730 /* For PFIFO and PGRAPH. */ 731 spinlock_t context_switch_lock; 732 733 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 734 spinlock_t vm_lock; 735 736 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 737 struct nouveau_ramht *ramht; 738 struct nouveau_gpuobj *ramfc; 739 struct nouveau_gpuobj *ramro; 740 741 uint32_t ramin_rsvd_vram; 742 743 struct { 744 enum { 745 NOUVEAU_GART_NONE = 0, 746 NOUVEAU_GART_AGP, /* AGP */ 747 NOUVEAU_GART_PDMA, /* paged dma object */ 748 NOUVEAU_GART_HW /* on-chip gart/vm */ 749 } type; 750 uint64_t aper_base; 751 uint64_t aper_size; 752 uint64_t aper_free; 753 754 struct ttm_backend_func *func; 755 756 struct { 757 struct page *page; 758 dma_addr_t addr; 759 } dummy; 760 761 struct nouveau_gpuobj *sg_ctxdma; 762 } gart_info; 763 764 /* nv10-nv40 tiling regions */ 765 struct { 766 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 767 spinlock_t lock; 768 } tile; 769 770 /* VRAM/fb configuration */ 771 enum { 772 NV_MEM_TYPE_UNKNOWN = 0, 773 NV_MEM_TYPE_STOLEN, 774 NV_MEM_TYPE_SGRAM, 775 NV_MEM_TYPE_SDRAM, 776 NV_MEM_TYPE_DDR1, 777 NV_MEM_TYPE_DDR2, 778 NV_MEM_TYPE_DDR3, 779 NV_MEM_TYPE_GDDR2, 780 NV_MEM_TYPE_GDDR3, 781 NV_MEM_TYPE_GDDR4, 782 NV_MEM_TYPE_GDDR5 783 } vram_type; 784 uint64_t vram_size; 785 uint64_t vram_sys_base; 786 787 uint64_t fb_available_size; 788 uint64_t fb_mappable_pages; 789 uint64_t fb_aper_free; 790 int fb_mtrr; 791 792 /* BAR control (NV50-) */ 793 struct nouveau_vm *bar1_vm; 794 struct nouveau_vm *bar3_vm; 795 796 /* G8x/G9x virtual address space */ 797 struct nouveau_vm *chan_vm; 798 799 struct nvbios vbios; 800 u8 *mxms; 801 struct list_head i2c_ports; 802 803 struct nv04_mode_state mode_reg; 804 struct nv04_mode_state saved_reg; 805 uint32_t saved_vga_font[4][16384]; 806 uint32_t crtc_owner; 807 uint32_t dac_users[4]; 808 809 struct backlight_device *backlight; 810 811 struct { 812 struct dentry *channel_root; 813 } debugfs; 814 815 struct nouveau_fbdev *nfbdev; 816 struct apertures_struct *apertures; 817}; 818 819static inline struct drm_nouveau_private * 820nouveau_private(struct drm_device *dev) 821{ 822 return dev->dev_private; 823} 824 825static inline struct drm_nouveau_private * 826nouveau_bdev(struct ttm_bo_device *bd) 827{ 828 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 829} 830 831static inline int 832nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 833{ 834 struct nouveau_bo *prev; 835 836 if (!pnvbo) 837 return -EINVAL; 838 prev = *pnvbo; 839 840 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 841 if (prev) { 842 struct ttm_buffer_object *bo = &prev->bo; 843 844 ttm_bo_unref(&bo); 845 } 846 847 return 0; 848} 849 850/* nouveau_drv.c */ 851extern int nouveau_modeset; 852extern int nouveau_agpmode; 853extern int nouveau_duallink; 854extern int nouveau_uscript_lvds; 855extern int nouveau_uscript_tmds; 856extern int nouveau_vram_pushbuf; 857extern int nouveau_vram_notify; 858extern char *nouveau_vram_type; 859extern int nouveau_fbpercrtc; 860extern int nouveau_tv_disable; 861extern char *nouveau_tv_norm; 862extern int nouveau_reg_debug; 863extern char *nouveau_vbios; 864extern int nouveau_ignorelid; 865extern int nouveau_nofbaccel; 866extern int nouveau_noaccel; 867extern int nouveau_force_post; 868extern int nouveau_override_conntype; 869extern char *nouveau_perflvl; 870extern int nouveau_perflvl_wr; 871extern int nouveau_msi; 872extern int nouveau_ctxfw; 873extern int nouveau_mxmdcb; 874 875extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 876extern int nouveau_pci_resume(struct pci_dev *pdev); 877 878/* nouveau_state.c */ 879extern int nouveau_open(struct drm_device *, struct drm_file *); 880extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 881extern void nouveau_postclose(struct drm_device *, struct drm_file *); 882extern int nouveau_load(struct drm_device *, unsigned long flags); 883extern int nouveau_firstopen(struct drm_device *); 884extern void nouveau_lastclose(struct drm_device *); 885extern int nouveau_unload(struct drm_device *); 886extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 887 struct drm_file *); 888extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 889 struct drm_file *); 890extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 891 uint32_t reg, uint32_t mask, uint32_t val); 892extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 893 uint32_t reg, uint32_t mask, uint32_t val); 894extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 895 bool (*cond)(void *), void *); 896extern bool nouveau_wait_for_idle(struct drm_device *); 897extern int nouveau_card_init(struct drm_device *); 898 899/* nouveau_mem.c */ 900extern int nouveau_mem_vram_init(struct drm_device *); 901extern void nouveau_mem_vram_fini(struct drm_device *); 902extern int nouveau_mem_gart_init(struct drm_device *); 903extern void nouveau_mem_gart_fini(struct drm_device *); 904extern int nouveau_mem_init_agp(struct drm_device *); 905extern int nouveau_mem_reset_agp(struct drm_device *); 906extern void nouveau_mem_close(struct drm_device *); 907extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 908extern int nouveau_mem_vbios_type(struct drm_device *); 909extern struct nouveau_tile_reg *nv10_mem_set_tiling( 910 struct drm_device *dev, uint32_t addr, uint32_t size, 911 uint32_t pitch, uint32_t flags); 912extern void nv10_mem_put_tile_region(struct drm_device *dev, 913 struct nouveau_tile_reg *tile, 914 struct nouveau_fence *fence); 915extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 916extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 917void nv30_mem_timing_entry(struct drm_device *dev, 918 struct nouveau_pm_tbl_header *hdr, 919 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 920 struct nouveau_pm_memtiming *timing); 921 922/* nouveau_notifier.c */ 923extern int nouveau_notifier_init_channel(struct nouveau_channel *); 924extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 925extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 926 int cout, uint32_t start, uint32_t end, 927 uint32_t *offset); 928extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 929extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 930 struct drm_file *); 931extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 932 struct drm_file *); 933 934/* nouveau_channel.c */ 935extern struct drm_ioctl_desc nouveau_ioctls[]; 936extern int nouveau_max_ioctl; 937extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 938extern int nouveau_channel_alloc(struct drm_device *dev, 939 struct nouveau_channel **chan, 940 struct drm_file *file_priv, 941 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 942extern struct nouveau_channel * 943nouveau_channel_get_unlocked(struct nouveau_channel *); 944extern struct nouveau_channel * 945nouveau_channel_get(struct drm_file *, int id); 946extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 947extern void nouveau_channel_put(struct nouveau_channel **); 948extern void nouveau_channel_ref(struct nouveau_channel *chan, 949 struct nouveau_channel **pchan); 950extern void nouveau_channel_idle(struct nouveau_channel *chan); 951 952/* nouveau_object.c */ 953#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 954 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 955 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 956} while (0) 957 958#define NVOBJ_ENGINE_DEL(d, e) do { \ 959 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 960 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 961} while (0) 962 963#define NVOBJ_CLASS(d, c, e) do { \ 964 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 965 if (ret) \ 966 return ret; \ 967} while (0) 968 969#define NVOBJ_MTHD(d, c, m, e) do { \ 970 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 971 if (ret) \ 972 return ret; \ 973} while (0) 974 975extern int nouveau_gpuobj_early_init(struct drm_device *); 976extern int nouveau_gpuobj_init(struct drm_device *); 977extern void nouveau_gpuobj_takedown(struct drm_device *); 978extern int nouveau_gpuobj_suspend(struct drm_device *dev); 979extern void nouveau_gpuobj_resume(struct drm_device *dev); 980extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 981extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 982 int (*exec)(struct nouveau_channel *, 983 u32 class, u32 mthd, u32 data)); 984extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 985extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 986extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 987 uint32_t vram_h, uint32_t tt_h); 988extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 989extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 990 uint32_t size, int align, uint32_t flags, 991 struct nouveau_gpuobj **); 992extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 993 struct nouveau_gpuobj **); 994extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 995 u32 size, u32 flags, 996 struct nouveau_gpuobj **); 997extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 998 uint64_t offset, uint64_t size, int access, 999 int target, struct nouveau_gpuobj **); 1000extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1001extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1002 u64 size, int target, int access, u32 type, 1003 u32 comp, struct nouveau_gpuobj **pobj); 1004extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1005 int class, u64 base, u64 size, int target, 1006 int access, u32 type, u32 comp); 1007extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1008 struct drm_file *); 1009extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1010 struct drm_file *); 1011 1012/* nouveau_irq.c */ 1013extern int nouveau_irq_init(struct drm_device *); 1014extern void nouveau_irq_fini(struct drm_device *); 1015extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1016extern void nouveau_irq_register(struct drm_device *, int status_bit, 1017 void (*)(struct drm_device *)); 1018extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1019extern void nouveau_irq_preinstall(struct drm_device *); 1020extern int nouveau_irq_postinstall(struct drm_device *); 1021extern void nouveau_irq_uninstall(struct drm_device *); 1022 1023/* nouveau_sgdma.c */ 1024extern int nouveau_sgdma_init(struct drm_device *); 1025extern void nouveau_sgdma_takedown(struct drm_device *); 1026extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1027 uint32_t offset); 1028extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1029 unsigned long size, 1030 uint32_t page_flags, 1031 struct page *dummy_read_page); 1032 1033/* nouveau_debugfs.c */ 1034#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1035extern int nouveau_debugfs_init(struct drm_minor *); 1036extern void nouveau_debugfs_takedown(struct drm_minor *); 1037extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1038extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1039#else 1040static inline int 1041nouveau_debugfs_init(struct drm_minor *minor) 1042{ 1043 return 0; 1044} 1045 1046static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1047{ 1048} 1049 1050static inline int 1051nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1052{ 1053 return 0; 1054} 1055 1056static inline void 1057nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1058{ 1059} 1060#endif 1061 1062/* nouveau_dma.c */ 1063extern void nouveau_dma_pre_init(struct nouveau_channel *); 1064extern int nouveau_dma_init(struct nouveau_channel *); 1065extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1066 1067/* nouveau_acpi.c */ 1068#define ROM_BIOS_PAGE 4096 1069#if defined(CONFIG_ACPI) 1070void nouveau_register_dsm_handler(void); 1071void nouveau_unregister_dsm_handler(void); 1072void nouveau_switcheroo_optimus_dsm(void); 1073int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1074bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1075int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1076#else 1077static inline void nouveau_register_dsm_handler(void) {} 1078static inline void nouveau_unregister_dsm_handler(void) {} 1079static inline void nouveau_switcheroo_optimus_dsm(void) {} 1080static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1081static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1082static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1083#endif 1084 1085/* nouveau_backlight.c */ 1086#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1087extern int nouveau_backlight_init(struct drm_device *); 1088extern void nouveau_backlight_exit(struct drm_device *); 1089#else 1090static inline int nouveau_backlight_init(struct drm_device *dev) 1091{ 1092 return 0; 1093} 1094 1095static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1096#endif 1097 1098/* nouveau_bios.c */ 1099extern int nouveau_bios_init(struct drm_device *); 1100extern void nouveau_bios_takedown(struct drm_device *dev); 1101extern int nouveau_run_vbios_init(struct drm_device *); 1102extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1103 struct dcb_entry *, int crtc); 1104extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1105extern struct dcb_connector_table_entry * 1106nouveau_bios_connector_entry(struct drm_device *, int index); 1107extern u32 get_pll_register(struct drm_device *, enum pll_types); 1108extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1109 struct pll_lims *); 1110extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1111 struct dcb_entry *, int crtc); 1112extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1113extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1114extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1115 bool *dl, bool *if_is_24bit); 1116extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1117 int head, int pxclk); 1118extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1119 enum LVDS_script, int pxclk); 1120bool bios_encoder_match(struct dcb_entry *, u32 hash); 1121 1122/* nouveau_mxm.c */ 1123int nouveau_mxm_init(struct drm_device *dev); 1124void nouveau_mxm_fini(struct drm_device *dev); 1125 1126/* nouveau_ttm.c */ 1127int nouveau_ttm_global_init(struct drm_nouveau_private *); 1128void nouveau_ttm_global_release(struct drm_nouveau_private *); 1129int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1130 1131/* nouveau_hdmi.c */ 1132void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1133 1134/* nouveau_dp.c */ 1135int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1136 uint8_t *data, int data_nr); 1137bool nouveau_dp_detect(struct drm_encoder *); 1138bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1139void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1140u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1141 1142/* nv04_fb.c */ 1143extern int nv04_fb_vram_init(struct drm_device *); 1144extern int nv04_fb_init(struct drm_device *); 1145extern void nv04_fb_takedown(struct drm_device *); 1146 1147/* nv10_fb.c */ 1148extern int nv10_fb_vram_init(struct drm_device *dev); 1149extern int nv1a_fb_vram_init(struct drm_device *dev); 1150extern int nv10_fb_init(struct drm_device *); 1151extern void nv10_fb_takedown(struct drm_device *); 1152extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1153 uint32_t addr, uint32_t size, 1154 uint32_t pitch, uint32_t flags); 1155extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1156extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1157 1158/* nv20_fb.c */ 1159extern int nv20_fb_vram_init(struct drm_device *dev); 1160extern int nv20_fb_init(struct drm_device *); 1161extern void nv20_fb_takedown(struct drm_device *); 1162extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1163 uint32_t addr, uint32_t size, 1164 uint32_t pitch, uint32_t flags); 1165extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1166extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1167 1168/* nv30_fb.c */ 1169extern int nv30_fb_init(struct drm_device *); 1170extern void nv30_fb_takedown(struct drm_device *); 1171extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1172 uint32_t addr, uint32_t size, 1173 uint32_t pitch, uint32_t flags); 1174extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1175 1176/* nv40_fb.c */ 1177extern int nv40_fb_vram_init(struct drm_device *dev); 1178extern int nv40_fb_init(struct drm_device *); 1179extern void nv40_fb_takedown(struct drm_device *); 1180extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1181 1182/* nv50_fb.c */ 1183extern int nv50_fb_init(struct drm_device *); 1184extern void nv50_fb_takedown(struct drm_device *); 1185extern void nv50_fb_vm_trap(struct drm_device *, int display); 1186 1187/* nvc0_fb.c */ 1188extern int nvc0_fb_init(struct drm_device *); 1189extern void nvc0_fb_takedown(struct drm_device *); 1190 1191/* nv04_fifo.c */ 1192extern int nv04_fifo_init(struct drm_device *); 1193extern void nv04_fifo_fini(struct drm_device *); 1194extern void nv04_fifo_disable(struct drm_device *); 1195extern void nv04_fifo_enable(struct drm_device *); 1196extern bool nv04_fifo_reassign(struct drm_device *, bool); 1197extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1198extern int nv04_fifo_channel_id(struct drm_device *); 1199extern int nv04_fifo_create_context(struct nouveau_channel *); 1200extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1201extern int nv04_fifo_load_context(struct nouveau_channel *); 1202extern int nv04_fifo_unload_context(struct drm_device *); 1203extern void nv04_fifo_isr(struct drm_device *); 1204 1205/* nv10_fifo.c */ 1206extern int nv10_fifo_init(struct drm_device *); 1207extern int nv10_fifo_channel_id(struct drm_device *); 1208extern int nv10_fifo_create_context(struct nouveau_channel *); 1209extern int nv10_fifo_load_context(struct nouveau_channel *); 1210extern int nv10_fifo_unload_context(struct drm_device *); 1211 1212/* nv40_fifo.c */ 1213extern int nv40_fifo_init(struct drm_device *); 1214extern int nv40_fifo_create_context(struct nouveau_channel *); 1215extern int nv40_fifo_load_context(struct nouveau_channel *); 1216extern int nv40_fifo_unload_context(struct drm_device *); 1217 1218/* nv50_fifo.c */ 1219extern int nv50_fifo_init(struct drm_device *); 1220extern void nv50_fifo_takedown(struct drm_device *); 1221extern int nv50_fifo_channel_id(struct drm_device *); 1222extern int nv50_fifo_create_context(struct nouveau_channel *); 1223extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1224extern int nv50_fifo_load_context(struct nouveau_channel *); 1225extern int nv50_fifo_unload_context(struct drm_device *); 1226extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1227 1228/* nvc0_fifo.c */ 1229extern int nvc0_fifo_init(struct drm_device *); 1230extern void nvc0_fifo_takedown(struct drm_device *); 1231extern void nvc0_fifo_disable(struct drm_device *); 1232extern void nvc0_fifo_enable(struct drm_device *); 1233extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1234extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1235extern int nvc0_fifo_channel_id(struct drm_device *); 1236extern int nvc0_fifo_create_context(struct nouveau_channel *); 1237extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1238extern int nvc0_fifo_load_context(struct nouveau_channel *); 1239extern int nvc0_fifo_unload_context(struct drm_device *); 1240 1241/* nv04_graph.c */ 1242extern int nv04_graph_create(struct drm_device *); 1243extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1244extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1245 u32 class, u32 mthd, u32 data); 1246extern struct nouveau_bitfield nv04_graph_nsource[]; 1247 1248/* nv10_graph.c */ 1249extern int nv10_graph_create(struct drm_device *); 1250extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1251extern struct nouveau_bitfield nv10_graph_intr[]; 1252extern struct nouveau_bitfield nv10_graph_nstatus[]; 1253 1254/* nv20_graph.c */ 1255extern int nv20_graph_create(struct drm_device *); 1256 1257/* nv40_graph.c */ 1258extern int nv40_graph_create(struct drm_device *); 1259extern void nv40_grctx_init(struct nouveau_grctx *); 1260 1261/* nv50_graph.c */ 1262extern int nv50_graph_create(struct drm_device *); 1263extern int nv50_grctx_init(struct nouveau_grctx *); 1264extern struct nouveau_enum nv50_data_error_names[]; 1265extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1266 1267/* nvc0_graph.c */ 1268extern int nvc0_graph_create(struct drm_device *); 1269extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1270 1271/* nv84_crypt.c */ 1272extern int nv84_crypt_create(struct drm_device *); 1273 1274/* nv98_crypt.c */ 1275extern int nv98_crypt_create(struct drm_device *dev); 1276 1277/* nva3_copy.c */ 1278extern int nva3_copy_create(struct drm_device *dev); 1279 1280/* nvc0_copy.c */ 1281extern int nvc0_copy_create(struct drm_device *dev, int engine); 1282 1283/* nv31_mpeg.c */ 1284extern int nv31_mpeg_create(struct drm_device *dev); 1285 1286/* nv50_mpeg.c */ 1287extern int nv50_mpeg_create(struct drm_device *dev); 1288 1289/* nv84_bsp.c */ 1290/* nv98_bsp.c */ 1291extern int nv84_bsp_create(struct drm_device *dev); 1292 1293/* nv84_vp.c */ 1294/* nv98_vp.c */ 1295extern int nv84_vp_create(struct drm_device *dev); 1296 1297/* nv98_ppp.c */ 1298extern int nv98_ppp_create(struct drm_device *dev); 1299 1300/* nv04_instmem.c */ 1301extern int nv04_instmem_init(struct drm_device *); 1302extern void nv04_instmem_takedown(struct drm_device *); 1303extern int nv04_instmem_suspend(struct drm_device *); 1304extern void nv04_instmem_resume(struct drm_device *); 1305extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1306 u32 size, u32 align); 1307extern void nv04_instmem_put(struct nouveau_gpuobj *); 1308extern int nv04_instmem_map(struct nouveau_gpuobj *); 1309extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1310extern void nv04_instmem_flush(struct drm_device *); 1311 1312/* nv50_instmem.c */ 1313extern int nv50_instmem_init(struct drm_device *); 1314extern void nv50_instmem_takedown(struct drm_device *); 1315extern int nv50_instmem_suspend(struct drm_device *); 1316extern void nv50_instmem_resume(struct drm_device *); 1317extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1318 u32 size, u32 align); 1319extern void nv50_instmem_put(struct nouveau_gpuobj *); 1320extern int nv50_instmem_map(struct nouveau_gpuobj *); 1321extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1322extern void nv50_instmem_flush(struct drm_device *); 1323extern void nv84_instmem_flush(struct drm_device *); 1324 1325/* nvc0_instmem.c */ 1326extern int nvc0_instmem_init(struct drm_device *); 1327extern void nvc0_instmem_takedown(struct drm_device *); 1328extern int nvc0_instmem_suspend(struct drm_device *); 1329extern void nvc0_instmem_resume(struct drm_device *); 1330 1331/* nv04_mc.c */ 1332extern int nv04_mc_init(struct drm_device *); 1333extern void nv04_mc_takedown(struct drm_device *); 1334 1335/* nv40_mc.c */ 1336extern int nv40_mc_init(struct drm_device *); 1337extern void nv40_mc_takedown(struct drm_device *); 1338 1339/* nv50_mc.c */ 1340extern int nv50_mc_init(struct drm_device *); 1341extern void nv50_mc_takedown(struct drm_device *); 1342 1343/* nv04_timer.c */ 1344extern int nv04_timer_init(struct drm_device *); 1345extern uint64_t nv04_timer_read(struct drm_device *); 1346extern void nv04_timer_takedown(struct drm_device *); 1347 1348extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1349 unsigned long arg); 1350 1351/* nv04_dac.c */ 1352extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1353extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1354extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1355extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1356extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1357 1358/* nv04_dfp.c */ 1359extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1360extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1361extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1362 int head, bool dl); 1363extern void nv04_dfp_disable(struct drm_device *dev, int head); 1364extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1365 1366/* nv04_tv.c */ 1367extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1368extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1369 1370/* nv17_tv.c */ 1371extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1372 1373/* nv04_display.c */ 1374extern int nv04_display_early_init(struct drm_device *); 1375extern void nv04_display_late_takedown(struct drm_device *); 1376extern int nv04_display_create(struct drm_device *); 1377extern void nv04_display_destroy(struct drm_device *); 1378extern int nv04_display_init(struct drm_device *); 1379extern void nv04_display_fini(struct drm_device *); 1380 1381/* nvd0_display.c */ 1382extern int nvd0_display_create(struct drm_device *); 1383extern void nvd0_display_destroy(struct drm_device *); 1384extern int nvd0_display_init(struct drm_device *); 1385extern void nvd0_display_fini(struct drm_device *); 1386struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1387void nvd0_display_flip_stop(struct drm_crtc *); 1388int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1389 struct nouveau_channel *, u32 swap_interval); 1390 1391/* nv04_crtc.c */ 1392extern int nv04_crtc_create(struct drm_device *, int index); 1393 1394/* nouveau_bo.c */ 1395extern struct ttm_bo_driver nouveau_bo_driver; 1396extern int nouveau_bo_new(struct drm_device *, int size, int align, 1397 uint32_t flags, uint32_t tile_mode, 1398 uint32_t tile_flags, struct nouveau_bo **); 1399extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1400extern int nouveau_bo_unpin(struct nouveau_bo *); 1401extern int nouveau_bo_map(struct nouveau_bo *); 1402extern void nouveau_bo_unmap(struct nouveau_bo *); 1403extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1404 uint32_t busy); 1405extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1406extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1407extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1408extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1409extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1410extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1411 bool no_wait_reserve, bool no_wait_gpu); 1412 1413extern struct nouveau_vma * 1414nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1415extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1416 struct nouveau_vma *); 1417extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1418 1419/* nouveau_fence.c */ 1420struct nouveau_fence; 1421extern int nouveau_fence_init(struct drm_device *); 1422extern void nouveau_fence_fini(struct drm_device *); 1423extern int nouveau_fence_channel_init(struct nouveau_channel *); 1424extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1425extern void nouveau_fence_update(struct nouveau_channel *); 1426extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1427 bool emit); 1428extern int nouveau_fence_emit(struct nouveau_fence *); 1429extern void nouveau_fence_work(struct nouveau_fence *fence, 1430 void (*work)(void *priv, bool signalled), 1431 void *priv); 1432struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1433 1434extern bool __nouveau_fence_signalled(void *obj, void *arg); 1435extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1436extern int __nouveau_fence_flush(void *obj, void *arg); 1437extern void __nouveau_fence_unref(void **obj); 1438extern void *__nouveau_fence_ref(void *obj); 1439 1440static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1441{ 1442 return __nouveau_fence_signalled(obj, NULL); 1443} 1444static inline int 1445nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1446{ 1447 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1448} 1449extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1450static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1451{ 1452 return __nouveau_fence_flush(obj, NULL); 1453} 1454static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1455{ 1456 __nouveau_fence_unref((void **)obj); 1457} 1458static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1459{ 1460 return __nouveau_fence_ref(obj); 1461} 1462 1463/* nouveau_gem.c */ 1464extern int nouveau_gem_new(struct drm_device *, int size, int align, 1465 uint32_t domain, uint32_t tile_mode, 1466 uint32_t tile_flags, struct nouveau_bo **); 1467extern int nouveau_gem_object_new(struct drm_gem_object *); 1468extern void nouveau_gem_object_del(struct drm_gem_object *); 1469extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1470extern void nouveau_gem_object_close(struct drm_gem_object *, 1471 struct drm_file *); 1472extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1473 struct drm_file *); 1474extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1475 struct drm_file *); 1476extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1477 struct drm_file *); 1478extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1479 struct drm_file *); 1480extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1481 struct drm_file *); 1482 1483/* nouveau_display.c */ 1484int nouveau_display_create(struct drm_device *dev); 1485void nouveau_display_destroy(struct drm_device *dev); 1486int nouveau_display_init(struct drm_device *dev); 1487void nouveau_display_fini(struct drm_device *dev); 1488int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1489void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1490int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1491 struct drm_pending_vblank_event *event); 1492int nouveau_finish_page_flip(struct nouveau_channel *, 1493 struct nouveau_page_flip_state *); 1494int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1495 struct drm_mode_create_dumb *args); 1496int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1497 uint32_t handle, uint64_t *offset); 1498int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1499 uint32_t handle); 1500 1501/* nv10_gpio.c */ 1502int nv10_gpio_init(struct drm_device *dev); 1503void nv10_gpio_fini(struct drm_device *dev); 1504int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1505int nv10_gpio_sense(struct drm_device *dev, int line); 1506void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1507 1508/* nv50_gpio.c */ 1509int nv50_gpio_init(struct drm_device *dev); 1510void nv50_gpio_fini(struct drm_device *dev); 1511int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1512int nv50_gpio_sense(struct drm_device *dev, int line); 1513void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1514int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1515int nvd0_gpio_sense(struct drm_device *dev, int line); 1516 1517/* nv50_calc.c */ 1518int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1519 int *N1, int *M1, int *N2, int *M2, int *P); 1520int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1521 int clk, int *N, int *fN, int *M, int *P); 1522 1523#ifndef ioread32_native 1524#ifdef __BIG_ENDIAN 1525#define ioread16_native ioread16be 1526#define iowrite16_native iowrite16be 1527#define ioread32_native ioread32be 1528#define iowrite32_native iowrite32be 1529#else /* def __BIG_ENDIAN */ 1530#define ioread16_native ioread16 1531#define iowrite16_native iowrite16 1532#define ioread32_native ioread32 1533#define iowrite32_native iowrite32 1534#endif /* def __BIG_ENDIAN else */ 1535#endif /* !ioread32_native */ 1536 1537/* channel control reg access */ 1538static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1539{ 1540 return ioread32_native(chan->user + reg); 1541} 1542 1543static inline void nvchan_wr32(struct nouveau_channel *chan, 1544 unsigned reg, u32 val) 1545{ 1546 iowrite32_native(val, chan->user + reg); 1547} 1548 1549/* register access */ 1550static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1551{ 1552 struct drm_nouveau_private *dev_priv = dev->dev_private; 1553 return ioread32_native(dev_priv->mmio + reg); 1554} 1555 1556static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1557{ 1558 struct drm_nouveau_private *dev_priv = dev->dev_private; 1559 iowrite32_native(val, dev_priv->mmio + reg); 1560} 1561 1562static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1563{ 1564 u32 tmp = nv_rd32(dev, reg); 1565 nv_wr32(dev, reg, (tmp & ~mask) | val); 1566 return tmp; 1567} 1568 1569static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1570{ 1571 struct drm_nouveau_private *dev_priv = dev->dev_private; 1572 return ioread8(dev_priv->mmio + reg); 1573} 1574 1575static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1576{ 1577 struct drm_nouveau_private *dev_priv = dev->dev_private; 1578 iowrite8(val, dev_priv->mmio + reg); 1579} 1580 1581#define nv_wait(dev, reg, mask, val) \ 1582 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1583#define nv_wait_ne(dev, reg, mask, val) \ 1584 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1585#define nv_wait_cb(dev, func, data) \ 1586 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1587 1588/* PRAMIN access */ 1589static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1590{ 1591 struct drm_nouveau_private *dev_priv = dev->dev_private; 1592 return ioread32_native(dev_priv->ramin + offset); 1593} 1594 1595static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1596{ 1597 struct drm_nouveau_private *dev_priv = dev->dev_private; 1598 iowrite32_native(val, dev_priv->ramin + offset); 1599} 1600 1601/* object access */ 1602extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1603extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1604 1605/* 1606 * Logging 1607 * Argument d is (struct drm_device *). 1608 */ 1609#define NV_PRINTK(level, d, fmt, arg...) \ 1610 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1611 pci_name(d->pdev), ##arg) 1612#ifndef NV_DEBUG_NOTRACE 1613#define NV_DEBUG(d, fmt, arg...) do { \ 1614 if (drm_debug & DRM_UT_DRIVER) { \ 1615 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1616 __LINE__, ##arg); \ 1617 } \ 1618} while (0) 1619#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1620 if (drm_debug & DRM_UT_KMS) { \ 1621 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1622 __LINE__, ##arg); \ 1623 } \ 1624} while (0) 1625#else 1626#define NV_DEBUG(d, fmt, arg...) do { \ 1627 if (drm_debug & DRM_UT_DRIVER) \ 1628 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1629} while (0) 1630#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1631 if (drm_debug & DRM_UT_KMS) \ 1632 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1633} while (0) 1634#endif 1635#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1636#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1637#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1638#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1639#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1640#define NV_WARNONCE(d, fmt, arg...) do { \ 1641 static int _warned = 0; \ 1642 if (!_warned) { \ 1643 NV_WARN(d, fmt, ##arg); \ 1644 _warned = 1; \ 1645 } \ 1646} while(0) 1647 1648/* nouveau_reg_debug bitmask */ 1649enum { 1650 NOUVEAU_REG_DEBUG_MC = 0x1, 1651 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1652 NOUVEAU_REG_DEBUG_FB = 0x4, 1653 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1654 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1655 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1656 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1657 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1658 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1659 NOUVEAU_REG_DEBUG_EVO = 0x200, 1660 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1661}; 1662 1663#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1664 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1665 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1666} while (0) 1667 1668static inline bool 1669nv_two_heads(struct drm_device *dev) 1670{ 1671 struct drm_nouveau_private *dev_priv = dev->dev_private; 1672 const int impl = dev->pci_device & 0x0ff0; 1673 1674 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1675 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1676 return true; 1677 1678 return false; 1679} 1680 1681static inline bool 1682nv_gf4_disp_arch(struct drm_device *dev) 1683{ 1684 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1685} 1686 1687static inline bool 1688nv_two_reg_pll(struct drm_device *dev) 1689{ 1690 struct drm_nouveau_private *dev_priv = dev->dev_private; 1691 const int impl = dev->pci_device & 0x0ff0; 1692 1693 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1694 return true; 1695 return false; 1696} 1697 1698static inline bool 1699nv_match_device(struct drm_device *dev, unsigned device, 1700 unsigned sub_vendor, unsigned sub_device) 1701{ 1702 return dev->pdev->device == device && 1703 dev->pdev->subsystem_vendor == sub_vendor && 1704 dev->pdev->subsystem_device == sub_device; 1705} 1706 1707static inline void * 1708nv_engine(struct drm_device *dev, int engine) 1709{ 1710 struct drm_nouveau_private *dev_priv = dev->dev_private; 1711 return (void *)dev_priv->eng[engine]; 1712} 1713 1714/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1715 * helpful to determine a number of other hardware features 1716 */ 1717static inline int 1718nv44_graph_class(struct drm_device *dev) 1719{ 1720 struct drm_nouveau_private *dev_priv = dev->dev_private; 1721 1722 if ((dev_priv->chipset & 0xf0) == 0x60) 1723 return 1; 1724 1725 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1726} 1727 1728/* memory type/access flags, do not match hardware values */ 1729#define NV_MEM_ACCESS_RO 1 1730#define NV_MEM_ACCESS_WO 2 1731#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1732#define NV_MEM_ACCESS_SYS 4 1733#define NV_MEM_ACCESS_VM 8 1734 1735#define NV_MEM_TARGET_VRAM 0 1736#define NV_MEM_TARGET_PCI 1 1737#define NV_MEM_TARGET_PCI_NOSNOOP 2 1738#define NV_MEM_TARGET_VM 3 1739#define NV_MEM_TARGET_GART 4 1740 1741#define NV_MEM_TYPE_VM 0x7f 1742#define NV_MEM_COMP_VM 0x03 1743 1744/* NV_SW object class */ 1745#define NV_SW 0x0000506e 1746#define NV_SW_DMA_SEMAPHORE 0x00000060 1747#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1748#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1749#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1750#define NV_SW_YIELD 0x00000080 1751#define NV_SW_DMA_VBLSEM 0x0000018c 1752#define NV_SW_VBLSEM_OFFSET 0x00000400 1753#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1754#define NV_SW_VBLSEM_RELEASE 0x00000408 1755#define NV_SW_PAGE_FLIP 0x00000500 1756 1757#endif /* __NOUVEAU_DRV_H__ */ 1758