nouveau_drv.h revision c0924326c8306249aaae27016b80f3c07bb51705
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_CRYPT 2 154#define NVOBJ_ENGINE_COPY0 3 155#define NVOBJ_ENGINE_COPY1 4 156#define NVOBJ_ENGINE_MPEG 5 157#define NVOBJ_ENGINE_DISPLAY 15 158#define NVOBJ_ENGINE_NR 16 159 160#define NVOBJ_FLAG_DONT_MAP (1 << 0) 161#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 162#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 163#define NVOBJ_FLAG_VM (1 << 3) 164#define NVOBJ_FLAG_VM_USER (1 << 4) 165 166#define NVOBJ_CINST_GLOBAL 0xdeadbeef 167 168struct nouveau_gpuobj { 169 struct drm_device *dev; 170 struct kref refcount; 171 struct list_head list; 172 173 void *node; 174 u32 *suspend; 175 176 uint32_t flags; 177 178 u32 size; 179 u32 pinst; 180 u32 cinst; 181 u64 vinst; 182 183 uint32_t engine; 184 uint32_t class; 185 186 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 187 void *priv; 188}; 189 190struct nouveau_page_flip_state { 191 struct list_head head; 192 struct drm_pending_vblank_event *event; 193 int crtc, bpp, pitch, x, y; 194 uint64_t offset; 195}; 196 197enum nouveau_channel_mutex_class { 198 NOUVEAU_UCHANNEL_MUTEX, 199 NOUVEAU_KCHANNEL_MUTEX 200}; 201 202struct nouveau_channel { 203 struct drm_device *dev; 204 int id; 205 206 /* references to the channel data structure */ 207 struct kref ref; 208 /* users of the hardware channel resources, the hardware 209 * context will be kicked off when it reaches zero. */ 210 atomic_t users; 211 struct mutex mutex; 212 213 /* owner of this fifo */ 214 struct drm_file *file_priv; 215 /* mapping of the fifo itself */ 216 struct drm_local_map *map; 217 218 /* mapping of the regs controlling the fifo */ 219 void __iomem *user; 220 uint32_t user_get; 221 uint32_t user_put; 222 223 /* Fencing */ 224 struct { 225 /* lock protects the pending list only */ 226 spinlock_t lock; 227 struct list_head pending; 228 uint32_t sequence; 229 uint32_t sequence_ack; 230 atomic_t last_sequence_irq; 231 } fence; 232 233 /* DMA push buffer */ 234 struct nouveau_gpuobj *pushbuf; 235 struct nouveau_bo *pushbuf_bo; 236 uint32_t pushbuf_base; 237 238 /* Notifier memory */ 239 struct nouveau_bo *notifier_bo; 240 struct drm_mm notifier_heap; 241 242 /* PFIFO context */ 243 struct nouveau_gpuobj *ramfc; 244 struct nouveau_gpuobj *cache; 245 void *fifo_priv; 246 247 /* Execution engine contexts */ 248 void *engctx[NVOBJ_ENGINE_NR]; 249 250 /* NV50 VM */ 251 struct nouveau_vm *vm; 252 struct nouveau_gpuobj *vm_pd; 253 254 /* Objects */ 255 struct nouveau_gpuobj *ramin; /* Private instmem */ 256 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 257 struct nouveau_ramht *ramht; /* Hash table */ 258 259 /* GPU object info for stuff used in-kernel (mm_enabled) */ 260 uint32_t m2mf_ntfy; 261 uint32_t vram_handle; 262 uint32_t gart_handle; 263 bool accel_done; 264 265 /* Push buffer state (only for drm's channel on !mm_enabled) */ 266 struct { 267 int max; 268 int free; 269 int cur; 270 int put; 271 /* access via pushbuf_bo */ 272 273 int ib_base; 274 int ib_max; 275 int ib_free; 276 int ib_put; 277 } dma; 278 279 uint32_t sw_subchannel[8]; 280 281 struct { 282 struct nouveau_gpuobj *vblsem; 283 uint32_t vblsem_head; 284 uint32_t vblsem_offset; 285 uint32_t vblsem_rval; 286 struct list_head vbl_wait; 287 struct list_head flip; 288 } nvsw; 289 290 struct { 291 bool active; 292 char name[32]; 293 struct drm_info_list info; 294 } debugfs; 295}; 296 297struct nouveau_exec_engine { 298 void (*destroy)(struct drm_device *, int engine); 299 int (*init)(struct drm_device *, int engine); 300 int (*fini)(struct drm_device *, int engine); 301 int (*context_new)(struct nouveau_channel *, int engine); 302 void (*context_del)(struct nouveau_channel *, int engine); 303 int (*object_new)(struct nouveau_channel *, int engine, 304 u32 handle, u16 class); 305 void (*set_tile_region)(struct drm_device *dev, int i); 306 void (*tlb_flush)(struct drm_device *, int engine); 307}; 308 309struct nouveau_instmem_engine { 310 void *priv; 311 312 int (*init)(struct drm_device *dev); 313 void (*takedown)(struct drm_device *dev); 314 int (*suspend)(struct drm_device *dev); 315 void (*resume)(struct drm_device *dev); 316 317 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 318 void (*put)(struct nouveau_gpuobj *); 319 int (*map)(struct nouveau_gpuobj *); 320 void (*unmap)(struct nouveau_gpuobj *); 321 322 void (*flush)(struct drm_device *); 323}; 324 325struct nouveau_mc_engine { 326 int (*init)(struct drm_device *dev); 327 void (*takedown)(struct drm_device *dev); 328}; 329 330struct nouveau_timer_engine { 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 uint64_t (*read)(struct drm_device *dev); 334}; 335 336struct nouveau_fb_engine { 337 int num_tiles; 338 struct drm_mm tag_heap; 339 void *priv; 340 341 int (*init)(struct drm_device *dev); 342 void (*takedown)(struct drm_device *dev); 343 344 void (*init_tile_region)(struct drm_device *dev, int i, 345 uint32_t addr, uint32_t size, 346 uint32_t pitch, uint32_t flags); 347 void (*set_tile_region)(struct drm_device *dev, int i); 348 void (*free_tile_region)(struct drm_device *dev, int i); 349}; 350 351struct nouveau_fifo_engine { 352 void *priv; 353 int channels; 354 355 struct nouveau_gpuobj *playlist[2]; 356 int cur_playlist; 357 358 int (*init)(struct drm_device *); 359 void (*takedown)(struct drm_device *); 360 361 void (*disable)(struct drm_device *); 362 void (*enable)(struct drm_device *); 363 bool (*reassign)(struct drm_device *, bool enable); 364 bool (*cache_pull)(struct drm_device *dev, bool enable); 365 366 int (*channel_id)(struct drm_device *); 367 368 int (*create_context)(struct nouveau_channel *); 369 void (*destroy_context)(struct nouveau_channel *); 370 int (*load_context)(struct nouveau_channel *); 371 int (*unload_context)(struct drm_device *); 372 void (*tlb_flush)(struct drm_device *dev); 373}; 374 375struct nouveau_display_engine { 376 void *priv; 377 int (*early_init)(struct drm_device *); 378 void (*late_takedown)(struct drm_device *); 379 int (*create)(struct drm_device *); 380 int (*init)(struct drm_device *); 381 void (*destroy)(struct drm_device *); 382}; 383 384struct nouveau_gpio_engine { 385 void *priv; 386 387 int (*init)(struct drm_device *); 388 void (*takedown)(struct drm_device *); 389 390 int (*get)(struct drm_device *, enum dcb_gpio_tag); 391 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 392 393 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 394 void (*)(void *, int), void *); 395 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 396 void (*)(void *, int), void *); 397 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 398}; 399 400struct nouveau_pm_voltage_level { 401 u8 voltage; 402 u8 vid; 403}; 404 405struct nouveau_pm_voltage { 406 bool supported; 407 u8 vid_mask; 408 409 struct nouveau_pm_voltage_level *level; 410 int nr_level; 411}; 412 413#define NOUVEAU_PM_MAX_LEVEL 8 414struct nouveau_pm_level { 415 struct device_attribute dev_attr; 416 char name[32]; 417 int id; 418 419 u32 core; 420 u32 memory; 421 u32 shader; 422 u32 unk05; 423 424 u8 voltage; 425 u8 fanspeed; 426 427 u16 memscript; 428}; 429 430struct nouveau_pm_temp_sensor_constants { 431 u16 offset_constant; 432 s16 offset_mult; 433 u16 offset_div; 434 u16 slope_mult; 435 u16 slope_div; 436}; 437 438struct nouveau_pm_threshold_temp { 439 s16 critical; 440 s16 down_clock; 441 s16 fan_boost; 442}; 443 444struct nouveau_pm_memtiming { 445 u32 reg_100220; 446 u32 reg_100224; 447 u32 reg_100228; 448 u32 reg_10022c; 449 u32 reg_100230; 450 u32 reg_100234; 451 u32 reg_100238; 452 u32 reg_10023c; 453 u32 reg_100240; 454}; 455 456struct nouveau_pm_memtimings { 457 bool supported; 458 struct nouveau_pm_memtiming *timing; 459 int nr_timing; 460}; 461 462struct nouveau_pm_engine { 463 struct nouveau_pm_voltage voltage; 464 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 465 int nr_perflvl; 466 struct nouveau_pm_memtimings memtimings; 467 struct nouveau_pm_temp_sensor_constants sensor_constants; 468 struct nouveau_pm_threshold_temp threshold_temp; 469 470 struct nouveau_pm_level boot; 471 struct nouveau_pm_level *cur; 472 473 struct device *hwmon; 474 struct notifier_block acpi_nb; 475 476 int (*clock_get)(struct drm_device *, u32 id); 477 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 478 u32 id, int khz); 479 void (*clock_set)(struct drm_device *, void *); 480 int (*voltage_get)(struct drm_device *); 481 int (*voltage_set)(struct drm_device *, int voltage); 482 int (*fanspeed_get)(struct drm_device *); 483 int (*fanspeed_set)(struct drm_device *, int fanspeed); 484 int (*temp_get)(struct drm_device *); 485}; 486 487struct nouveau_vram_engine { 488 int (*init)(struct drm_device *); 489 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 490 u32 type, struct nouveau_mem **); 491 void (*put)(struct drm_device *, struct nouveau_mem **); 492 493 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 494}; 495 496struct nouveau_engine { 497 struct nouveau_instmem_engine instmem; 498 struct nouveau_mc_engine mc; 499 struct nouveau_timer_engine timer; 500 struct nouveau_fb_engine fb; 501 struct nouveau_fifo_engine fifo; 502 struct nouveau_display_engine display; 503 struct nouveau_gpio_engine gpio; 504 struct nouveau_pm_engine pm; 505 struct nouveau_vram_engine vram; 506}; 507 508struct nouveau_pll_vals { 509 union { 510 struct { 511#ifdef __BIG_ENDIAN 512 uint8_t N1, M1, N2, M2; 513#else 514 uint8_t M1, N1, M2, N2; 515#endif 516 }; 517 struct { 518 uint16_t NM1, NM2; 519 } __attribute__((packed)); 520 }; 521 int log2P; 522 523 int refclk; 524}; 525 526enum nv04_fp_display_regs { 527 FP_DISPLAY_END, 528 FP_TOTAL, 529 FP_CRTC, 530 FP_SYNC_START, 531 FP_SYNC_END, 532 FP_VALID_START, 533 FP_VALID_END 534}; 535 536struct nv04_crtc_reg { 537 unsigned char MiscOutReg; 538 uint8_t CRTC[0xa0]; 539 uint8_t CR58[0x10]; 540 uint8_t Sequencer[5]; 541 uint8_t Graphics[9]; 542 uint8_t Attribute[21]; 543 unsigned char DAC[768]; 544 545 /* PCRTC regs */ 546 uint32_t fb_start; 547 uint32_t crtc_cfg; 548 uint32_t cursor_cfg; 549 uint32_t gpio_ext; 550 uint32_t crtc_830; 551 uint32_t crtc_834; 552 uint32_t crtc_850; 553 uint32_t crtc_eng_ctrl; 554 555 /* PRAMDAC regs */ 556 uint32_t nv10_cursync; 557 struct nouveau_pll_vals pllvals; 558 uint32_t ramdac_gen_ctrl; 559 uint32_t ramdac_630; 560 uint32_t ramdac_634; 561 uint32_t tv_setup; 562 uint32_t tv_vtotal; 563 uint32_t tv_vskew; 564 uint32_t tv_vsync_delay; 565 uint32_t tv_htotal; 566 uint32_t tv_hskew; 567 uint32_t tv_hsync_delay; 568 uint32_t tv_hsync_delay2; 569 uint32_t fp_horiz_regs[7]; 570 uint32_t fp_vert_regs[7]; 571 uint32_t dither; 572 uint32_t fp_control; 573 uint32_t dither_regs[6]; 574 uint32_t fp_debug_0; 575 uint32_t fp_debug_1; 576 uint32_t fp_debug_2; 577 uint32_t fp_margin_color; 578 uint32_t ramdac_8c0; 579 uint32_t ramdac_a20; 580 uint32_t ramdac_a24; 581 uint32_t ramdac_a34; 582 uint32_t ctv_regs[38]; 583}; 584 585struct nv04_output_reg { 586 uint32_t output; 587 int head; 588}; 589 590struct nv04_mode_state { 591 struct nv04_crtc_reg crtc_reg[2]; 592 uint32_t pllsel; 593 uint32_t sel_clk; 594}; 595 596enum nouveau_card_type { 597 NV_04 = 0x00, 598 NV_10 = 0x10, 599 NV_20 = 0x20, 600 NV_30 = 0x30, 601 NV_40 = 0x40, 602 NV_50 = 0x50, 603 NV_C0 = 0xc0, 604}; 605 606struct drm_nouveau_private { 607 struct drm_device *dev; 608 609 /* the card type, takes NV_* as values */ 610 enum nouveau_card_type card_type; 611 /* exact chipset, derived from NV_PMC_BOOT_0 */ 612 int chipset; 613 int stepping; 614 int flags; 615 616 void __iomem *mmio; 617 618 spinlock_t ramin_lock; 619 void __iomem *ramin; 620 u32 ramin_size; 621 u32 ramin_base; 622 bool ramin_available; 623 struct drm_mm ramin_heap; 624 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 625 struct list_head gpuobj_list; 626 struct list_head classes; 627 628 struct nouveau_bo *vga_ram; 629 630 /* interrupt handling */ 631 void (*irq_handler[32])(struct drm_device *); 632 bool msi_enabled; 633 634 struct list_head vbl_waiting; 635 636 struct { 637 struct drm_global_reference mem_global_ref; 638 struct ttm_bo_global_ref bo_global_ref; 639 struct ttm_bo_device bdev; 640 atomic_t validate_sequence; 641 } ttm; 642 643 struct { 644 spinlock_t lock; 645 struct drm_mm heap; 646 struct nouveau_bo *bo; 647 } fence; 648 649 struct { 650 spinlock_t lock; 651 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 652 } channels; 653 654 struct nouveau_engine engine; 655 struct nouveau_channel *channel; 656 657 /* For PFIFO and PGRAPH. */ 658 spinlock_t context_switch_lock; 659 660 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 661 spinlock_t vm_lock; 662 663 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 664 struct nouveau_ramht *ramht; 665 struct nouveau_gpuobj *ramfc; 666 struct nouveau_gpuobj *ramro; 667 668 uint32_t ramin_rsvd_vram; 669 670 struct { 671 enum { 672 NOUVEAU_GART_NONE = 0, 673 NOUVEAU_GART_AGP, /* AGP */ 674 NOUVEAU_GART_PDMA, /* paged dma object */ 675 NOUVEAU_GART_HW /* on-chip gart/vm */ 676 } type; 677 uint64_t aper_base; 678 uint64_t aper_size; 679 uint64_t aper_free; 680 681 struct ttm_backend_func *func; 682 683 struct { 684 struct page *page; 685 dma_addr_t addr; 686 } dummy; 687 688 struct nouveau_gpuobj *sg_ctxdma; 689 } gart_info; 690 691 /* nv10-nv40 tiling regions */ 692 struct { 693 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 694 spinlock_t lock; 695 } tile; 696 697 /* VRAM/fb configuration */ 698 uint64_t vram_size; 699 uint64_t vram_sys_base; 700 u32 vram_rblock_size; 701 702 uint64_t fb_phys; 703 uint64_t fb_available_size; 704 uint64_t fb_mappable_pages; 705 uint64_t fb_aper_free; 706 int fb_mtrr; 707 708 /* BAR control (NV50-) */ 709 struct nouveau_vm *bar1_vm; 710 struct nouveau_vm *bar3_vm; 711 712 /* G8x/G9x virtual address space */ 713 struct nouveau_vm *chan_vm; 714 715 struct nvbios vbios; 716 717 struct nv04_mode_state mode_reg; 718 struct nv04_mode_state saved_reg; 719 uint32_t saved_vga_font[4][16384]; 720 uint32_t crtc_owner; 721 uint32_t dac_users[4]; 722 723 struct backlight_device *backlight; 724 725 struct { 726 struct dentry *channel_root; 727 } debugfs; 728 729 struct nouveau_fbdev *nfbdev; 730 struct apertures_struct *apertures; 731}; 732 733static inline struct drm_nouveau_private * 734nouveau_private(struct drm_device *dev) 735{ 736 return dev->dev_private; 737} 738 739static inline struct drm_nouveau_private * 740nouveau_bdev(struct ttm_bo_device *bd) 741{ 742 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 743} 744 745static inline int 746nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 747{ 748 struct nouveau_bo *prev; 749 750 if (!pnvbo) 751 return -EINVAL; 752 prev = *pnvbo; 753 754 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 755 if (prev) { 756 struct ttm_buffer_object *bo = &prev->bo; 757 758 ttm_bo_unref(&bo); 759 } 760 761 return 0; 762} 763 764/* nouveau_drv.c */ 765extern int nouveau_agpmode; 766extern int nouveau_duallink; 767extern int nouveau_uscript_lvds; 768extern int nouveau_uscript_tmds; 769extern int nouveau_vram_pushbuf; 770extern int nouveau_vram_notify; 771extern int nouveau_fbpercrtc; 772extern int nouveau_tv_disable; 773extern char *nouveau_tv_norm; 774extern int nouveau_reg_debug; 775extern char *nouveau_vbios; 776extern int nouveau_ignorelid; 777extern int nouveau_nofbaccel; 778extern int nouveau_noaccel; 779extern int nouveau_force_post; 780extern int nouveau_override_conntype; 781extern char *nouveau_perflvl; 782extern int nouveau_perflvl_wr; 783extern int nouveau_msi; 784 785extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 786extern int nouveau_pci_resume(struct pci_dev *pdev); 787 788/* nouveau_state.c */ 789extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 790extern int nouveau_load(struct drm_device *, unsigned long flags); 791extern int nouveau_firstopen(struct drm_device *); 792extern void nouveau_lastclose(struct drm_device *); 793extern int nouveau_unload(struct drm_device *); 794extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 795 struct drm_file *); 796extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 797 struct drm_file *); 798extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 799 uint32_t reg, uint32_t mask, uint32_t val); 800extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 801 uint32_t reg, uint32_t mask, uint32_t val); 802extern bool nouveau_wait_for_idle(struct drm_device *); 803extern int nouveau_card_init(struct drm_device *); 804 805/* nouveau_mem.c */ 806extern int nouveau_mem_vram_init(struct drm_device *); 807extern void nouveau_mem_vram_fini(struct drm_device *); 808extern int nouveau_mem_gart_init(struct drm_device *); 809extern void nouveau_mem_gart_fini(struct drm_device *); 810extern int nouveau_mem_init_agp(struct drm_device *); 811extern int nouveau_mem_reset_agp(struct drm_device *); 812extern void nouveau_mem_close(struct drm_device *); 813extern int nouveau_mem_detect(struct drm_device *); 814extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 815extern struct nouveau_tile_reg *nv10_mem_set_tiling( 816 struct drm_device *dev, uint32_t addr, uint32_t size, 817 uint32_t pitch, uint32_t flags); 818extern void nv10_mem_put_tile_region(struct drm_device *dev, 819 struct nouveau_tile_reg *tile, 820 struct nouveau_fence *fence); 821extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 822extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 823 824/* nouveau_notifier.c */ 825extern int nouveau_notifier_init_channel(struct nouveau_channel *); 826extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 827extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 828 int cout, uint32_t start, uint32_t end, 829 uint32_t *offset); 830extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 831extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 832 struct drm_file *); 833extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 834 struct drm_file *); 835 836/* nouveau_channel.c */ 837extern struct drm_ioctl_desc nouveau_ioctls[]; 838extern int nouveau_max_ioctl; 839extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 840extern int nouveau_channel_alloc(struct drm_device *dev, 841 struct nouveau_channel **chan, 842 struct drm_file *file_priv, 843 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 844extern struct nouveau_channel * 845nouveau_channel_get_unlocked(struct nouveau_channel *); 846extern struct nouveau_channel * 847nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 848extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 849extern void nouveau_channel_put(struct nouveau_channel **); 850extern void nouveau_channel_ref(struct nouveau_channel *chan, 851 struct nouveau_channel **pchan); 852extern void nouveau_channel_idle(struct nouveau_channel *chan); 853 854/* nouveau_object.c */ 855#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 856 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 857 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 858} while (0) 859 860#define NVOBJ_ENGINE_DEL(d, e) do { \ 861 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 862 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 863} while (0) 864 865#define NVOBJ_CLASS(d, c, e) do { \ 866 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 867 if (ret) \ 868 return ret; \ 869} while (0) 870 871#define NVOBJ_MTHD(d, c, m, e) do { \ 872 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 873 if (ret) \ 874 return ret; \ 875} while (0) 876 877extern int nouveau_gpuobj_early_init(struct drm_device *); 878extern int nouveau_gpuobj_init(struct drm_device *); 879extern void nouveau_gpuobj_takedown(struct drm_device *); 880extern int nouveau_gpuobj_suspend(struct drm_device *dev); 881extern void nouveau_gpuobj_resume(struct drm_device *dev); 882extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 883extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 884 int (*exec)(struct nouveau_channel *, 885 u32 class, u32 mthd, u32 data)); 886extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 887extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 888extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 889 uint32_t vram_h, uint32_t tt_h); 890extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 891extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 892 uint32_t size, int align, uint32_t flags, 893 struct nouveau_gpuobj **); 894extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 895 struct nouveau_gpuobj **); 896extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 897 u32 size, u32 flags, 898 struct nouveau_gpuobj **); 899extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 900 uint64_t offset, uint64_t size, int access, 901 int target, struct nouveau_gpuobj **); 902extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 903extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 904 u64 size, int target, int access, u32 type, 905 u32 comp, struct nouveau_gpuobj **pobj); 906extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 907 int class, u64 base, u64 size, int target, 908 int access, u32 type, u32 comp); 909extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 910 struct drm_file *); 911extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 912 struct drm_file *); 913 914/* nouveau_irq.c */ 915extern int nouveau_irq_init(struct drm_device *); 916extern void nouveau_irq_fini(struct drm_device *); 917extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 918extern void nouveau_irq_register(struct drm_device *, int status_bit, 919 void (*)(struct drm_device *)); 920extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 921extern void nouveau_irq_preinstall(struct drm_device *); 922extern int nouveau_irq_postinstall(struct drm_device *); 923extern void nouveau_irq_uninstall(struct drm_device *); 924 925/* nouveau_sgdma.c */ 926extern int nouveau_sgdma_init(struct drm_device *); 927extern void nouveau_sgdma_takedown(struct drm_device *); 928extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 929 uint32_t offset); 930extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 931 932/* nouveau_debugfs.c */ 933#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 934extern int nouveau_debugfs_init(struct drm_minor *); 935extern void nouveau_debugfs_takedown(struct drm_minor *); 936extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 937extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 938#else 939static inline int 940nouveau_debugfs_init(struct drm_minor *minor) 941{ 942 return 0; 943} 944 945static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 946{ 947} 948 949static inline int 950nouveau_debugfs_channel_init(struct nouveau_channel *chan) 951{ 952 return 0; 953} 954 955static inline void 956nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 957{ 958} 959#endif 960 961/* nouveau_dma.c */ 962extern void nouveau_dma_pre_init(struct nouveau_channel *); 963extern int nouveau_dma_init(struct nouveau_channel *); 964extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 965 966/* nouveau_acpi.c */ 967#define ROM_BIOS_PAGE 4096 968#if defined(CONFIG_ACPI) 969void nouveau_register_dsm_handler(void); 970void nouveau_unregister_dsm_handler(void); 971int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 972bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 973int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 974#else 975static inline void nouveau_register_dsm_handler(void) {} 976static inline void nouveau_unregister_dsm_handler(void) {} 977static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 978static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 979static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 980#endif 981 982/* nouveau_backlight.c */ 983#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 984extern int nouveau_backlight_init(struct drm_connector *); 985extern void nouveau_backlight_exit(struct drm_connector *); 986#else 987static inline int nouveau_backlight_init(struct drm_connector *dev) 988{ 989 return 0; 990} 991 992static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 993#endif 994 995/* nouveau_bios.c */ 996extern int nouveau_bios_init(struct drm_device *); 997extern void nouveau_bios_takedown(struct drm_device *dev); 998extern int nouveau_run_vbios_init(struct drm_device *); 999extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1000 struct dcb_entry *); 1001extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1002 enum dcb_gpio_tag); 1003extern struct dcb_connector_table_entry * 1004nouveau_bios_connector_entry(struct drm_device *, int index); 1005extern u32 get_pll_register(struct drm_device *, enum pll_types); 1006extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1007 struct pll_lims *); 1008extern int nouveau_bios_run_display_table(struct drm_device *, 1009 struct dcb_entry *, 1010 uint32_t script, int pxclk); 1011extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1012 int *length); 1013extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1014extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1015extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1016 bool *dl, bool *if_is_24bit); 1017extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1018 int head, int pxclk); 1019extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1020 enum LVDS_script, int pxclk); 1021 1022/* nouveau_ttm.c */ 1023int nouveau_ttm_global_init(struct drm_nouveau_private *); 1024void nouveau_ttm_global_release(struct drm_nouveau_private *); 1025int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1026 1027/* nouveau_dp.c */ 1028int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1029 uint8_t *data, int data_nr); 1030bool nouveau_dp_detect(struct drm_encoder *); 1031bool nouveau_dp_link_train(struct drm_encoder *); 1032 1033/* nv04_fb.c */ 1034extern int nv04_fb_init(struct drm_device *); 1035extern void nv04_fb_takedown(struct drm_device *); 1036 1037/* nv10_fb.c */ 1038extern int nv10_fb_init(struct drm_device *); 1039extern void nv10_fb_takedown(struct drm_device *); 1040extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1041 uint32_t addr, uint32_t size, 1042 uint32_t pitch, uint32_t flags); 1043extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1044extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1045 1046/* nv30_fb.c */ 1047extern int nv30_fb_init(struct drm_device *); 1048extern void nv30_fb_takedown(struct drm_device *); 1049extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1050 uint32_t addr, uint32_t size, 1051 uint32_t pitch, uint32_t flags); 1052extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1053 1054/* nv40_fb.c */ 1055extern int nv40_fb_init(struct drm_device *); 1056extern void nv40_fb_takedown(struct drm_device *); 1057extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1058 1059/* nv50_fb.c */ 1060extern int nv50_fb_init(struct drm_device *); 1061extern void nv50_fb_takedown(struct drm_device *); 1062extern void nv50_fb_vm_trap(struct drm_device *, int display); 1063 1064/* nvc0_fb.c */ 1065extern int nvc0_fb_init(struct drm_device *); 1066extern void nvc0_fb_takedown(struct drm_device *); 1067 1068/* nv04_fifo.c */ 1069extern int nv04_fifo_init(struct drm_device *); 1070extern void nv04_fifo_fini(struct drm_device *); 1071extern void nv04_fifo_disable(struct drm_device *); 1072extern void nv04_fifo_enable(struct drm_device *); 1073extern bool nv04_fifo_reassign(struct drm_device *, bool); 1074extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1075extern int nv04_fifo_channel_id(struct drm_device *); 1076extern int nv04_fifo_create_context(struct nouveau_channel *); 1077extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1078extern int nv04_fifo_load_context(struct nouveau_channel *); 1079extern int nv04_fifo_unload_context(struct drm_device *); 1080extern void nv04_fifo_isr(struct drm_device *); 1081 1082/* nv10_fifo.c */ 1083extern int nv10_fifo_init(struct drm_device *); 1084extern int nv10_fifo_channel_id(struct drm_device *); 1085extern int nv10_fifo_create_context(struct nouveau_channel *); 1086extern int nv10_fifo_load_context(struct nouveau_channel *); 1087extern int nv10_fifo_unload_context(struct drm_device *); 1088 1089/* nv40_fifo.c */ 1090extern int nv40_fifo_init(struct drm_device *); 1091extern int nv40_fifo_create_context(struct nouveau_channel *); 1092extern int nv40_fifo_load_context(struct nouveau_channel *); 1093extern int nv40_fifo_unload_context(struct drm_device *); 1094 1095/* nv50_fifo.c */ 1096extern int nv50_fifo_init(struct drm_device *); 1097extern void nv50_fifo_takedown(struct drm_device *); 1098extern int nv50_fifo_channel_id(struct drm_device *); 1099extern int nv50_fifo_create_context(struct nouveau_channel *); 1100extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1101extern int nv50_fifo_load_context(struct nouveau_channel *); 1102extern int nv50_fifo_unload_context(struct drm_device *); 1103extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1104 1105/* nvc0_fifo.c */ 1106extern int nvc0_fifo_init(struct drm_device *); 1107extern void nvc0_fifo_takedown(struct drm_device *); 1108extern void nvc0_fifo_disable(struct drm_device *); 1109extern void nvc0_fifo_enable(struct drm_device *); 1110extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1111extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1112extern int nvc0_fifo_channel_id(struct drm_device *); 1113extern int nvc0_fifo_create_context(struct nouveau_channel *); 1114extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1115extern int nvc0_fifo_load_context(struct nouveau_channel *); 1116extern int nvc0_fifo_unload_context(struct drm_device *); 1117 1118/* nv04_graph.c */ 1119extern int nv04_graph_create(struct drm_device *); 1120extern void nv04_graph_fifo_access(struct drm_device *, bool); 1121extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1122extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1123 u32 class, u32 mthd, u32 data); 1124extern struct nouveau_bitfield nv04_graph_nsource[]; 1125 1126/* nv10_graph.c */ 1127extern int nv10_graph_create(struct drm_device *); 1128extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1129extern struct nouveau_bitfield nv10_graph_intr[]; 1130extern struct nouveau_bitfield nv10_graph_nstatus[]; 1131 1132/* nv20_graph.c */ 1133extern int nv20_graph_create(struct drm_device *); 1134 1135/* nv40_graph.c */ 1136extern int nv40_graph_create(struct drm_device *); 1137extern void nv40_grctx_init(struct nouveau_grctx *); 1138 1139/* nv50_graph.c */ 1140extern int nv50_graph_create(struct drm_device *); 1141extern int nv50_grctx_init(struct nouveau_grctx *); 1142extern struct nouveau_enum nv50_data_error_names[]; 1143extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1144 1145/* nvc0_graph.c */ 1146extern int nvc0_graph_create(struct drm_device *); 1147extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1148 1149/* nv84_crypt.c */ 1150extern int nv84_crypt_create(struct drm_device *); 1151 1152/* nva3_copy.c */ 1153extern int nva3_copy_create(struct drm_device *dev); 1154 1155/* nvc0_copy.c */ 1156extern int nvc0_copy_create(struct drm_device *dev, int engine); 1157 1158/* nv40_mpeg.c */ 1159extern int nv40_mpeg_create(struct drm_device *dev); 1160 1161/* nv84_mpeg.c */ 1162extern int nv84_mpeg_create(struct drm_device *dev); 1163 1164/* nv04_instmem.c */ 1165extern int nv04_instmem_init(struct drm_device *); 1166extern void nv04_instmem_takedown(struct drm_device *); 1167extern int nv04_instmem_suspend(struct drm_device *); 1168extern void nv04_instmem_resume(struct drm_device *); 1169extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1170extern void nv04_instmem_put(struct nouveau_gpuobj *); 1171extern int nv04_instmem_map(struct nouveau_gpuobj *); 1172extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1173extern void nv04_instmem_flush(struct drm_device *); 1174 1175/* nv50_instmem.c */ 1176extern int nv50_instmem_init(struct drm_device *); 1177extern void nv50_instmem_takedown(struct drm_device *); 1178extern int nv50_instmem_suspend(struct drm_device *); 1179extern void nv50_instmem_resume(struct drm_device *); 1180extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1181extern void nv50_instmem_put(struct nouveau_gpuobj *); 1182extern int nv50_instmem_map(struct nouveau_gpuobj *); 1183extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1184extern void nv50_instmem_flush(struct drm_device *); 1185extern void nv84_instmem_flush(struct drm_device *); 1186 1187/* nvc0_instmem.c */ 1188extern int nvc0_instmem_init(struct drm_device *); 1189extern void nvc0_instmem_takedown(struct drm_device *); 1190extern int nvc0_instmem_suspend(struct drm_device *); 1191extern void nvc0_instmem_resume(struct drm_device *); 1192 1193/* nv04_mc.c */ 1194extern int nv04_mc_init(struct drm_device *); 1195extern void nv04_mc_takedown(struct drm_device *); 1196 1197/* nv40_mc.c */ 1198extern int nv40_mc_init(struct drm_device *); 1199extern void nv40_mc_takedown(struct drm_device *); 1200 1201/* nv50_mc.c */ 1202extern int nv50_mc_init(struct drm_device *); 1203extern void nv50_mc_takedown(struct drm_device *); 1204 1205/* nv04_timer.c */ 1206extern int nv04_timer_init(struct drm_device *); 1207extern uint64_t nv04_timer_read(struct drm_device *); 1208extern void nv04_timer_takedown(struct drm_device *); 1209 1210extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1211 unsigned long arg); 1212 1213/* nv04_dac.c */ 1214extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1215extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1216extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1217extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1218extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1219 1220/* nv04_dfp.c */ 1221extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1222extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1223extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1224 int head, bool dl); 1225extern void nv04_dfp_disable(struct drm_device *dev, int head); 1226extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1227 1228/* nv04_tv.c */ 1229extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1230extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1231 1232/* nv17_tv.c */ 1233extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1234 1235/* nv04_display.c */ 1236extern int nv04_display_early_init(struct drm_device *); 1237extern void nv04_display_late_takedown(struct drm_device *); 1238extern int nv04_display_create(struct drm_device *); 1239extern int nv04_display_init(struct drm_device *); 1240extern void nv04_display_destroy(struct drm_device *); 1241 1242/* nv04_crtc.c */ 1243extern int nv04_crtc_create(struct drm_device *, int index); 1244 1245/* nouveau_bo.c */ 1246extern struct ttm_bo_driver nouveau_bo_driver; 1247extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1248 int size, int align, uint32_t flags, 1249 uint32_t tile_mode, uint32_t tile_flags, 1250 struct nouveau_bo **); 1251extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1252extern int nouveau_bo_unpin(struct nouveau_bo *); 1253extern int nouveau_bo_map(struct nouveau_bo *); 1254extern void nouveau_bo_unmap(struct nouveau_bo *); 1255extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1256 uint32_t busy); 1257extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1258extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1259extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1260extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1261extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1262extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1263 bool no_wait_reserve, bool no_wait_gpu); 1264 1265/* nouveau_fence.c */ 1266struct nouveau_fence; 1267extern int nouveau_fence_init(struct drm_device *); 1268extern void nouveau_fence_fini(struct drm_device *); 1269extern int nouveau_fence_channel_init(struct nouveau_channel *); 1270extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1271extern void nouveau_fence_update(struct nouveau_channel *); 1272extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1273 bool emit); 1274extern int nouveau_fence_emit(struct nouveau_fence *); 1275extern void nouveau_fence_work(struct nouveau_fence *fence, 1276 void (*work)(void *priv, bool signalled), 1277 void *priv); 1278struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1279 1280extern bool __nouveau_fence_signalled(void *obj, void *arg); 1281extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1282extern int __nouveau_fence_flush(void *obj, void *arg); 1283extern void __nouveau_fence_unref(void **obj); 1284extern void *__nouveau_fence_ref(void *obj); 1285 1286static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1287{ 1288 return __nouveau_fence_signalled(obj, NULL); 1289} 1290static inline int 1291nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1292{ 1293 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1294} 1295extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1296static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1297{ 1298 return __nouveau_fence_flush(obj, NULL); 1299} 1300static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1301{ 1302 __nouveau_fence_unref((void **)obj); 1303} 1304static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1305{ 1306 return __nouveau_fence_ref(obj); 1307} 1308 1309/* nouveau_gem.c */ 1310extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1311 int size, int align, uint32_t domain, 1312 uint32_t tile_mode, uint32_t tile_flags, 1313 struct nouveau_bo **); 1314extern int nouveau_gem_object_new(struct drm_gem_object *); 1315extern void nouveau_gem_object_del(struct drm_gem_object *); 1316extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1317 struct drm_file *); 1318extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1319 struct drm_file *); 1320extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1321 struct drm_file *); 1322extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1323 struct drm_file *); 1324extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1325 struct drm_file *); 1326 1327/* nouveau_display.c */ 1328int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1329void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1330int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1331 struct drm_pending_vblank_event *event); 1332int nouveau_finish_page_flip(struct nouveau_channel *, 1333 struct nouveau_page_flip_state *); 1334 1335/* nv10_gpio.c */ 1336int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1337int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1338 1339/* nv50_gpio.c */ 1340int nv50_gpio_init(struct drm_device *dev); 1341void nv50_gpio_fini(struct drm_device *dev); 1342int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1343int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1344int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1345 void (*)(void *, int), void *); 1346void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1347 void (*)(void *, int), void *); 1348bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1349 1350/* nv50_calc. */ 1351int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1352 int *N1, int *M1, int *N2, int *M2, int *P); 1353int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1354 int clk, int *N, int *fN, int *M, int *P); 1355 1356#ifndef ioread32_native 1357#ifdef __BIG_ENDIAN 1358#define ioread16_native ioread16be 1359#define iowrite16_native iowrite16be 1360#define ioread32_native ioread32be 1361#define iowrite32_native iowrite32be 1362#else /* def __BIG_ENDIAN */ 1363#define ioread16_native ioread16 1364#define iowrite16_native iowrite16 1365#define ioread32_native ioread32 1366#define iowrite32_native iowrite32 1367#endif /* def __BIG_ENDIAN else */ 1368#endif /* !ioread32_native */ 1369 1370/* channel control reg access */ 1371static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1372{ 1373 return ioread32_native(chan->user + reg); 1374} 1375 1376static inline void nvchan_wr32(struct nouveau_channel *chan, 1377 unsigned reg, u32 val) 1378{ 1379 iowrite32_native(val, chan->user + reg); 1380} 1381 1382/* register access */ 1383static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1384{ 1385 struct drm_nouveau_private *dev_priv = dev->dev_private; 1386 return ioread32_native(dev_priv->mmio + reg); 1387} 1388 1389static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1390{ 1391 struct drm_nouveau_private *dev_priv = dev->dev_private; 1392 iowrite32_native(val, dev_priv->mmio + reg); 1393} 1394 1395static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1396{ 1397 u32 tmp = nv_rd32(dev, reg); 1398 nv_wr32(dev, reg, (tmp & ~mask) | val); 1399 return tmp; 1400} 1401 1402static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1403{ 1404 struct drm_nouveau_private *dev_priv = dev->dev_private; 1405 return ioread8(dev_priv->mmio + reg); 1406} 1407 1408static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1409{ 1410 struct drm_nouveau_private *dev_priv = dev->dev_private; 1411 iowrite8(val, dev_priv->mmio + reg); 1412} 1413 1414#define nv_wait(dev, reg, mask, val) \ 1415 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1416#define nv_wait_ne(dev, reg, mask, val) \ 1417 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1418 1419/* PRAMIN access */ 1420static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1421{ 1422 struct drm_nouveau_private *dev_priv = dev->dev_private; 1423 return ioread32_native(dev_priv->ramin + offset); 1424} 1425 1426static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1427{ 1428 struct drm_nouveau_private *dev_priv = dev->dev_private; 1429 iowrite32_native(val, dev_priv->ramin + offset); 1430} 1431 1432/* object access */ 1433extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1434extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1435 1436/* 1437 * Logging 1438 * Argument d is (struct drm_device *). 1439 */ 1440#define NV_PRINTK(level, d, fmt, arg...) \ 1441 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1442 pci_name(d->pdev), ##arg) 1443#ifndef NV_DEBUG_NOTRACE 1444#define NV_DEBUG(d, fmt, arg...) do { \ 1445 if (drm_debug & DRM_UT_DRIVER) { \ 1446 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1447 __LINE__, ##arg); \ 1448 } \ 1449} while (0) 1450#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1451 if (drm_debug & DRM_UT_KMS) { \ 1452 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1453 __LINE__, ##arg); \ 1454 } \ 1455} while (0) 1456#else 1457#define NV_DEBUG(d, fmt, arg...) do { \ 1458 if (drm_debug & DRM_UT_DRIVER) \ 1459 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1460} while (0) 1461#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1462 if (drm_debug & DRM_UT_KMS) \ 1463 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1464} while (0) 1465#endif 1466#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1467#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1468#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1469#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1470#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1471 1472/* nouveau_reg_debug bitmask */ 1473enum { 1474 NOUVEAU_REG_DEBUG_MC = 0x1, 1475 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1476 NOUVEAU_REG_DEBUG_FB = 0x4, 1477 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1478 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1479 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1480 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1481 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1482 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1483 NOUVEAU_REG_DEBUG_EVO = 0x200, 1484}; 1485 1486#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1487 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1488 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1489} while (0) 1490 1491static inline bool 1492nv_two_heads(struct drm_device *dev) 1493{ 1494 struct drm_nouveau_private *dev_priv = dev->dev_private; 1495 const int impl = dev->pci_device & 0x0ff0; 1496 1497 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1498 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1499 return true; 1500 1501 return false; 1502} 1503 1504static inline bool 1505nv_gf4_disp_arch(struct drm_device *dev) 1506{ 1507 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1508} 1509 1510static inline bool 1511nv_two_reg_pll(struct drm_device *dev) 1512{ 1513 struct drm_nouveau_private *dev_priv = dev->dev_private; 1514 const int impl = dev->pci_device & 0x0ff0; 1515 1516 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1517 return true; 1518 return false; 1519} 1520 1521static inline bool 1522nv_match_device(struct drm_device *dev, unsigned device, 1523 unsigned sub_vendor, unsigned sub_device) 1524{ 1525 return dev->pdev->device == device && 1526 dev->pdev->subsystem_vendor == sub_vendor && 1527 dev->pdev->subsystem_device == sub_device; 1528} 1529 1530static inline void * 1531nv_engine(struct drm_device *dev, int engine) 1532{ 1533 struct drm_nouveau_private *dev_priv = dev->dev_private; 1534 return (void *)dev_priv->eng[engine]; 1535} 1536 1537/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1538 * helpful to determine a number of other hardware features 1539 */ 1540static inline int 1541nv44_graph_class(struct drm_device *dev) 1542{ 1543 struct drm_nouveau_private *dev_priv = dev->dev_private; 1544 1545 if ((dev_priv->chipset & 0xf0) == 0x60) 1546 return 1; 1547 1548 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1549} 1550 1551/* memory type/access flags, do not match hardware values */ 1552#define NV_MEM_ACCESS_RO 1 1553#define NV_MEM_ACCESS_WO 2 1554#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1555#define NV_MEM_ACCESS_SYS 4 1556#define NV_MEM_ACCESS_VM 8 1557 1558#define NV_MEM_TARGET_VRAM 0 1559#define NV_MEM_TARGET_PCI 1 1560#define NV_MEM_TARGET_PCI_NOSNOOP 2 1561#define NV_MEM_TARGET_VM 3 1562#define NV_MEM_TARGET_GART 4 1563 1564#define NV_MEM_TYPE_VM 0x7f 1565#define NV_MEM_COMP_VM 0x03 1566 1567/* NV_SW object class */ 1568#define NV_SW 0x0000506e 1569#define NV_SW_DMA_SEMAPHORE 0x00000060 1570#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1571#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1572#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1573#define NV_SW_YIELD 0x00000080 1574#define NV_SW_DMA_VBLSEM 0x0000018c 1575#define NV_SW_VBLSEM_OFFSET 0x00000400 1576#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1577#define NV_SW_VBLSEM_RELEASE 0x00000408 1578#define NV_SW_PAGE_FLIP 0x00000500 1579 1580#endif /* __NOUVEAU_DRV_H__ */ 1581