nouveau_drv.h revision cbab95db84f2a444d99bec77bac8b9b6ef20d11c
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_pull)(struct drm_device *dev, bool enable); 300 301 int (*channel_id)(struct drm_device *); 302 303 int (*create_context)(struct nouveau_channel *); 304 void (*destroy_context)(struct nouveau_channel *); 305 int (*load_context)(struct nouveau_channel *); 306 int (*unload_context)(struct drm_device *); 307}; 308 309struct nouveau_pgraph_object_method { 310 int id; 311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 312 uint32_t data); 313}; 314 315struct nouveau_pgraph_object_class { 316 int id; 317 bool software; 318 struct nouveau_pgraph_object_method *methods; 319}; 320 321struct nouveau_pgraph_engine { 322 struct nouveau_pgraph_object_class *grclass; 323 bool accel_blocked; 324 int grctx_size; 325 326 /* NV2x/NV3x context table (0x400780) */ 327 struct nouveau_gpuobj *ctx_table; 328 329 int (*init)(struct drm_device *); 330 void (*takedown)(struct drm_device *); 331 332 void (*fifo_access)(struct drm_device *, bool); 333 334 struct nouveau_channel *(*channel)(struct drm_device *); 335 int (*create_context)(struct nouveau_channel *); 336 void (*destroy_context)(struct nouveau_channel *); 337 int (*load_context)(struct nouveau_channel *); 338 int (*unload_context)(struct drm_device *); 339 340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 341 uint32_t size, uint32_t pitch); 342}; 343 344struct nouveau_display_engine { 345 int (*early_init)(struct drm_device *); 346 void (*late_takedown)(struct drm_device *); 347 int (*create)(struct drm_device *); 348 int (*init)(struct drm_device *); 349 void (*destroy)(struct drm_device *); 350}; 351 352struct nouveau_gpio_engine { 353 int (*init)(struct drm_device *); 354 void (*takedown)(struct drm_device *); 355 356 int (*get)(struct drm_device *, enum dcb_gpio_tag); 357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 358 359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 360}; 361 362struct nouveau_pm_voltage_level { 363 u8 voltage; 364 u8 vid; 365}; 366 367struct nouveau_pm_voltage { 368 bool supported; 369 u8 vid_mask; 370 371 struct nouveau_pm_voltage_level *level; 372 int nr_level; 373}; 374 375#define NOUVEAU_PM_MAX_LEVEL 8 376struct nouveau_pm_level { 377 struct device_attribute dev_attr; 378 char name[32]; 379 int id; 380 381 u32 core; 382 u32 memory; 383 u32 shader; 384 u32 unk05; 385 386 u8 voltage; 387 u8 fanspeed; 388 389 u16 memscript; 390}; 391 392struct nouveau_pm_temp_sensor_constants { 393 u16 offset_constant; 394 s16 offset_mult; 395 u16 offset_div; 396 u16 slope_mult; 397 u16 slope_div; 398}; 399 400struct nouveau_pm_threshold_temp { 401 s16 critical; 402 s16 down_clock; 403 s16 fan_boost; 404}; 405 406struct nouveau_pm_memtiming { 407 u32 reg_100220; 408 u32 reg_100224; 409 u32 reg_100228; 410 u32 reg_10022c; 411 u32 reg_100230; 412 u32 reg_100234; 413 u32 reg_100238; 414 u32 reg_10023c; 415}; 416 417struct nouveau_pm_memtimings { 418 bool supported; 419 struct nouveau_pm_memtiming *timing; 420 int nr_timing; 421}; 422 423struct nouveau_pm_engine { 424 struct nouveau_pm_voltage voltage; 425 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 426 int nr_perflvl; 427 struct nouveau_pm_memtimings memtimings; 428 struct nouveau_pm_temp_sensor_constants sensor_constants; 429 struct nouveau_pm_threshold_temp threshold_temp; 430 431 struct nouveau_pm_level boot; 432 struct nouveau_pm_level *cur; 433 434 struct device *hwmon; 435 436 int (*clock_get)(struct drm_device *, u32 id); 437 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 438 u32 id, int khz); 439 void (*clock_set)(struct drm_device *, void *); 440 int (*voltage_get)(struct drm_device *); 441 int (*voltage_set)(struct drm_device *, int voltage); 442 int (*fanspeed_get)(struct drm_device *); 443 int (*fanspeed_set)(struct drm_device *, int fanspeed); 444 int (*temp_get)(struct drm_device *); 445}; 446 447struct nouveau_engine { 448 struct nouveau_instmem_engine instmem; 449 struct nouveau_mc_engine mc; 450 struct nouveau_timer_engine timer; 451 struct nouveau_fb_engine fb; 452 struct nouveau_pgraph_engine graph; 453 struct nouveau_fifo_engine fifo; 454 struct nouveau_display_engine display; 455 struct nouveau_gpio_engine gpio; 456 struct nouveau_pm_engine pm; 457}; 458 459struct nouveau_pll_vals { 460 union { 461 struct { 462#ifdef __BIG_ENDIAN 463 uint8_t N1, M1, N2, M2; 464#else 465 uint8_t M1, N1, M2, N2; 466#endif 467 }; 468 struct { 469 uint16_t NM1, NM2; 470 } __attribute__((packed)); 471 }; 472 int log2P; 473 474 int refclk; 475}; 476 477enum nv04_fp_display_regs { 478 FP_DISPLAY_END, 479 FP_TOTAL, 480 FP_CRTC, 481 FP_SYNC_START, 482 FP_SYNC_END, 483 FP_VALID_START, 484 FP_VALID_END 485}; 486 487struct nv04_crtc_reg { 488 unsigned char MiscOutReg; 489 uint8_t CRTC[0xa0]; 490 uint8_t CR58[0x10]; 491 uint8_t Sequencer[5]; 492 uint8_t Graphics[9]; 493 uint8_t Attribute[21]; 494 unsigned char DAC[768]; 495 496 /* PCRTC regs */ 497 uint32_t fb_start; 498 uint32_t crtc_cfg; 499 uint32_t cursor_cfg; 500 uint32_t gpio_ext; 501 uint32_t crtc_830; 502 uint32_t crtc_834; 503 uint32_t crtc_850; 504 uint32_t crtc_eng_ctrl; 505 506 /* PRAMDAC regs */ 507 uint32_t nv10_cursync; 508 struct nouveau_pll_vals pllvals; 509 uint32_t ramdac_gen_ctrl; 510 uint32_t ramdac_630; 511 uint32_t ramdac_634; 512 uint32_t tv_setup; 513 uint32_t tv_vtotal; 514 uint32_t tv_vskew; 515 uint32_t tv_vsync_delay; 516 uint32_t tv_htotal; 517 uint32_t tv_hskew; 518 uint32_t tv_hsync_delay; 519 uint32_t tv_hsync_delay2; 520 uint32_t fp_horiz_regs[7]; 521 uint32_t fp_vert_regs[7]; 522 uint32_t dither; 523 uint32_t fp_control; 524 uint32_t dither_regs[6]; 525 uint32_t fp_debug_0; 526 uint32_t fp_debug_1; 527 uint32_t fp_debug_2; 528 uint32_t fp_margin_color; 529 uint32_t ramdac_8c0; 530 uint32_t ramdac_a20; 531 uint32_t ramdac_a24; 532 uint32_t ramdac_a34; 533 uint32_t ctv_regs[38]; 534}; 535 536struct nv04_output_reg { 537 uint32_t output; 538 int head; 539}; 540 541struct nv04_mode_state { 542 struct nv04_crtc_reg crtc_reg[2]; 543 uint32_t pllsel; 544 uint32_t sel_clk; 545}; 546 547enum nouveau_card_type { 548 NV_04 = 0x00, 549 NV_10 = 0x10, 550 NV_20 = 0x20, 551 NV_30 = 0x30, 552 NV_40 = 0x40, 553 NV_50 = 0x50, 554 NV_C0 = 0xc0, 555}; 556 557struct drm_nouveau_private { 558 struct drm_device *dev; 559 560 /* the card type, takes NV_* as values */ 561 enum nouveau_card_type card_type; 562 /* exact chipset, derived from NV_PMC_BOOT_0 */ 563 int chipset; 564 int flags; 565 566 void __iomem *mmio; 567 568 spinlock_t ramin_lock; 569 void __iomem *ramin; 570 u32 ramin_size; 571 u32 ramin_base; 572 bool ramin_available; 573 struct drm_mm ramin_heap; 574 struct list_head gpuobj_list; 575 576 struct nouveau_bo *vga_ram; 577 578 struct workqueue_struct *wq; 579 struct work_struct irq_work; 580 struct work_struct hpd_work; 581 582 struct list_head vbl_waiting; 583 584 struct { 585 struct drm_global_reference mem_global_ref; 586 struct ttm_bo_global_ref bo_global_ref; 587 struct ttm_bo_device bdev; 588 atomic_t validate_sequence; 589 } ttm; 590 591 struct { 592 spinlock_t lock; 593 struct drm_mm heap; 594 struct nouveau_bo *bo; 595 } fence; 596 597 int fifo_alloc_count; 598 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 599 600 struct nouveau_engine engine; 601 struct nouveau_channel *channel; 602 603 /* For PFIFO and PGRAPH. */ 604 spinlock_t context_switch_lock; 605 606 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 607 struct nouveau_ramht *ramht; 608 struct nouveau_gpuobj *ramfc; 609 struct nouveau_gpuobj *ramro; 610 611 uint32_t ramin_rsvd_vram; 612 613 struct { 614 enum { 615 NOUVEAU_GART_NONE = 0, 616 NOUVEAU_GART_AGP, 617 NOUVEAU_GART_SGDMA 618 } type; 619 uint64_t aper_base; 620 uint64_t aper_size; 621 uint64_t aper_free; 622 623 struct nouveau_gpuobj *sg_ctxdma; 624 struct page *sg_dummy_page; 625 dma_addr_t sg_dummy_bus; 626 } gart_info; 627 628 /* nv10-nv40 tiling regions */ 629 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 630 631 /* VRAM/fb configuration */ 632 uint64_t vram_size; 633 uint64_t vram_sys_base; 634 u32 vram_rblock_size; 635 636 uint64_t fb_phys; 637 uint64_t fb_available_size; 638 uint64_t fb_mappable_pages; 639 uint64_t fb_aper_free; 640 int fb_mtrr; 641 642 /* G8x/G9x virtual address space */ 643 uint64_t vm_gart_base; 644 uint64_t vm_gart_size; 645 uint64_t vm_vram_base; 646 uint64_t vm_vram_size; 647 uint64_t vm_end; 648 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 649 int vm_vram_pt_nr; 650 651 struct nvbios vbios; 652 653 struct nv04_mode_state mode_reg; 654 struct nv04_mode_state saved_reg; 655 uint32_t saved_vga_font[4][16384]; 656 uint32_t crtc_owner; 657 uint32_t dac_users[4]; 658 659 struct nouveau_suspend_resume { 660 uint32_t *ramin_copy; 661 } susres; 662 663 struct backlight_device *backlight; 664 665 struct nouveau_channel *evo; 666 struct { 667 struct dcb_entry *dcb; 668 u16 script; 669 u32 pclk; 670 } evo_irq; 671 672 struct { 673 struct dentry *channel_root; 674 } debugfs; 675 676 struct nouveau_fbdev *nfbdev; 677 struct apertures_struct *apertures; 678}; 679 680static inline struct drm_nouveau_private * 681nouveau_private(struct drm_device *dev) 682{ 683 return dev->dev_private; 684} 685 686static inline struct drm_nouveau_private * 687nouveau_bdev(struct ttm_bo_device *bd) 688{ 689 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 690} 691 692static inline int 693nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 694{ 695 struct nouveau_bo *prev; 696 697 if (!pnvbo) 698 return -EINVAL; 699 prev = *pnvbo; 700 701 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 702 if (prev) { 703 struct ttm_buffer_object *bo = &prev->bo; 704 705 ttm_bo_unref(&bo); 706 } 707 708 return 0; 709} 710 711#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 712 struct drm_nouveau_private *nv = dev->dev_private; \ 713 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 714 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 715 DRM_CURRENTPID, (id)); \ 716 return -EPERM; \ 717 } \ 718 (ch) = nv->fifos[(id)]; \ 719} while (0) 720 721/* nouveau_drv.c */ 722extern int nouveau_agpmode; 723extern int nouveau_duallink; 724extern int nouveau_uscript_lvds; 725extern int nouveau_uscript_tmds; 726extern int nouveau_vram_pushbuf; 727extern int nouveau_vram_notify; 728extern int nouveau_fbpercrtc; 729extern int nouveau_tv_disable; 730extern char *nouveau_tv_norm; 731extern int nouveau_reg_debug; 732extern char *nouveau_vbios; 733extern int nouveau_ignorelid; 734extern int nouveau_nofbaccel; 735extern int nouveau_noaccel; 736extern int nouveau_force_post; 737extern int nouveau_override_conntype; 738extern char *nouveau_perflvl; 739extern int nouveau_perflvl_wr; 740 741extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 742extern int nouveau_pci_resume(struct pci_dev *pdev); 743 744/* nouveau_state.c */ 745extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 746extern int nouveau_load(struct drm_device *, unsigned long flags); 747extern int nouveau_firstopen(struct drm_device *); 748extern void nouveau_lastclose(struct drm_device *); 749extern int nouveau_unload(struct drm_device *); 750extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 751 struct drm_file *); 752extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 753 struct drm_file *); 754extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 755 uint32_t reg, uint32_t mask, uint32_t val); 756extern bool nouveau_wait_for_idle(struct drm_device *); 757extern int nouveau_card_init(struct drm_device *); 758 759/* nouveau_mem.c */ 760extern int nouveau_mem_vram_init(struct drm_device *); 761extern void nouveau_mem_vram_fini(struct drm_device *); 762extern int nouveau_mem_gart_init(struct drm_device *); 763extern void nouveau_mem_gart_fini(struct drm_device *); 764extern int nouveau_mem_init_agp(struct drm_device *); 765extern int nouveau_mem_reset_agp(struct drm_device *); 766extern void nouveau_mem_close(struct drm_device *); 767extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 768 uint32_t addr, 769 uint32_t size, 770 uint32_t pitch); 771extern void nv10_mem_expire_tiling(struct drm_device *dev, 772 struct nouveau_tile_reg *tile, 773 struct nouveau_fence *fence); 774extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 775 uint32_t size, uint32_t flags, 776 uint64_t phys); 777extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 778 uint32_t size); 779 780/* nouveau_notifier.c */ 781extern int nouveau_notifier_init_channel(struct nouveau_channel *); 782extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 783extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 784 int cout, uint32_t *offset); 785extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 786extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 787 struct drm_file *); 788extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 789 struct drm_file *); 790 791/* nouveau_channel.c */ 792extern struct drm_ioctl_desc nouveau_ioctls[]; 793extern int nouveau_max_ioctl; 794extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 795extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 796 int channel); 797extern int nouveau_channel_alloc(struct drm_device *dev, 798 struct nouveau_channel **chan, 799 struct drm_file *file_priv, 800 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 801extern void nouveau_channel_free(struct nouveau_channel *); 802 803/* nouveau_object.c */ 804extern int nouveau_gpuobj_early_init(struct drm_device *); 805extern int nouveau_gpuobj_init(struct drm_device *); 806extern void nouveau_gpuobj_takedown(struct drm_device *); 807extern int nouveau_gpuobj_suspend(struct drm_device *dev); 808extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 809extern void nouveau_gpuobj_resume(struct drm_device *dev); 810extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 811 uint32_t vram_h, uint32_t tt_h); 812extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 813extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 814 uint32_t size, int align, uint32_t flags, 815 struct nouveau_gpuobj **); 816extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 817 struct nouveau_gpuobj **); 818extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 819 u32 size, u32 flags, 820 struct nouveau_gpuobj **); 821extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 822 uint64_t offset, uint64_t size, int access, 823 int target, struct nouveau_gpuobj **); 824extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 825 uint64_t offset, uint64_t size, 826 int access, struct nouveau_gpuobj **, 827 uint32_t *o_ret); 828extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 829 struct nouveau_gpuobj **); 830extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 831 struct nouveau_gpuobj **); 832extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 833 struct drm_file *); 834extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 835 struct drm_file *); 836 837/* nouveau_irq.c */ 838extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 839extern void nouveau_irq_preinstall(struct drm_device *); 840extern int nouveau_irq_postinstall(struct drm_device *); 841extern void nouveau_irq_uninstall(struct drm_device *); 842 843/* nouveau_sgdma.c */ 844extern int nouveau_sgdma_init(struct drm_device *); 845extern void nouveau_sgdma_takedown(struct drm_device *); 846extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 847 uint32_t *page); 848extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 849 850/* nouveau_debugfs.c */ 851#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 852extern int nouveau_debugfs_init(struct drm_minor *); 853extern void nouveau_debugfs_takedown(struct drm_minor *); 854extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 855extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 856#else 857static inline int 858nouveau_debugfs_init(struct drm_minor *minor) 859{ 860 return 0; 861} 862 863static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 864{ 865} 866 867static inline int 868nouveau_debugfs_channel_init(struct nouveau_channel *chan) 869{ 870 return 0; 871} 872 873static inline void 874nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 875{ 876} 877#endif 878 879/* nouveau_dma.c */ 880extern void nouveau_dma_pre_init(struct nouveau_channel *); 881extern int nouveau_dma_init(struct nouveau_channel *); 882extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 883 884/* nouveau_acpi.c */ 885#define ROM_BIOS_PAGE 4096 886#if defined(CONFIG_ACPI) 887void nouveau_register_dsm_handler(void); 888void nouveau_unregister_dsm_handler(void); 889int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 890bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 891int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 892#else 893static inline void nouveau_register_dsm_handler(void) {} 894static inline void nouveau_unregister_dsm_handler(void) {} 895static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 896static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 897static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 898#endif 899 900/* nouveau_backlight.c */ 901#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 902extern int nouveau_backlight_init(struct drm_device *); 903extern void nouveau_backlight_exit(struct drm_device *); 904#else 905static inline int nouveau_backlight_init(struct drm_device *dev) 906{ 907 return 0; 908} 909 910static inline void nouveau_backlight_exit(struct drm_device *dev) { } 911#endif 912 913/* nouveau_bios.c */ 914extern int nouveau_bios_init(struct drm_device *); 915extern void nouveau_bios_takedown(struct drm_device *dev); 916extern int nouveau_run_vbios_init(struct drm_device *); 917extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 918 struct dcb_entry *); 919extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 920 enum dcb_gpio_tag); 921extern struct dcb_connector_table_entry * 922nouveau_bios_connector_entry(struct drm_device *, int index); 923extern u32 get_pll_register(struct drm_device *, enum pll_types); 924extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 925 struct pll_lims *); 926extern int nouveau_bios_run_display_table(struct drm_device *, 927 struct dcb_entry *, 928 uint32_t script, int pxclk); 929extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 930 int *length); 931extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 932extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 933extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 934 bool *dl, bool *if_is_24bit); 935extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 936 int head, int pxclk); 937extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 938 enum LVDS_script, int pxclk); 939 940/* nouveau_ttm.c */ 941int nouveau_ttm_global_init(struct drm_nouveau_private *); 942void nouveau_ttm_global_release(struct drm_nouveau_private *); 943int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 944 945/* nouveau_dp.c */ 946int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 947 uint8_t *data, int data_nr); 948bool nouveau_dp_detect(struct drm_encoder *); 949bool nouveau_dp_link_train(struct drm_encoder *); 950 951/* nv04_fb.c */ 952extern int nv04_fb_init(struct drm_device *); 953extern void nv04_fb_takedown(struct drm_device *); 954 955/* nv10_fb.c */ 956extern int nv10_fb_init(struct drm_device *); 957extern void nv10_fb_takedown(struct drm_device *); 958extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 959 uint32_t, uint32_t); 960 961/* nv30_fb.c */ 962extern int nv30_fb_init(struct drm_device *); 963extern void nv30_fb_takedown(struct drm_device *); 964 965/* nv40_fb.c */ 966extern int nv40_fb_init(struct drm_device *); 967extern void nv40_fb_takedown(struct drm_device *); 968extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 969 uint32_t, uint32_t); 970/* nv50_fb.c */ 971extern int nv50_fb_init(struct drm_device *); 972extern void nv50_fb_takedown(struct drm_device *); 973extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 974 975/* nvc0_fb.c */ 976extern int nvc0_fb_init(struct drm_device *); 977extern void nvc0_fb_takedown(struct drm_device *); 978 979/* nv04_fifo.c */ 980extern int nv04_fifo_init(struct drm_device *); 981extern void nv04_fifo_disable(struct drm_device *); 982extern void nv04_fifo_enable(struct drm_device *); 983extern bool nv04_fifo_reassign(struct drm_device *, bool); 984extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 985extern int nv04_fifo_channel_id(struct drm_device *); 986extern int nv04_fifo_create_context(struct nouveau_channel *); 987extern void nv04_fifo_destroy_context(struct nouveau_channel *); 988extern int nv04_fifo_load_context(struct nouveau_channel *); 989extern int nv04_fifo_unload_context(struct drm_device *); 990 991/* nv10_fifo.c */ 992extern int nv10_fifo_init(struct drm_device *); 993extern int nv10_fifo_channel_id(struct drm_device *); 994extern int nv10_fifo_create_context(struct nouveau_channel *); 995extern void nv10_fifo_destroy_context(struct nouveau_channel *); 996extern int nv10_fifo_load_context(struct nouveau_channel *); 997extern int nv10_fifo_unload_context(struct drm_device *); 998 999/* nv40_fifo.c */ 1000extern int nv40_fifo_init(struct drm_device *); 1001extern int nv40_fifo_create_context(struct nouveau_channel *); 1002extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1003extern int nv40_fifo_load_context(struct nouveau_channel *); 1004extern int nv40_fifo_unload_context(struct drm_device *); 1005 1006/* nv50_fifo.c */ 1007extern int nv50_fifo_init(struct drm_device *); 1008extern void nv50_fifo_takedown(struct drm_device *); 1009extern int nv50_fifo_channel_id(struct drm_device *); 1010extern int nv50_fifo_create_context(struct nouveau_channel *); 1011extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1012extern int nv50_fifo_load_context(struct nouveau_channel *); 1013extern int nv50_fifo_unload_context(struct drm_device *); 1014 1015/* nvc0_fifo.c */ 1016extern int nvc0_fifo_init(struct drm_device *); 1017extern void nvc0_fifo_takedown(struct drm_device *); 1018extern void nvc0_fifo_disable(struct drm_device *); 1019extern void nvc0_fifo_enable(struct drm_device *); 1020extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1021extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1022extern int nvc0_fifo_channel_id(struct drm_device *); 1023extern int nvc0_fifo_create_context(struct nouveau_channel *); 1024extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1025extern int nvc0_fifo_load_context(struct nouveau_channel *); 1026extern int nvc0_fifo_unload_context(struct drm_device *); 1027 1028/* nv04_graph.c */ 1029extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1030extern int nv04_graph_init(struct drm_device *); 1031extern void nv04_graph_takedown(struct drm_device *); 1032extern void nv04_graph_fifo_access(struct drm_device *, bool); 1033extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1034extern int nv04_graph_create_context(struct nouveau_channel *); 1035extern void nv04_graph_destroy_context(struct nouveau_channel *); 1036extern int nv04_graph_load_context(struct nouveau_channel *); 1037extern int nv04_graph_unload_context(struct drm_device *); 1038extern void nv04_graph_context_switch(struct drm_device *); 1039 1040/* nv10_graph.c */ 1041extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1042extern int nv10_graph_init(struct drm_device *); 1043extern void nv10_graph_takedown(struct drm_device *); 1044extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1045extern int nv10_graph_create_context(struct nouveau_channel *); 1046extern void nv10_graph_destroy_context(struct nouveau_channel *); 1047extern int nv10_graph_load_context(struct nouveau_channel *); 1048extern int nv10_graph_unload_context(struct drm_device *); 1049extern void nv10_graph_context_switch(struct drm_device *); 1050extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1051 uint32_t, uint32_t); 1052 1053/* nv20_graph.c */ 1054extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1055extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1056extern int nv20_graph_create_context(struct nouveau_channel *); 1057extern void nv20_graph_destroy_context(struct nouveau_channel *); 1058extern int nv20_graph_load_context(struct nouveau_channel *); 1059extern int nv20_graph_unload_context(struct drm_device *); 1060extern int nv20_graph_init(struct drm_device *); 1061extern void nv20_graph_takedown(struct drm_device *); 1062extern int nv30_graph_init(struct drm_device *); 1063extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1064 uint32_t, uint32_t); 1065 1066/* nv40_graph.c */ 1067extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1068extern int nv40_graph_init(struct drm_device *); 1069extern void nv40_graph_takedown(struct drm_device *); 1070extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1071extern int nv40_graph_create_context(struct nouveau_channel *); 1072extern void nv40_graph_destroy_context(struct nouveau_channel *); 1073extern int nv40_graph_load_context(struct nouveau_channel *); 1074extern int nv40_graph_unload_context(struct drm_device *); 1075extern void nv40_grctx_init(struct nouveau_grctx *); 1076extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1077 uint32_t, uint32_t); 1078 1079/* nv50_graph.c */ 1080extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1081extern int nv50_graph_init(struct drm_device *); 1082extern void nv50_graph_takedown(struct drm_device *); 1083extern void nv50_graph_fifo_access(struct drm_device *, bool); 1084extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1085extern int nv50_graph_create_context(struct nouveau_channel *); 1086extern void nv50_graph_destroy_context(struct nouveau_channel *); 1087extern int nv50_graph_load_context(struct nouveau_channel *); 1088extern int nv50_graph_unload_context(struct drm_device *); 1089extern void nv50_graph_context_switch(struct drm_device *); 1090extern int nv50_grctx_init(struct nouveau_grctx *); 1091 1092/* nvc0_graph.c */ 1093extern int nvc0_graph_init(struct drm_device *); 1094extern void nvc0_graph_takedown(struct drm_device *); 1095extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1096extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1097extern int nvc0_graph_create_context(struct nouveau_channel *); 1098extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1099extern int nvc0_graph_load_context(struct nouveau_channel *); 1100extern int nvc0_graph_unload_context(struct drm_device *); 1101 1102/* nv04_instmem.c */ 1103extern int nv04_instmem_init(struct drm_device *); 1104extern void nv04_instmem_takedown(struct drm_device *); 1105extern int nv04_instmem_suspend(struct drm_device *); 1106extern void nv04_instmem_resume(struct drm_device *); 1107extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1108 uint32_t *size); 1109extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1110extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1111extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1112extern void nv04_instmem_flush(struct drm_device *); 1113 1114/* nv50_instmem.c */ 1115extern int nv50_instmem_init(struct drm_device *); 1116extern void nv50_instmem_takedown(struct drm_device *); 1117extern int nv50_instmem_suspend(struct drm_device *); 1118extern void nv50_instmem_resume(struct drm_device *); 1119extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1120 uint32_t *size); 1121extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1122extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1123extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1124extern void nv50_instmem_flush(struct drm_device *); 1125extern void nv84_instmem_flush(struct drm_device *); 1126extern void nv50_vm_flush(struct drm_device *, int engine); 1127 1128/* nvc0_instmem.c */ 1129extern int nvc0_instmem_init(struct drm_device *); 1130extern void nvc0_instmem_takedown(struct drm_device *); 1131extern int nvc0_instmem_suspend(struct drm_device *); 1132extern void nvc0_instmem_resume(struct drm_device *); 1133extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1134 uint32_t *size); 1135extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1136extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1137extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1138extern void nvc0_instmem_flush(struct drm_device *); 1139 1140/* nv04_mc.c */ 1141extern int nv04_mc_init(struct drm_device *); 1142extern void nv04_mc_takedown(struct drm_device *); 1143 1144/* nv40_mc.c */ 1145extern int nv40_mc_init(struct drm_device *); 1146extern void nv40_mc_takedown(struct drm_device *); 1147 1148/* nv50_mc.c */ 1149extern int nv50_mc_init(struct drm_device *); 1150extern void nv50_mc_takedown(struct drm_device *); 1151 1152/* nv04_timer.c */ 1153extern int nv04_timer_init(struct drm_device *); 1154extern uint64_t nv04_timer_read(struct drm_device *); 1155extern void nv04_timer_takedown(struct drm_device *); 1156 1157extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1158 unsigned long arg); 1159 1160/* nv04_dac.c */ 1161extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1162extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1163extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1164extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1165extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1166 1167/* nv04_dfp.c */ 1168extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1169extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1170extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1171 int head, bool dl); 1172extern void nv04_dfp_disable(struct drm_device *dev, int head); 1173extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1174 1175/* nv04_tv.c */ 1176extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1177extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1178 1179/* nv17_tv.c */ 1180extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1181 1182/* nv04_display.c */ 1183extern int nv04_display_early_init(struct drm_device *); 1184extern void nv04_display_late_takedown(struct drm_device *); 1185extern int nv04_display_create(struct drm_device *); 1186extern int nv04_display_init(struct drm_device *); 1187extern void nv04_display_destroy(struct drm_device *); 1188 1189/* nv04_crtc.c */ 1190extern int nv04_crtc_create(struct drm_device *, int index); 1191 1192/* nouveau_bo.c */ 1193extern struct ttm_bo_driver nouveau_bo_driver; 1194extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1195 int size, int align, uint32_t flags, 1196 uint32_t tile_mode, uint32_t tile_flags, 1197 bool no_vm, bool mappable, struct nouveau_bo **); 1198extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1199extern int nouveau_bo_unpin(struct nouveau_bo *); 1200extern int nouveau_bo_map(struct nouveau_bo *); 1201extern void nouveau_bo_unmap(struct nouveau_bo *); 1202extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1203 uint32_t busy); 1204extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1205extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1206extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1207extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1208 1209/* nouveau_fence.c */ 1210struct nouveau_fence; 1211extern int nouveau_fence_init(struct drm_device *); 1212extern void nouveau_fence_fini(struct drm_device *); 1213extern int nouveau_fence_channel_init(struct nouveau_channel *); 1214extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1215extern void nouveau_fence_update(struct nouveau_channel *); 1216extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1217 bool emit); 1218extern int nouveau_fence_emit(struct nouveau_fence *); 1219extern void nouveau_fence_work(struct nouveau_fence *fence, 1220 void (*work)(void *priv, bool signalled), 1221 void *priv); 1222struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1223extern bool nouveau_fence_signalled(void *obj, void *arg); 1224extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1225extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1226extern int nouveau_fence_flush(void *obj, void *arg); 1227extern void nouveau_fence_unref(void **obj); 1228extern void *nouveau_fence_ref(void *obj); 1229 1230/* nouveau_gem.c */ 1231extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1232 int size, int align, uint32_t flags, 1233 uint32_t tile_mode, uint32_t tile_flags, 1234 bool no_vm, bool mappable, struct nouveau_bo **); 1235extern int nouveau_gem_object_new(struct drm_gem_object *); 1236extern void nouveau_gem_object_del(struct drm_gem_object *); 1237extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1238 struct drm_file *); 1239extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1240 struct drm_file *); 1241extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1242 struct drm_file *); 1243extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1244 struct drm_file *); 1245extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1246 struct drm_file *); 1247 1248/* nv10_gpio.c */ 1249int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1250int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1251 1252/* nv50_gpio.c */ 1253int nv50_gpio_init(struct drm_device *dev); 1254int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1255int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1256void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1257 1258/* nv50_calc. */ 1259int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1260 int *N1, int *M1, int *N2, int *M2, int *P); 1261int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1262 int clk, int *N, int *fN, int *M, int *P); 1263 1264#ifndef ioread32_native 1265#ifdef __BIG_ENDIAN 1266#define ioread16_native ioread16be 1267#define iowrite16_native iowrite16be 1268#define ioread32_native ioread32be 1269#define iowrite32_native iowrite32be 1270#else /* def __BIG_ENDIAN */ 1271#define ioread16_native ioread16 1272#define iowrite16_native iowrite16 1273#define ioread32_native ioread32 1274#define iowrite32_native iowrite32 1275#endif /* def __BIG_ENDIAN else */ 1276#endif /* !ioread32_native */ 1277 1278/* channel control reg access */ 1279static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1280{ 1281 return ioread32_native(chan->user + reg); 1282} 1283 1284static inline void nvchan_wr32(struct nouveau_channel *chan, 1285 unsigned reg, u32 val) 1286{ 1287 iowrite32_native(val, chan->user + reg); 1288} 1289 1290/* register access */ 1291static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1292{ 1293 struct drm_nouveau_private *dev_priv = dev->dev_private; 1294 return ioread32_native(dev_priv->mmio + reg); 1295} 1296 1297static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1298{ 1299 struct drm_nouveau_private *dev_priv = dev->dev_private; 1300 iowrite32_native(val, dev_priv->mmio + reg); 1301} 1302 1303static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1304{ 1305 u32 tmp = nv_rd32(dev, reg); 1306 nv_wr32(dev, reg, (tmp & ~mask) | val); 1307 return tmp; 1308} 1309 1310static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1311{ 1312 struct drm_nouveau_private *dev_priv = dev->dev_private; 1313 return ioread8(dev_priv->mmio + reg); 1314} 1315 1316static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1317{ 1318 struct drm_nouveau_private *dev_priv = dev->dev_private; 1319 iowrite8(val, dev_priv->mmio + reg); 1320} 1321 1322#define nv_wait(dev, reg, mask, val) \ 1323 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1324 1325/* PRAMIN access */ 1326static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1327{ 1328 struct drm_nouveau_private *dev_priv = dev->dev_private; 1329 return ioread32_native(dev_priv->ramin + offset); 1330} 1331 1332static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1333{ 1334 struct drm_nouveau_private *dev_priv = dev->dev_private; 1335 iowrite32_native(val, dev_priv->ramin + offset); 1336} 1337 1338/* object access */ 1339extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1340extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1341 1342/* 1343 * Logging 1344 * Argument d is (struct drm_device *). 1345 */ 1346#define NV_PRINTK(level, d, fmt, arg...) \ 1347 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1348 pci_name(d->pdev), ##arg) 1349#ifndef NV_DEBUG_NOTRACE 1350#define NV_DEBUG(d, fmt, arg...) do { \ 1351 if (drm_debug & DRM_UT_DRIVER) { \ 1352 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1353 __LINE__, ##arg); \ 1354 } \ 1355} while (0) 1356#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1357 if (drm_debug & DRM_UT_KMS) { \ 1358 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1359 __LINE__, ##arg); \ 1360 } \ 1361} while (0) 1362#else 1363#define NV_DEBUG(d, fmt, arg...) do { \ 1364 if (drm_debug & DRM_UT_DRIVER) \ 1365 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1366} while (0) 1367#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1368 if (drm_debug & DRM_UT_KMS) \ 1369 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1370} while (0) 1371#endif 1372#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1373#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1374#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1375#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1376#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1377 1378/* nouveau_reg_debug bitmask */ 1379enum { 1380 NOUVEAU_REG_DEBUG_MC = 0x1, 1381 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1382 NOUVEAU_REG_DEBUG_FB = 0x4, 1383 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1384 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1385 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1386 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1387 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1388 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1389 NOUVEAU_REG_DEBUG_EVO = 0x200, 1390}; 1391 1392#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1393 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1394 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1395} while (0) 1396 1397static inline bool 1398nv_two_heads(struct drm_device *dev) 1399{ 1400 struct drm_nouveau_private *dev_priv = dev->dev_private; 1401 const int impl = dev->pci_device & 0x0ff0; 1402 1403 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1404 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1405 return true; 1406 1407 return false; 1408} 1409 1410static inline bool 1411nv_gf4_disp_arch(struct drm_device *dev) 1412{ 1413 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1414} 1415 1416static inline bool 1417nv_two_reg_pll(struct drm_device *dev) 1418{ 1419 struct drm_nouveau_private *dev_priv = dev->dev_private; 1420 const int impl = dev->pci_device & 0x0ff0; 1421 1422 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1423 return true; 1424 return false; 1425} 1426 1427static inline bool 1428nv_match_device(struct drm_device *dev, unsigned device, 1429 unsigned sub_vendor, unsigned sub_device) 1430{ 1431 return dev->pdev->device == device && 1432 dev->pdev->subsystem_vendor == sub_vendor && 1433 dev->pdev->subsystem_device == sub_device; 1434} 1435 1436#define NV_SW 0x0000506e 1437#define NV_SW_DMA_SEMAPHORE 0x00000060 1438#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1439#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1440#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1441#define NV_SW_YIELD 0x00000080 1442#define NV_SW_DMA_VBLSEM 0x0000018c 1443#define NV_SW_VBLSEM_OFFSET 0x00000400 1444#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1445#define NV_SW_VBLSEM_RELEASE 0x00000408 1446 1447#endif /* __NOUVEAU_DRV_H__ */ 1448