nouveau_drv.h revision ce163f6967121d77e3983aa06d416afacf3070c2
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 struct list_head vma_list; 120 unsigned page_shift; 121 122 uint32_t tile_mode; 123 uint32_t tile_flags; 124 struct nouveau_tile_reg *tile; 125 126 struct drm_gem_object *gem; 127 int pin_refcnt; 128}; 129 130#define nouveau_bo_tile_layout(nvbo) \ 131 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 132 133static inline struct nouveau_bo * 134nouveau_bo(struct ttm_buffer_object *bo) 135{ 136 return container_of(bo, struct nouveau_bo, bo); 137} 138 139static inline struct nouveau_bo * 140nouveau_gem_object(struct drm_gem_object *gem) 141{ 142 return gem ? gem->driver_private : NULL; 143} 144 145/* TODO: submit equivalent to TTM generic API upstream? */ 146static inline void __iomem * 147nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 148{ 149 bool is_iomem; 150 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 151 &nvbo->kmap, &is_iomem); 152 WARN_ON_ONCE(ioptr && !is_iomem); 153 return ioptr; 154} 155 156enum nouveau_flags { 157 NV_NFORCE = 0x10000000, 158 NV_NFORCE2 = 0x20000000 159}; 160 161#define NVOBJ_ENGINE_SW 0 162#define NVOBJ_ENGINE_GR 1 163#define NVOBJ_ENGINE_CRYPT 2 164#define NVOBJ_ENGINE_COPY0 3 165#define NVOBJ_ENGINE_COPY1 4 166#define NVOBJ_ENGINE_MPEG 5 167#define NVOBJ_ENGINE_DISPLAY 15 168#define NVOBJ_ENGINE_NR 16 169 170#define NVOBJ_FLAG_DONT_MAP (1 << 0) 171#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 172#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 173#define NVOBJ_FLAG_VM (1 << 3) 174#define NVOBJ_FLAG_VM_USER (1 << 4) 175 176#define NVOBJ_CINST_GLOBAL 0xdeadbeef 177 178struct nouveau_gpuobj { 179 struct drm_device *dev; 180 struct kref refcount; 181 struct list_head list; 182 183 void *node; 184 u32 *suspend; 185 186 uint32_t flags; 187 188 u32 size; 189 u32 pinst; /* PRAMIN BAR offset */ 190 u32 cinst; /* Channel offset */ 191 u64 vinst; /* VRAM address */ 192 u64 linst; /* VM address */ 193 194 uint32_t engine; 195 uint32_t class; 196 197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 198 void *priv; 199}; 200 201struct nouveau_page_flip_state { 202 struct list_head head; 203 struct drm_pending_vblank_event *event; 204 int crtc, bpp, pitch, x, y; 205 uint64_t offset; 206}; 207 208enum nouveau_channel_mutex_class { 209 NOUVEAU_UCHANNEL_MUTEX, 210 NOUVEAU_KCHANNEL_MUTEX 211}; 212 213struct nouveau_channel { 214 struct drm_device *dev; 215 struct list_head list; 216 int id; 217 218 /* references to the channel data structure */ 219 struct kref ref; 220 /* users of the hardware channel resources, the hardware 221 * context will be kicked off when it reaches zero. */ 222 atomic_t users; 223 struct mutex mutex; 224 225 /* owner of this fifo */ 226 struct drm_file *file_priv; 227 /* mapping of the fifo itself */ 228 struct drm_local_map *map; 229 230 /* mapping of the regs controlling the fifo */ 231 void __iomem *user; 232 uint32_t user_get; 233 uint32_t user_put; 234 235 /* Fencing */ 236 struct { 237 /* lock protects the pending list only */ 238 spinlock_t lock; 239 struct list_head pending; 240 uint32_t sequence; 241 uint32_t sequence_ack; 242 atomic_t last_sequence_irq; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct { 296 struct nouveau_gpuobj *vblsem; 297 uint32_t vblsem_head; 298 uint32_t vblsem_offset; 299 uint32_t vblsem_rval; 300 struct list_head vbl_wait; 301 struct list_head flip; 302 } nvsw; 303 304 struct { 305 bool active; 306 char name[32]; 307 struct drm_info_list info; 308 } debugfs; 309}; 310 311struct nouveau_exec_engine { 312 void (*destroy)(struct drm_device *, int engine); 313 int (*init)(struct drm_device *, int engine); 314 int (*fini)(struct drm_device *, int engine); 315 int (*context_new)(struct nouveau_channel *, int engine); 316 void (*context_del)(struct nouveau_channel *, int engine); 317 int (*object_new)(struct nouveau_channel *, int engine, 318 u32 handle, u16 class); 319 void (*set_tile_region)(struct drm_device *dev, int i); 320 void (*tlb_flush)(struct drm_device *, int engine); 321}; 322 323struct nouveau_instmem_engine { 324 void *priv; 325 326 int (*init)(struct drm_device *dev); 327 void (*takedown)(struct drm_device *dev); 328 int (*suspend)(struct drm_device *dev); 329 void (*resume)(struct drm_device *dev); 330 331 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 332 u32 size, u32 align); 333 void (*put)(struct nouveau_gpuobj *); 334 int (*map)(struct nouveau_gpuobj *); 335 void (*unmap)(struct nouveau_gpuobj *); 336 337 void (*flush)(struct drm_device *); 338}; 339 340struct nouveau_mc_engine { 341 int (*init)(struct drm_device *dev); 342 void (*takedown)(struct drm_device *dev); 343}; 344 345struct nouveau_timer_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348 uint64_t (*read)(struct drm_device *dev); 349}; 350 351struct nouveau_fb_engine { 352 int num_tiles; 353 struct drm_mm tag_heap; 354 void *priv; 355 356 int (*init)(struct drm_device *dev); 357 void (*takedown)(struct drm_device *dev); 358 359 void (*init_tile_region)(struct drm_device *dev, int i, 360 uint32_t addr, uint32_t size, 361 uint32_t pitch, uint32_t flags); 362 void (*set_tile_region)(struct drm_device *dev, int i); 363 void (*free_tile_region)(struct drm_device *dev, int i); 364}; 365 366struct nouveau_fifo_engine { 367 void *priv; 368 int channels; 369 370 struct nouveau_gpuobj *playlist[2]; 371 int cur_playlist; 372 373 int (*init)(struct drm_device *); 374 void (*takedown)(struct drm_device *); 375 376 void (*disable)(struct drm_device *); 377 void (*enable)(struct drm_device *); 378 bool (*reassign)(struct drm_device *, bool enable); 379 bool (*cache_pull)(struct drm_device *dev, bool enable); 380 381 int (*channel_id)(struct drm_device *); 382 383 int (*create_context)(struct nouveau_channel *); 384 void (*destroy_context)(struct nouveau_channel *); 385 int (*load_context)(struct nouveau_channel *); 386 int (*unload_context)(struct drm_device *); 387 void (*tlb_flush)(struct drm_device *dev); 388}; 389 390struct nouveau_display_engine { 391 void *priv; 392 int (*early_init)(struct drm_device *); 393 void (*late_takedown)(struct drm_device *); 394 int (*create)(struct drm_device *); 395 int (*init)(struct drm_device *); 396 void (*destroy)(struct drm_device *); 397}; 398 399struct nouveau_gpio_engine { 400 void *priv; 401 402 int (*init)(struct drm_device *); 403 void (*takedown)(struct drm_device *); 404 405 int (*get)(struct drm_device *, enum dcb_gpio_tag); 406 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 407 408 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 409 void (*)(void *, int), void *); 410 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 411 void (*)(void *, int), void *); 412 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 413}; 414 415struct nouveau_pm_voltage_level { 416 u8 voltage; 417 u8 vid; 418}; 419 420struct nouveau_pm_voltage { 421 bool supported; 422 u8 vid_mask; 423 424 struct nouveau_pm_voltage_level *level; 425 int nr_level; 426}; 427 428struct nouveau_pm_memtiming { 429 int id; 430 u32 reg_100220; 431 u32 reg_100224; 432 u32 reg_100228; 433 u32 reg_10022c; 434 u32 reg_100230; 435 u32 reg_100234; 436 u32 reg_100238; 437 u32 reg_10023c; 438 u32 reg_100240; 439}; 440 441#define NOUVEAU_PM_MAX_LEVEL 8 442struct nouveau_pm_level { 443 struct device_attribute dev_attr; 444 char name[32]; 445 int id; 446 447 u32 core; 448 u32 memory; 449 u32 shader; 450 u32 unk05; 451 u32 unk0a; 452 453 u8 voltage; 454 u8 fanspeed; 455 456 u16 memscript; 457 struct nouveau_pm_memtiming *timing; 458}; 459 460struct nouveau_pm_temp_sensor_constants { 461 u16 offset_constant; 462 s16 offset_mult; 463 u16 offset_div; 464 u16 slope_mult; 465 u16 slope_div; 466}; 467 468struct nouveau_pm_threshold_temp { 469 s16 critical; 470 s16 down_clock; 471 s16 fan_boost; 472}; 473 474struct nouveau_pm_memtimings { 475 bool supported; 476 struct nouveau_pm_memtiming *timing; 477 int nr_timing; 478}; 479 480struct nouveau_pm_engine { 481 struct nouveau_pm_voltage voltage; 482 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 483 int nr_perflvl; 484 struct nouveau_pm_memtimings memtimings; 485 struct nouveau_pm_temp_sensor_constants sensor_constants; 486 struct nouveau_pm_threshold_temp threshold_temp; 487 488 struct nouveau_pm_level boot; 489 struct nouveau_pm_level *cur; 490 491 struct device *hwmon; 492 struct notifier_block acpi_nb; 493 494 int (*clock_get)(struct drm_device *, u32 id); 495 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 496 u32 id, int khz); 497 void (*clock_set)(struct drm_device *, void *); 498 int (*voltage_get)(struct drm_device *); 499 int (*voltage_set)(struct drm_device *, int voltage); 500 int (*fanspeed_get)(struct drm_device *); 501 int (*fanspeed_set)(struct drm_device *, int fanspeed); 502 int (*temp_get)(struct drm_device *); 503}; 504 505struct nouveau_vram_engine { 506 int (*init)(struct drm_device *); 507 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 508 u32 type, struct nouveau_mem **); 509 void (*put)(struct drm_device *, struct nouveau_mem **); 510 511 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 512}; 513 514struct nouveau_engine { 515 struct nouveau_instmem_engine instmem; 516 struct nouveau_mc_engine mc; 517 struct nouveau_timer_engine timer; 518 struct nouveau_fb_engine fb; 519 struct nouveau_fifo_engine fifo; 520 struct nouveau_display_engine display; 521 struct nouveau_gpio_engine gpio; 522 struct nouveau_pm_engine pm; 523 struct nouveau_vram_engine vram; 524}; 525 526struct nouveau_pll_vals { 527 union { 528 struct { 529#ifdef __BIG_ENDIAN 530 uint8_t N1, M1, N2, M2; 531#else 532 uint8_t M1, N1, M2, N2; 533#endif 534 }; 535 struct { 536 uint16_t NM1, NM2; 537 } __attribute__((packed)); 538 }; 539 int log2P; 540 541 int refclk; 542}; 543 544enum nv04_fp_display_regs { 545 FP_DISPLAY_END, 546 FP_TOTAL, 547 FP_CRTC, 548 FP_SYNC_START, 549 FP_SYNC_END, 550 FP_VALID_START, 551 FP_VALID_END 552}; 553 554struct nv04_crtc_reg { 555 unsigned char MiscOutReg; 556 uint8_t CRTC[0xa0]; 557 uint8_t CR58[0x10]; 558 uint8_t Sequencer[5]; 559 uint8_t Graphics[9]; 560 uint8_t Attribute[21]; 561 unsigned char DAC[768]; 562 563 /* PCRTC regs */ 564 uint32_t fb_start; 565 uint32_t crtc_cfg; 566 uint32_t cursor_cfg; 567 uint32_t gpio_ext; 568 uint32_t crtc_830; 569 uint32_t crtc_834; 570 uint32_t crtc_850; 571 uint32_t crtc_eng_ctrl; 572 573 /* PRAMDAC regs */ 574 uint32_t nv10_cursync; 575 struct nouveau_pll_vals pllvals; 576 uint32_t ramdac_gen_ctrl; 577 uint32_t ramdac_630; 578 uint32_t ramdac_634; 579 uint32_t tv_setup; 580 uint32_t tv_vtotal; 581 uint32_t tv_vskew; 582 uint32_t tv_vsync_delay; 583 uint32_t tv_htotal; 584 uint32_t tv_hskew; 585 uint32_t tv_hsync_delay; 586 uint32_t tv_hsync_delay2; 587 uint32_t fp_horiz_regs[7]; 588 uint32_t fp_vert_regs[7]; 589 uint32_t dither; 590 uint32_t fp_control; 591 uint32_t dither_regs[6]; 592 uint32_t fp_debug_0; 593 uint32_t fp_debug_1; 594 uint32_t fp_debug_2; 595 uint32_t fp_margin_color; 596 uint32_t ramdac_8c0; 597 uint32_t ramdac_a20; 598 uint32_t ramdac_a24; 599 uint32_t ramdac_a34; 600 uint32_t ctv_regs[38]; 601}; 602 603struct nv04_output_reg { 604 uint32_t output; 605 int head; 606}; 607 608struct nv04_mode_state { 609 struct nv04_crtc_reg crtc_reg[2]; 610 uint32_t pllsel; 611 uint32_t sel_clk; 612}; 613 614enum nouveau_card_type { 615 NV_04 = 0x00, 616 NV_10 = 0x10, 617 NV_20 = 0x20, 618 NV_30 = 0x30, 619 NV_40 = 0x40, 620 NV_50 = 0x50, 621 NV_C0 = 0xc0, 622}; 623 624struct drm_nouveau_private { 625 struct drm_device *dev; 626 bool noaccel; 627 628 /* the card type, takes NV_* as values */ 629 enum nouveau_card_type card_type; 630 /* exact chipset, derived from NV_PMC_BOOT_0 */ 631 int chipset; 632 int stepping; 633 int flags; 634 635 void __iomem *mmio; 636 637 spinlock_t ramin_lock; 638 void __iomem *ramin; 639 u32 ramin_size; 640 u32 ramin_base; 641 bool ramin_available; 642 struct drm_mm ramin_heap; 643 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 644 struct list_head gpuobj_list; 645 struct list_head classes; 646 647 struct nouveau_bo *vga_ram; 648 649 /* interrupt handling */ 650 void (*irq_handler[32])(struct drm_device *); 651 bool msi_enabled; 652 653 struct list_head vbl_waiting; 654 655 struct { 656 struct drm_global_reference mem_global_ref; 657 struct ttm_bo_global_ref bo_global_ref; 658 struct ttm_bo_device bdev; 659 atomic_t validate_sequence; 660 } ttm; 661 662 struct { 663 spinlock_t lock; 664 struct drm_mm heap; 665 struct nouveau_bo *bo; 666 } fence; 667 668 struct { 669 spinlock_t lock; 670 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 671 } channels; 672 673 struct nouveau_engine engine; 674 struct nouveau_channel *channel; 675 676 /* For PFIFO and PGRAPH. */ 677 spinlock_t context_switch_lock; 678 679 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 680 spinlock_t vm_lock; 681 682 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 683 struct nouveau_ramht *ramht; 684 struct nouveau_gpuobj *ramfc; 685 struct nouveau_gpuobj *ramro; 686 687 uint32_t ramin_rsvd_vram; 688 689 struct { 690 enum { 691 NOUVEAU_GART_NONE = 0, 692 NOUVEAU_GART_AGP, /* AGP */ 693 NOUVEAU_GART_PDMA, /* paged dma object */ 694 NOUVEAU_GART_HW /* on-chip gart/vm */ 695 } type; 696 uint64_t aper_base; 697 uint64_t aper_size; 698 uint64_t aper_free; 699 700 struct ttm_backend_func *func; 701 702 struct { 703 struct page *page; 704 dma_addr_t addr; 705 } dummy; 706 707 struct nouveau_gpuobj *sg_ctxdma; 708 } gart_info; 709 710 /* nv10-nv40 tiling regions */ 711 struct { 712 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 713 spinlock_t lock; 714 } tile; 715 716 /* VRAM/fb configuration */ 717 uint64_t vram_size; 718 uint64_t vram_sys_base; 719 u32 vram_rblock_size; 720 721 uint64_t fb_phys; 722 uint64_t fb_available_size; 723 uint64_t fb_mappable_pages; 724 uint64_t fb_aper_free; 725 int fb_mtrr; 726 727 /* BAR control (NV50-) */ 728 struct nouveau_vm *bar1_vm; 729 struct nouveau_vm *bar3_vm; 730 731 /* G8x/G9x virtual address space */ 732 struct nouveau_vm *chan_vm; 733 734 struct nvbios vbios; 735 736 struct nv04_mode_state mode_reg; 737 struct nv04_mode_state saved_reg; 738 uint32_t saved_vga_font[4][16384]; 739 uint32_t crtc_owner; 740 uint32_t dac_users[4]; 741 742 struct backlight_device *backlight; 743 744 struct { 745 struct dentry *channel_root; 746 } debugfs; 747 748 struct nouveau_fbdev *nfbdev; 749 struct apertures_struct *apertures; 750}; 751 752static inline struct drm_nouveau_private * 753nouveau_private(struct drm_device *dev) 754{ 755 return dev->dev_private; 756} 757 758static inline struct drm_nouveau_private * 759nouveau_bdev(struct ttm_bo_device *bd) 760{ 761 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 762} 763 764static inline int 765nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 766{ 767 struct nouveau_bo *prev; 768 769 if (!pnvbo) 770 return -EINVAL; 771 prev = *pnvbo; 772 773 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 774 if (prev) { 775 struct ttm_buffer_object *bo = &prev->bo; 776 777 ttm_bo_unref(&bo); 778 } 779 780 return 0; 781} 782 783/* nouveau_drv.c */ 784extern int nouveau_agpmode; 785extern int nouveau_duallink; 786extern int nouveau_uscript_lvds; 787extern int nouveau_uscript_tmds; 788extern int nouveau_vram_pushbuf; 789extern int nouveau_vram_notify; 790extern int nouveau_fbpercrtc; 791extern int nouveau_tv_disable; 792extern char *nouveau_tv_norm; 793extern int nouveau_reg_debug; 794extern char *nouveau_vbios; 795extern int nouveau_ignorelid; 796extern int nouveau_nofbaccel; 797extern int nouveau_noaccel; 798extern int nouveau_force_post; 799extern int nouveau_override_conntype; 800extern char *nouveau_perflvl; 801extern int nouveau_perflvl_wr; 802extern int nouveau_msi; 803extern int nouveau_ctxfw; 804 805extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 806extern int nouveau_pci_resume(struct pci_dev *pdev); 807 808/* nouveau_state.c */ 809extern int nouveau_open(struct drm_device *, struct drm_file *); 810extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 811extern void nouveau_postclose(struct drm_device *, struct drm_file *); 812extern int nouveau_load(struct drm_device *, unsigned long flags); 813extern int nouveau_firstopen(struct drm_device *); 814extern void nouveau_lastclose(struct drm_device *); 815extern int nouveau_unload(struct drm_device *); 816extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 817 struct drm_file *); 818extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 819 struct drm_file *); 820extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 821 uint32_t reg, uint32_t mask, uint32_t val); 822extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 823 uint32_t reg, uint32_t mask, uint32_t val); 824extern bool nouveau_wait_for_idle(struct drm_device *); 825extern int nouveau_card_init(struct drm_device *); 826 827/* nouveau_mem.c */ 828extern int nouveau_mem_vram_init(struct drm_device *); 829extern void nouveau_mem_vram_fini(struct drm_device *); 830extern int nouveau_mem_gart_init(struct drm_device *); 831extern void nouveau_mem_gart_fini(struct drm_device *); 832extern int nouveau_mem_init_agp(struct drm_device *); 833extern int nouveau_mem_reset_agp(struct drm_device *); 834extern void nouveau_mem_close(struct drm_device *); 835extern int nouveau_mem_detect(struct drm_device *); 836extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 837extern struct nouveau_tile_reg *nv10_mem_set_tiling( 838 struct drm_device *dev, uint32_t addr, uint32_t size, 839 uint32_t pitch, uint32_t flags); 840extern void nv10_mem_put_tile_region(struct drm_device *dev, 841 struct nouveau_tile_reg *tile, 842 struct nouveau_fence *fence); 843extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 844extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 845 846/* nouveau_notifier.c */ 847extern int nouveau_notifier_init_channel(struct nouveau_channel *); 848extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 849extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 850 int cout, uint32_t start, uint32_t end, 851 uint32_t *offset); 852extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 853extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 854 struct drm_file *); 855extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 856 struct drm_file *); 857 858/* nouveau_channel.c */ 859extern struct drm_ioctl_desc nouveau_ioctls[]; 860extern int nouveau_max_ioctl; 861extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 862extern int nouveau_channel_alloc(struct drm_device *dev, 863 struct nouveau_channel **chan, 864 struct drm_file *file_priv, 865 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 866extern struct nouveau_channel * 867nouveau_channel_get_unlocked(struct nouveau_channel *); 868extern struct nouveau_channel * 869nouveau_channel_get(struct drm_file *, int id); 870extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 871extern void nouveau_channel_put(struct nouveau_channel **); 872extern void nouveau_channel_ref(struct nouveau_channel *chan, 873 struct nouveau_channel **pchan); 874extern void nouveau_channel_idle(struct nouveau_channel *chan); 875 876/* nouveau_object.c */ 877#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 878 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 879 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 880} while (0) 881 882#define NVOBJ_ENGINE_DEL(d, e) do { \ 883 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 884 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 885} while (0) 886 887#define NVOBJ_CLASS(d, c, e) do { \ 888 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 889 if (ret) \ 890 return ret; \ 891} while (0) 892 893#define NVOBJ_MTHD(d, c, m, e) do { \ 894 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 895 if (ret) \ 896 return ret; \ 897} while (0) 898 899extern int nouveau_gpuobj_early_init(struct drm_device *); 900extern int nouveau_gpuobj_init(struct drm_device *); 901extern void nouveau_gpuobj_takedown(struct drm_device *); 902extern int nouveau_gpuobj_suspend(struct drm_device *dev); 903extern void nouveau_gpuobj_resume(struct drm_device *dev); 904extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 905extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 906 int (*exec)(struct nouveau_channel *, 907 u32 class, u32 mthd, u32 data)); 908extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 909extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 910extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 911 uint32_t vram_h, uint32_t tt_h); 912extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 913extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 914 uint32_t size, int align, uint32_t flags, 915 struct nouveau_gpuobj **); 916extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 917 struct nouveau_gpuobj **); 918extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 919 u32 size, u32 flags, 920 struct nouveau_gpuobj **); 921extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 922 uint64_t offset, uint64_t size, int access, 923 int target, struct nouveau_gpuobj **); 924extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 925extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 926 u64 size, int target, int access, u32 type, 927 u32 comp, struct nouveau_gpuobj **pobj); 928extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 929 int class, u64 base, u64 size, int target, 930 int access, u32 type, u32 comp); 931extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 932 struct drm_file *); 933extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 934 struct drm_file *); 935 936/* nouveau_irq.c */ 937extern int nouveau_irq_init(struct drm_device *); 938extern void nouveau_irq_fini(struct drm_device *); 939extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 940extern void nouveau_irq_register(struct drm_device *, int status_bit, 941 void (*)(struct drm_device *)); 942extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 943extern void nouveau_irq_preinstall(struct drm_device *); 944extern int nouveau_irq_postinstall(struct drm_device *); 945extern void nouveau_irq_uninstall(struct drm_device *); 946 947/* nouveau_sgdma.c */ 948extern int nouveau_sgdma_init(struct drm_device *); 949extern void nouveau_sgdma_takedown(struct drm_device *); 950extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 951 uint32_t offset); 952extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 953 954/* nouveau_debugfs.c */ 955#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 956extern int nouveau_debugfs_init(struct drm_minor *); 957extern void nouveau_debugfs_takedown(struct drm_minor *); 958extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 959extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 960#else 961static inline int 962nouveau_debugfs_init(struct drm_minor *minor) 963{ 964 return 0; 965} 966 967static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 968{ 969} 970 971static inline int 972nouveau_debugfs_channel_init(struct nouveau_channel *chan) 973{ 974 return 0; 975} 976 977static inline void 978nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 979{ 980} 981#endif 982 983/* nouveau_dma.c */ 984extern void nouveau_dma_pre_init(struct nouveau_channel *); 985extern int nouveau_dma_init(struct nouveau_channel *); 986extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 987 988/* nouveau_acpi.c */ 989#define ROM_BIOS_PAGE 4096 990#if defined(CONFIG_ACPI) 991void nouveau_register_dsm_handler(void); 992void nouveau_unregister_dsm_handler(void); 993int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 994bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 995int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 996#else 997static inline void nouveau_register_dsm_handler(void) {} 998static inline void nouveau_unregister_dsm_handler(void) {} 999static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1000static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1001static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1002#endif 1003 1004/* nouveau_backlight.c */ 1005#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1006extern int nouveau_backlight_init(struct drm_connector *); 1007extern void nouveau_backlight_exit(struct drm_connector *); 1008#else 1009static inline int nouveau_backlight_init(struct drm_connector *dev) 1010{ 1011 return 0; 1012} 1013 1014static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1015#endif 1016 1017/* nouveau_bios.c */ 1018extern int nouveau_bios_init(struct drm_device *); 1019extern void nouveau_bios_takedown(struct drm_device *dev); 1020extern int nouveau_run_vbios_init(struct drm_device *); 1021extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1022 struct dcb_entry *); 1023extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1024 enum dcb_gpio_tag); 1025extern struct dcb_connector_table_entry * 1026nouveau_bios_connector_entry(struct drm_device *, int index); 1027extern u32 get_pll_register(struct drm_device *, enum pll_types); 1028extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1029 struct pll_lims *); 1030extern int nouveau_bios_run_display_table(struct drm_device *, 1031 struct dcb_entry *, 1032 uint32_t script, int pxclk); 1033extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1034 int *length); 1035extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1036extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1037extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1038 bool *dl, bool *if_is_24bit); 1039extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1040 int head, int pxclk); 1041extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1042 enum LVDS_script, int pxclk); 1043 1044/* nouveau_ttm.c */ 1045int nouveau_ttm_global_init(struct drm_nouveau_private *); 1046void nouveau_ttm_global_release(struct drm_nouveau_private *); 1047int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1048 1049/* nouveau_dp.c */ 1050int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1051 uint8_t *data, int data_nr); 1052bool nouveau_dp_detect(struct drm_encoder *); 1053bool nouveau_dp_link_train(struct drm_encoder *); 1054 1055/* nv04_fb.c */ 1056extern int nv04_fb_init(struct drm_device *); 1057extern void nv04_fb_takedown(struct drm_device *); 1058 1059/* nv10_fb.c */ 1060extern int nv10_fb_init(struct drm_device *); 1061extern void nv10_fb_takedown(struct drm_device *); 1062extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1063 uint32_t addr, uint32_t size, 1064 uint32_t pitch, uint32_t flags); 1065extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1066extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1067 1068/* nv30_fb.c */ 1069extern int nv30_fb_init(struct drm_device *); 1070extern void nv30_fb_takedown(struct drm_device *); 1071extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1072 uint32_t addr, uint32_t size, 1073 uint32_t pitch, uint32_t flags); 1074extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1075 1076/* nv40_fb.c */ 1077extern int nv40_fb_init(struct drm_device *); 1078extern void nv40_fb_takedown(struct drm_device *); 1079extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1080 1081/* nv50_fb.c */ 1082extern int nv50_fb_init(struct drm_device *); 1083extern void nv50_fb_takedown(struct drm_device *); 1084extern void nv50_fb_vm_trap(struct drm_device *, int display); 1085 1086/* nvc0_fb.c */ 1087extern int nvc0_fb_init(struct drm_device *); 1088extern void nvc0_fb_takedown(struct drm_device *); 1089 1090/* nv04_fifo.c */ 1091extern int nv04_fifo_init(struct drm_device *); 1092extern void nv04_fifo_fini(struct drm_device *); 1093extern void nv04_fifo_disable(struct drm_device *); 1094extern void nv04_fifo_enable(struct drm_device *); 1095extern bool nv04_fifo_reassign(struct drm_device *, bool); 1096extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1097extern int nv04_fifo_channel_id(struct drm_device *); 1098extern int nv04_fifo_create_context(struct nouveau_channel *); 1099extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1100extern int nv04_fifo_load_context(struct nouveau_channel *); 1101extern int nv04_fifo_unload_context(struct drm_device *); 1102extern void nv04_fifo_isr(struct drm_device *); 1103 1104/* nv10_fifo.c */ 1105extern int nv10_fifo_init(struct drm_device *); 1106extern int nv10_fifo_channel_id(struct drm_device *); 1107extern int nv10_fifo_create_context(struct nouveau_channel *); 1108extern int nv10_fifo_load_context(struct nouveau_channel *); 1109extern int nv10_fifo_unload_context(struct drm_device *); 1110 1111/* nv40_fifo.c */ 1112extern int nv40_fifo_init(struct drm_device *); 1113extern int nv40_fifo_create_context(struct nouveau_channel *); 1114extern int nv40_fifo_load_context(struct nouveau_channel *); 1115extern int nv40_fifo_unload_context(struct drm_device *); 1116 1117/* nv50_fifo.c */ 1118extern int nv50_fifo_init(struct drm_device *); 1119extern void nv50_fifo_takedown(struct drm_device *); 1120extern int nv50_fifo_channel_id(struct drm_device *); 1121extern int nv50_fifo_create_context(struct nouveau_channel *); 1122extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1123extern int nv50_fifo_load_context(struct nouveau_channel *); 1124extern int nv50_fifo_unload_context(struct drm_device *); 1125extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1126 1127/* nvc0_fifo.c */ 1128extern int nvc0_fifo_init(struct drm_device *); 1129extern void nvc0_fifo_takedown(struct drm_device *); 1130extern void nvc0_fifo_disable(struct drm_device *); 1131extern void nvc0_fifo_enable(struct drm_device *); 1132extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1133extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1134extern int nvc0_fifo_channel_id(struct drm_device *); 1135extern int nvc0_fifo_create_context(struct nouveau_channel *); 1136extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1137extern int nvc0_fifo_load_context(struct nouveau_channel *); 1138extern int nvc0_fifo_unload_context(struct drm_device *); 1139 1140/* nv04_graph.c */ 1141extern int nv04_graph_create(struct drm_device *); 1142extern void nv04_graph_fifo_access(struct drm_device *, bool); 1143extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1144extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1145 u32 class, u32 mthd, u32 data); 1146extern struct nouveau_bitfield nv04_graph_nsource[]; 1147 1148/* nv10_graph.c */ 1149extern int nv10_graph_create(struct drm_device *); 1150extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1151extern struct nouveau_bitfield nv10_graph_intr[]; 1152extern struct nouveau_bitfield nv10_graph_nstatus[]; 1153 1154/* nv20_graph.c */ 1155extern int nv20_graph_create(struct drm_device *); 1156 1157/* nv40_graph.c */ 1158extern int nv40_graph_create(struct drm_device *); 1159extern void nv40_grctx_init(struct nouveau_grctx *); 1160 1161/* nv50_graph.c */ 1162extern int nv50_graph_create(struct drm_device *); 1163extern int nv50_grctx_init(struct nouveau_grctx *); 1164extern struct nouveau_enum nv50_data_error_names[]; 1165extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1166 1167/* nvc0_graph.c */ 1168extern int nvc0_graph_create(struct drm_device *); 1169extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1170 1171/* nv84_crypt.c */ 1172extern int nv84_crypt_create(struct drm_device *); 1173 1174/* nva3_copy.c */ 1175extern int nva3_copy_create(struct drm_device *dev); 1176 1177/* nvc0_copy.c */ 1178extern int nvc0_copy_create(struct drm_device *dev, int engine); 1179 1180/* nv40_mpeg.c */ 1181extern int nv40_mpeg_create(struct drm_device *dev); 1182 1183/* nv50_mpeg.c */ 1184extern int nv50_mpeg_create(struct drm_device *dev); 1185 1186/* nv04_instmem.c */ 1187extern int nv04_instmem_init(struct drm_device *); 1188extern void nv04_instmem_takedown(struct drm_device *); 1189extern int nv04_instmem_suspend(struct drm_device *); 1190extern void nv04_instmem_resume(struct drm_device *); 1191extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1192 u32 size, u32 align); 1193extern void nv04_instmem_put(struct nouveau_gpuobj *); 1194extern int nv04_instmem_map(struct nouveau_gpuobj *); 1195extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1196extern void nv04_instmem_flush(struct drm_device *); 1197 1198/* nv50_instmem.c */ 1199extern int nv50_instmem_init(struct drm_device *); 1200extern void nv50_instmem_takedown(struct drm_device *); 1201extern int nv50_instmem_suspend(struct drm_device *); 1202extern void nv50_instmem_resume(struct drm_device *); 1203extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1204 u32 size, u32 align); 1205extern void nv50_instmem_put(struct nouveau_gpuobj *); 1206extern int nv50_instmem_map(struct nouveau_gpuobj *); 1207extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1208extern void nv50_instmem_flush(struct drm_device *); 1209extern void nv84_instmem_flush(struct drm_device *); 1210 1211/* nvc0_instmem.c */ 1212extern int nvc0_instmem_init(struct drm_device *); 1213extern void nvc0_instmem_takedown(struct drm_device *); 1214extern int nvc0_instmem_suspend(struct drm_device *); 1215extern void nvc0_instmem_resume(struct drm_device *); 1216 1217/* nv04_mc.c */ 1218extern int nv04_mc_init(struct drm_device *); 1219extern void nv04_mc_takedown(struct drm_device *); 1220 1221/* nv40_mc.c */ 1222extern int nv40_mc_init(struct drm_device *); 1223extern void nv40_mc_takedown(struct drm_device *); 1224 1225/* nv50_mc.c */ 1226extern int nv50_mc_init(struct drm_device *); 1227extern void nv50_mc_takedown(struct drm_device *); 1228 1229/* nv04_timer.c */ 1230extern int nv04_timer_init(struct drm_device *); 1231extern uint64_t nv04_timer_read(struct drm_device *); 1232extern void nv04_timer_takedown(struct drm_device *); 1233 1234extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1235 unsigned long arg); 1236 1237/* nv04_dac.c */ 1238extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1239extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1240extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1241extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1242extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1243 1244/* nv04_dfp.c */ 1245extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1246extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1247extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1248 int head, bool dl); 1249extern void nv04_dfp_disable(struct drm_device *dev, int head); 1250extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1251 1252/* nv04_tv.c */ 1253extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1254extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1255 1256/* nv17_tv.c */ 1257extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1258 1259/* nv04_display.c */ 1260extern int nv04_display_early_init(struct drm_device *); 1261extern void nv04_display_late_takedown(struct drm_device *); 1262extern int nv04_display_create(struct drm_device *); 1263extern int nv04_display_init(struct drm_device *); 1264extern void nv04_display_destroy(struct drm_device *); 1265 1266/* nv04_crtc.c */ 1267extern int nv04_crtc_create(struct drm_device *, int index); 1268 1269/* nouveau_bo.c */ 1270extern struct ttm_bo_driver nouveau_bo_driver; 1271extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1272 int size, int align, uint32_t flags, 1273 uint32_t tile_mode, uint32_t tile_flags, 1274 struct nouveau_bo **); 1275extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1276extern int nouveau_bo_unpin(struct nouveau_bo *); 1277extern int nouveau_bo_map(struct nouveau_bo *); 1278extern void nouveau_bo_unmap(struct nouveau_bo *); 1279extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1280 uint32_t busy); 1281extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1282extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1283extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1284extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1285extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1286extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1287 bool no_wait_reserve, bool no_wait_gpu); 1288 1289extern struct nouveau_vma * 1290nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1291extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1292 struct nouveau_vma *); 1293extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1294 1295/* nouveau_fence.c */ 1296struct nouveau_fence; 1297extern int nouveau_fence_init(struct drm_device *); 1298extern void nouveau_fence_fini(struct drm_device *); 1299extern int nouveau_fence_channel_init(struct nouveau_channel *); 1300extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1301extern void nouveau_fence_update(struct nouveau_channel *); 1302extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1303 bool emit); 1304extern int nouveau_fence_emit(struct nouveau_fence *); 1305extern void nouveau_fence_work(struct nouveau_fence *fence, 1306 void (*work)(void *priv, bool signalled), 1307 void *priv); 1308struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1309 1310extern bool __nouveau_fence_signalled(void *obj, void *arg); 1311extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1312extern int __nouveau_fence_flush(void *obj, void *arg); 1313extern void __nouveau_fence_unref(void **obj); 1314extern void *__nouveau_fence_ref(void *obj); 1315 1316static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1317{ 1318 return __nouveau_fence_signalled(obj, NULL); 1319} 1320static inline int 1321nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1322{ 1323 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1324} 1325extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1326static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1327{ 1328 return __nouveau_fence_flush(obj, NULL); 1329} 1330static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1331{ 1332 __nouveau_fence_unref((void **)obj); 1333} 1334static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1335{ 1336 return __nouveau_fence_ref(obj); 1337} 1338 1339/* nouveau_gem.c */ 1340extern int nouveau_gem_new(struct drm_device *, int size, int align, 1341 uint32_t domain, uint32_t tile_mode, 1342 uint32_t tile_flags, struct nouveau_bo **); 1343extern int nouveau_gem_object_new(struct drm_gem_object *); 1344extern void nouveau_gem_object_del(struct drm_gem_object *); 1345extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1346extern void nouveau_gem_object_close(struct drm_gem_object *, 1347 struct drm_file *); 1348extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1349 struct drm_file *); 1350extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1351 struct drm_file *); 1352extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1353 struct drm_file *); 1354extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1355 struct drm_file *); 1356extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1357 struct drm_file *); 1358 1359/* nouveau_display.c */ 1360int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1361void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1362int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1363 struct drm_pending_vblank_event *event); 1364int nouveau_finish_page_flip(struct nouveau_channel *, 1365 struct nouveau_page_flip_state *); 1366 1367/* nv10_gpio.c */ 1368int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1369int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1370 1371/* nv50_gpio.c */ 1372int nv50_gpio_init(struct drm_device *dev); 1373void nv50_gpio_fini(struct drm_device *dev); 1374int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1375int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1376int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1377 void (*)(void *, int), void *); 1378void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1379 void (*)(void *, int), void *); 1380bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1381 1382/* nv50_calc. */ 1383int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1384 int *N1, int *M1, int *N2, int *M2, int *P); 1385int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1386 int clk, int *N, int *fN, int *M, int *P); 1387 1388#ifndef ioread32_native 1389#ifdef __BIG_ENDIAN 1390#define ioread16_native ioread16be 1391#define iowrite16_native iowrite16be 1392#define ioread32_native ioread32be 1393#define iowrite32_native iowrite32be 1394#else /* def __BIG_ENDIAN */ 1395#define ioread16_native ioread16 1396#define iowrite16_native iowrite16 1397#define ioread32_native ioread32 1398#define iowrite32_native iowrite32 1399#endif /* def __BIG_ENDIAN else */ 1400#endif /* !ioread32_native */ 1401 1402/* channel control reg access */ 1403static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1404{ 1405 return ioread32_native(chan->user + reg); 1406} 1407 1408static inline void nvchan_wr32(struct nouveau_channel *chan, 1409 unsigned reg, u32 val) 1410{ 1411 iowrite32_native(val, chan->user + reg); 1412} 1413 1414/* register access */ 1415static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1416{ 1417 struct drm_nouveau_private *dev_priv = dev->dev_private; 1418 return ioread32_native(dev_priv->mmio + reg); 1419} 1420 1421static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1422{ 1423 struct drm_nouveau_private *dev_priv = dev->dev_private; 1424 iowrite32_native(val, dev_priv->mmio + reg); 1425} 1426 1427static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1428{ 1429 u32 tmp = nv_rd32(dev, reg); 1430 nv_wr32(dev, reg, (tmp & ~mask) | val); 1431 return tmp; 1432} 1433 1434static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1435{ 1436 struct drm_nouveau_private *dev_priv = dev->dev_private; 1437 return ioread8(dev_priv->mmio + reg); 1438} 1439 1440static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1441{ 1442 struct drm_nouveau_private *dev_priv = dev->dev_private; 1443 iowrite8(val, dev_priv->mmio + reg); 1444} 1445 1446#define nv_wait(dev, reg, mask, val) \ 1447 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1448#define nv_wait_ne(dev, reg, mask, val) \ 1449 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1450 1451/* PRAMIN access */ 1452static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1453{ 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 return ioread32_native(dev_priv->ramin + offset); 1456} 1457 1458static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1459{ 1460 struct drm_nouveau_private *dev_priv = dev->dev_private; 1461 iowrite32_native(val, dev_priv->ramin + offset); 1462} 1463 1464/* object access */ 1465extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1466extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1467 1468/* 1469 * Logging 1470 * Argument d is (struct drm_device *). 1471 */ 1472#define NV_PRINTK(level, d, fmt, arg...) \ 1473 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1474 pci_name(d->pdev), ##arg) 1475#ifndef NV_DEBUG_NOTRACE 1476#define NV_DEBUG(d, fmt, arg...) do { \ 1477 if (drm_debug & DRM_UT_DRIVER) { \ 1478 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1479 __LINE__, ##arg); \ 1480 } \ 1481} while (0) 1482#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1483 if (drm_debug & DRM_UT_KMS) { \ 1484 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1485 __LINE__, ##arg); \ 1486 } \ 1487} while (0) 1488#else 1489#define NV_DEBUG(d, fmt, arg...) do { \ 1490 if (drm_debug & DRM_UT_DRIVER) \ 1491 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1492} while (0) 1493#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1494 if (drm_debug & DRM_UT_KMS) \ 1495 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1496} while (0) 1497#endif 1498#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1499#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1500#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1501#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1502#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1503 1504/* nouveau_reg_debug bitmask */ 1505enum { 1506 NOUVEAU_REG_DEBUG_MC = 0x1, 1507 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1508 NOUVEAU_REG_DEBUG_FB = 0x4, 1509 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1510 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1511 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1512 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1513 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1514 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1515 NOUVEAU_REG_DEBUG_EVO = 0x200, 1516}; 1517 1518#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1519 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1520 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1521} while (0) 1522 1523static inline bool 1524nv_two_heads(struct drm_device *dev) 1525{ 1526 struct drm_nouveau_private *dev_priv = dev->dev_private; 1527 const int impl = dev->pci_device & 0x0ff0; 1528 1529 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1530 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1531 return true; 1532 1533 return false; 1534} 1535 1536static inline bool 1537nv_gf4_disp_arch(struct drm_device *dev) 1538{ 1539 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1540} 1541 1542static inline bool 1543nv_two_reg_pll(struct drm_device *dev) 1544{ 1545 struct drm_nouveau_private *dev_priv = dev->dev_private; 1546 const int impl = dev->pci_device & 0x0ff0; 1547 1548 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1549 return true; 1550 return false; 1551} 1552 1553static inline bool 1554nv_match_device(struct drm_device *dev, unsigned device, 1555 unsigned sub_vendor, unsigned sub_device) 1556{ 1557 return dev->pdev->device == device && 1558 dev->pdev->subsystem_vendor == sub_vendor && 1559 dev->pdev->subsystem_device == sub_device; 1560} 1561 1562static inline void * 1563nv_engine(struct drm_device *dev, int engine) 1564{ 1565 struct drm_nouveau_private *dev_priv = dev->dev_private; 1566 return (void *)dev_priv->eng[engine]; 1567} 1568 1569/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1570 * helpful to determine a number of other hardware features 1571 */ 1572static inline int 1573nv44_graph_class(struct drm_device *dev) 1574{ 1575 struct drm_nouveau_private *dev_priv = dev->dev_private; 1576 1577 if ((dev_priv->chipset & 0xf0) == 0x60) 1578 return 1; 1579 1580 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1581} 1582 1583/* memory type/access flags, do not match hardware values */ 1584#define NV_MEM_ACCESS_RO 1 1585#define NV_MEM_ACCESS_WO 2 1586#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1587#define NV_MEM_ACCESS_SYS 4 1588#define NV_MEM_ACCESS_VM 8 1589 1590#define NV_MEM_TARGET_VRAM 0 1591#define NV_MEM_TARGET_PCI 1 1592#define NV_MEM_TARGET_PCI_NOSNOOP 2 1593#define NV_MEM_TARGET_VM 3 1594#define NV_MEM_TARGET_GART 4 1595 1596#define NV_MEM_TYPE_VM 0x7f 1597#define NV_MEM_COMP_VM 0x03 1598 1599/* NV_SW object class */ 1600#define NV_SW 0x0000506e 1601#define NV_SW_DMA_SEMAPHORE 0x00000060 1602#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1603#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1604#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1605#define NV_SW_YIELD 0x00000080 1606#define NV_SW_DMA_VBLSEM 0x0000018c 1607#define NV_SW_VBLSEM_OFFSET 0x00000400 1608#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1609#define NV_SW_VBLSEM_RELEASE 0x00000408 1610#define NV_SW_PAGE_FLIP 0x00000500 1611 1612#endif /* __NOUVEAU_DRV_H__ */ 1613