nouveau_drv.h revision d02836b4f5c24d2a38b3bdc10f05251e1f6e111d
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 struct list_head vma_list; 120 unsigned page_shift; 121 122 uint32_t tile_mode; 123 uint32_t tile_flags; 124 struct nouveau_tile_reg *tile; 125 126 struct drm_gem_object *gem; 127 int pin_refcnt; 128}; 129 130#define nouveau_bo_tile_layout(nvbo) \ 131 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 132 133static inline struct nouveau_bo * 134nouveau_bo(struct ttm_buffer_object *bo) 135{ 136 return container_of(bo, struct nouveau_bo, bo); 137} 138 139static inline struct nouveau_bo * 140nouveau_gem_object(struct drm_gem_object *gem) 141{ 142 return gem ? gem->driver_private : NULL; 143} 144 145/* TODO: submit equivalent to TTM generic API upstream? */ 146static inline void __iomem * 147nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 148{ 149 bool is_iomem; 150 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 151 &nvbo->kmap, &is_iomem); 152 WARN_ON_ONCE(ioptr && !is_iomem); 153 return ioptr; 154} 155 156enum nouveau_flags { 157 NV_NFORCE = 0x10000000, 158 NV_NFORCE2 = 0x20000000 159}; 160 161#define NVOBJ_ENGINE_SW 0 162#define NVOBJ_ENGINE_GR 1 163#define NVOBJ_ENGINE_CRYPT 2 164#define NVOBJ_ENGINE_COPY0 3 165#define NVOBJ_ENGINE_COPY1 4 166#define NVOBJ_ENGINE_MPEG 5 167#define NVOBJ_ENGINE_DISPLAY 15 168#define NVOBJ_ENGINE_NR 16 169 170#define NVOBJ_FLAG_DONT_MAP (1 << 0) 171#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 172#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 173#define NVOBJ_FLAG_VM (1 << 3) 174#define NVOBJ_FLAG_VM_USER (1 << 4) 175 176#define NVOBJ_CINST_GLOBAL 0xdeadbeef 177 178struct nouveau_gpuobj { 179 struct drm_device *dev; 180 struct kref refcount; 181 struct list_head list; 182 183 void *node; 184 u32 *suspend; 185 186 uint32_t flags; 187 188 u32 size; 189 u32 pinst; /* PRAMIN BAR offset */ 190 u32 cinst; /* Channel offset */ 191 u64 vinst; /* VRAM address */ 192 u64 linst; /* VM address */ 193 194 uint32_t engine; 195 uint32_t class; 196 197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 198 void *priv; 199}; 200 201struct nouveau_page_flip_state { 202 struct list_head head; 203 struct drm_pending_vblank_event *event; 204 int crtc, bpp, pitch, x, y; 205 uint64_t offset; 206}; 207 208enum nouveau_channel_mutex_class { 209 NOUVEAU_UCHANNEL_MUTEX, 210 NOUVEAU_KCHANNEL_MUTEX 211}; 212 213struct nouveau_channel { 214 struct drm_device *dev; 215 struct list_head list; 216 int id; 217 218 /* references to the channel data structure */ 219 struct kref ref; 220 /* users of the hardware channel resources, the hardware 221 * context will be kicked off when it reaches zero. */ 222 atomic_t users; 223 struct mutex mutex; 224 225 /* owner of this fifo */ 226 struct drm_file *file_priv; 227 /* mapping of the fifo itself */ 228 struct drm_local_map *map; 229 230 /* mapping of the regs controlling the fifo */ 231 void __iomem *user; 232 uint32_t user_get; 233 uint32_t user_put; 234 235 /* Fencing */ 236 struct { 237 /* lock protects the pending list only */ 238 spinlock_t lock; 239 struct list_head pending; 240 uint32_t sequence; 241 uint32_t sequence_ack; 242 atomic_t last_sequence_irq; 243 struct nouveau_vma vma; 244 } fence; 245 246 /* DMA push buffer */ 247 struct nouveau_gpuobj *pushbuf; 248 struct nouveau_bo *pushbuf_bo; 249 struct nouveau_vma pushbuf_vma; 250 uint32_t pushbuf_base; 251 252 /* Notifier memory */ 253 struct nouveau_bo *notifier_bo; 254 struct nouveau_vma notifier_vma; 255 struct drm_mm notifier_heap; 256 257 /* PFIFO context */ 258 struct nouveau_gpuobj *ramfc; 259 struct nouveau_gpuobj *cache; 260 void *fifo_priv; 261 262 /* Execution engine contexts */ 263 void *engctx[NVOBJ_ENGINE_NR]; 264 265 /* NV50 VM */ 266 struct nouveau_vm *vm; 267 struct nouveau_gpuobj *vm_pd; 268 269 /* Objects */ 270 struct nouveau_gpuobj *ramin; /* Private instmem */ 271 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 272 struct nouveau_ramht *ramht; /* Hash table */ 273 274 /* GPU object info for stuff used in-kernel (mm_enabled) */ 275 uint32_t m2mf_ntfy; 276 uint32_t vram_handle; 277 uint32_t gart_handle; 278 bool accel_done; 279 280 /* Push buffer state (only for drm's channel on !mm_enabled) */ 281 struct { 282 int max; 283 int free; 284 int cur; 285 int put; 286 /* access via pushbuf_bo */ 287 288 int ib_base; 289 int ib_max; 290 int ib_free; 291 int ib_put; 292 } dma; 293 294 uint32_t sw_subchannel[8]; 295 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310}; 311 312struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322}; 323 324struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339}; 340 341struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344}; 345 346struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350}; 351 352struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365}; 366 367struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389}; 390 391struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398}; 399 400struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414}; 415 416struct nouveau_pm_voltage_level { 417 u8 voltage; 418 u8 vid; 419}; 420 421struct nouveau_pm_voltage { 422 bool supported; 423 u8 vid_mask; 424 425 struct nouveau_pm_voltage_level *level; 426 int nr_level; 427}; 428 429struct nouveau_pm_memtiming { 430 int id; 431 u32 reg_100220; 432 u32 reg_100224; 433 u32 reg_100228; 434 u32 reg_10022c; 435 u32 reg_100230; 436 u32 reg_100234; 437 u32 reg_100238; 438 u32 reg_10023c; 439 u32 reg_100240; 440}; 441 442#define NOUVEAU_PM_MAX_LEVEL 8 443struct nouveau_pm_level { 444 struct device_attribute dev_attr; 445 char name[32]; 446 int id; 447 448 u32 core; 449 u32 memory; 450 u32 shader; 451 u32 unk05; 452 u32 unk0a; 453 454 u8 voltage; 455 u8 fanspeed; 456 457 u16 memscript; 458 struct nouveau_pm_memtiming *timing; 459}; 460 461struct nouveau_pm_temp_sensor_constants { 462 u16 offset_constant; 463 s16 offset_mult; 464 u16 offset_div; 465 u16 slope_mult; 466 u16 slope_div; 467}; 468 469struct nouveau_pm_threshold_temp { 470 s16 critical; 471 s16 down_clock; 472 s16 fan_boost; 473}; 474 475struct nouveau_pm_memtimings { 476 bool supported; 477 struct nouveau_pm_memtiming *timing; 478 int nr_timing; 479}; 480 481struct nouveau_pm_engine { 482 struct nouveau_pm_voltage voltage; 483 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 484 int nr_perflvl; 485 struct nouveau_pm_memtimings memtimings; 486 struct nouveau_pm_temp_sensor_constants sensor_constants; 487 struct nouveau_pm_threshold_temp threshold_temp; 488 489 struct nouveau_pm_level boot; 490 struct nouveau_pm_level *cur; 491 492 struct device *hwmon; 493 struct notifier_block acpi_nb; 494 495 int (*clock_get)(struct drm_device *, u32 id); 496 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 497 u32 id, int khz); 498 void (*clock_set)(struct drm_device *, void *); 499 int (*voltage_get)(struct drm_device *); 500 int (*voltage_set)(struct drm_device *, int voltage); 501 int (*fanspeed_get)(struct drm_device *); 502 int (*fanspeed_set)(struct drm_device *, int fanspeed); 503 int (*temp_get)(struct drm_device *); 504}; 505 506struct nouveau_vram_engine { 507 int (*init)(struct drm_device *); 508 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 509 u32 type, struct nouveau_mem **); 510 void (*put)(struct drm_device *, struct nouveau_mem **); 511 512 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 513}; 514 515struct nouveau_engine { 516 struct nouveau_instmem_engine instmem; 517 struct nouveau_mc_engine mc; 518 struct nouveau_timer_engine timer; 519 struct nouveau_fb_engine fb; 520 struct nouveau_fifo_engine fifo; 521 struct nouveau_display_engine display; 522 struct nouveau_gpio_engine gpio; 523 struct nouveau_pm_engine pm; 524 struct nouveau_vram_engine vram; 525}; 526 527struct nouveau_pll_vals { 528 union { 529 struct { 530#ifdef __BIG_ENDIAN 531 uint8_t N1, M1, N2, M2; 532#else 533 uint8_t M1, N1, M2, N2; 534#endif 535 }; 536 struct { 537 uint16_t NM1, NM2; 538 } __attribute__((packed)); 539 }; 540 int log2P; 541 542 int refclk; 543}; 544 545enum nv04_fp_display_regs { 546 FP_DISPLAY_END, 547 FP_TOTAL, 548 FP_CRTC, 549 FP_SYNC_START, 550 FP_SYNC_END, 551 FP_VALID_START, 552 FP_VALID_END 553}; 554 555struct nv04_crtc_reg { 556 unsigned char MiscOutReg; 557 uint8_t CRTC[0xa0]; 558 uint8_t CR58[0x10]; 559 uint8_t Sequencer[5]; 560 uint8_t Graphics[9]; 561 uint8_t Attribute[21]; 562 unsigned char DAC[768]; 563 564 /* PCRTC regs */ 565 uint32_t fb_start; 566 uint32_t crtc_cfg; 567 uint32_t cursor_cfg; 568 uint32_t gpio_ext; 569 uint32_t crtc_830; 570 uint32_t crtc_834; 571 uint32_t crtc_850; 572 uint32_t crtc_eng_ctrl; 573 574 /* PRAMDAC regs */ 575 uint32_t nv10_cursync; 576 struct nouveau_pll_vals pllvals; 577 uint32_t ramdac_gen_ctrl; 578 uint32_t ramdac_630; 579 uint32_t ramdac_634; 580 uint32_t tv_setup; 581 uint32_t tv_vtotal; 582 uint32_t tv_vskew; 583 uint32_t tv_vsync_delay; 584 uint32_t tv_htotal; 585 uint32_t tv_hskew; 586 uint32_t tv_hsync_delay; 587 uint32_t tv_hsync_delay2; 588 uint32_t fp_horiz_regs[7]; 589 uint32_t fp_vert_regs[7]; 590 uint32_t dither; 591 uint32_t fp_control; 592 uint32_t dither_regs[6]; 593 uint32_t fp_debug_0; 594 uint32_t fp_debug_1; 595 uint32_t fp_debug_2; 596 uint32_t fp_margin_color; 597 uint32_t ramdac_8c0; 598 uint32_t ramdac_a20; 599 uint32_t ramdac_a24; 600 uint32_t ramdac_a34; 601 uint32_t ctv_regs[38]; 602}; 603 604struct nv04_output_reg { 605 uint32_t output; 606 int head; 607}; 608 609struct nv04_mode_state { 610 struct nv04_crtc_reg crtc_reg[2]; 611 uint32_t pllsel; 612 uint32_t sel_clk; 613}; 614 615enum nouveau_card_type { 616 NV_04 = 0x00, 617 NV_10 = 0x10, 618 NV_20 = 0x20, 619 NV_30 = 0x30, 620 NV_40 = 0x40, 621 NV_50 = 0x50, 622 NV_C0 = 0xc0, 623}; 624 625struct drm_nouveau_private { 626 struct drm_device *dev; 627 bool noaccel; 628 629 /* the card type, takes NV_* as values */ 630 enum nouveau_card_type card_type; 631 /* exact chipset, derived from NV_PMC_BOOT_0 */ 632 int chipset; 633 int stepping; 634 int flags; 635 636 void __iomem *mmio; 637 638 spinlock_t ramin_lock; 639 void __iomem *ramin; 640 u32 ramin_size; 641 u32 ramin_base; 642 bool ramin_available; 643 struct drm_mm ramin_heap; 644 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 645 struct list_head gpuobj_list; 646 struct list_head classes; 647 648 struct nouveau_bo *vga_ram; 649 650 /* interrupt handling */ 651 void (*irq_handler[32])(struct drm_device *); 652 bool msi_enabled; 653 654 struct list_head vbl_waiting; 655 656 struct { 657 struct drm_global_reference mem_global_ref; 658 struct ttm_bo_global_ref bo_global_ref; 659 struct ttm_bo_device bdev; 660 atomic_t validate_sequence; 661 } ttm; 662 663 struct { 664 spinlock_t lock; 665 struct drm_mm heap; 666 struct nouveau_bo *bo; 667 } fence; 668 669 struct { 670 spinlock_t lock; 671 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 672 } channels; 673 674 struct nouveau_engine engine; 675 struct nouveau_channel *channel; 676 677 /* For PFIFO and PGRAPH. */ 678 spinlock_t context_switch_lock; 679 680 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 681 spinlock_t vm_lock; 682 683 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 684 struct nouveau_ramht *ramht; 685 struct nouveau_gpuobj *ramfc; 686 struct nouveau_gpuobj *ramro; 687 688 uint32_t ramin_rsvd_vram; 689 690 struct { 691 enum { 692 NOUVEAU_GART_NONE = 0, 693 NOUVEAU_GART_AGP, /* AGP */ 694 NOUVEAU_GART_PDMA, /* paged dma object */ 695 NOUVEAU_GART_HW /* on-chip gart/vm */ 696 } type; 697 uint64_t aper_base; 698 uint64_t aper_size; 699 uint64_t aper_free; 700 701 struct ttm_backend_func *func; 702 703 struct { 704 struct page *page; 705 dma_addr_t addr; 706 } dummy; 707 708 struct nouveau_gpuobj *sg_ctxdma; 709 } gart_info; 710 711 /* nv10-nv40 tiling regions */ 712 struct { 713 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 714 spinlock_t lock; 715 } tile; 716 717 /* VRAM/fb configuration */ 718 uint64_t vram_size; 719 uint64_t vram_sys_base; 720 u32 vram_rblock_size; 721 722 uint64_t fb_phys; 723 uint64_t fb_available_size; 724 uint64_t fb_mappable_pages; 725 uint64_t fb_aper_free; 726 int fb_mtrr; 727 728 /* BAR control (NV50-) */ 729 struct nouveau_vm *bar1_vm; 730 struct nouveau_vm *bar3_vm; 731 732 /* G8x/G9x virtual address space */ 733 struct nouveau_vm *chan_vm; 734 735 struct nvbios vbios; 736 737 struct nv04_mode_state mode_reg; 738 struct nv04_mode_state saved_reg; 739 uint32_t saved_vga_font[4][16384]; 740 uint32_t crtc_owner; 741 uint32_t dac_users[4]; 742 743 struct backlight_device *backlight; 744 745 struct { 746 struct dentry *channel_root; 747 } debugfs; 748 749 struct nouveau_fbdev *nfbdev; 750 struct apertures_struct *apertures; 751}; 752 753static inline struct drm_nouveau_private * 754nouveau_private(struct drm_device *dev) 755{ 756 return dev->dev_private; 757} 758 759static inline struct drm_nouveau_private * 760nouveau_bdev(struct ttm_bo_device *bd) 761{ 762 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 763} 764 765static inline int 766nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 767{ 768 struct nouveau_bo *prev; 769 770 if (!pnvbo) 771 return -EINVAL; 772 prev = *pnvbo; 773 774 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 775 if (prev) { 776 struct ttm_buffer_object *bo = &prev->bo; 777 778 ttm_bo_unref(&bo); 779 } 780 781 return 0; 782} 783 784/* nouveau_drv.c */ 785extern int nouveau_agpmode; 786extern int nouveau_duallink; 787extern int nouveau_uscript_lvds; 788extern int nouveau_uscript_tmds; 789extern int nouveau_vram_pushbuf; 790extern int nouveau_vram_notify; 791extern int nouveau_fbpercrtc; 792extern int nouveau_tv_disable; 793extern char *nouveau_tv_norm; 794extern int nouveau_reg_debug; 795extern char *nouveau_vbios; 796extern int nouveau_ignorelid; 797extern int nouveau_nofbaccel; 798extern int nouveau_noaccel; 799extern int nouveau_force_post; 800extern int nouveau_override_conntype; 801extern char *nouveau_perflvl; 802extern int nouveau_perflvl_wr; 803extern int nouveau_msi; 804extern int nouveau_ctxfw; 805 806extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 807extern int nouveau_pci_resume(struct pci_dev *pdev); 808 809/* nouveau_state.c */ 810extern int nouveau_open(struct drm_device *, struct drm_file *); 811extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 812extern void nouveau_postclose(struct drm_device *, struct drm_file *); 813extern int nouveau_load(struct drm_device *, unsigned long flags); 814extern int nouveau_firstopen(struct drm_device *); 815extern void nouveau_lastclose(struct drm_device *); 816extern int nouveau_unload(struct drm_device *); 817extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 818 struct drm_file *); 819extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 820 struct drm_file *); 821extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 822 uint32_t reg, uint32_t mask, uint32_t val); 823extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 824 uint32_t reg, uint32_t mask, uint32_t val); 825extern bool nouveau_wait_for_idle(struct drm_device *); 826extern int nouveau_card_init(struct drm_device *); 827 828/* nouveau_mem.c */ 829extern int nouveau_mem_vram_init(struct drm_device *); 830extern void nouveau_mem_vram_fini(struct drm_device *); 831extern int nouveau_mem_gart_init(struct drm_device *); 832extern void nouveau_mem_gart_fini(struct drm_device *); 833extern int nouveau_mem_init_agp(struct drm_device *); 834extern int nouveau_mem_reset_agp(struct drm_device *); 835extern void nouveau_mem_close(struct drm_device *); 836extern int nouveau_mem_detect(struct drm_device *); 837extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 838extern struct nouveau_tile_reg *nv10_mem_set_tiling( 839 struct drm_device *dev, uint32_t addr, uint32_t size, 840 uint32_t pitch, uint32_t flags); 841extern void nv10_mem_put_tile_region(struct drm_device *dev, 842 struct nouveau_tile_reg *tile, 843 struct nouveau_fence *fence); 844extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 845extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 846 847/* nouveau_notifier.c */ 848extern int nouveau_notifier_init_channel(struct nouveau_channel *); 849extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 850extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 851 int cout, uint32_t start, uint32_t end, 852 uint32_t *offset); 853extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 854extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 855 struct drm_file *); 856extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 857 struct drm_file *); 858 859/* nouveau_channel.c */ 860extern struct drm_ioctl_desc nouveau_ioctls[]; 861extern int nouveau_max_ioctl; 862extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 863extern int nouveau_channel_alloc(struct drm_device *dev, 864 struct nouveau_channel **chan, 865 struct drm_file *file_priv, 866 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 867extern struct nouveau_channel * 868nouveau_channel_get_unlocked(struct nouveau_channel *); 869extern struct nouveau_channel * 870nouveau_channel_get(struct drm_file *, int id); 871extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 872extern void nouveau_channel_put(struct nouveau_channel **); 873extern void nouveau_channel_ref(struct nouveau_channel *chan, 874 struct nouveau_channel **pchan); 875extern void nouveau_channel_idle(struct nouveau_channel *chan); 876 877/* nouveau_object.c */ 878#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 879 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 880 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 881} while (0) 882 883#define NVOBJ_ENGINE_DEL(d, e) do { \ 884 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 885 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 886} while (0) 887 888#define NVOBJ_CLASS(d, c, e) do { \ 889 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 890 if (ret) \ 891 return ret; \ 892} while (0) 893 894#define NVOBJ_MTHD(d, c, m, e) do { \ 895 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 896 if (ret) \ 897 return ret; \ 898} while (0) 899 900extern int nouveau_gpuobj_early_init(struct drm_device *); 901extern int nouveau_gpuobj_init(struct drm_device *); 902extern void nouveau_gpuobj_takedown(struct drm_device *); 903extern int nouveau_gpuobj_suspend(struct drm_device *dev); 904extern void nouveau_gpuobj_resume(struct drm_device *dev); 905extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 906extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 907 int (*exec)(struct nouveau_channel *, 908 u32 class, u32 mthd, u32 data)); 909extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 910extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 911extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 912 uint32_t vram_h, uint32_t tt_h); 913extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 914extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 915 uint32_t size, int align, uint32_t flags, 916 struct nouveau_gpuobj **); 917extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 918 struct nouveau_gpuobj **); 919extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 920 u32 size, u32 flags, 921 struct nouveau_gpuobj **); 922extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 923 uint64_t offset, uint64_t size, int access, 924 int target, struct nouveau_gpuobj **); 925extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 926extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 927 u64 size, int target, int access, u32 type, 928 u32 comp, struct nouveau_gpuobj **pobj); 929extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 930 int class, u64 base, u64 size, int target, 931 int access, u32 type, u32 comp); 932extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 933 struct drm_file *); 934extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 935 struct drm_file *); 936 937/* nouveau_irq.c */ 938extern int nouveau_irq_init(struct drm_device *); 939extern void nouveau_irq_fini(struct drm_device *); 940extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 941extern void nouveau_irq_register(struct drm_device *, int status_bit, 942 void (*)(struct drm_device *)); 943extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 944extern void nouveau_irq_preinstall(struct drm_device *); 945extern int nouveau_irq_postinstall(struct drm_device *); 946extern void nouveau_irq_uninstall(struct drm_device *); 947 948/* nouveau_sgdma.c */ 949extern int nouveau_sgdma_init(struct drm_device *); 950extern void nouveau_sgdma_takedown(struct drm_device *); 951extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 952 uint32_t offset); 953extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 954 955/* nouveau_debugfs.c */ 956#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 957extern int nouveau_debugfs_init(struct drm_minor *); 958extern void nouveau_debugfs_takedown(struct drm_minor *); 959extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 960extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 961#else 962static inline int 963nouveau_debugfs_init(struct drm_minor *minor) 964{ 965 return 0; 966} 967 968static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 969{ 970} 971 972static inline int 973nouveau_debugfs_channel_init(struct nouveau_channel *chan) 974{ 975 return 0; 976} 977 978static inline void 979nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 980{ 981} 982#endif 983 984/* nouveau_dma.c */ 985extern void nouveau_dma_pre_init(struct nouveau_channel *); 986extern int nouveau_dma_init(struct nouveau_channel *); 987extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 988 989/* nouveau_acpi.c */ 990#define ROM_BIOS_PAGE 4096 991#if defined(CONFIG_ACPI) 992void nouveau_register_dsm_handler(void); 993void nouveau_unregister_dsm_handler(void); 994int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 995bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 996int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 997#else 998static inline void nouveau_register_dsm_handler(void) {} 999static inline void nouveau_unregister_dsm_handler(void) {} 1000static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1001static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1002static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1003#endif 1004 1005/* nouveau_backlight.c */ 1006#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1007extern int nouveau_backlight_init(struct drm_connector *); 1008extern void nouveau_backlight_exit(struct drm_connector *); 1009#else 1010static inline int nouveau_backlight_init(struct drm_connector *dev) 1011{ 1012 return 0; 1013} 1014 1015static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1016#endif 1017 1018/* nouveau_bios.c */ 1019extern int nouveau_bios_init(struct drm_device *); 1020extern void nouveau_bios_takedown(struct drm_device *dev); 1021extern int nouveau_run_vbios_init(struct drm_device *); 1022extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1023 struct dcb_entry *); 1024extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1025 enum dcb_gpio_tag); 1026extern struct dcb_connector_table_entry * 1027nouveau_bios_connector_entry(struct drm_device *, int index); 1028extern u32 get_pll_register(struct drm_device *, enum pll_types); 1029extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1030 struct pll_lims *); 1031extern int nouveau_bios_run_display_table(struct drm_device *, 1032 struct dcb_entry *, 1033 uint32_t script, int pxclk); 1034extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1035 int *length); 1036extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1037extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1038extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1039 bool *dl, bool *if_is_24bit); 1040extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1041 int head, int pxclk); 1042extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1043 enum LVDS_script, int pxclk); 1044 1045/* nouveau_ttm.c */ 1046int nouveau_ttm_global_init(struct drm_nouveau_private *); 1047void nouveau_ttm_global_release(struct drm_nouveau_private *); 1048int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1049 1050/* nouveau_dp.c */ 1051int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1052 uint8_t *data, int data_nr); 1053bool nouveau_dp_detect(struct drm_encoder *); 1054bool nouveau_dp_link_train(struct drm_encoder *); 1055 1056/* nv04_fb.c */ 1057extern int nv04_fb_init(struct drm_device *); 1058extern void nv04_fb_takedown(struct drm_device *); 1059 1060/* nv10_fb.c */ 1061extern int nv10_fb_init(struct drm_device *); 1062extern void nv10_fb_takedown(struct drm_device *); 1063extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1064 uint32_t addr, uint32_t size, 1065 uint32_t pitch, uint32_t flags); 1066extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1067extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1068 1069/* nv30_fb.c */ 1070extern int nv30_fb_init(struct drm_device *); 1071extern void nv30_fb_takedown(struct drm_device *); 1072extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1073 uint32_t addr, uint32_t size, 1074 uint32_t pitch, uint32_t flags); 1075extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1076 1077/* nv40_fb.c */ 1078extern int nv40_fb_init(struct drm_device *); 1079extern void nv40_fb_takedown(struct drm_device *); 1080extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1081 1082/* nv50_fb.c */ 1083extern int nv50_fb_init(struct drm_device *); 1084extern void nv50_fb_takedown(struct drm_device *); 1085extern void nv50_fb_vm_trap(struct drm_device *, int display); 1086 1087/* nvc0_fb.c */ 1088extern int nvc0_fb_init(struct drm_device *); 1089extern void nvc0_fb_takedown(struct drm_device *); 1090 1091/* nv04_fifo.c */ 1092extern int nv04_fifo_init(struct drm_device *); 1093extern void nv04_fifo_fini(struct drm_device *); 1094extern void nv04_fifo_disable(struct drm_device *); 1095extern void nv04_fifo_enable(struct drm_device *); 1096extern bool nv04_fifo_reassign(struct drm_device *, bool); 1097extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1098extern int nv04_fifo_channel_id(struct drm_device *); 1099extern int nv04_fifo_create_context(struct nouveau_channel *); 1100extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1101extern int nv04_fifo_load_context(struct nouveau_channel *); 1102extern int nv04_fifo_unload_context(struct drm_device *); 1103extern void nv04_fifo_isr(struct drm_device *); 1104 1105/* nv10_fifo.c */ 1106extern int nv10_fifo_init(struct drm_device *); 1107extern int nv10_fifo_channel_id(struct drm_device *); 1108extern int nv10_fifo_create_context(struct nouveau_channel *); 1109extern int nv10_fifo_load_context(struct nouveau_channel *); 1110extern int nv10_fifo_unload_context(struct drm_device *); 1111 1112/* nv40_fifo.c */ 1113extern int nv40_fifo_init(struct drm_device *); 1114extern int nv40_fifo_create_context(struct nouveau_channel *); 1115extern int nv40_fifo_load_context(struct nouveau_channel *); 1116extern int nv40_fifo_unload_context(struct drm_device *); 1117 1118/* nv50_fifo.c */ 1119extern int nv50_fifo_init(struct drm_device *); 1120extern void nv50_fifo_takedown(struct drm_device *); 1121extern int nv50_fifo_channel_id(struct drm_device *); 1122extern int nv50_fifo_create_context(struct nouveau_channel *); 1123extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1124extern int nv50_fifo_load_context(struct nouveau_channel *); 1125extern int nv50_fifo_unload_context(struct drm_device *); 1126extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1127 1128/* nvc0_fifo.c */ 1129extern int nvc0_fifo_init(struct drm_device *); 1130extern void nvc0_fifo_takedown(struct drm_device *); 1131extern void nvc0_fifo_disable(struct drm_device *); 1132extern void nvc0_fifo_enable(struct drm_device *); 1133extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1134extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1135extern int nvc0_fifo_channel_id(struct drm_device *); 1136extern int nvc0_fifo_create_context(struct nouveau_channel *); 1137extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1138extern int nvc0_fifo_load_context(struct nouveau_channel *); 1139extern int nvc0_fifo_unload_context(struct drm_device *); 1140 1141/* nv04_graph.c */ 1142extern int nv04_graph_create(struct drm_device *); 1143extern void nv04_graph_fifo_access(struct drm_device *, bool); 1144extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1145extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1146 u32 class, u32 mthd, u32 data); 1147extern struct nouveau_bitfield nv04_graph_nsource[]; 1148 1149/* nv10_graph.c */ 1150extern int nv10_graph_create(struct drm_device *); 1151extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1152extern struct nouveau_bitfield nv10_graph_intr[]; 1153extern struct nouveau_bitfield nv10_graph_nstatus[]; 1154 1155/* nv20_graph.c */ 1156extern int nv20_graph_create(struct drm_device *); 1157 1158/* nv40_graph.c */ 1159extern int nv40_graph_create(struct drm_device *); 1160extern void nv40_grctx_init(struct nouveau_grctx *); 1161 1162/* nv50_graph.c */ 1163extern int nv50_graph_create(struct drm_device *); 1164extern int nv50_grctx_init(struct nouveau_grctx *); 1165extern struct nouveau_enum nv50_data_error_names[]; 1166extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1167 1168/* nvc0_graph.c */ 1169extern int nvc0_graph_create(struct drm_device *); 1170extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1171 1172/* nv84_crypt.c */ 1173extern int nv84_crypt_create(struct drm_device *); 1174 1175/* nva3_copy.c */ 1176extern int nva3_copy_create(struct drm_device *dev); 1177 1178/* nvc0_copy.c */ 1179extern int nvc0_copy_create(struct drm_device *dev, int engine); 1180 1181/* nv40_mpeg.c */ 1182extern int nv40_mpeg_create(struct drm_device *dev); 1183 1184/* nv50_mpeg.c */ 1185extern int nv50_mpeg_create(struct drm_device *dev); 1186 1187/* nv04_instmem.c */ 1188extern int nv04_instmem_init(struct drm_device *); 1189extern void nv04_instmem_takedown(struct drm_device *); 1190extern int nv04_instmem_suspend(struct drm_device *); 1191extern void nv04_instmem_resume(struct drm_device *); 1192extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1193 u32 size, u32 align); 1194extern void nv04_instmem_put(struct nouveau_gpuobj *); 1195extern int nv04_instmem_map(struct nouveau_gpuobj *); 1196extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1197extern void nv04_instmem_flush(struct drm_device *); 1198 1199/* nv50_instmem.c */ 1200extern int nv50_instmem_init(struct drm_device *); 1201extern void nv50_instmem_takedown(struct drm_device *); 1202extern int nv50_instmem_suspend(struct drm_device *); 1203extern void nv50_instmem_resume(struct drm_device *); 1204extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1205 u32 size, u32 align); 1206extern void nv50_instmem_put(struct nouveau_gpuobj *); 1207extern int nv50_instmem_map(struct nouveau_gpuobj *); 1208extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1209extern void nv50_instmem_flush(struct drm_device *); 1210extern void nv84_instmem_flush(struct drm_device *); 1211 1212/* nvc0_instmem.c */ 1213extern int nvc0_instmem_init(struct drm_device *); 1214extern void nvc0_instmem_takedown(struct drm_device *); 1215extern int nvc0_instmem_suspend(struct drm_device *); 1216extern void nvc0_instmem_resume(struct drm_device *); 1217 1218/* nv04_mc.c */ 1219extern int nv04_mc_init(struct drm_device *); 1220extern void nv04_mc_takedown(struct drm_device *); 1221 1222/* nv40_mc.c */ 1223extern int nv40_mc_init(struct drm_device *); 1224extern void nv40_mc_takedown(struct drm_device *); 1225 1226/* nv50_mc.c */ 1227extern int nv50_mc_init(struct drm_device *); 1228extern void nv50_mc_takedown(struct drm_device *); 1229 1230/* nv04_timer.c */ 1231extern int nv04_timer_init(struct drm_device *); 1232extern uint64_t nv04_timer_read(struct drm_device *); 1233extern void nv04_timer_takedown(struct drm_device *); 1234 1235extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1236 unsigned long arg); 1237 1238/* nv04_dac.c */ 1239extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1240extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1241extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1242extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1243extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1244 1245/* nv04_dfp.c */ 1246extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1247extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1248extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1249 int head, bool dl); 1250extern void nv04_dfp_disable(struct drm_device *dev, int head); 1251extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1252 1253/* nv04_tv.c */ 1254extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1255extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1256 1257/* nv17_tv.c */ 1258extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1259 1260/* nv04_display.c */ 1261extern int nv04_display_early_init(struct drm_device *); 1262extern void nv04_display_late_takedown(struct drm_device *); 1263extern int nv04_display_create(struct drm_device *); 1264extern int nv04_display_init(struct drm_device *); 1265extern void nv04_display_destroy(struct drm_device *); 1266 1267/* nv04_crtc.c */ 1268extern int nv04_crtc_create(struct drm_device *, int index); 1269 1270/* nouveau_bo.c */ 1271extern struct ttm_bo_driver nouveau_bo_driver; 1272extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1273 int size, int align, uint32_t flags, 1274 uint32_t tile_mode, uint32_t tile_flags, 1275 struct nouveau_bo **); 1276extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1277extern int nouveau_bo_unpin(struct nouveau_bo *); 1278extern int nouveau_bo_map(struct nouveau_bo *); 1279extern void nouveau_bo_unmap(struct nouveau_bo *); 1280extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1281 uint32_t busy); 1282extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1283extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1284extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1285extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1286extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1287extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1288 bool no_wait_reserve, bool no_wait_gpu); 1289 1290extern struct nouveau_vma * 1291nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1292extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1293 struct nouveau_vma *); 1294extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1295 1296/* nouveau_fence.c */ 1297struct nouveau_fence; 1298extern int nouveau_fence_init(struct drm_device *); 1299extern void nouveau_fence_fini(struct drm_device *); 1300extern int nouveau_fence_channel_init(struct nouveau_channel *); 1301extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1302extern void nouveau_fence_update(struct nouveau_channel *); 1303extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1304 bool emit); 1305extern int nouveau_fence_emit(struct nouveau_fence *); 1306extern void nouveau_fence_work(struct nouveau_fence *fence, 1307 void (*work)(void *priv, bool signalled), 1308 void *priv); 1309struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1310 1311extern bool __nouveau_fence_signalled(void *obj, void *arg); 1312extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1313extern int __nouveau_fence_flush(void *obj, void *arg); 1314extern void __nouveau_fence_unref(void **obj); 1315extern void *__nouveau_fence_ref(void *obj); 1316 1317static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1318{ 1319 return __nouveau_fence_signalled(obj, NULL); 1320} 1321static inline int 1322nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1323{ 1324 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1325} 1326extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1327static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1328{ 1329 return __nouveau_fence_flush(obj, NULL); 1330} 1331static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1332{ 1333 __nouveau_fence_unref((void **)obj); 1334} 1335static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1336{ 1337 return __nouveau_fence_ref(obj); 1338} 1339 1340/* nouveau_gem.c */ 1341extern int nouveau_gem_new(struct drm_device *, int size, int align, 1342 uint32_t domain, uint32_t tile_mode, 1343 uint32_t tile_flags, struct nouveau_bo **); 1344extern int nouveau_gem_object_new(struct drm_gem_object *); 1345extern void nouveau_gem_object_del(struct drm_gem_object *); 1346extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1347extern void nouveau_gem_object_close(struct drm_gem_object *, 1348 struct drm_file *); 1349extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1350 struct drm_file *); 1351extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1352 struct drm_file *); 1353extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1354 struct drm_file *); 1355extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1356 struct drm_file *); 1357extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1358 struct drm_file *); 1359 1360/* nouveau_display.c */ 1361int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1362void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1363int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1364 struct drm_pending_vblank_event *event); 1365int nouveau_finish_page_flip(struct nouveau_channel *, 1366 struct nouveau_page_flip_state *); 1367 1368/* nv10_gpio.c */ 1369int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1370int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1371 1372/* nv50_gpio.c */ 1373int nv50_gpio_init(struct drm_device *dev); 1374void nv50_gpio_fini(struct drm_device *dev); 1375int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1376int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1377int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1378 void (*)(void *, int), void *); 1379void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1380 void (*)(void *, int), void *); 1381bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1382 1383/* nv50_calc. */ 1384int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1385 int *N1, int *M1, int *N2, int *M2, int *P); 1386int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1387 int clk, int *N, int *fN, int *M, int *P); 1388 1389#ifndef ioread32_native 1390#ifdef __BIG_ENDIAN 1391#define ioread16_native ioread16be 1392#define iowrite16_native iowrite16be 1393#define ioread32_native ioread32be 1394#define iowrite32_native iowrite32be 1395#else /* def __BIG_ENDIAN */ 1396#define ioread16_native ioread16 1397#define iowrite16_native iowrite16 1398#define ioread32_native ioread32 1399#define iowrite32_native iowrite32 1400#endif /* def __BIG_ENDIAN else */ 1401#endif /* !ioread32_native */ 1402 1403/* channel control reg access */ 1404static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1405{ 1406 return ioread32_native(chan->user + reg); 1407} 1408 1409static inline void nvchan_wr32(struct nouveau_channel *chan, 1410 unsigned reg, u32 val) 1411{ 1412 iowrite32_native(val, chan->user + reg); 1413} 1414 1415/* register access */ 1416static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1417{ 1418 struct drm_nouveau_private *dev_priv = dev->dev_private; 1419 return ioread32_native(dev_priv->mmio + reg); 1420} 1421 1422static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1423{ 1424 struct drm_nouveau_private *dev_priv = dev->dev_private; 1425 iowrite32_native(val, dev_priv->mmio + reg); 1426} 1427 1428static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1429{ 1430 u32 tmp = nv_rd32(dev, reg); 1431 nv_wr32(dev, reg, (tmp & ~mask) | val); 1432 return tmp; 1433} 1434 1435static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1436{ 1437 struct drm_nouveau_private *dev_priv = dev->dev_private; 1438 return ioread8(dev_priv->mmio + reg); 1439} 1440 1441static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1442{ 1443 struct drm_nouveau_private *dev_priv = dev->dev_private; 1444 iowrite8(val, dev_priv->mmio + reg); 1445} 1446 1447#define nv_wait(dev, reg, mask, val) \ 1448 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1449#define nv_wait_ne(dev, reg, mask, val) \ 1450 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1451 1452/* PRAMIN access */ 1453static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1454{ 1455 struct drm_nouveau_private *dev_priv = dev->dev_private; 1456 return ioread32_native(dev_priv->ramin + offset); 1457} 1458 1459static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1460{ 1461 struct drm_nouveau_private *dev_priv = dev->dev_private; 1462 iowrite32_native(val, dev_priv->ramin + offset); 1463} 1464 1465/* object access */ 1466extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1467extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1468 1469/* 1470 * Logging 1471 * Argument d is (struct drm_device *). 1472 */ 1473#define NV_PRINTK(level, d, fmt, arg...) \ 1474 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1475 pci_name(d->pdev), ##arg) 1476#ifndef NV_DEBUG_NOTRACE 1477#define NV_DEBUG(d, fmt, arg...) do { \ 1478 if (drm_debug & DRM_UT_DRIVER) { \ 1479 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1480 __LINE__, ##arg); \ 1481 } \ 1482} while (0) 1483#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1484 if (drm_debug & DRM_UT_KMS) { \ 1485 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1486 __LINE__, ##arg); \ 1487 } \ 1488} while (0) 1489#else 1490#define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) \ 1492 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1493} while (0) 1494#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1495 if (drm_debug & DRM_UT_KMS) \ 1496 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1497} while (0) 1498#endif 1499#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1500#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1501#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1502#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1503#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1504 1505/* nouveau_reg_debug bitmask */ 1506enum { 1507 NOUVEAU_REG_DEBUG_MC = 0x1, 1508 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1509 NOUVEAU_REG_DEBUG_FB = 0x4, 1510 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1511 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1512 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1513 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1514 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1515 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1516 NOUVEAU_REG_DEBUG_EVO = 0x200, 1517}; 1518 1519#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1520 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1521 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1522} while (0) 1523 1524static inline bool 1525nv_two_heads(struct drm_device *dev) 1526{ 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 const int impl = dev->pci_device & 0x0ff0; 1529 1530 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1531 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1532 return true; 1533 1534 return false; 1535} 1536 1537static inline bool 1538nv_gf4_disp_arch(struct drm_device *dev) 1539{ 1540 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1541} 1542 1543static inline bool 1544nv_two_reg_pll(struct drm_device *dev) 1545{ 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 const int impl = dev->pci_device & 0x0ff0; 1548 1549 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1550 return true; 1551 return false; 1552} 1553 1554static inline bool 1555nv_match_device(struct drm_device *dev, unsigned device, 1556 unsigned sub_vendor, unsigned sub_device) 1557{ 1558 return dev->pdev->device == device && 1559 dev->pdev->subsystem_vendor == sub_vendor && 1560 dev->pdev->subsystem_device == sub_device; 1561} 1562 1563static inline void * 1564nv_engine(struct drm_device *dev, int engine) 1565{ 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 return (void *)dev_priv->eng[engine]; 1568} 1569 1570/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1571 * helpful to determine a number of other hardware features 1572 */ 1573static inline int 1574nv44_graph_class(struct drm_device *dev) 1575{ 1576 struct drm_nouveau_private *dev_priv = dev->dev_private; 1577 1578 if ((dev_priv->chipset & 0xf0) == 0x60) 1579 return 1; 1580 1581 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1582} 1583 1584/* memory type/access flags, do not match hardware values */ 1585#define NV_MEM_ACCESS_RO 1 1586#define NV_MEM_ACCESS_WO 2 1587#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1588#define NV_MEM_ACCESS_SYS 4 1589#define NV_MEM_ACCESS_VM 8 1590 1591#define NV_MEM_TARGET_VRAM 0 1592#define NV_MEM_TARGET_PCI 1 1593#define NV_MEM_TARGET_PCI_NOSNOOP 2 1594#define NV_MEM_TARGET_VM 3 1595#define NV_MEM_TARGET_GART 4 1596 1597#define NV_MEM_TYPE_VM 0x7f 1598#define NV_MEM_COMP_VM 0x03 1599 1600/* NV_SW object class */ 1601#define NV_SW 0x0000506e 1602#define NV_SW_DMA_SEMAPHORE 0x00000060 1603#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1604#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1605#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1606#define NV_SW_YIELD 0x00000080 1607#define NV_SW_DMA_VBLSEM 0x0000018c 1608#define NV_SW_VBLSEM_OFFSET 0x00000400 1609#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1610#define NV_SW_VBLSEM_RELEASE 0x00000408 1611#define NV_SW_PAGE_FLIP 0x00000500 1612 1613#endif /* __NOUVEAU_DRV_H__ */ 1614