nouveau_drv.h revision d81c19e312a22bdcebef1370f3af30a146670787
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435struct nouveau_pm_memtiming { 436 int id; 437 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 438 u32 reg_1; 439 u32 reg_2; 440 u32 reg_3; 441 u32 reg_4; 442 u32 reg_5; 443 u32 reg_6; 444 u32 reg_7; 445 u32 reg_8; 446 /* To be written to 0x1002c0 */ 447 u8 CL; 448 u8 WR; 449}; 450 451struct nouveau_pm_tbl_header{ 452 u8 version; 453 u8 header_len; 454 u8 entry_cnt; 455 u8 entry_len; 456}; 457 458struct nouveau_pm_tbl_entry{ 459 u8 tWR; 460 u8 tUNK_1; 461 u8 tCL; 462 u8 tRP; /* Byte 3 */ 463 u8 empty_4; 464 u8 tRAS; /* Byte 5 */ 465 u8 empty_6; 466 u8 tRFC; /* Byte 7 */ 467 u8 empty_8; 468 u8 tRC; /* Byte 9 */ 469 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 470 u8 empty_15,empty_16,empty_17; 471 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 472}; 473 474/* nouveau_mem.c */ 475void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 476 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 477 struct nouveau_pm_memtiming *timing); 478 479#define NOUVEAU_PM_MAX_LEVEL 8 480struct nouveau_pm_level { 481 struct device_attribute dev_attr; 482 char name[32]; 483 int id; 484 485 u32 core; 486 u32 memory; 487 u32 shader; 488 u32 rop; 489 u32 copy; 490 u32 daemon; 491 u32 vdec; 492 u32 dom6; 493 u32 unka0; /* nva3:nvc0 */ 494 u32 hub01; /* nvc0- */ 495 u32 hub06; /* nvc0- */ 496 u32 hub07; /* nvc0- */ 497 498 u32 volt_min; /* microvolts */ 499 u32 volt_max; 500 u8 fanspeed; 501 502 u16 memscript; 503 struct nouveau_pm_memtiming *timing; 504}; 505 506struct nouveau_pm_temp_sensor_constants { 507 u16 offset_constant; 508 s16 offset_mult; 509 s16 offset_div; 510 s16 slope_mult; 511 s16 slope_div; 512}; 513 514struct nouveau_pm_threshold_temp { 515 s16 critical; 516 s16 down_clock; 517 s16 fan_boost; 518}; 519 520struct nouveau_pm_memtimings { 521 bool supported; 522 struct nouveau_pm_memtiming *timing; 523 int nr_timing; 524}; 525 526struct nouveau_pm_fan { 527 u32 min_duty; 528 u32 max_duty; 529 u32 pwm_freq; 530}; 531 532struct nouveau_pm_engine { 533 struct nouveau_pm_voltage voltage; 534 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 535 int nr_perflvl; 536 struct nouveau_pm_memtimings memtimings; 537 struct nouveau_pm_temp_sensor_constants sensor_constants; 538 struct nouveau_pm_threshold_temp threshold_temp; 539 struct nouveau_pm_fan fan; 540 u32 pwm_divisor; 541 542 struct nouveau_pm_level boot; 543 struct nouveau_pm_level *cur; 544 545 struct device *hwmon; 546 struct notifier_block acpi_nb; 547 548 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 549 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 550 int (*clocks_set)(struct drm_device *, void *); 551 552 int (*voltage_get)(struct drm_device *); 553 int (*voltage_set)(struct drm_device *, int voltage); 554 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 555 int (*pwm_set)(struct drm_device *, int line, u32, u32); 556 int (*temp_get)(struct drm_device *); 557}; 558 559struct nouveau_vram_engine { 560 struct nouveau_mm mm; 561 562 int (*init)(struct drm_device *); 563 void (*takedown)(struct drm_device *dev); 564 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 565 u32 type, struct nouveau_mem **); 566 void (*put)(struct drm_device *, struct nouveau_mem **); 567 568 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 569}; 570 571struct nouveau_engine { 572 struct nouveau_instmem_engine instmem; 573 struct nouveau_mc_engine mc; 574 struct nouveau_timer_engine timer; 575 struct nouveau_fb_engine fb; 576 struct nouveau_fifo_engine fifo; 577 struct nouveau_display_engine display; 578 struct nouveau_gpio_engine gpio; 579 struct nouveau_pm_engine pm; 580 struct nouveau_vram_engine vram; 581}; 582 583struct nouveau_pll_vals { 584 union { 585 struct { 586#ifdef __BIG_ENDIAN 587 uint8_t N1, M1, N2, M2; 588#else 589 uint8_t M1, N1, M2, N2; 590#endif 591 }; 592 struct { 593 uint16_t NM1, NM2; 594 } __attribute__((packed)); 595 }; 596 int log2P; 597 598 int refclk; 599}; 600 601enum nv04_fp_display_regs { 602 FP_DISPLAY_END, 603 FP_TOTAL, 604 FP_CRTC, 605 FP_SYNC_START, 606 FP_SYNC_END, 607 FP_VALID_START, 608 FP_VALID_END 609}; 610 611struct nv04_crtc_reg { 612 unsigned char MiscOutReg; 613 uint8_t CRTC[0xa0]; 614 uint8_t CR58[0x10]; 615 uint8_t Sequencer[5]; 616 uint8_t Graphics[9]; 617 uint8_t Attribute[21]; 618 unsigned char DAC[768]; 619 620 /* PCRTC regs */ 621 uint32_t fb_start; 622 uint32_t crtc_cfg; 623 uint32_t cursor_cfg; 624 uint32_t gpio_ext; 625 uint32_t crtc_830; 626 uint32_t crtc_834; 627 uint32_t crtc_850; 628 uint32_t crtc_eng_ctrl; 629 630 /* PRAMDAC regs */ 631 uint32_t nv10_cursync; 632 struct nouveau_pll_vals pllvals; 633 uint32_t ramdac_gen_ctrl; 634 uint32_t ramdac_630; 635 uint32_t ramdac_634; 636 uint32_t tv_setup; 637 uint32_t tv_vtotal; 638 uint32_t tv_vskew; 639 uint32_t tv_vsync_delay; 640 uint32_t tv_htotal; 641 uint32_t tv_hskew; 642 uint32_t tv_hsync_delay; 643 uint32_t tv_hsync_delay2; 644 uint32_t fp_horiz_regs[7]; 645 uint32_t fp_vert_regs[7]; 646 uint32_t dither; 647 uint32_t fp_control; 648 uint32_t dither_regs[6]; 649 uint32_t fp_debug_0; 650 uint32_t fp_debug_1; 651 uint32_t fp_debug_2; 652 uint32_t fp_margin_color; 653 uint32_t ramdac_8c0; 654 uint32_t ramdac_a20; 655 uint32_t ramdac_a24; 656 uint32_t ramdac_a34; 657 uint32_t ctv_regs[38]; 658}; 659 660struct nv04_output_reg { 661 uint32_t output; 662 int head; 663}; 664 665struct nv04_mode_state { 666 struct nv04_crtc_reg crtc_reg[2]; 667 uint32_t pllsel; 668 uint32_t sel_clk; 669}; 670 671enum nouveau_card_type { 672 NV_04 = 0x00, 673 NV_10 = 0x10, 674 NV_20 = 0x20, 675 NV_30 = 0x30, 676 NV_40 = 0x40, 677 NV_50 = 0x50, 678 NV_C0 = 0xc0, 679 NV_D0 = 0xd0 680}; 681 682struct drm_nouveau_private { 683 struct drm_device *dev; 684 bool noaccel; 685 686 /* the card type, takes NV_* as values */ 687 enum nouveau_card_type card_type; 688 /* exact chipset, derived from NV_PMC_BOOT_0 */ 689 int chipset; 690 int flags; 691 u32 crystal; 692 693 void __iomem *mmio; 694 695 spinlock_t ramin_lock; 696 void __iomem *ramin; 697 u32 ramin_size; 698 u32 ramin_base; 699 bool ramin_available; 700 struct drm_mm ramin_heap; 701 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 702 struct list_head gpuobj_list; 703 struct list_head classes; 704 705 struct nouveau_bo *vga_ram; 706 707 /* interrupt handling */ 708 void (*irq_handler[32])(struct drm_device *); 709 bool msi_enabled; 710 711 struct list_head vbl_waiting; 712 713 struct { 714 struct drm_global_reference mem_global_ref; 715 struct ttm_bo_global_ref bo_global_ref; 716 struct ttm_bo_device bdev; 717 atomic_t validate_sequence; 718 } ttm; 719 720 struct { 721 spinlock_t lock; 722 struct drm_mm heap; 723 struct nouveau_bo *bo; 724 } fence; 725 726 struct { 727 spinlock_t lock; 728 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 729 } channels; 730 731 struct nouveau_engine engine; 732 struct nouveau_channel *channel; 733 734 /* For PFIFO and PGRAPH. */ 735 spinlock_t context_switch_lock; 736 737 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 738 spinlock_t vm_lock; 739 740 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 741 struct nouveau_ramht *ramht; 742 struct nouveau_gpuobj *ramfc; 743 struct nouveau_gpuobj *ramro; 744 745 uint32_t ramin_rsvd_vram; 746 747 struct { 748 enum { 749 NOUVEAU_GART_NONE = 0, 750 NOUVEAU_GART_AGP, /* AGP */ 751 NOUVEAU_GART_PDMA, /* paged dma object */ 752 NOUVEAU_GART_HW /* on-chip gart/vm */ 753 } type; 754 uint64_t aper_base; 755 uint64_t aper_size; 756 uint64_t aper_free; 757 758 struct ttm_backend_func *func; 759 760 struct { 761 struct page *page; 762 dma_addr_t addr; 763 } dummy; 764 765 struct nouveau_gpuobj *sg_ctxdma; 766 } gart_info; 767 768 /* nv10-nv40 tiling regions */ 769 struct { 770 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 771 spinlock_t lock; 772 } tile; 773 774 /* VRAM/fb configuration */ 775 enum { 776 NV_MEM_TYPE_UNKNOWN = 0, 777 NV_MEM_TYPE_STOLEN, 778 NV_MEM_TYPE_SGRAM, 779 NV_MEM_TYPE_SDRAM, 780 NV_MEM_TYPE_DDR1, 781 NV_MEM_TYPE_DDR2, 782 NV_MEM_TYPE_DDR3, 783 NV_MEM_TYPE_GDDR2, 784 NV_MEM_TYPE_GDDR3, 785 NV_MEM_TYPE_GDDR4, 786 NV_MEM_TYPE_GDDR5 787 } vram_type; 788 uint64_t vram_size; 789 uint64_t vram_sys_base; 790 791 uint64_t fb_available_size; 792 uint64_t fb_mappable_pages; 793 uint64_t fb_aper_free; 794 int fb_mtrr; 795 796 /* BAR control (NV50-) */ 797 struct nouveau_vm *bar1_vm; 798 struct nouveau_vm *bar3_vm; 799 800 /* G8x/G9x virtual address space */ 801 struct nouveau_vm *chan_vm; 802 803 struct nvbios vbios; 804 u8 *mxms; 805 struct list_head i2c_ports; 806 807 struct nv04_mode_state mode_reg; 808 struct nv04_mode_state saved_reg; 809 uint32_t saved_vga_font[4][16384]; 810 uint32_t crtc_owner; 811 uint32_t dac_users[4]; 812 813 struct backlight_device *backlight; 814 815 struct { 816 struct dentry *channel_root; 817 } debugfs; 818 819 struct nouveau_fbdev *nfbdev; 820 struct apertures_struct *apertures; 821}; 822 823static inline struct drm_nouveau_private * 824nouveau_private(struct drm_device *dev) 825{ 826 return dev->dev_private; 827} 828 829static inline struct drm_nouveau_private * 830nouveau_bdev(struct ttm_bo_device *bd) 831{ 832 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 833} 834 835static inline int 836nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 837{ 838 struct nouveau_bo *prev; 839 840 if (!pnvbo) 841 return -EINVAL; 842 prev = *pnvbo; 843 844 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 845 if (prev) { 846 struct ttm_buffer_object *bo = &prev->bo; 847 848 ttm_bo_unref(&bo); 849 } 850 851 return 0; 852} 853 854/* nouveau_drv.c */ 855extern int nouveau_modeset; 856extern int nouveau_agpmode; 857extern int nouveau_duallink; 858extern int nouveau_uscript_lvds; 859extern int nouveau_uscript_tmds; 860extern int nouveau_vram_pushbuf; 861extern int nouveau_vram_notify; 862extern char *nouveau_vram_type; 863extern int nouveau_fbpercrtc; 864extern int nouveau_tv_disable; 865extern char *nouveau_tv_norm; 866extern int nouveau_reg_debug; 867extern char *nouveau_vbios; 868extern int nouveau_ignorelid; 869extern int nouveau_nofbaccel; 870extern int nouveau_noaccel; 871extern int nouveau_force_post; 872extern int nouveau_override_conntype; 873extern char *nouveau_perflvl; 874extern int nouveau_perflvl_wr; 875extern int nouveau_msi; 876extern int nouveau_ctxfw; 877extern int nouveau_mxmdcb; 878 879extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 880extern int nouveau_pci_resume(struct pci_dev *pdev); 881 882/* nouveau_state.c */ 883extern int nouveau_open(struct drm_device *, struct drm_file *); 884extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 885extern void nouveau_postclose(struct drm_device *, struct drm_file *); 886extern int nouveau_load(struct drm_device *, unsigned long flags); 887extern int nouveau_firstopen(struct drm_device *); 888extern void nouveau_lastclose(struct drm_device *); 889extern int nouveau_unload(struct drm_device *); 890extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 891 struct drm_file *); 892extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 893 struct drm_file *); 894extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 895 uint32_t reg, uint32_t mask, uint32_t val); 896extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 897 uint32_t reg, uint32_t mask, uint32_t val); 898extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 899 bool (*cond)(void *), void *); 900extern bool nouveau_wait_for_idle(struct drm_device *); 901extern int nouveau_card_init(struct drm_device *); 902 903/* nouveau_mem.c */ 904extern int nouveau_mem_vram_init(struct drm_device *); 905extern void nouveau_mem_vram_fini(struct drm_device *); 906extern int nouveau_mem_gart_init(struct drm_device *); 907extern void nouveau_mem_gart_fini(struct drm_device *); 908extern int nouveau_mem_init_agp(struct drm_device *); 909extern int nouveau_mem_reset_agp(struct drm_device *); 910extern void nouveau_mem_close(struct drm_device *); 911extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 912extern struct nouveau_tile_reg *nv10_mem_set_tiling( 913 struct drm_device *dev, uint32_t addr, uint32_t size, 914 uint32_t pitch, uint32_t flags); 915extern void nv10_mem_put_tile_region(struct drm_device *dev, 916 struct nouveau_tile_reg *tile, 917 struct nouveau_fence *fence); 918extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 919extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 920 921/* nouveau_notifier.c */ 922extern int nouveau_notifier_init_channel(struct nouveau_channel *); 923extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 924extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 925 int cout, uint32_t start, uint32_t end, 926 uint32_t *offset); 927extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 928extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 929 struct drm_file *); 930extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 931 struct drm_file *); 932 933/* nouveau_channel.c */ 934extern struct drm_ioctl_desc nouveau_ioctls[]; 935extern int nouveau_max_ioctl; 936extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 937extern int nouveau_channel_alloc(struct drm_device *dev, 938 struct nouveau_channel **chan, 939 struct drm_file *file_priv, 940 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 941extern struct nouveau_channel * 942nouveau_channel_get_unlocked(struct nouveau_channel *); 943extern struct nouveau_channel * 944nouveau_channel_get(struct drm_file *, int id); 945extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 946extern void nouveau_channel_put(struct nouveau_channel **); 947extern void nouveau_channel_ref(struct nouveau_channel *chan, 948 struct nouveau_channel **pchan); 949extern void nouveau_channel_idle(struct nouveau_channel *chan); 950 951/* nouveau_object.c */ 952#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 953 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 954 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 955} while (0) 956 957#define NVOBJ_ENGINE_DEL(d, e) do { \ 958 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 959 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 960} while (0) 961 962#define NVOBJ_CLASS(d, c, e) do { \ 963 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 964 if (ret) \ 965 return ret; \ 966} while (0) 967 968#define NVOBJ_MTHD(d, c, m, e) do { \ 969 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 970 if (ret) \ 971 return ret; \ 972} while (0) 973 974extern int nouveau_gpuobj_early_init(struct drm_device *); 975extern int nouveau_gpuobj_init(struct drm_device *); 976extern void nouveau_gpuobj_takedown(struct drm_device *); 977extern int nouveau_gpuobj_suspend(struct drm_device *dev); 978extern void nouveau_gpuobj_resume(struct drm_device *dev); 979extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 980extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 981 int (*exec)(struct nouveau_channel *, 982 u32 class, u32 mthd, u32 data)); 983extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 984extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 985extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 986 uint32_t vram_h, uint32_t tt_h); 987extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 988extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 989 uint32_t size, int align, uint32_t flags, 990 struct nouveau_gpuobj **); 991extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 992 struct nouveau_gpuobj **); 993extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 994 u32 size, u32 flags, 995 struct nouveau_gpuobj **); 996extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 997 uint64_t offset, uint64_t size, int access, 998 int target, struct nouveau_gpuobj **); 999extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1000extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1001 u64 size, int target, int access, u32 type, 1002 u32 comp, struct nouveau_gpuobj **pobj); 1003extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1004 int class, u64 base, u64 size, int target, 1005 int access, u32 type, u32 comp); 1006extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1007 struct drm_file *); 1008extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1009 struct drm_file *); 1010 1011/* nouveau_irq.c */ 1012extern int nouveau_irq_init(struct drm_device *); 1013extern void nouveau_irq_fini(struct drm_device *); 1014extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1015extern void nouveau_irq_register(struct drm_device *, int status_bit, 1016 void (*)(struct drm_device *)); 1017extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1018extern void nouveau_irq_preinstall(struct drm_device *); 1019extern int nouveau_irq_postinstall(struct drm_device *); 1020extern void nouveau_irq_uninstall(struct drm_device *); 1021 1022/* nouveau_sgdma.c */ 1023extern int nouveau_sgdma_init(struct drm_device *); 1024extern void nouveau_sgdma_takedown(struct drm_device *); 1025extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1026 uint32_t offset); 1027extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1028 unsigned long size, 1029 uint32_t page_flags, 1030 struct page *dummy_read_page); 1031 1032/* nouveau_debugfs.c */ 1033#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1034extern int nouveau_debugfs_init(struct drm_minor *); 1035extern void nouveau_debugfs_takedown(struct drm_minor *); 1036extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1037extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1038#else 1039static inline int 1040nouveau_debugfs_init(struct drm_minor *minor) 1041{ 1042 return 0; 1043} 1044 1045static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1046{ 1047} 1048 1049static inline int 1050nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1051{ 1052 return 0; 1053} 1054 1055static inline void 1056nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1057{ 1058} 1059#endif 1060 1061/* nouveau_dma.c */ 1062extern void nouveau_dma_pre_init(struct nouveau_channel *); 1063extern int nouveau_dma_init(struct nouveau_channel *); 1064extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1065 1066/* nouveau_acpi.c */ 1067#define ROM_BIOS_PAGE 4096 1068#if defined(CONFIG_ACPI) 1069void nouveau_register_dsm_handler(void); 1070void nouveau_unregister_dsm_handler(void); 1071void nouveau_switcheroo_optimus_dsm(void); 1072int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1073bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1074int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1075#else 1076static inline void nouveau_register_dsm_handler(void) {} 1077static inline void nouveau_unregister_dsm_handler(void) {} 1078static inline void nouveau_switcheroo_optimus_dsm(void) {} 1079static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1080static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1081static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1082#endif 1083 1084/* nouveau_backlight.c */ 1085#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1086extern int nouveau_backlight_init(struct drm_device *); 1087extern void nouveau_backlight_exit(struct drm_device *); 1088#else 1089static inline int nouveau_backlight_init(struct drm_device *dev) 1090{ 1091 return 0; 1092} 1093 1094static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1095#endif 1096 1097/* nouveau_bios.c */ 1098extern int nouveau_bios_init(struct drm_device *); 1099extern void nouveau_bios_takedown(struct drm_device *dev); 1100extern int nouveau_run_vbios_init(struct drm_device *); 1101extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1102 struct dcb_entry *, int crtc); 1103extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1104extern struct dcb_connector_table_entry * 1105nouveau_bios_connector_entry(struct drm_device *, int index); 1106extern u32 get_pll_register(struct drm_device *, enum pll_types); 1107extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1108 struct pll_lims *); 1109extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1110 struct dcb_entry *, int crtc); 1111extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1112extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1113extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1114 bool *dl, bool *if_is_24bit); 1115extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1116 int head, int pxclk); 1117extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1118 enum LVDS_script, int pxclk); 1119bool bios_encoder_match(struct dcb_entry *, u32 hash); 1120 1121/* nouveau_mxm.c */ 1122int nouveau_mxm_init(struct drm_device *dev); 1123void nouveau_mxm_fini(struct drm_device *dev); 1124 1125/* nouveau_ttm.c */ 1126int nouveau_ttm_global_init(struct drm_nouveau_private *); 1127void nouveau_ttm_global_release(struct drm_nouveau_private *); 1128int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1129 1130/* nouveau_hdmi.c */ 1131void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1132 1133/* nouveau_dp.c */ 1134int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1135 uint8_t *data, int data_nr); 1136bool nouveau_dp_detect(struct drm_encoder *); 1137bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1138void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1139u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1140 1141/* nv04_fb.c */ 1142extern int nv04_fb_vram_init(struct drm_device *); 1143extern int nv04_fb_init(struct drm_device *); 1144extern void nv04_fb_takedown(struct drm_device *); 1145 1146/* nv10_fb.c */ 1147extern int nv10_fb_vram_init(struct drm_device *dev); 1148extern int nv1a_fb_vram_init(struct drm_device *dev); 1149extern int nv10_fb_init(struct drm_device *); 1150extern void nv10_fb_takedown(struct drm_device *); 1151extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1152 uint32_t addr, uint32_t size, 1153 uint32_t pitch, uint32_t flags); 1154extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1155extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1156 1157/* nv20_fb.c */ 1158extern int nv20_fb_vram_init(struct drm_device *dev); 1159extern int nv20_fb_init(struct drm_device *); 1160extern void nv20_fb_takedown(struct drm_device *); 1161extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1162 uint32_t addr, uint32_t size, 1163 uint32_t pitch, uint32_t flags); 1164extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1165extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1166 1167/* nv30_fb.c */ 1168extern int nv30_fb_init(struct drm_device *); 1169extern void nv30_fb_takedown(struct drm_device *); 1170extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1171 uint32_t addr, uint32_t size, 1172 uint32_t pitch, uint32_t flags); 1173extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1174 1175/* nv40_fb.c */ 1176extern int nv40_fb_init(struct drm_device *); 1177extern void nv40_fb_takedown(struct drm_device *); 1178extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1179 1180/* nv50_fb.c */ 1181extern int nv50_fb_init(struct drm_device *); 1182extern void nv50_fb_takedown(struct drm_device *); 1183extern void nv50_fb_vm_trap(struct drm_device *, int display); 1184 1185/* nvc0_fb.c */ 1186extern int nvc0_fb_init(struct drm_device *); 1187extern void nvc0_fb_takedown(struct drm_device *); 1188 1189/* nv04_fifo.c */ 1190extern int nv04_fifo_init(struct drm_device *); 1191extern void nv04_fifo_fini(struct drm_device *); 1192extern void nv04_fifo_disable(struct drm_device *); 1193extern void nv04_fifo_enable(struct drm_device *); 1194extern bool nv04_fifo_reassign(struct drm_device *, bool); 1195extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1196extern int nv04_fifo_channel_id(struct drm_device *); 1197extern int nv04_fifo_create_context(struct nouveau_channel *); 1198extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1199extern int nv04_fifo_load_context(struct nouveau_channel *); 1200extern int nv04_fifo_unload_context(struct drm_device *); 1201extern void nv04_fifo_isr(struct drm_device *); 1202 1203/* nv10_fifo.c */ 1204extern int nv10_fifo_init(struct drm_device *); 1205extern int nv10_fifo_channel_id(struct drm_device *); 1206extern int nv10_fifo_create_context(struct nouveau_channel *); 1207extern int nv10_fifo_load_context(struct nouveau_channel *); 1208extern int nv10_fifo_unload_context(struct drm_device *); 1209 1210/* nv40_fifo.c */ 1211extern int nv40_fifo_init(struct drm_device *); 1212extern int nv40_fifo_create_context(struct nouveau_channel *); 1213extern int nv40_fifo_load_context(struct nouveau_channel *); 1214extern int nv40_fifo_unload_context(struct drm_device *); 1215 1216/* nv50_fifo.c */ 1217extern int nv50_fifo_init(struct drm_device *); 1218extern void nv50_fifo_takedown(struct drm_device *); 1219extern int nv50_fifo_channel_id(struct drm_device *); 1220extern int nv50_fifo_create_context(struct nouveau_channel *); 1221extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1222extern int nv50_fifo_load_context(struct nouveau_channel *); 1223extern int nv50_fifo_unload_context(struct drm_device *); 1224extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1225 1226/* nvc0_fifo.c */ 1227extern int nvc0_fifo_init(struct drm_device *); 1228extern void nvc0_fifo_takedown(struct drm_device *); 1229extern void nvc0_fifo_disable(struct drm_device *); 1230extern void nvc0_fifo_enable(struct drm_device *); 1231extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1232extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1233extern int nvc0_fifo_channel_id(struct drm_device *); 1234extern int nvc0_fifo_create_context(struct nouveau_channel *); 1235extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1236extern int nvc0_fifo_load_context(struct nouveau_channel *); 1237extern int nvc0_fifo_unload_context(struct drm_device *); 1238 1239/* nv04_graph.c */ 1240extern int nv04_graph_create(struct drm_device *); 1241extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1242extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1243 u32 class, u32 mthd, u32 data); 1244extern struct nouveau_bitfield nv04_graph_nsource[]; 1245 1246/* nv10_graph.c */ 1247extern int nv10_graph_create(struct drm_device *); 1248extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1249extern struct nouveau_bitfield nv10_graph_intr[]; 1250extern struct nouveau_bitfield nv10_graph_nstatus[]; 1251 1252/* nv20_graph.c */ 1253extern int nv20_graph_create(struct drm_device *); 1254 1255/* nv40_graph.c */ 1256extern int nv40_graph_create(struct drm_device *); 1257extern void nv40_grctx_init(struct nouveau_grctx *); 1258 1259/* nv50_graph.c */ 1260extern int nv50_graph_create(struct drm_device *); 1261extern int nv50_grctx_init(struct nouveau_grctx *); 1262extern struct nouveau_enum nv50_data_error_names[]; 1263extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1264 1265/* nvc0_graph.c */ 1266extern int nvc0_graph_create(struct drm_device *); 1267extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1268 1269/* nv84_crypt.c */ 1270extern int nv84_crypt_create(struct drm_device *); 1271 1272/* nv98_crypt.c */ 1273extern int nv98_crypt_create(struct drm_device *dev); 1274 1275/* nva3_copy.c */ 1276extern int nva3_copy_create(struct drm_device *dev); 1277 1278/* nvc0_copy.c */ 1279extern int nvc0_copy_create(struct drm_device *dev, int engine); 1280 1281/* nv31_mpeg.c */ 1282extern int nv31_mpeg_create(struct drm_device *dev); 1283 1284/* nv50_mpeg.c */ 1285extern int nv50_mpeg_create(struct drm_device *dev); 1286 1287/* nv84_bsp.c */ 1288/* nv98_bsp.c */ 1289extern int nv84_bsp_create(struct drm_device *dev); 1290 1291/* nv84_vp.c */ 1292/* nv98_vp.c */ 1293extern int nv84_vp_create(struct drm_device *dev); 1294 1295/* nv98_ppp.c */ 1296extern int nv98_ppp_create(struct drm_device *dev); 1297 1298/* nv04_instmem.c */ 1299extern int nv04_instmem_init(struct drm_device *); 1300extern void nv04_instmem_takedown(struct drm_device *); 1301extern int nv04_instmem_suspend(struct drm_device *); 1302extern void nv04_instmem_resume(struct drm_device *); 1303extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1304 u32 size, u32 align); 1305extern void nv04_instmem_put(struct nouveau_gpuobj *); 1306extern int nv04_instmem_map(struct nouveau_gpuobj *); 1307extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1308extern void nv04_instmem_flush(struct drm_device *); 1309 1310/* nv50_instmem.c */ 1311extern int nv50_instmem_init(struct drm_device *); 1312extern void nv50_instmem_takedown(struct drm_device *); 1313extern int nv50_instmem_suspend(struct drm_device *); 1314extern void nv50_instmem_resume(struct drm_device *); 1315extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1316 u32 size, u32 align); 1317extern void nv50_instmem_put(struct nouveau_gpuobj *); 1318extern int nv50_instmem_map(struct nouveau_gpuobj *); 1319extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1320extern void nv50_instmem_flush(struct drm_device *); 1321extern void nv84_instmem_flush(struct drm_device *); 1322 1323/* nvc0_instmem.c */ 1324extern int nvc0_instmem_init(struct drm_device *); 1325extern void nvc0_instmem_takedown(struct drm_device *); 1326extern int nvc0_instmem_suspend(struct drm_device *); 1327extern void nvc0_instmem_resume(struct drm_device *); 1328 1329/* nv04_mc.c */ 1330extern int nv04_mc_init(struct drm_device *); 1331extern void nv04_mc_takedown(struct drm_device *); 1332 1333/* nv40_mc.c */ 1334extern int nv40_mc_init(struct drm_device *); 1335extern void nv40_mc_takedown(struct drm_device *); 1336 1337/* nv50_mc.c */ 1338extern int nv50_mc_init(struct drm_device *); 1339extern void nv50_mc_takedown(struct drm_device *); 1340 1341/* nv04_timer.c */ 1342extern int nv04_timer_init(struct drm_device *); 1343extern uint64_t nv04_timer_read(struct drm_device *); 1344extern void nv04_timer_takedown(struct drm_device *); 1345 1346extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1347 unsigned long arg); 1348 1349/* nv04_dac.c */ 1350extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1351extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1352extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1353extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1354extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1355 1356/* nv04_dfp.c */ 1357extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1358extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1359extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1360 int head, bool dl); 1361extern void nv04_dfp_disable(struct drm_device *dev, int head); 1362extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1363 1364/* nv04_tv.c */ 1365extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1366extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1367 1368/* nv17_tv.c */ 1369extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1370 1371/* nv04_display.c */ 1372extern int nv04_display_early_init(struct drm_device *); 1373extern void nv04_display_late_takedown(struct drm_device *); 1374extern int nv04_display_create(struct drm_device *); 1375extern void nv04_display_destroy(struct drm_device *); 1376extern int nv04_display_init(struct drm_device *); 1377extern void nv04_display_fini(struct drm_device *); 1378 1379/* nvd0_display.c */ 1380extern int nvd0_display_create(struct drm_device *); 1381extern void nvd0_display_destroy(struct drm_device *); 1382extern int nvd0_display_init(struct drm_device *); 1383extern void nvd0_display_fini(struct drm_device *); 1384struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1385void nvd0_display_flip_stop(struct drm_crtc *); 1386int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1387 struct nouveau_channel *, u32 swap_interval); 1388 1389/* nv04_crtc.c */ 1390extern int nv04_crtc_create(struct drm_device *, int index); 1391 1392/* nouveau_bo.c */ 1393extern struct ttm_bo_driver nouveau_bo_driver; 1394extern int nouveau_bo_new(struct drm_device *, int size, int align, 1395 uint32_t flags, uint32_t tile_mode, 1396 uint32_t tile_flags, struct nouveau_bo **); 1397extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1398extern int nouveau_bo_unpin(struct nouveau_bo *); 1399extern int nouveau_bo_map(struct nouveau_bo *); 1400extern void nouveau_bo_unmap(struct nouveau_bo *); 1401extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1402 uint32_t busy); 1403extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1404extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1405extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1406extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1407extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1408extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1409 bool no_wait_reserve, bool no_wait_gpu); 1410 1411extern struct nouveau_vma * 1412nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1413extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1414 struct nouveau_vma *); 1415extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1416 1417/* nouveau_fence.c */ 1418struct nouveau_fence; 1419extern int nouveau_fence_init(struct drm_device *); 1420extern void nouveau_fence_fini(struct drm_device *); 1421extern int nouveau_fence_channel_init(struct nouveau_channel *); 1422extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1423extern void nouveau_fence_update(struct nouveau_channel *); 1424extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1425 bool emit); 1426extern int nouveau_fence_emit(struct nouveau_fence *); 1427extern void nouveau_fence_work(struct nouveau_fence *fence, 1428 void (*work)(void *priv, bool signalled), 1429 void *priv); 1430struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1431 1432extern bool __nouveau_fence_signalled(void *obj, void *arg); 1433extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1434extern int __nouveau_fence_flush(void *obj, void *arg); 1435extern void __nouveau_fence_unref(void **obj); 1436extern void *__nouveau_fence_ref(void *obj); 1437 1438static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1439{ 1440 return __nouveau_fence_signalled(obj, NULL); 1441} 1442static inline int 1443nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1444{ 1445 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1446} 1447extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1448static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1449{ 1450 return __nouveau_fence_flush(obj, NULL); 1451} 1452static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1453{ 1454 __nouveau_fence_unref((void **)obj); 1455} 1456static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1457{ 1458 return __nouveau_fence_ref(obj); 1459} 1460 1461/* nouveau_gem.c */ 1462extern int nouveau_gem_new(struct drm_device *, int size, int align, 1463 uint32_t domain, uint32_t tile_mode, 1464 uint32_t tile_flags, struct nouveau_bo **); 1465extern int nouveau_gem_object_new(struct drm_gem_object *); 1466extern void nouveau_gem_object_del(struct drm_gem_object *); 1467extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1468extern void nouveau_gem_object_close(struct drm_gem_object *, 1469 struct drm_file *); 1470extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1471 struct drm_file *); 1472extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1473 struct drm_file *); 1474extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1475 struct drm_file *); 1476extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1477 struct drm_file *); 1478extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1479 struct drm_file *); 1480 1481/* nouveau_display.c */ 1482int nouveau_display_create(struct drm_device *dev); 1483void nouveau_display_destroy(struct drm_device *dev); 1484int nouveau_display_init(struct drm_device *dev); 1485void nouveau_display_fini(struct drm_device *dev); 1486int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1487void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1488int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1489 struct drm_pending_vblank_event *event); 1490int nouveau_finish_page_flip(struct nouveau_channel *, 1491 struct nouveau_page_flip_state *); 1492int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1493 struct drm_mode_create_dumb *args); 1494int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1495 uint32_t handle, uint64_t *offset); 1496int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1497 uint32_t handle); 1498 1499/* nv10_gpio.c */ 1500int nv10_gpio_init(struct drm_device *dev); 1501void nv10_gpio_fini(struct drm_device *dev); 1502int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1503int nv10_gpio_sense(struct drm_device *dev, int line); 1504void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1505 1506/* nv50_gpio.c */ 1507int nv50_gpio_init(struct drm_device *dev); 1508void nv50_gpio_fini(struct drm_device *dev); 1509int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1510int nv50_gpio_sense(struct drm_device *dev, int line); 1511void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1512int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1513int nvd0_gpio_sense(struct drm_device *dev, int line); 1514 1515/* nv50_calc.c */ 1516int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1517 int *N1, int *M1, int *N2, int *M2, int *P); 1518int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1519 int clk, int *N, int *fN, int *M, int *P); 1520 1521#ifndef ioread32_native 1522#ifdef __BIG_ENDIAN 1523#define ioread16_native ioread16be 1524#define iowrite16_native iowrite16be 1525#define ioread32_native ioread32be 1526#define iowrite32_native iowrite32be 1527#else /* def __BIG_ENDIAN */ 1528#define ioread16_native ioread16 1529#define iowrite16_native iowrite16 1530#define ioread32_native ioread32 1531#define iowrite32_native iowrite32 1532#endif /* def __BIG_ENDIAN else */ 1533#endif /* !ioread32_native */ 1534 1535/* channel control reg access */ 1536static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1537{ 1538 return ioread32_native(chan->user + reg); 1539} 1540 1541static inline void nvchan_wr32(struct nouveau_channel *chan, 1542 unsigned reg, u32 val) 1543{ 1544 iowrite32_native(val, chan->user + reg); 1545} 1546 1547/* register access */ 1548static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1549{ 1550 struct drm_nouveau_private *dev_priv = dev->dev_private; 1551 return ioread32_native(dev_priv->mmio + reg); 1552} 1553 1554static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1555{ 1556 struct drm_nouveau_private *dev_priv = dev->dev_private; 1557 iowrite32_native(val, dev_priv->mmio + reg); 1558} 1559 1560static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1561{ 1562 u32 tmp = nv_rd32(dev, reg); 1563 nv_wr32(dev, reg, (tmp & ~mask) | val); 1564 return tmp; 1565} 1566 1567static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1568{ 1569 struct drm_nouveau_private *dev_priv = dev->dev_private; 1570 return ioread8(dev_priv->mmio + reg); 1571} 1572 1573static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1574{ 1575 struct drm_nouveau_private *dev_priv = dev->dev_private; 1576 iowrite8(val, dev_priv->mmio + reg); 1577} 1578 1579#define nv_wait(dev, reg, mask, val) \ 1580 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1581#define nv_wait_ne(dev, reg, mask, val) \ 1582 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1583#define nv_wait_cb(dev, func, data) \ 1584 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1585 1586/* PRAMIN access */ 1587static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1588{ 1589 struct drm_nouveau_private *dev_priv = dev->dev_private; 1590 return ioread32_native(dev_priv->ramin + offset); 1591} 1592 1593static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1594{ 1595 struct drm_nouveau_private *dev_priv = dev->dev_private; 1596 iowrite32_native(val, dev_priv->ramin + offset); 1597} 1598 1599/* object access */ 1600extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1601extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1602 1603/* 1604 * Logging 1605 * Argument d is (struct drm_device *). 1606 */ 1607#define NV_PRINTK(level, d, fmt, arg...) \ 1608 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1609 pci_name(d->pdev), ##arg) 1610#ifndef NV_DEBUG_NOTRACE 1611#define NV_DEBUG(d, fmt, arg...) do { \ 1612 if (drm_debug & DRM_UT_DRIVER) { \ 1613 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1614 __LINE__, ##arg); \ 1615 } \ 1616} while (0) 1617#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1618 if (drm_debug & DRM_UT_KMS) { \ 1619 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1620 __LINE__, ##arg); \ 1621 } \ 1622} while (0) 1623#else 1624#define NV_DEBUG(d, fmt, arg...) do { \ 1625 if (drm_debug & DRM_UT_DRIVER) \ 1626 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1627} while (0) 1628#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1629 if (drm_debug & DRM_UT_KMS) \ 1630 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1631} while (0) 1632#endif 1633#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1634#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1635#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1636#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1637#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1638#define NV_WARNONCE(d, fmt, arg...) do { \ 1639 static int _warned = 0; \ 1640 if (!_warned) { \ 1641 NV_WARN(d, fmt, ##arg); \ 1642 _warned = 1; \ 1643 } \ 1644} while(0) 1645 1646/* nouveau_reg_debug bitmask */ 1647enum { 1648 NOUVEAU_REG_DEBUG_MC = 0x1, 1649 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1650 NOUVEAU_REG_DEBUG_FB = 0x4, 1651 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1652 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1653 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1654 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1655 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1656 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1657 NOUVEAU_REG_DEBUG_EVO = 0x200, 1658 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1659}; 1660 1661#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1662 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1663 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1664} while (0) 1665 1666static inline bool 1667nv_two_heads(struct drm_device *dev) 1668{ 1669 struct drm_nouveau_private *dev_priv = dev->dev_private; 1670 const int impl = dev->pci_device & 0x0ff0; 1671 1672 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1673 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1674 return true; 1675 1676 return false; 1677} 1678 1679static inline bool 1680nv_gf4_disp_arch(struct drm_device *dev) 1681{ 1682 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1683} 1684 1685static inline bool 1686nv_two_reg_pll(struct drm_device *dev) 1687{ 1688 struct drm_nouveau_private *dev_priv = dev->dev_private; 1689 const int impl = dev->pci_device & 0x0ff0; 1690 1691 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1692 return true; 1693 return false; 1694} 1695 1696static inline bool 1697nv_match_device(struct drm_device *dev, unsigned device, 1698 unsigned sub_vendor, unsigned sub_device) 1699{ 1700 return dev->pdev->device == device && 1701 dev->pdev->subsystem_vendor == sub_vendor && 1702 dev->pdev->subsystem_device == sub_device; 1703} 1704 1705static inline void * 1706nv_engine(struct drm_device *dev, int engine) 1707{ 1708 struct drm_nouveau_private *dev_priv = dev->dev_private; 1709 return (void *)dev_priv->eng[engine]; 1710} 1711 1712/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1713 * helpful to determine a number of other hardware features 1714 */ 1715static inline int 1716nv44_graph_class(struct drm_device *dev) 1717{ 1718 struct drm_nouveau_private *dev_priv = dev->dev_private; 1719 1720 if ((dev_priv->chipset & 0xf0) == 0x60) 1721 return 1; 1722 1723 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1724} 1725 1726/* memory type/access flags, do not match hardware values */ 1727#define NV_MEM_ACCESS_RO 1 1728#define NV_MEM_ACCESS_WO 2 1729#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1730#define NV_MEM_ACCESS_SYS 4 1731#define NV_MEM_ACCESS_VM 8 1732 1733#define NV_MEM_TARGET_VRAM 0 1734#define NV_MEM_TARGET_PCI 1 1735#define NV_MEM_TARGET_PCI_NOSNOOP 2 1736#define NV_MEM_TARGET_VM 3 1737#define NV_MEM_TARGET_GART 4 1738 1739#define NV_MEM_TYPE_VM 0x7f 1740#define NV_MEM_COMP_VM 0x03 1741 1742/* NV_SW object class */ 1743#define NV_SW 0x0000506e 1744#define NV_SW_DMA_SEMAPHORE 0x00000060 1745#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1746#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1747#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1748#define NV_SW_YIELD 0x00000080 1749#define NV_SW_DMA_VBLSEM 0x0000018c 1750#define NV_SW_VBLSEM_OFFSET 0x00000400 1751#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1752#define NV_SW_VBLSEM_RELEASE 0x00000408 1753#define NV_SW_PAGE_FLIP 0x00000500 1754 1755#endif /* __NOUVEAU_DRV_H__ */ 1756