nouveau_drv.h revision d96773e7b61d9976b8227e018a1c94fb7374e641
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 137#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 138struct nouveau_gpuobj { 139 struct drm_device *dev; 140 struct kref refcount; 141 struct list_head list; 142 143 struct drm_mm_node *im_pramin; 144 struct nouveau_bo *im_backing; 145 uint32_t *im_backing_suspend; 146 int im_bound; 147 148 uint32_t flags; 149 150 u32 size; 151 u32 pinst; 152 u32 cinst; 153 u64 vinst; 154 155 uint32_t engine; 156 uint32_t class; 157 158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 159 void *priv; 160}; 161 162struct nouveau_channel { 163 struct drm_device *dev; 164 int id; 165 166 /* owner of this fifo */ 167 struct drm_file *file_priv; 168 /* mapping of the fifo itself */ 169 struct drm_local_map *map; 170 171 /* mapping of the regs controling the fifo */ 172 void __iomem *user; 173 uint32_t user_get; 174 uint32_t user_put; 175 176 /* Fencing */ 177 struct { 178 /* lock protects the pending list only */ 179 spinlock_t lock; 180 struct list_head pending; 181 uint32_t sequence; 182 uint32_t sequence_ack; 183 atomic_t last_sequence_irq; 184 } fence; 185 186 /* DMA push buffer */ 187 struct nouveau_gpuobj *pushbuf; 188 struct nouveau_bo *pushbuf_bo; 189 uint32_t pushbuf_base; 190 191 /* Notifier memory */ 192 struct nouveau_bo *notifier_bo; 193 struct drm_mm notifier_heap; 194 195 /* PFIFO context */ 196 struct nouveau_gpuobj *ramfc; 197 struct nouveau_gpuobj *cache; 198 199 /* PGRAPH context */ 200 /* XXX may be merge 2 pointers as private data ??? */ 201 struct nouveau_gpuobj *ramin_grctx; 202 void *pgraph_ctx; 203 204 /* NV50 VM */ 205 struct nouveau_gpuobj *vm_pd; 206 struct nouveau_gpuobj *vm_gart_pt; 207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 208 209 /* Objects */ 210 struct nouveau_gpuobj *ramin; /* Private instmem */ 211 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 212 struct nouveau_ramht *ramht; /* Hash table */ 213 214 /* GPU object info for stuff used in-kernel (mm_enabled) */ 215 uint32_t m2mf_ntfy; 216 uint32_t vram_handle; 217 uint32_t gart_handle; 218 bool accel_done; 219 220 /* Push buffer state (only for drm's channel on !mm_enabled) */ 221 struct { 222 int max; 223 int free; 224 int cur; 225 int put; 226 /* access via pushbuf_bo */ 227 228 int ib_base; 229 int ib_max; 230 int ib_free; 231 int ib_put; 232 } dma; 233 234 uint32_t sw_subchannel[8]; 235 236 struct { 237 struct nouveau_gpuobj *vblsem; 238 uint32_t vblsem_offset; 239 uint32_t vblsem_rval; 240 struct list_head vbl_wait; 241 } nvsw; 242 243 struct { 244 bool active; 245 char name[32]; 246 struct drm_info_list info; 247 } debugfs; 248}; 249 250struct nouveau_instmem_engine { 251 void *priv; 252 253 int (*init)(struct drm_device *dev); 254 void (*takedown)(struct drm_device *dev); 255 int (*suspend)(struct drm_device *dev); 256 void (*resume)(struct drm_device *dev); 257 258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 259 uint32_t *size); 260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 263 void (*flush)(struct drm_device *); 264}; 265 266struct nouveau_mc_engine { 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269}; 270 271struct nouveau_timer_engine { 272 int (*init)(struct drm_device *dev); 273 void (*takedown)(struct drm_device *dev); 274 uint64_t (*read)(struct drm_device *dev); 275}; 276 277struct nouveau_fb_engine { 278 int num_tiles; 279 280 int (*init)(struct drm_device *dev); 281 void (*takedown)(struct drm_device *dev); 282 283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 284 uint32_t size, uint32_t pitch); 285}; 286 287struct nouveau_fifo_engine { 288 int channels; 289 290 struct nouveau_gpuobj *playlist[2]; 291 int cur_playlist; 292 293 int (*init)(struct drm_device *); 294 void (*takedown)(struct drm_device *); 295 296 void (*disable)(struct drm_device *); 297 void (*enable)(struct drm_device *); 298 bool (*reassign)(struct drm_device *, bool enable); 299 bool (*cache_flush)(struct drm_device *dev); 300 bool (*cache_pull)(struct drm_device *dev, bool enable); 301 302 int (*channel_id)(struct drm_device *); 303 304 int (*create_context)(struct nouveau_channel *); 305 void (*destroy_context)(struct nouveau_channel *); 306 int (*load_context)(struct nouveau_channel *); 307 int (*unload_context)(struct drm_device *); 308}; 309 310struct nouveau_pgraph_object_method { 311 int id; 312 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 313 uint32_t data); 314}; 315 316struct nouveau_pgraph_object_class { 317 int id; 318 bool software; 319 struct nouveau_pgraph_object_method *methods; 320}; 321 322struct nouveau_pgraph_engine { 323 struct nouveau_pgraph_object_class *grclass; 324 bool accel_blocked; 325 int grctx_size; 326 327 /* NV2x/NV3x context table (0x400780) */ 328 struct nouveau_gpuobj *ctx_table; 329 330 int (*init)(struct drm_device *); 331 void (*takedown)(struct drm_device *); 332 333 void (*fifo_access)(struct drm_device *, bool); 334 335 struct nouveau_channel *(*channel)(struct drm_device *); 336 int (*create_context)(struct nouveau_channel *); 337 void (*destroy_context)(struct nouveau_channel *); 338 int (*load_context)(struct nouveau_channel *); 339 int (*unload_context)(struct drm_device *); 340 341 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 342 uint32_t size, uint32_t pitch); 343}; 344 345struct nouveau_display_engine { 346 int (*early_init)(struct drm_device *); 347 void (*late_takedown)(struct drm_device *); 348 int (*create)(struct drm_device *); 349 int (*init)(struct drm_device *); 350 void (*destroy)(struct drm_device *); 351}; 352 353struct nouveau_gpio_engine { 354 int (*init)(struct drm_device *); 355 void (*takedown)(struct drm_device *); 356 357 int (*get)(struct drm_device *, enum dcb_gpio_tag); 358 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 359 360 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 361}; 362 363struct nouveau_engine { 364 struct nouveau_instmem_engine instmem; 365 struct nouveau_mc_engine mc; 366 struct nouveau_timer_engine timer; 367 struct nouveau_fb_engine fb; 368 struct nouveau_pgraph_engine graph; 369 struct nouveau_fifo_engine fifo; 370 struct nouveau_display_engine display; 371 struct nouveau_gpio_engine gpio; 372}; 373 374struct nouveau_pll_vals { 375 union { 376 struct { 377#ifdef __BIG_ENDIAN 378 uint8_t N1, M1, N2, M2; 379#else 380 uint8_t M1, N1, M2, N2; 381#endif 382 }; 383 struct { 384 uint16_t NM1, NM2; 385 } __attribute__((packed)); 386 }; 387 int log2P; 388 389 int refclk; 390}; 391 392enum nv04_fp_display_regs { 393 FP_DISPLAY_END, 394 FP_TOTAL, 395 FP_CRTC, 396 FP_SYNC_START, 397 FP_SYNC_END, 398 FP_VALID_START, 399 FP_VALID_END 400}; 401 402struct nv04_crtc_reg { 403 unsigned char MiscOutReg; /* */ 404 uint8_t CRTC[0xa0]; 405 uint8_t CR58[0x10]; 406 uint8_t Sequencer[5]; 407 uint8_t Graphics[9]; 408 uint8_t Attribute[21]; 409 unsigned char DAC[768]; /* Internal Colorlookuptable */ 410 411 /* PCRTC regs */ 412 uint32_t fb_start; 413 uint32_t crtc_cfg; 414 uint32_t cursor_cfg; 415 uint32_t gpio_ext; 416 uint32_t crtc_830; 417 uint32_t crtc_834; 418 uint32_t crtc_850; 419 uint32_t crtc_eng_ctrl; 420 421 /* PRAMDAC regs */ 422 uint32_t nv10_cursync; 423 struct nouveau_pll_vals pllvals; 424 uint32_t ramdac_gen_ctrl; 425 uint32_t ramdac_630; 426 uint32_t ramdac_634; 427 uint32_t tv_setup; 428 uint32_t tv_vtotal; 429 uint32_t tv_vskew; 430 uint32_t tv_vsync_delay; 431 uint32_t tv_htotal; 432 uint32_t tv_hskew; 433 uint32_t tv_hsync_delay; 434 uint32_t tv_hsync_delay2; 435 uint32_t fp_horiz_regs[7]; 436 uint32_t fp_vert_regs[7]; 437 uint32_t dither; 438 uint32_t fp_control; 439 uint32_t dither_regs[6]; 440 uint32_t fp_debug_0; 441 uint32_t fp_debug_1; 442 uint32_t fp_debug_2; 443 uint32_t fp_margin_color; 444 uint32_t ramdac_8c0; 445 uint32_t ramdac_a20; 446 uint32_t ramdac_a24; 447 uint32_t ramdac_a34; 448 uint32_t ctv_regs[38]; 449}; 450 451struct nv04_output_reg { 452 uint32_t output; 453 int head; 454}; 455 456struct nv04_mode_state { 457 uint32_t bpp; 458 uint32_t width; 459 uint32_t height; 460 uint32_t interlace; 461 uint32_t repaint0; 462 uint32_t repaint1; 463 uint32_t screen; 464 uint32_t scale; 465 uint32_t dither; 466 uint32_t extra; 467 uint32_t fifo; 468 uint32_t pixel; 469 uint32_t horiz; 470 int arbitration0; 471 int arbitration1; 472 uint32_t pll; 473 uint32_t pllB; 474 uint32_t vpll; 475 uint32_t vpll2; 476 uint32_t vpllB; 477 uint32_t vpll2B; 478 uint32_t pllsel; 479 uint32_t sel_clk; 480 uint32_t general; 481 uint32_t crtcOwner; 482 uint32_t head; 483 uint32_t head2; 484 uint32_t cursorConfig; 485 uint32_t cursor0; 486 uint32_t cursor1; 487 uint32_t cursor2; 488 uint32_t timingH; 489 uint32_t timingV; 490 uint32_t displayV; 491 uint32_t crtcSync; 492 493 struct nv04_crtc_reg crtc_reg[2]; 494}; 495 496enum nouveau_card_type { 497 NV_04 = 0x00, 498 NV_10 = 0x10, 499 NV_20 = 0x20, 500 NV_30 = 0x30, 501 NV_40 = 0x40, 502 NV_50 = 0x50, 503 NV_C0 = 0xc0, 504}; 505 506struct drm_nouveau_private { 507 struct drm_device *dev; 508 509 /* the card type, takes NV_* as values */ 510 enum nouveau_card_type card_type; 511 /* exact chipset, derived from NV_PMC_BOOT_0 */ 512 int chipset; 513 int flags; 514 515 void __iomem *mmio; 516 517 spinlock_t ramin_lock; 518 void __iomem *ramin; 519 u32 ramin_size; 520 u32 ramin_base; 521 bool ramin_available; 522 struct drm_mm ramin_heap; 523 struct list_head gpuobj_list; 524 525 struct nouveau_bo *vga_ram; 526 527 struct workqueue_struct *wq; 528 struct work_struct irq_work; 529 struct work_struct hpd_work; 530 531 struct list_head vbl_waiting; 532 533 struct { 534 struct drm_global_reference mem_global_ref; 535 struct ttm_bo_global_ref bo_global_ref; 536 struct ttm_bo_device bdev; 537 atomic_t validate_sequence; 538 } ttm; 539 540 int fifo_alloc_count; 541 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 542 543 struct nouveau_engine engine; 544 struct nouveau_channel *channel; 545 546 /* For PFIFO and PGRAPH. */ 547 spinlock_t context_switch_lock; 548 549 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 550 struct nouveau_ramht *ramht; 551 struct nouveau_gpuobj *ramfc; 552 struct nouveau_gpuobj *ramro; 553 554 uint32_t ramin_rsvd_vram; 555 556 struct { 557 enum { 558 NOUVEAU_GART_NONE = 0, 559 NOUVEAU_GART_AGP, 560 NOUVEAU_GART_SGDMA 561 } type; 562 uint64_t aper_base; 563 uint64_t aper_size; 564 uint64_t aper_free; 565 566 struct nouveau_gpuobj *sg_ctxdma; 567 struct page *sg_dummy_page; 568 dma_addr_t sg_dummy_bus; 569 } gart_info; 570 571 /* nv10-nv40 tiling regions */ 572 struct { 573 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 574 spinlock_t lock; 575 } tile; 576 577 /* VRAM/fb configuration */ 578 uint64_t vram_size; 579 uint64_t vram_sys_base; 580 u32 vram_rblock_size; 581 582 uint64_t fb_phys; 583 uint64_t fb_available_size; 584 uint64_t fb_mappable_pages; 585 uint64_t fb_aper_free; 586 int fb_mtrr; 587 588 /* G8x/G9x virtual address space */ 589 uint64_t vm_gart_base; 590 uint64_t vm_gart_size; 591 uint64_t vm_vram_base; 592 uint64_t vm_vram_size; 593 uint64_t vm_end; 594 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 595 int vm_vram_pt_nr; 596 597 struct nvbios vbios; 598 599 struct nv04_mode_state mode_reg; 600 struct nv04_mode_state saved_reg; 601 uint32_t saved_vga_font[4][16384]; 602 uint32_t crtc_owner; 603 uint32_t dac_users[4]; 604 605 struct nouveau_suspend_resume { 606 uint32_t *ramin_copy; 607 } susres; 608 609 struct backlight_device *backlight; 610 611 struct nouveau_channel *evo; 612 struct { 613 struct dcb_entry *dcb; 614 u16 script; 615 u32 pclk; 616 } evo_irq; 617 618 struct { 619 struct dentry *channel_root; 620 } debugfs; 621 622 struct nouveau_fbdev *nfbdev; 623 struct apertures_struct *apertures; 624}; 625 626static inline struct drm_nouveau_private * 627nouveau_bdev(struct ttm_bo_device *bd) 628{ 629 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 630} 631 632static inline int 633nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 634{ 635 struct nouveau_bo *prev; 636 637 if (!pnvbo) 638 return -EINVAL; 639 prev = *pnvbo; 640 641 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 642 if (prev) { 643 struct ttm_buffer_object *bo = &prev->bo; 644 645 ttm_bo_unref(&bo); 646 } 647 648 return 0; 649} 650 651#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 652 struct drm_nouveau_private *nv = dev->dev_private; \ 653 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 654 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 655 DRM_CURRENTPID, (id)); \ 656 return -EPERM; \ 657 } \ 658 (ch) = nv->fifos[(id)]; \ 659} while (0) 660 661/* nouveau_drv.c */ 662extern int nouveau_noagp; 663extern int nouveau_duallink; 664extern int nouveau_uscript_lvds; 665extern int nouveau_uscript_tmds; 666extern int nouveau_vram_pushbuf; 667extern int nouveau_vram_notify; 668extern int nouveau_fbpercrtc; 669extern int nouveau_tv_disable; 670extern char *nouveau_tv_norm; 671extern int nouveau_reg_debug; 672extern char *nouveau_vbios; 673extern int nouveau_ignorelid; 674extern int nouveau_nofbaccel; 675extern int nouveau_noaccel; 676extern int nouveau_override_conntype; 677 678extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 679extern int nouveau_pci_resume(struct pci_dev *pdev); 680 681/* nouveau_state.c */ 682extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 683extern int nouveau_load(struct drm_device *, unsigned long flags); 684extern int nouveau_firstopen(struct drm_device *); 685extern void nouveau_lastclose(struct drm_device *); 686extern int nouveau_unload(struct drm_device *); 687extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 688 struct drm_file *); 689extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 690 struct drm_file *); 691extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 692 uint32_t reg, uint32_t mask, uint32_t val); 693extern bool nouveau_wait_for_idle(struct drm_device *); 694extern int nouveau_card_init(struct drm_device *); 695 696/* nouveau_mem.c */ 697extern int nouveau_mem_vram_init(struct drm_device *); 698extern void nouveau_mem_vram_fini(struct drm_device *); 699extern int nouveau_mem_gart_init(struct drm_device *); 700extern void nouveau_mem_gart_fini(struct drm_device *); 701extern int nouveau_mem_init_agp(struct drm_device *); 702extern int nouveau_mem_reset_agp(struct drm_device *); 703extern void nouveau_mem_close(struct drm_device *); 704extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 705 uint32_t addr, 706 uint32_t size, 707 uint32_t pitch); 708extern void nv10_mem_expire_tiling(struct drm_device *dev, 709 struct nouveau_tile_reg *tile, 710 struct nouveau_fence *fence); 711extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 712 uint32_t size, uint32_t flags, 713 uint64_t phys); 714extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 715 uint32_t size); 716 717/* nouveau_notifier.c */ 718extern int nouveau_notifier_init_channel(struct nouveau_channel *); 719extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 720extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 721 int cout, uint32_t *offset); 722extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 723extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 724 struct drm_file *); 725extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 726 struct drm_file *); 727 728/* nouveau_channel.c */ 729extern struct drm_ioctl_desc nouveau_ioctls[]; 730extern int nouveau_max_ioctl; 731extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 732extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 733 int channel); 734extern int nouveau_channel_alloc(struct drm_device *dev, 735 struct nouveau_channel **chan, 736 struct drm_file *file_priv, 737 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 738extern void nouveau_channel_free(struct nouveau_channel *); 739 740/* nouveau_object.c */ 741extern int nouveau_gpuobj_early_init(struct drm_device *); 742extern int nouveau_gpuobj_init(struct drm_device *); 743extern void nouveau_gpuobj_takedown(struct drm_device *); 744extern int nouveau_gpuobj_suspend(struct drm_device *dev); 745extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 746extern void nouveau_gpuobj_resume(struct drm_device *dev); 747extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 748 uint32_t vram_h, uint32_t tt_h); 749extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 750extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 751 uint32_t size, int align, uint32_t flags, 752 struct nouveau_gpuobj **); 753extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 754 struct nouveau_gpuobj **); 755extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 756 u32 size, u32 flags, 757 struct nouveau_gpuobj **); 758extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 759 uint64_t offset, uint64_t size, int access, 760 int target, struct nouveau_gpuobj **); 761extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 762 uint64_t offset, uint64_t size, 763 int access, struct nouveau_gpuobj **, 764 uint32_t *o_ret); 765extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 766 struct nouveau_gpuobj **); 767extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 768 struct nouveau_gpuobj **); 769extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 770 struct drm_file *); 771extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 772 struct drm_file *); 773 774/* nouveau_irq.c */ 775extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 776extern void nouveau_irq_preinstall(struct drm_device *); 777extern int nouveau_irq_postinstall(struct drm_device *); 778extern void nouveau_irq_uninstall(struct drm_device *); 779 780/* nouveau_sgdma.c */ 781extern int nouveau_sgdma_init(struct drm_device *); 782extern void nouveau_sgdma_takedown(struct drm_device *); 783extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 784 uint32_t *page); 785extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 786 787/* nouveau_debugfs.c */ 788#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 789extern int nouveau_debugfs_init(struct drm_minor *); 790extern void nouveau_debugfs_takedown(struct drm_minor *); 791extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 792extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 793#else 794static inline int 795nouveau_debugfs_init(struct drm_minor *minor) 796{ 797 return 0; 798} 799 800static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 801{ 802} 803 804static inline int 805nouveau_debugfs_channel_init(struct nouveau_channel *chan) 806{ 807 return 0; 808} 809 810static inline void 811nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 812{ 813} 814#endif 815 816/* nouveau_dma.c */ 817extern void nouveau_dma_pre_init(struct nouveau_channel *); 818extern int nouveau_dma_init(struct nouveau_channel *); 819extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 820 821/* nouveau_acpi.c */ 822#define ROM_BIOS_PAGE 4096 823#if defined(CONFIG_ACPI) 824void nouveau_register_dsm_handler(void); 825void nouveau_unregister_dsm_handler(void); 826int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 827bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 828int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 829#else 830static inline void nouveau_register_dsm_handler(void) {} 831static inline void nouveau_unregister_dsm_handler(void) {} 832static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 833static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 834static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 835#endif 836 837/* nouveau_backlight.c */ 838#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 839extern int nouveau_backlight_init(struct drm_device *); 840extern void nouveau_backlight_exit(struct drm_device *); 841#else 842static inline int nouveau_backlight_init(struct drm_device *dev) 843{ 844 return 0; 845} 846 847static inline void nouveau_backlight_exit(struct drm_device *dev) { } 848#endif 849 850/* nouveau_bios.c */ 851extern int nouveau_bios_init(struct drm_device *); 852extern void nouveau_bios_takedown(struct drm_device *dev); 853extern int nouveau_run_vbios_init(struct drm_device *); 854extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 855 struct dcb_entry *); 856extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 857 enum dcb_gpio_tag); 858extern struct dcb_connector_table_entry * 859nouveau_bios_connector_entry(struct drm_device *, int index); 860extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 861 struct pll_lims *); 862extern int nouveau_bios_run_display_table(struct drm_device *, 863 struct dcb_entry *, 864 uint32_t script, int pxclk); 865extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 866 int *length); 867extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 868extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 869extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 870 bool *dl, bool *if_is_24bit); 871extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 872 int head, int pxclk); 873extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 874 enum LVDS_script, int pxclk); 875 876/* nouveau_ttm.c */ 877int nouveau_ttm_global_init(struct drm_nouveau_private *); 878void nouveau_ttm_global_release(struct drm_nouveau_private *); 879int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 880 881/* nouveau_dp.c */ 882int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 883 uint8_t *data, int data_nr); 884bool nouveau_dp_detect(struct drm_encoder *); 885bool nouveau_dp_link_train(struct drm_encoder *); 886 887/* nv04_fb.c */ 888extern int nv04_fb_init(struct drm_device *); 889extern void nv04_fb_takedown(struct drm_device *); 890 891/* nv10_fb.c */ 892extern int nv10_fb_init(struct drm_device *); 893extern void nv10_fb_takedown(struct drm_device *); 894extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 895 uint32_t, uint32_t); 896 897/* nv30_fb.c */ 898extern int nv30_fb_init(struct drm_device *); 899extern void nv30_fb_takedown(struct drm_device *); 900 901/* nv40_fb.c */ 902extern int nv40_fb_init(struct drm_device *); 903extern void nv40_fb_takedown(struct drm_device *); 904extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 905 uint32_t, uint32_t); 906/* nv50_fb.c */ 907extern int nv50_fb_init(struct drm_device *); 908extern void nv50_fb_takedown(struct drm_device *); 909extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 910 911/* nvc0_fb.c */ 912extern int nvc0_fb_init(struct drm_device *); 913extern void nvc0_fb_takedown(struct drm_device *); 914 915/* nv04_fifo.c */ 916extern int nv04_fifo_init(struct drm_device *); 917extern void nv04_fifo_disable(struct drm_device *); 918extern void nv04_fifo_enable(struct drm_device *); 919extern bool nv04_fifo_reassign(struct drm_device *, bool); 920extern bool nv04_fifo_cache_flush(struct drm_device *); 921extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 922extern int nv04_fifo_channel_id(struct drm_device *); 923extern int nv04_fifo_create_context(struct nouveau_channel *); 924extern void nv04_fifo_destroy_context(struct nouveau_channel *); 925extern int nv04_fifo_load_context(struct nouveau_channel *); 926extern int nv04_fifo_unload_context(struct drm_device *); 927 928/* nv10_fifo.c */ 929extern int nv10_fifo_init(struct drm_device *); 930extern int nv10_fifo_channel_id(struct drm_device *); 931extern int nv10_fifo_create_context(struct nouveau_channel *); 932extern void nv10_fifo_destroy_context(struct nouveau_channel *); 933extern int nv10_fifo_load_context(struct nouveau_channel *); 934extern int nv10_fifo_unload_context(struct drm_device *); 935 936/* nv40_fifo.c */ 937extern int nv40_fifo_init(struct drm_device *); 938extern int nv40_fifo_create_context(struct nouveau_channel *); 939extern void nv40_fifo_destroy_context(struct nouveau_channel *); 940extern int nv40_fifo_load_context(struct nouveau_channel *); 941extern int nv40_fifo_unload_context(struct drm_device *); 942 943/* nv50_fifo.c */ 944extern int nv50_fifo_init(struct drm_device *); 945extern void nv50_fifo_takedown(struct drm_device *); 946extern int nv50_fifo_channel_id(struct drm_device *); 947extern int nv50_fifo_create_context(struct nouveau_channel *); 948extern void nv50_fifo_destroy_context(struct nouveau_channel *); 949extern int nv50_fifo_load_context(struct nouveau_channel *); 950extern int nv50_fifo_unload_context(struct drm_device *); 951 952/* nvc0_fifo.c */ 953extern int nvc0_fifo_init(struct drm_device *); 954extern void nvc0_fifo_takedown(struct drm_device *); 955extern void nvc0_fifo_disable(struct drm_device *); 956extern void nvc0_fifo_enable(struct drm_device *); 957extern bool nvc0_fifo_reassign(struct drm_device *, bool); 958extern bool nvc0_fifo_cache_flush(struct drm_device *); 959extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 960extern int nvc0_fifo_channel_id(struct drm_device *); 961extern int nvc0_fifo_create_context(struct nouveau_channel *); 962extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 963extern int nvc0_fifo_load_context(struct nouveau_channel *); 964extern int nvc0_fifo_unload_context(struct drm_device *); 965 966/* nv04_graph.c */ 967extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 968extern int nv04_graph_init(struct drm_device *); 969extern void nv04_graph_takedown(struct drm_device *); 970extern void nv04_graph_fifo_access(struct drm_device *, bool); 971extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 972extern int nv04_graph_create_context(struct nouveau_channel *); 973extern void nv04_graph_destroy_context(struct nouveau_channel *); 974extern int nv04_graph_load_context(struct nouveau_channel *); 975extern int nv04_graph_unload_context(struct drm_device *); 976extern void nv04_graph_context_switch(struct drm_device *); 977 978/* nv10_graph.c */ 979extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 980extern int nv10_graph_init(struct drm_device *); 981extern void nv10_graph_takedown(struct drm_device *); 982extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 983extern int nv10_graph_create_context(struct nouveau_channel *); 984extern void nv10_graph_destroy_context(struct nouveau_channel *); 985extern int nv10_graph_load_context(struct nouveau_channel *); 986extern int nv10_graph_unload_context(struct drm_device *); 987extern void nv10_graph_context_switch(struct drm_device *); 988extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 989 uint32_t, uint32_t); 990 991/* nv20_graph.c */ 992extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 993extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 994extern int nv20_graph_create_context(struct nouveau_channel *); 995extern void nv20_graph_destroy_context(struct nouveau_channel *); 996extern int nv20_graph_load_context(struct nouveau_channel *); 997extern int nv20_graph_unload_context(struct drm_device *); 998extern int nv20_graph_init(struct drm_device *); 999extern void nv20_graph_takedown(struct drm_device *); 1000extern int nv30_graph_init(struct drm_device *); 1001extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1002 uint32_t, uint32_t); 1003 1004/* nv40_graph.c */ 1005extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1006extern int nv40_graph_init(struct drm_device *); 1007extern void nv40_graph_takedown(struct drm_device *); 1008extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1009extern int nv40_graph_create_context(struct nouveau_channel *); 1010extern void nv40_graph_destroy_context(struct nouveau_channel *); 1011extern int nv40_graph_load_context(struct nouveau_channel *); 1012extern int nv40_graph_unload_context(struct drm_device *); 1013extern void nv40_grctx_init(struct nouveau_grctx *); 1014extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1015 uint32_t, uint32_t); 1016 1017/* nv50_graph.c */ 1018extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1019extern int nv50_graph_init(struct drm_device *); 1020extern void nv50_graph_takedown(struct drm_device *); 1021extern void nv50_graph_fifo_access(struct drm_device *, bool); 1022extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1023extern int nv50_graph_create_context(struct nouveau_channel *); 1024extern void nv50_graph_destroy_context(struct nouveau_channel *); 1025extern int nv50_graph_load_context(struct nouveau_channel *); 1026extern int nv50_graph_unload_context(struct drm_device *); 1027extern void nv50_graph_context_switch(struct drm_device *); 1028extern int nv50_grctx_init(struct nouveau_grctx *); 1029 1030/* nvc0_graph.c */ 1031extern int nvc0_graph_init(struct drm_device *); 1032extern void nvc0_graph_takedown(struct drm_device *); 1033extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1034extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1035extern int nvc0_graph_create_context(struct nouveau_channel *); 1036extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1037extern int nvc0_graph_load_context(struct nouveau_channel *); 1038extern int nvc0_graph_unload_context(struct drm_device *); 1039 1040/* nv04_instmem.c */ 1041extern int nv04_instmem_init(struct drm_device *); 1042extern void nv04_instmem_takedown(struct drm_device *); 1043extern int nv04_instmem_suspend(struct drm_device *); 1044extern void nv04_instmem_resume(struct drm_device *); 1045extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1046 uint32_t *size); 1047extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1048extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1049extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1050extern void nv04_instmem_flush(struct drm_device *); 1051 1052/* nv50_instmem.c */ 1053extern int nv50_instmem_init(struct drm_device *); 1054extern void nv50_instmem_takedown(struct drm_device *); 1055extern int nv50_instmem_suspend(struct drm_device *); 1056extern void nv50_instmem_resume(struct drm_device *); 1057extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1058 uint32_t *size); 1059extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1060extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1061extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1062extern void nv50_instmem_flush(struct drm_device *); 1063extern void nv84_instmem_flush(struct drm_device *); 1064extern void nv50_vm_flush(struct drm_device *, int engine); 1065 1066/* nvc0_instmem.c */ 1067extern int nvc0_instmem_init(struct drm_device *); 1068extern void nvc0_instmem_takedown(struct drm_device *); 1069extern int nvc0_instmem_suspend(struct drm_device *); 1070extern void nvc0_instmem_resume(struct drm_device *); 1071extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1072 uint32_t *size); 1073extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1074extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1075extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1076extern void nvc0_instmem_flush(struct drm_device *); 1077 1078/* nv04_mc.c */ 1079extern int nv04_mc_init(struct drm_device *); 1080extern void nv04_mc_takedown(struct drm_device *); 1081 1082/* nv40_mc.c */ 1083extern int nv40_mc_init(struct drm_device *); 1084extern void nv40_mc_takedown(struct drm_device *); 1085 1086/* nv50_mc.c */ 1087extern int nv50_mc_init(struct drm_device *); 1088extern void nv50_mc_takedown(struct drm_device *); 1089 1090/* nv04_timer.c */ 1091extern int nv04_timer_init(struct drm_device *); 1092extern uint64_t nv04_timer_read(struct drm_device *); 1093extern void nv04_timer_takedown(struct drm_device *); 1094 1095extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1096 unsigned long arg); 1097 1098/* nv04_dac.c */ 1099extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1100extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1101extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1102extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1103extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1104 1105/* nv04_dfp.c */ 1106extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1107extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1108extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1109 int head, bool dl); 1110extern void nv04_dfp_disable(struct drm_device *dev, int head); 1111extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1112 1113/* nv04_tv.c */ 1114extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1115extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1116 1117/* nv17_tv.c */ 1118extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1119 1120/* nv04_display.c */ 1121extern int nv04_display_early_init(struct drm_device *); 1122extern void nv04_display_late_takedown(struct drm_device *); 1123extern int nv04_display_create(struct drm_device *); 1124extern int nv04_display_init(struct drm_device *); 1125extern void nv04_display_destroy(struct drm_device *); 1126 1127/* nv04_crtc.c */ 1128extern int nv04_crtc_create(struct drm_device *, int index); 1129 1130/* nouveau_bo.c */ 1131extern struct ttm_bo_driver nouveau_bo_driver; 1132extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1133 int size, int align, uint32_t flags, 1134 uint32_t tile_mode, uint32_t tile_flags, 1135 bool no_vm, bool mappable, struct nouveau_bo **); 1136extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1137extern int nouveau_bo_unpin(struct nouveau_bo *); 1138extern int nouveau_bo_map(struct nouveau_bo *); 1139extern void nouveau_bo_unmap(struct nouveau_bo *); 1140extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1141 uint32_t busy); 1142extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1143extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1144extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1145extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1146extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1147 1148/* nouveau_fence.c */ 1149struct nouveau_fence; 1150extern int nouveau_fence_init(struct nouveau_channel *); 1151extern void nouveau_fence_fini(struct nouveau_channel *); 1152extern void nouveau_fence_update(struct nouveau_channel *); 1153extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1154 bool emit); 1155extern int nouveau_fence_emit(struct nouveau_fence *); 1156struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1157extern bool nouveau_fence_signalled(void *obj, void *arg); 1158extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1159extern int nouveau_fence_flush(void *obj, void *arg); 1160extern void nouveau_fence_unref(void **obj); 1161extern void *nouveau_fence_ref(void *obj); 1162 1163/* nouveau_gem.c */ 1164extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1165 int size, int align, uint32_t flags, 1166 uint32_t tile_mode, uint32_t tile_flags, 1167 bool no_vm, bool mappable, struct nouveau_bo **); 1168extern int nouveau_gem_object_new(struct drm_gem_object *); 1169extern void nouveau_gem_object_del(struct drm_gem_object *); 1170extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1171 struct drm_file *); 1172extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1173 struct drm_file *); 1174extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1175 struct drm_file *); 1176extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1177 struct drm_file *); 1178extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1179 struct drm_file *); 1180 1181/* nv10_gpio.c */ 1182int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1183int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1184 1185/* nv50_gpio.c */ 1186int nv50_gpio_init(struct drm_device *dev); 1187int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1188int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1189void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1190 1191/* nv50_calc. */ 1192int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1193 int *N1, int *M1, int *N2, int *M2, int *P); 1194int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1195 int clk, int *N, int *fN, int *M, int *P); 1196 1197#ifndef ioread32_native 1198#ifdef __BIG_ENDIAN 1199#define ioread16_native ioread16be 1200#define iowrite16_native iowrite16be 1201#define ioread32_native ioread32be 1202#define iowrite32_native iowrite32be 1203#else /* def __BIG_ENDIAN */ 1204#define ioread16_native ioread16 1205#define iowrite16_native iowrite16 1206#define ioread32_native ioread32 1207#define iowrite32_native iowrite32 1208#endif /* def __BIG_ENDIAN else */ 1209#endif /* !ioread32_native */ 1210 1211/* channel control reg access */ 1212static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1213{ 1214 return ioread32_native(chan->user + reg); 1215} 1216 1217static inline void nvchan_wr32(struct nouveau_channel *chan, 1218 unsigned reg, u32 val) 1219{ 1220 iowrite32_native(val, chan->user + reg); 1221} 1222 1223/* register access */ 1224static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1225{ 1226 struct drm_nouveau_private *dev_priv = dev->dev_private; 1227 return ioread32_native(dev_priv->mmio + reg); 1228} 1229 1230static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1231{ 1232 struct drm_nouveau_private *dev_priv = dev->dev_private; 1233 iowrite32_native(val, dev_priv->mmio + reg); 1234} 1235 1236static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1237{ 1238 u32 tmp = nv_rd32(dev, reg); 1239 nv_wr32(dev, reg, (tmp & ~mask) | val); 1240 return tmp; 1241} 1242 1243static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1244{ 1245 struct drm_nouveau_private *dev_priv = dev->dev_private; 1246 return ioread8(dev_priv->mmio + reg); 1247} 1248 1249static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1250{ 1251 struct drm_nouveau_private *dev_priv = dev->dev_private; 1252 iowrite8(val, dev_priv->mmio + reg); 1253} 1254 1255#define nv_wait(reg, mask, val) \ 1256 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1257 1258/* PRAMIN access */ 1259static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1260{ 1261 struct drm_nouveau_private *dev_priv = dev->dev_private; 1262 return ioread32_native(dev_priv->ramin + offset); 1263} 1264 1265static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1266{ 1267 struct drm_nouveau_private *dev_priv = dev->dev_private; 1268 iowrite32_native(val, dev_priv->ramin + offset); 1269} 1270 1271/* object access */ 1272extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1273extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1274 1275/* 1276 * Logging 1277 * Argument d is (struct drm_device *). 1278 */ 1279#define NV_PRINTK(level, d, fmt, arg...) \ 1280 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1281 pci_name(d->pdev), ##arg) 1282#ifndef NV_DEBUG_NOTRACE 1283#define NV_DEBUG(d, fmt, arg...) do { \ 1284 if (drm_debug & DRM_UT_DRIVER) { \ 1285 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1286 __LINE__, ##arg); \ 1287 } \ 1288} while (0) 1289#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1290 if (drm_debug & DRM_UT_KMS) { \ 1291 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1292 __LINE__, ##arg); \ 1293 } \ 1294} while (0) 1295#else 1296#define NV_DEBUG(d, fmt, arg...) do { \ 1297 if (drm_debug & DRM_UT_DRIVER) \ 1298 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1299} while (0) 1300#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1301 if (drm_debug & DRM_UT_KMS) \ 1302 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1303} while (0) 1304#endif 1305#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1306#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1307#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1308#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1309#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1310 1311/* nouveau_reg_debug bitmask */ 1312enum { 1313 NOUVEAU_REG_DEBUG_MC = 0x1, 1314 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1315 NOUVEAU_REG_DEBUG_FB = 0x4, 1316 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1317 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1318 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1319 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1320 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1321 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1322 NOUVEAU_REG_DEBUG_EVO = 0x200, 1323}; 1324 1325#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1326 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1327 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1328} while (0) 1329 1330static inline bool 1331nv_two_heads(struct drm_device *dev) 1332{ 1333 struct drm_nouveau_private *dev_priv = dev->dev_private; 1334 const int impl = dev->pci_device & 0x0ff0; 1335 1336 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1337 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1338 return true; 1339 1340 return false; 1341} 1342 1343static inline bool 1344nv_gf4_disp_arch(struct drm_device *dev) 1345{ 1346 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1347} 1348 1349static inline bool 1350nv_two_reg_pll(struct drm_device *dev) 1351{ 1352 struct drm_nouveau_private *dev_priv = dev->dev_private; 1353 const int impl = dev->pci_device & 0x0ff0; 1354 1355 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1356 return true; 1357 return false; 1358} 1359 1360static inline bool 1361nv_match_device(struct drm_device *dev, unsigned device, 1362 unsigned sub_vendor, unsigned sub_device) 1363{ 1364 return dev->pdev->device == device && 1365 dev->pdev->subsystem_vendor == sub_vendor && 1366 dev->pdev->subsystem_device == sub_device; 1367} 1368 1369#define NV_SW 0x0000506e 1370#define NV_SW_DMA_SEMAPHORE 0x00000060 1371#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1372#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1373#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1374#define NV_SW_DMA_VBLSEM 0x0000018c 1375#define NV_SW_VBLSEM_OFFSET 0x00000400 1376#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1377#define NV_SW_VBLSEM_RELEASE 0x00000408 1378 1379#endif /* __NOUVEAU_DRV_H__ */ 1380