nouveau_drv.h revision dc1e5c0dbff27c2b5147eaea16c578d2337870c3
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58struct nouveau_grctx; 59 60#define MAX_NUM_DCB_ENTRIES 16 61 62#define NOUVEAU_MAX_CHANNEL_NR 128 63#define NOUVEAU_MAX_TILE_NR 15 64 65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 66#define NV50_VM_BLOCK (512*1024*1024ULL) 67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 68 69struct nouveau_tile_reg { 70 bool used; 71 uint32_t addr; 72 uint32_t limit; 73 uint32_t pitch; 74 uint32_t zcomp; 75 struct drm_mm_node *tag_mem; 76 struct nouveau_fence *fence; 77}; 78 79struct nouveau_bo { 80 struct ttm_buffer_object bo; 81 struct ttm_placement placement; 82 u32 placements[3]; 83 u32 busy_placements[3]; 84 struct ttm_bo_kmap_obj kmap; 85 struct list_head head; 86 87 /* protected by ttm_bo_reserve() */ 88 struct drm_file *reserved_by; 89 struct list_head entry; 90 int pbbo_index; 91 bool validate_mapped; 92 93 struct nouveau_channel *channel; 94 95 bool mappable; 96 bool no_vm; 97 98 uint32_t tile_mode; 99 uint32_t tile_flags; 100 struct nouveau_tile_reg *tile; 101 102 struct drm_gem_object *gem; 103 int pin_refcnt; 104}; 105 106#define nouveau_bo_tile_layout(nvbo) \ 107 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 108 109static inline struct nouveau_bo * 110nouveau_bo(struct ttm_buffer_object *bo) 111{ 112 return container_of(bo, struct nouveau_bo, bo); 113} 114 115static inline struct nouveau_bo * 116nouveau_gem_object(struct drm_gem_object *gem) 117{ 118 return gem ? gem->driver_private : NULL; 119} 120 121/* TODO: submit equivalent to TTM generic API upstream? */ 122static inline void __iomem * 123nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 124{ 125 bool is_iomem; 126 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 127 &nvbo->kmap, &is_iomem); 128 WARN_ON_ONCE(ioptr && !is_iomem); 129 return ioptr; 130} 131 132enum nouveau_flags { 133 NV_NFORCE = 0x10000000, 134 NV_NFORCE2 = 0x20000000 135}; 136 137#define NVOBJ_ENGINE_SW 0 138#define NVOBJ_ENGINE_GR 1 139#define NVOBJ_ENGINE_PPP 2 140#define NVOBJ_ENGINE_COPY 3 141#define NVOBJ_ENGINE_VP 4 142#define NVOBJ_ENGINE_CRYPT 5 143#define NVOBJ_ENGINE_BSP 6 144#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 145#define NVOBJ_ENGINE_INT 0xdeadbeef 146 147#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 148#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 149struct nouveau_gpuobj { 150 struct drm_device *dev; 151 struct kref refcount; 152 struct list_head list; 153 154 struct drm_mm_node *im_pramin; 155 struct nouveau_bo *im_backing; 156 u32 *suspend; 157 int im_bound; 158 159 uint32_t flags; 160 161 u32 size; 162 u32 pinst; 163 u32 cinst; 164 u64 vinst; 165 166 uint32_t engine; 167 uint32_t class; 168 169 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 170 void *priv; 171}; 172 173struct nouveau_page_flip_state { 174 struct list_head head; 175 struct drm_pending_vblank_event *event; 176 int crtc, bpp, pitch, x, y; 177 uint64_t offset; 178}; 179 180enum nouveau_channel_mutex_class { 181 NOUVEAU_UCHANNEL_MUTEX, 182 NOUVEAU_KCHANNEL_MUTEX 183}; 184 185struct nouveau_channel { 186 struct drm_device *dev; 187 int id; 188 189 /* references to the channel data structure */ 190 struct kref ref; 191 /* users of the hardware channel resources, the hardware 192 * context will be kicked off when it reaches zero. */ 193 atomic_t users; 194 struct mutex mutex; 195 196 /* owner of this fifo */ 197 struct drm_file *file_priv; 198 /* mapping of the fifo itself */ 199 struct drm_local_map *map; 200 201 /* mapping of the regs controling the fifo */ 202 void __iomem *user; 203 uint32_t user_get; 204 uint32_t user_put; 205 206 /* Fencing */ 207 struct { 208 /* lock protects the pending list only */ 209 spinlock_t lock; 210 struct list_head pending; 211 uint32_t sequence; 212 uint32_t sequence_ack; 213 atomic_t last_sequence_irq; 214 } fence; 215 216 /* DMA push buffer */ 217 struct nouveau_gpuobj *pushbuf; 218 struct nouveau_bo *pushbuf_bo; 219 uint32_t pushbuf_base; 220 221 /* Notifier memory */ 222 struct nouveau_bo *notifier_bo; 223 struct drm_mm notifier_heap; 224 225 /* PFIFO context */ 226 struct nouveau_gpuobj *ramfc; 227 struct nouveau_gpuobj *cache; 228 229 /* PGRAPH context */ 230 /* XXX may be merge 2 pointers as private data ??? */ 231 struct nouveau_gpuobj *ramin_grctx; 232 struct nouveau_gpuobj *crypt_ctx; 233 void *pgraph_ctx; 234 235 /* NV50 VM */ 236 struct nouveau_gpuobj *vm_pd; 237 struct nouveau_gpuobj *vm_gart_pt; 238 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 239 240 /* Objects */ 241 struct nouveau_gpuobj *ramin; /* Private instmem */ 242 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 243 struct nouveau_ramht *ramht; /* Hash table */ 244 245 /* GPU object info for stuff used in-kernel (mm_enabled) */ 246 uint32_t m2mf_ntfy; 247 uint32_t vram_handle; 248 uint32_t gart_handle; 249 bool accel_done; 250 251 /* Push buffer state (only for drm's channel on !mm_enabled) */ 252 struct { 253 int max; 254 int free; 255 int cur; 256 int put; 257 /* access via pushbuf_bo */ 258 259 int ib_base; 260 int ib_max; 261 int ib_free; 262 int ib_put; 263 } dma; 264 265 uint32_t sw_subchannel[8]; 266 267 struct { 268 struct nouveau_gpuobj *vblsem; 269 uint32_t vblsem_head; 270 uint32_t vblsem_offset; 271 uint32_t vblsem_rval; 272 struct list_head vbl_wait; 273 struct list_head flip; 274 } nvsw; 275 276 struct { 277 bool active; 278 char name[32]; 279 struct drm_info_list info; 280 } debugfs; 281}; 282 283struct nouveau_instmem_engine { 284 void *priv; 285 286 int (*init)(struct drm_device *dev); 287 void (*takedown)(struct drm_device *dev); 288 int (*suspend)(struct drm_device *dev); 289 void (*resume)(struct drm_device *dev); 290 291 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 292 u32 *size, u32 align); 293 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 294 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 295 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 296 void (*flush)(struct drm_device *); 297}; 298 299struct nouveau_mc_engine { 300 int (*init)(struct drm_device *dev); 301 void (*takedown)(struct drm_device *dev); 302}; 303 304struct nouveau_timer_engine { 305 int (*init)(struct drm_device *dev); 306 void (*takedown)(struct drm_device *dev); 307 uint64_t (*read)(struct drm_device *dev); 308}; 309 310struct nouveau_fb_engine { 311 int num_tiles; 312 struct drm_mm tag_heap; 313 314 int (*init)(struct drm_device *dev); 315 void (*takedown)(struct drm_device *dev); 316 317 void (*init_tile_region)(struct drm_device *dev, int i, 318 uint32_t addr, uint32_t size, 319 uint32_t pitch, uint32_t flags); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*free_tile_region)(struct drm_device *dev, int i); 322}; 323 324struct nouveau_fifo_engine { 325 int channels; 326 327 struct nouveau_gpuobj *playlist[2]; 328 int cur_playlist; 329 330 int (*init)(struct drm_device *); 331 void (*takedown)(struct drm_device *); 332 333 void (*disable)(struct drm_device *); 334 void (*enable)(struct drm_device *); 335 bool (*reassign)(struct drm_device *, bool enable); 336 bool (*cache_pull)(struct drm_device *dev, bool enable); 337 338 int (*channel_id)(struct drm_device *); 339 340 int (*create_context)(struct nouveau_channel *); 341 void (*destroy_context)(struct nouveau_channel *); 342 int (*load_context)(struct nouveau_channel *); 343 int (*unload_context)(struct drm_device *); 344 void (*tlb_flush)(struct drm_device *dev); 345}; 346 347struct nouveau_pgraph_engine { 348 bool accel_blocked; 349 bool registered; 350 int grctx_size; 351 352 /* NV2x/NV3x context table (0x400780) */ 353 struct nouveau_gpuobj *ctx_table; 354 355 int (*init)(struct drm_device *); 356 void (*takedown)(struct drm_device *); 357 358 void (*fifo_access)(struct drm_device *, bool); 359 360 struct nouveau_channel *(*channel)(struct drm_device *); 361 int (*create_context)(struct nouveau_channel *); 362 void (*destroy_context)(struct nouveau_channel *); 363 int (*load_context)(struct nouveau_channel *); 364 int (*unload_context)(struct drm_device *); 365 void (*tlb_flush)(struct drm_device *dev); 366 367 void (*set_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_display_engine { 371 int (*early_init)(struct drm_device *); 372 void (*late_takedown)(struct drm_device *); 373 int (*create)(struct drm_device *); 374 int (*init)(struct drm_device *); 375 void (*destroy)(struct drm_device *); 376}; 377 378struct nouveau_gpio_engine { 379 void *priv; 380 381 int (*init)(struct drm_device *); 382 void (*takedown)(struct drm_device *); 383 384 int (*get)(struct drm_device *, enum dcb_gpio_tag); 385 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 386 387 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 388 void (*)(void *, int), void *); 389 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 390 void (*)(void *, int), void *); 391 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 392}; 393 394struct nouveau_pm_voltage_level { 395 u8 voltage; 396 u8 vid; 397}; 398 399struct nouveau_pm_voltage { 400 bool supported; 401 u8 vid_mask; 402 403 struct nouveau_pm_voltage_level *level; 404 int nr_level; 405}; 406 407#define NOUVEAU_PM_MAX_LEVEL 8 408struct nouveau_pm_level { 409 struct device_attribute dev_attr; 410 char name[32]; 411 int id; 412 413 u32 core; 414 u32 memory; 415 u32 shader; 416 u32 unk05; 417 418 u8 voltage; 419 u8 fanspeed; 420 421 u16 memscript; 422}; 423 424struct nouveau_pm_temp_sensor_constants { 425 u16 offset_constant; 426 s16 offset_mult; 427 u16 offset_div; 428 u16 slope_mult; 429 u16 slope_div; 430}; 431 432struct nouveau_pm_threshold_temp { 433 s16 critical; 434 s16 down_clock; 435 s16 fan_boost; 436}; 437 438struct nouveau_pm_memtiming { 439 u32 reg_100220; 440 u32 reg_100224; 441 u32 reg_100228; 442 u32 reg_10022c; 443 u32 reg_100230; 444 u32 reg_100234; 445 u32 reg_100238; 446 u32 reg_10023c; 447}; 448 449struct nouveau_pm_memtimings { 450 bool supported; 451 struct nouveau_pm_memtiming *timing; 452 int nr_timing; 453}; 454 455struct nouveau_pm_engine { 456 struct nouveau_pm_voltage voltage; 457 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 458 int nr_perflvl; 459 struct nouveau_pm_memtimings memtimings; 460 struct nouveau_pm_temp_sensor_constants sensor_constants; 461 struct nouveau_pm_threshold_temp threshold_temp; 462 463 struct nouveau_pm_level boot; 464 struct nouveau_pm_level *cur; 465 466 struct device *hwmon; 467 struct notifier_block acpi_nb; 468 469 int (*clock_get)(struct drm_device *, u32 id); 470 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 471 u32 id, int khz); 472 void (*clock_set)(struct drm_device *, void *); 473 int (*voltage_get)(struct drm_device *); 474 int (*voltage_set)(struct drm_device *, int voltage); 475 int (*fanspeed_get)(struct drm_device *); 476 int (*fanspeed_set)(struct drm_device *, int fanspeed); 477 int (*temp_get)(struct drm_device *); 478}; 479 480struct nouveau_crypt_engine { 481 bool registered; 482 483 int (*init)(struct drm_device *); 484 void (*takedown)(struct drm_device *); 485 int (*create_context)(struct nouveau_channel *); 486 void (*destroy_context)(struct nouveau_channel *); 487 void (*tlb_flush)(struct drm_device *dev); 488}; 489 490struct nouveau_engine { 491 struct nouveau_instmem_engine instmem; 492 struct nouveau_mc_engine mc; 493 struct nouveau_timer_engine timer; 494 struct nouveau_fb_engine fb; 495 struct nouveau_pgraph_engine graph; 496 struct nouveau_fifo_engine fifo; 497 struct nouveau_display_engine display; 498 struct nouveau_gpio_engine gpio; 499 struct nouveau_pm_engine pm; 500 struct nouveau_crypt_engine crypt; 501}; 502 503struct nouveau_pll_vals { 504 union { 505 struct { 506#ifdef __BIG_ENDIAN 507 uint8_t N1, M1, N2, M2; 508#else 509 uint8_t M1, N1, M2, N2; 510#endif 511 }; 512 struct { 513 uint16_t NM1, NM2; 514 } __attribute__((packed)); 515 }; 516 int log2P; 517 518 int refclk; 519}; 520 521enum nv04_fp_display_regs { 522 FP_DISPLAY_END, 523 FP_TOTAL, 524 FP_CRTC, 525 FP_SYNC_START, 526 FP_SYNC_END, 527 FP_VALID_START, 528 FP_VALID_END 529}; 530 531struct nv04_crtc_reg { 532 unsigned char MiscOutReg; 533 uint8_t CRTC[0xa0]; 534 uint8_t CR58[0x10]; 535 uint8_t Sequencer[5]; 536 uint8_t Graphics[9]; 537 uint8_t Attribute[21]; 538 unsigned char DAC[768]; 539 540 /* PCRTC regs */ 541 uint32_t fb_start; 542 uint32_t crtc_cfg; 543 uint32_t cursor_cfg; 544 uint32_t gpio_ext; 545 uint32_t crtc_830; 546 uint32_t crtc_834; 547 uint32_t crtc_850; 548 uint32_t crtc_eng_ctrl; 549 550 /* PRAMDAC regs */ 551 uint32_t nv10_cursync; 552 struct nouveau_pll_vals pllvals; 553 uint32_t ramdac_gen_ctrl; 554 uint32_t ramdac_630; 555 uint32_t ramdac_634; 556 uint32_t tv_setup; 557 uint32_t tv_vtotal; 558 uint32_t tv_vskew; 559 uint32_t tv_vsync_delay; 560 uint32_t tv_htotal; 561 uint32_t tv_hskew; 562 uint32_t tv_hsync_delay; 563 uint32_t tv_hsync_delay2; 564 uint32_t fp_horiz_regs[7]; 565 uint32_t fp_vert_regs[7]; 566 uint32_t dither; 567 uint32_t fp_control; 568 uint32_t dither_regs[6]; 569 uint32_t fp_debug_0; 570 uint32_t fp_debug_1; 571 uint32_t fp_debug_2; 572 uint32_t fp_margin_color; 573 uint32_t ramdac_8c0; 574 uint32_t ramdac_a20; 575 uint32_t ramdac_a24; 576 uint32_t ramdac_a34; 577 uint32_t ctv_regs[38]; 578}; 579 580struct nv04_output_reg { 581 uint32_t output; 582 int head; 583}; 584 585struct nv04_mode_state { 586 struct nv04_crtc_reg crtc_reg[2]; 587 uint32_t pllsel; 588 uint32_t sel_clk; 589}; 590 591enum nouveau_card_type { 592 NV_04 = 0x00, 593 NV_10 = 0x10, 594 NV_20 = 0x20, 595 NV_30 = 0x30, 596 NV_40 = 0x40, 597 NV_50 = 0x50, 598 NV_C0 = 0xc0, 599}; 600 601struct drm_nouveau_private { 602 struct drm_device *dev; 603 604 /* the card type, takes NV_* as values */ 605 enum nouveau_card_type card_type; 606 /* exact chipset, derived from NV_PMC_BOOT_0 */ 607 int chipset; 608 int flags; 609 610 void __iomem *mmio; 611 612 spinlock_t ramin_lock; 613 void __iomem *ramin; 614 u32 ramin_size; 615 u32 ramin_base; 616 bool ramin_available; 617 struct drm_mm ramin_heap; 618 struct list_head gpuobj_list; 619 struct list_head classes; 620 621 struct nouveau_bo *vga_ram; 622 623 /* interrupt handling */ 624 void (*irq_handler[32])(struct drm_device *); 625 bool msi_enabled; 626 struct workqueue_struct *wq; 627 struct work_struct irq_work; 628 629 struct list_head vbl_waiting; 630 631 struct { 632 struct drm_global_reference mem_global_ref; 633 struct ttm_bo_global_ref bo_global_ref; 634 struct ttm_bo_device bdev; 635 atomic_t validate_sequence; 636 } ttm; 637 638 struct { 639 spinlock_t lock; 640 struct drm_mm heap; 641 struct nouveau_bo *bo; 642 } fence; 643 644 struct { 645 spinlock_t lock; 646 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 647 } channels; 648 649 struct nouveau_engine engine; 650 struct nouveau_channel *channel; 651 652 /* For PFIFO and PGRAPH. */ 653 spinlock_t context_switch_lock; 654 655 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 656 struct nouveau_ramht *ramht; 657 struct nouveau_gpuobj *ramfc; 658 struct nouveau_gpuobj *ramro; 659 660 uint32_t ramin_rsvd_vram; 661 662 struct { 663 enum { 664 NOUVEAU_GART_NONE = 0, 665 NOUVEAU_GART_AGP, 666 NOUVEAU_GART_SGDMA 667 } type; 668 uint64_t aper_base; 669 uint64_t aper_size; 670 uint64_t aper_free; 671 672 struct nouveau_gpuobj *sg_ctxdma; 673 struct page *sg_dummy_page; 674 dma_addr_t sg_dummy_bus; 675 } gart_info; 676 677 /* nv10-nv40 tiling regions */ 678 struct { 679 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 680 spinlock_t lock; 681 } tile; 682 683 /* VRAM/fb configuration */ 684 uint64_t vram_size; 685 uint64_t vram_sys_base; 686 u32 vram_rblock_size; 687 688 uint64_t fb_phys; 689 uint64_t fb_available_size; 690 uint64_t fb_mappable_pages; 691 uint64_t fb_aper_free; 692 int fb_mtrr; 693 694 /* G8x/G9x virtual address space */ 695 uint64_t vm_gart_base; 696 uint64_t vm_gart_size; 697 uint64_t vm_vram_base; 698 uint64_t vm_vram_size; 699 uint64_t vm_end; 700 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 701 int vm_vram_pt_nr; 702 703 struct nvbios vbios; 704 705 struct nv04_mode_state mode_reg; 706 struct nv04_mode_state saved_reg; 707 uint32_t saved_vga_font[4][16384]; 708 uint32_t crtc_owner; 709 uint32_t dac_users[4]; 710 711 struct nouveau_suspend_resume { 712 uint32_t *ramin_copy; 713 } susres; 714 715 struct backlight_device *backlight; 716 717 struct nouveau_channel *evo; 718 u32 evo_alloc; 719 struct { 720 struct dcb_entry *dcb; 721 u16 script; 722 u32 pclk; 723 } evo_irq; 724 725 struct { 726 struct dentry *channel_root; 727 } debugfs; 728 729 struct nouveau_fbdev *nfbdev; 730 struct apertures_struct *apertures; 731}; 732 733static inline struct drm_nouveau_private * 734nouveau_private(struct drm_device *dev) 735{ 736 return dev->dev_private; 737} 738 739static inline struct drm_nouveau_private * 740nouveau_bdev(struct ttm_bo_device *bd) 741{ 742 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 743} 744 745static inline int 746nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 747{ 748 struct nouveau_bo *prev; 749 750 if (!pnvbo) 751 return -EINVAL; 752 prev = *pnvbo; 753 754 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 755 if (prev) { 756 struct ttm_buffer_object *bo = &prev->bo; 757 758 ttm_bo_unref(&bo); 759 } 760 761 return 0; 762} 763 764/* nouveau_drv.c */ 765extern int nouveau_agpmode; 766extern int nouveau_duallink; 767extern int nouveau_uscript_lvds; 768extern int nouveau_uscript_tmds; 769extern int nouveau_vram_pushbuf; 770extern int nouveau_vram_notify; 771extern int nouveau_fbpercrtc; 772extern int nouveau_tv_disable; 773extern char *nouveau_tv_norm; 774extern int nouveau_reg_debug; 775extern char *nouveau_vbios; 776extern int nouveau_ignorelid; 777extern int nouveau_nofbaccel; 778extern int nouveau_noaccel; 779extern int nouveau_force_post; 780extern int nouveau_override_conntype; 781extern char *nouveau_perflvl; 782extern int nouveau_perflvl_wr; 783extern int nouveau_msi; 784 785extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 786extern int nouveau_pci_resume(struct pci_dev *pdev); 787 788/* nouveau_state.c */ 789extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 790extern int nouveau_load(struct drm_device *, unsigned long flags); 791extern int nouveau_firstopen(struct drm_device *); 792extern void nouveau_lastclose(struct drm_device *); 793extern int nouveau_unload(struct drm_device *); 794extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 795 struct drm_file *); 796extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 797 struct drm_file *); 798extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 799 uint32_t reg, uint32_t mask, uint32_t val); 800extern bool nouveau_wait_for_idle(struct drm_device *); 801extern int nouveau_card_init(struct drm_device *); 802 803/* nouveau_mem.c */ 804extern int nouveau_mem_vram_init(struct drm_device *); 805extern void nouveau_mem_vram_fini(struct drm_device *); 806extern int nouveau_mem_gart_init(struct drm_device *); 807extern void nouveau_mem_gart_fini(struct drm_device *); 808extern int nouveau_mem_init_agp(struct drm_device *); 809extern int nouveau_mem_reset_agp(struct drm_device *); 810extern void nouveau_mem_close(struct drm_device *); 811extern struct nouveau_tile_reg *nv10_mem_set_tiling( 812 struct drm_device *dev, uint32_t addr, uint32_t size, 813 uint32_t pitch, uint32_t flags); 814extern void nv10_mem_put_tile_region(struct drm_device *dev, 815 struct nouveau_tile_reg *tile, 816 struct nouveau_fence *fence); 817extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 818 uint32_t size, uint32_t flags, 819 uint64_t phys); 820extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 821 uint32_t size); 822 823/* nouveau_notifier.c */ 824extern int nouveau_notifier_init_channel(struct nouveau_channel *); 825extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 826extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 827 int cout, uint32_t *offset); 828extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 829extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 830 struct drm_file *); 831extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 832 struct drm_file *); 833 834/* nouveau_channel.c */ 835extern struct drm_ioctl_desc nouveau_ioctls[]; 836extern int nouveau_max_ioctl; 837extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 838extern int nouveau_channel_alloc(struct drm_device *dev, 839 struct nouveau_channel **chan, 840 struct drm_file *file_priv, 841 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 842extern struct nouveau_channel * 843nouveau_channel_get_unlocked(struct nouveau_channel *); 844extern struct nouveau_channel * 845nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 846extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 847extern void nouveau_channel_put(struct nouveau_channel **); 848extern void nouveau_channel_ref(struct nouveau_channel *chan, 849 struct nouveau_channel **pchan); 850 851/* nouveau_object.c */ 852#define NVOBJ_CLASS(d,c,e) do { \ 853 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 854 if (ret) \ 855 return ret; \ 856} while(0) 857 858#define NVOBJ_MTHD(d,c,m,e) do { \ 859 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 860 if (ret) \ 861 return ret; \ 862} while(0) 863 864extern int nouveau_gpuobj_early_init(struct drm_device *); 865extern int nouveau_gpuobj_init(struct drm_device *); 866extern void nouveau_gpuobj_takedown(struct drm_device *); 867extern int nouveau_gpuobj_suspend(struct drm_device *dev); 868extern void nouveau_gpuobj_resume(struct drm_device *dev); 869extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 870extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 871 int (*exec)(struct nouveau_channel *, 872 u32 class, u32 mthd, u32 data)); 873extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 874extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 875extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 876 uint32_t vram_h, uint32_t tt_h); 877extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 878extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 879 uint32_t size, int align, uint32_t flags, 880 struct nouveau_gpuobj **); 881extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 882 struct nouveau_gpuobj **); 883extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 884 u32 size, u32 flags, 885 struct nouveau_gpuobj **); 886extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 887 uint64_t offset, uint64_t size, int access, 888 int target, struct nouveau_gpuobj **); 889extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 890 uint64_t offset, uint64_t size, 891 int access, struct nouveau_gpuobj **, 892 uint32_t *o_ret); 893extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 894 struct nouveau_gpuobj **); 895extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 896 struct drm_file *); 897extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 898 struct drm_file *); 899 900/* nouveau_irq.c */ 901extern int nouveau_irq_init(struct drm_device *); 902extern void nouveau_irq_fini(struct drm_device *); 903extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 904extern void nouveau_irq_register(struct drm_device *, int status_bit, 905 void (*)(struct drm_device *)); 906extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 907extern void nouveau_irq_preinstall(struct drm_device *); 908extern int nouveau_irq_postinstall(struct drm_device *); 909extern void nouveau_irq_uninstall(struct drm_device *); 910 911/* nouveau_sgdma.c */ 912extern int nouveau_sgdma_init(struct drm_device *); 913extern void nouveau_sgdma_takedown(struct drm_device *); 914extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 915 uint32_t *page); 916extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 917 918/* nouveau_debugfs.c */ 919#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 920extern int nouveau_debugfs_init(struct drm_minor *); 921extern void nouveau_debugfs_takedown(struct drm_minor *); 922extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 923extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 924#else 925static inline int 926nouveau_debugfs_init(struct drm_minor *minor) 927{ 928 return 0; 929} 930 931static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 932{ 933} 934 935static inline int 936nouveau_debugfs_channel_init(struct nouveau_channel *chan) 937{ 938 return 0; 939} 940 941static inline void 942nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 943{ 944} 945#endif 946 947/* nouveau_dma.c */ 948extern void nouveau_dma_pre_init(struct nouveau_channel *); 949extern int nouveau_dma_init(struct nouveau_channel *); 950extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 951 952/* nouveau_acpi.c */ 953#define ROM_BIOS_PAGE 4096 954#if defined(CONFIG_ACPI) 955void nouveau_register_dsm_handler(void); 956void nouveau_unregister_dsm_handler(void); 957int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 958bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 959int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 960#else 961static inline void nouveau_register_dsm_handler(void) {} 962static inline void nouveau_unregister_dsm_handler(void) {} 963static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 964static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 965static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 966#endif 967 968/* nouveau_backlight.c */ 969#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 970extern int nouveau_backlight_init(struct drm_device *); 971extern void nouveau_backlight_exit(struct drm_device *); 972#else 973static inline int nouveau_backlight_init(struct drm_device *dev) 974{ 975 return 0; 976} 977 978static inline void nouveau_backlight_exit(struct drm_device *dev) { } 979#endif 980 981/* nouveau_bios.c */ 982extern int nouveau_bios_init(struct drm_device *); 983extern void nouveau_bios_takedown(struct drm_device *dev); 984extern int nouveau_run_vbios_init(struct drm_device *); 985extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 986 struct dcb_entry *); 987extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 988 enum dcb_gpio_tag); 989extern struct dcb_connector_table_entry * 990nouveau_bios_connector_entry(struct drm_device *, int index); 991extern u32 get_pll_register(struct drm_device *, enum pll_types); 992extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 993 struct pll_lims *); 994extern int nouveau_bios_run_display_table(struct drm_device *, 995 struct dcb_entry *, 996 uint32_t script, int pxclk); 997extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 998 int *length); 999extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1000extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1001extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1002 bool *dl, bool *if_is_24bit); 1003extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1004 int head, int pxclk); 1005extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1006 enum LVDS_script, int pxclk); 1007 1008/* nouveau_ttm.c */ 1009int nouveau_ttm_global_init(struct drm_nouveau_private *); 1010void nouveau_ttm_global_release(struct drm_nouveau_private *); 1011int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1012 1013/* nouveau_dp.c */ 1014int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1015 uint8_t *data, int data_nr); 1016bool nouveau_dp_detect(struct drm_encoder *); 1017bool nouveau_dp_link_train(struct drm_encoder *); 1018 1019/* nv04_fb.c */ 1020extern int nv04_fb_init(struct drm_device *); 1021extern void nv04_fb_takedown(struct drm_device *); 1022 1023/* nv10_fb.c */ 1024extern int nv10_fb_init(struct drm_device *); 1025extern void nv10_fb_takedown(struct drm_device *); 1026extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1027 uint32_t addr, uint32_t size, 1028 uint32_t pitch, uint32_t flags); 1029extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1030extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1031 1032/* nv30_fb.c */ 1033extern int nv30_fb_init(struct drm_device *); 1034extern void nv30_fb_takedown(struct drm_device *); 1035extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1036 uint32_t addr, uint32_t size, 1037 uint32_t pitch, uint32_t flags); 1038extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1039 1040/* nv40_fb.c */ 1041extern int nv40_fb_init(struct drm_device *); 1042extern void nv40_fb_takedown(struct drm_device *); 1043extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1044 1045/* nv50_fb.c */ 1046extern int nv50_fb_init(struct drm_device *); 1047extern void nv50_fb_takedown(struct drm_device *); 1048extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1049 1050/* nvc0_fb.c */ 1051extern int nvc0_fb_init(struct drm_device *); 1052extern void nvc0_fb_takedown(struct drm_device *); 1053 1054/* nv04_fifo.c */ 1055extern int nv04_fifo_init(struct drm_device *); 1056extern void nv04_fifo_fini(struct drm_device *); 1057extern void nv04_fifo_disable(struct drm_device *); 1058extern void nv04_fifo_enable(struct drm_device *); 1059extern bool nv04_fifo_reassign(struct drm_device *, bool); 1060extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1061extern int nv04_fifo_channel_id(struct drm_device *); 1062extern int nv04_fifo_create_context(struct nouveau_channel *); 1063extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1064extern int nv04_fifo_load_context(struct nouveau_channel *); 1065extern int nv04_fifo_unload_context(struct drm_device *); 1066extern void nv04_fifo_isr(struct drm_device *); 1067 1068/* nv10_fifo.c */ 1069extern int nv10_fifo_init(struct drm_device *); 1070extern int nv10_fifo_channel_id(struct drm_device *); 1071extern int nv10_fifo_create_context(struct nouveau_channel *); 1072extern int nv10_fifo_load_context(struct nouveau_channel *); 1073extern int nv10_fifo_unload_context(struct drm_device *); 1074 1075/* nv40_fifo.c */ 1076extern int nv40_fifo_init(struct drm_device *); 1077extern int nv40_fifo_create_context(struct nouveau_channel *); 1078extern int nv40_fifo_load_context(struct nouveau_channel *); 1079extern int nv40_fifo_unload_context(struct drm_device *); 1080 1081/* nv50_fifo.c */ 1082extern int nv50_fifo_init(struct drm_device *); 1083extern void nv50_fifo_takedown(struct drm_device *); 1084extern int nv50_fifo_channel_id(struct drm_device *); 1085extern int nv50_fifo_create_context(struct nouveau_channel *); 1086extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1087extern int nv50_fifo_load_context(struct nouveau_channel *); 1088extern int nv50_fifo_unload_context(struct drm_device *); 1089extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1090 1091/* nvc0_fifo.c */ 1092extern int nvc0_fifo_init(struct drm_device *); 1093extern void nvc0_fifo_takedown(struct drm_device *); 1094extern void nvc0_fifo_disable(struct drm_device *); 1095extern void nvc0_fifo_enable(struct drm_device *); 1096extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1097extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1098extern int nvc0_fifo_channel_id(struct drm_device *); 1099extern int nvc0_fifo_create_context(struct nouveau_channel *); 1100extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1101extern int nvc0_fifo_load_context(struct nouveau_channel *); 1102extern int nvc0_fifo_unload_context(struct drm_device *); 1103 1104/* nv04_graph.c */ 1105extern int nv04_graph_init(struct drm_device *); 1106extern void nv04_graph_takedown(struct drm_device *); 1107extern void nv04_graph_fifo_access(struct drm_device *, bool); 1108extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1109extern int nv04_graph_create_context(struct nouveau_channel *); 1110extern void nv04_graph_destroy_context(struct nouveau_channel *); 1111extern int nv04_graph_load_context(struct nouveau_channel *); 1112extern int nv04_graph_unload_context(struct drm_device *); 1113extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1114 u32 class, u32 mthd, u32 data); 1115extern struct nouveau_bitfield nv04_graph_nsource[]; 1116 1117/* nv10_graph.c */ 1118extern int nv10_graph_init(struct drm_device *); 1119extern void nv10_graph_takedown(struct drm_device *); 1120extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1121extern int nv10_graph_create_context(struct nouveau_channel *); 1122extern void nv10_graph_destroy_context(struct nouveau_channel *); 1123extern int nv10_graph_load_context(struct nouveau_channel *); 1124extern int nv10_graph_unload_context(struct drm_device *); 1125extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1126extern struct nouveau_bitfield nv10_graph_intr[]; 1127extern struct nouveau_bitfield nv10_graph_nstatus[]; 1128 1129/* nv20_graph.c */ 1130extern int nv20_graph_create_context(struct nouveau_channel *); 1131extern void nv20_graph_destroy_context(struct nouveau_channel *); 1132extern int nv20_graph_load_context(struct nouveau_channel *); 1133extern int nv20_graph_unload_context(struct drm_device *); 1134extern int nv20_graph_init(struct drm_device *); 1135extern void nv20_graph_takedown(struct drm_device *); 1136extern int nv30_graph_init(struct drm_device *); 1137extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1138 1139/* nv40_graph.c */ 1140extern int nv40_graph_init(struct drm_device *); 1141extern void nv40_graph_takedown(struct drm_device *); 1142extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1143extern int nv40_graph_create_context(struct nouveau_channel *); 1144extern void nv40_graph_destroy_context(struct nouveau_channel *); 1145extern int nv40_graph_load_context(struct nouveau_channel *); 1146extern int nv40_graph_unload_context(struct drm_device *); 1147extern void nv40_grctx_init(struct nouveau_grctx *); 1148extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1149 1150/* nv50_graph.c */ 1151extern int nv50_graph_init(struct drm_device *); 1152extern void nv50_graph_takedown(struct drm_device *); 1153extern void nv50_graph_fifo_access(struct drm_device *, bool); 1154extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1155extern int nv50_graph_create_context(struct nouveau_channel *); 1156extern void nv50_graph_destroy_context(struct nouveau_channel *); 1157extern int nv50_graph_load_context(struct nouveau_channel *); 1158extern int nv50_graph_unload_context(struct drm_device *); 1159extern int nv50_grctx_init(struct nouveau_grctx *); 1160extern void nv50_graph_tlb_flush(struct drm_device *dev); 1161extern void nv86_graph_tlb_flush(struct drm_device *dev); 1162 1163/* nvc0_graph.c */ 1164extern int nvc0_graph_init(struct drm_device *); 1165extern void nvc0_graph_takedown(struct drm_device *); 1166extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1167extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1168extern int nvc0_graph_create_context(struct nouveau_channel *); 1169extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1170extern int nvc0_graph_load_context(struct nouveau_channel *); 1171extern int nvc0_graph_unload_context(struct drm_device *); 1172 1173/* nv84_crypt.c */ 1174extern int nv84_crypt_init(struct drm_device *dev); 1175extern void nv84_crypt_fini(struct drm_device *dev); 1176extern int nv84_crypt_create_context(struct nouveau_channel *); 1177extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1178extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1179 1180/* nv04_instmem.c */ 1181extern int nv04_instmem_init(struct drm_device *); 1182extern void nv04_instmem_takedown(struct drm_device *); 1183extern int nv04_instmem_suspend(struct drm_device *); 1184extern void nv04_instmem_resume(struct drm_device *); 1185extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1186 u32 *size, u32 align); 1187extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1188extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1189extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1190extern void nv04_instmem_flush(struct drm_device *); 1191 1192/* nv50_instmem.c */ 1193extern int nv50_instmem_init(struct drm_device *); 1194extern void nv50_instmem_takedown(struct drm_device *); 1195extern int nv50_instmem_suspend(struct drm_device *); 1196extern void nv50_instmem_resume(struct drm_device *); 1197extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1198 u32 *size, u32 align); 1199extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1200extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1201extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1202extern void nv50_instmem_flush(struct drm_device *); 1203extern void nv84_instmem_flush(struct drm_device *); 1204extern void nv50_vm_flush(struct drm_device *, int engine); 1205 1206/* nvc0_instmem.c */ 1207extern int nvc0_instmem_init(struct drm_device *); 1208extern void nvc0_instmem_takedown(struct drm_device *); 1209extern int nvc0_instmem_suspend(struct drm_device *); 1210extern void nvc0_instmem_resume(struct drm_device *); 1211extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1212 u32 *size, u32 align); 1213extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1214extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1215extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1216extern void nvc0_instmem_flush(struct drm_device *); 1217 1218/* nv04_mc.c */ 1219extern int nv04_mc_init(struct drm_device *); 1220extern void nv04_mc_takedown(struct drm_device *); 1221 1222/* nv40_mc.c */ 1223extern int nv40_mc_init(struct drm_device *); 1224extern void nv40_mc_takedown(struct drm_device *); 1225 1226/* nv50_mc.c */ 1227extern int nv50_mc_init(struct drm_device *); 1228extern void nv50_mc_takedown(struct drm_device *); 1229 1230/* nv04_timer.c */ 1231extern int nv04_timer_init(struct drm_device *); 1232extern uint64_t nv04_timer_read(struct drm_device *); 1233extern void nv04_timer_takedown(struct drm_device *); 1234 1235extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1236 unsigned long arg); 1237 1238/* nv04_dac.c */ 1239extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1240extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1241extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1242extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1243extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1244 1245/* nv04_dfp.c */ 1246extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1247extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1248extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1249 int head, bool dl); 1250extern void nv04_dfp_disable(struct drm_device *dev, int head); 1251extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1252 1253/* nv04_tv.c */ 1254extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1255extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1256 1257/* nv17_tv.c */ 1258extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1259 1260/* nv04_display.c */ 1261extern int nv04_display_early_init(struct drm_device *); 1262extern void nv04_display_late_takedown(struct drm_device *); 1263extern int nv04_display_create(struct drm_device *); 1264extern int nv04_display_init(struct drm_device *); 1265extern void nv04_display_destroy(struct drm_device *); 1266 1267/* nv04_crtc.c */ 1268extern int nv04_crtc_create(struct drm_device *, int index); 1269 1270/* nouveau_bo.c */ 1271extern struct ttm_bo_driver nouveau_bo_driver; 1272extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1273 int size, int align, uint32_t flags, 1274 uint32_t tile_mode, uint32_t tile_flags, 1275 bool no_vm, bool mappable, struct nouveau_bo **); 1276extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1277extern int nouveau_bo_unpin(struct nouveau_bo *); 1278extern int nouveau_bo_map(struct nouveau_bo *); 1279extern void nouveau_bo_unmap(struct nouveau_bo *); 1280extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1281 uint32_t busy); 1282extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1283extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1284extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1285extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1286extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1287 1288/* nouveau_fence.c */ 1289struct nouveau_fence; 1290extern int nouveau_fence_init(struct drm_device *); 1291extern void nouveau_fence_fini(struct drm_device *); 1292extern int nouveau_fence_channel_init(struct nouveau_channel *); 1293extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1294extern void nouveau_fence_update(struct nouveau_channel *); 1295extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1296 bool emit); 1297extern int nouveau_fence_emit(struct nouveau_fence *); 1298extern void nouveau_fence_work(struct nouveau_fence *fence, 1299 void (*work)(void *priv, bool signalled), 1300 void *priv); 1301struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1302 1303extern bool __nouveau_fence_signalled(void *obj, void *arg); 1304extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1305extern int __nouveau_fence_flush(void *obj, void *arg); 1306extern void __nouveau_fence_unref(void **obj); 1307extern void *__nouveau_fence_ref(void *obj); 1308 1309static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1310{ 1311 return __nouveau_fence_signalled(obj, NULL); 1312} 1313static inline int 1314nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1315{ 1316 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1317} 1318extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1319static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1320{ 1321 return __nouveau_fence_flush(obj, NULL); 1322} 1323static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1324{ 1325 __nouveau_fence_unref((void **)obj); 1326} 1327static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1328{ 1329 return __nouveau_fence_ref(obj); 1330} 1331 1332/* nouveau_gem.c */ 1333extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1334 int size, int align, uint32_t flags, 1335 uint32_t tile_mode, uint32_t tile_flags, 1336 bool no_vm, bool mappable, struct nouveau_bo **); 1337extern int nouveau_gem_object_new(struct drm_gem_object *); 1338extern void nouveau_gem_object_del(struct drm_gem_object *); 1339extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1340 struct drm_file *); 1341extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1342 struct drm_file *); 1343extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1344 struct drm_file *); 1345extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1346 struct drm_file *); 1347extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1348 struct drm_file *); 1349 1350/* nouveau_display.c */ 1351int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1352void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1353int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1354 struct drm_pending_vblank_event *event); 1355int nouveau_finish_page_flip(struct nouveau_channel *, 1356 struct nouveau_page_flip_state *); 1357 1358/* nv10_gpio.c */ 1359int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1360int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1361 1362/* nv50_gpio.c */ 1363int nv50_gpio_init(struct drm_device *dev); 1364void nv50_gpio_fini(struct drm_device *dev); 1365int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1366int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1367int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1368 void (*)(void *, int), void *); 1369void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1370 void (*)(void *, int), void *); 1371bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1372 1373/* nv50_calc. */ 1374int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1375 int *N1, int *M1, int *N2, int *M2, int *P); 1376int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1377 int clk, int *N, int *fN, int *M, int *P); 1378 1379#ifndef ioread32_native 1380#ifdef __BIG_ENDIAN 1381#define ioread16_native ioread16be 1382#define iowrite16_native iowrite16be 1383#define ioread32_native ioread32be 1384#define iowrite32_native iowrite32be 1385#else /* def __BIG_ENDIAN */ 1386#define ioread16_native ioread16 1387#define iowrite16_native iowrite16 1388#define ioread32_native ioread32 1389#define iowrite32_native iowrite32 1390#endif /* def __BIG_ENDIAN else */ 1391#endif /* !ioread32_native */ 1392 1393/* channel control reg access */ 1394static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1395{ 1396 return ioread32_native(chan->user + reg); 1397} 1398 1399static inline void nvchan_wr32(struct nouveau_channel *chan, 1400 unsigned reg, u32 val) 1401{ 1402 iowrite32_native(val, chan->user + reg); 1403} 1404 1405/* register access */ 1406static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1407{ 1408 struct drm_nouveau_private *dev_priv = dev->dev_private; 1409 return ioread32_native(dev_priv->mmio + reg); 1410} 1411 1412static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1413{ 1414 struct drm_nouveau_private *dev_priv = dev->dev_private; 1415 iowrite32_native(val, dev_priv->mmio + reg); 1416} 1417 1418static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1419{ 1420 u32 tmp = nv_rd32(dev, reg); 1421 nv_wr32(dev, reg, (tmp & ~mask) | val); 1422 return tmp; 1423} 1424 1425static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1426{ 1427 struct drm_nouveau_private *dev_priv = dev->dev_private; 1428 return ioread8(dev_priv->mmio + reg); 1429} 1430 1431static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1432{ 1433 struct drm_nouveau_private *dev_priv = dev->dev_private; 1434 iowrite8(val, dev_priv->mmio + reg); 1435} 1436 1437#define nv_wait(dev, reg, mask, val) \ 1438 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1439 1440/* PRAMIN access */ 1441static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1442{ 1443 struct drm_nouveau_private *dev_priv = dev->dev_private; 1444 return ioread32_native(dev_priv->ramin + offset); 1445} 1446 1447static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1448{ 1449 struct drm_nouveau_private *dev_priv = dev->dev_private; 1450 iowrite32_native(val, dev_priv->ramin + offset); 1451} 1452 1453/* object access */ 1454extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1455extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1456 1457/* 1458 * Logging 1459 * Argument d is (struct drm_device *). 1460 */ 1461#define NV_PRINTK(level, d, fmt, arg...) \ 1462 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1463 pci_name(d->pdev), ##arg) 1464#ifndef NV_DEBUG_NOTRACE 1465#define NV_DEBUG(d, fmt, arg...) do { \ 1466 if (drm_debug & DRM_UT_DRIVER) { \ 1467 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1468 __LINE__, ##arg); \ 1469 } \ 1470} while (0) 1471#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1472 if (drm_debug & DRM_UT_KMS) { \ 1473 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1474 __LINE__, ##arg); \ 1475 } \ 1476} while (0) 1477#else 1478#define NV_DEBUG(d, fmt, arg...) do { \ 1479 if (drm_debug & DRM_UT_DRIVER) \ 1480 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1481} while (0) 1482#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1483 if (drm_debug & DRM_UT_KMS) \ 1484 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1485} while (0) 1486#endif 1487#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1488#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1489#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1490#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1491#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1492 1493/* nouveau_reg_debug bitmask */ 1494enum { 1495 NOUVEAU_REG_DEBUG_MC = 0x1, 1496 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1497 NOUVEAU_REG_DEBUG_FB = 0x4, 1498 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1499 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1500 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1501 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1502 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1503 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1504 NOUVEAU_REG_DEBUG_EVO = 0x200, 1505}; 1506 1507#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1508 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1509 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1510} while (0) 1511 1512static inline bool 1513nv_two_heads(struct drm_device *dev) 1514{ 1515 struct drm_nouveau_private *dev_priv = dev->dev_private; 1516 const int impl = dev->pci_device & 0x0ff0; 1517 1518 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1519 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1520 return true; 1521 1522 return false; 1523} 1524 1525static inline bool 1526nv_gf4_disp_arch(struct drm_device *dev) 1527{ 1528 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1529} 1530 1531static inline bool 1532nv_two_reg_pll(struct drm_device *dev) 1533{ 1534 struct drm_nouveau_private *dev_priv = dev->dev_private; 1535 const int impl = dev->pci_device & 0x0ff0; 1536 1537 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1538 return true; 1539 return false; 1540} 1541 1542static inline bool 1543nv_match_device(struct drm_device *dev, unsigned device, 1544 unsigned sub_vendor, unsigned sub_device) 1545{ 1546 return dev->pdev->device == device && 1547 dev->pdev->subsystem_vendor == sub_vendor && 1548 dev->pdev->subsystem_device == sub_device; 1549} 1550 1551#define NV_SW 0x0000506e 1552#define NV_SW_DMA_SEMAPHORE 0x00000060 1553#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1554#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1555#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1556#define NV_SW_YIELD 0x00000080 1557#define NV_SW_DMA_VBLSEM 0x0000018c 1558#define NV_SW_VBLSEM_OFFSET 0x00000400 1559#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1560#define NV_SW_VBLSEM_RELEASE 0x00000408 1561#define NV_SW_PAGE_FLIP 0x00000500 1562 1563#endif /* __NOUVEAU_DRV_H__ */ 1564