nouveau_drv.h revision dd1da8de172057b36860f427777ecfa293bb8f6c
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 402 struct drm_property *dithering_mode; 403 struct drm_property *dithering_depth; 404 struct drm_property *underscan_property; 405 struct drm_property *underscan_hborder_property; 406 struct drm_property *underscan_vborder_property; 407}; 408 409struct nouveau_gpio_engine { 410 void *priv; 411 412 int (*init)(struct drm_device *); 413 void (*takedown)(struct drm_device *); 414 415 int (*get)(struct drm_device *, enum dcb_gpio_tag); 416 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 417 418 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 419 void (*)(void *, int), void *); 420 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 421 void (*)(void *, int), void *); 422 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 423}; 424 425struct nouveau_pm_voltage_level { 426 u32 voltage; /* microvolts */ 427 u8 vid; 428}; 429 430struct nouveau_pm_voltage { 431 bool supported; 432 u8 version; 433 u8 vid_mask; 434 435 struct nouveau_pm_voltage_level *level; 436 int nr_level; 437}; 438 439struct nouveau_pm_memtiming { 440 int id; 441 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 442 u32 reg_1; 443 u32 reg_2; 444 u32 reg_3; 445 u32 reg_4; 446 u32 reg_5; 447 u32 reg_6; 448 u32 reg_7; 449 u32 reg_8; 450 /* To be written to 0x1002c0 */ 451 u8 CL; 452 u8 WR; 453}; 454 455struct nouveau_pm_tbl_header{ 456 u8 version; 457 u8 header_len; 458 u8 entry_cnt; 459 u8 entry_len; 460}; 461 462struct nouveau_pm_tbl_entry{ 463 u8 tWR; 464 u8 tUNK_1; 465 u8 tCL; 466 u8 tRP; /* Byte 3 */ 467 u8 empty_4; 468 u8 tRAS; /* Byte 5 */ 469 u8 empty_6; 470 u8 tRFC; /* Byte 7 */ 471 u8 empty_8; 472 u8 tRC; /* Byte 9 */ 473 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 474 u8 empty_15,empty_16,empty_17; 475 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 476}; 477 478/* nouveau_mem.c */ 479void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 480 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 481 struct nouveau_pm_memtiming *timing); 482 483#define NOUVEAU_PM_MAX_LEVEL 8 484struct nouveau_pm_level { 485 struct device_attribute dev_attr; 486 char name[32]; 487 int id; 488 489 u32 core; 490 u32 memory; 491 u32 shader; 492 u32 rop; 493 u32 copy; 494 u32 daemon; 495 u32 vdec; 496 u32 unka0; /* nva3:nvc0 */ 497 u32 hub01; /* nvc0- */ 498 u32 hub06; /* nvc0- */ 499 u32 hub07; /* nvc0- */ 500 501 u32 volt_min; /* microvolts */ 502 u32 volt_max; 503 u8 fanspeed; 504 505 u16 memscript; 506 struct nouveau_pm_memtiming *timing; 507}; 508 509struct nouveau_pm_temp_sensor_constants { 510 u16 offset_constant; 511 s16 offset_mult; 512 s16 offset_div; 513 s16 slope_mult; 514 s16 slope_div; 515}; 516 517struct nouveau_pm_threshold_temp { 518 s16 critical; 519 s16 down_clock; 520 s16 fan_boost; 521}; 522 523struct nouveau_pm_memtimings { 524 bool supported; 525 struct nouveau_pm_memtiming *timing; 526 int nr_timing; 527}; 528 529struct nouveau_pm_fan { 530 u32 min_duty; 531 u32 max_duty; 532 u32 pwm_freq; 533}; 534 535struct nouveau_pm_engine { 536 struct nouveau_pm_voltage voltage; 537 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 538 int nr_perflvl; 539 struct nouveau_pm_memtimings memtimings; 540 struct nouveau_pm_temp_sensor_constants sensor_constants; 541 struct nouveau_pm_threshold_temp threshold_temp; 542 struct nouveau_pm_fan fan; 543 u32 pwm_divisor; 544 545 struct nouveau_pm_level boot; 546 struct nouveau_pm_level *cur; 547 548 struct device *hwmon; 549 struct notifier_block acpi_nb; 550 551 int (*clock_get)(struct drm_device *, u32 id); 552 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 553 u32 id, int khz); 554 void (*clock_set)(struct drm_device *, void *); 555 556 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 557 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 558 int (*clocks_set)(struct drm_device *, void *); 559 560 int (*voltage_get)(struct drm_device *); 561 int (*voltage_set)(struct drm_device *, int voltage); 562 int (*pwm_get)(struct drm_device *, struct dcb_gpio_entry*, u32*, u32*); 563 int (*pwm_set)(struct drm_device *, struct dcb_gpio_entry*, u32, u32); 564 int (*temp_get)(struct drm_device *); 565}; 566 567struct nouveau_vram_engine { 568 struct nouveau_mm mm; 569 570 int (*init)(struct drm_device *); 571 void (*takedown)(struct drm_device *dev); 572 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 573 u32 type, struct nouveau_mem **); 574 void (*put)(struct drm_device *, struct nouveau_mem **); 575 576 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 577}; 578 579struct nouveau_engine { 580 struct nouveau_instmem_engine instmem; 581 struct nouveau_mc_engine mc; 582 struct nouveau_timer_engine timer; 583 struct nouveau_fb_engine fb; 584 struct nouveau_fifo_engine fifo; 585 struct nouveau_display_engine display; 586 struct nouveau_gpio_engine gpio; 587 struct nouveau_pm_engine pm; 588 struct nouveau_vram_engine vram; 589}; 590 591struct nouveau_pll_vals { 592 union { 593 struct { 594#ifdef __BIG_ENDIAN 595 uint8_t N1, M1, N2, M2; 596#else 597 uint8_t M1, N1, M2, N2; 598#endif 599 }; 600 struct { 601 uint16_t NM1, NM2; 602 } __attribute__((packed)); 603 }; 604 int log2P; 605 606 int refclk; 607}; 608 609enum nv04_fp_display_regs { 610 FP_DISPLAY_END, 611 FP_TOTAL, 612 FP_CRTC, 613 FP_SYNC_START, 614 FP_SYNC_END, 615 FP_VALID_START, 616 FP_VALID_END 617}; 618 619struct nv04_crtc_reg { 620 unsigned char MiscOutReg; 621 uint8_t CRTC[0xa0]; 622 uint8_t CR58[0x10]; 623 uint8_t Sequencer[5]; 624 uint8_t Graphics[9]; 625 uint8_t Attribute[21]; 626 unsigned char DAC[768]; 627 628 /* PCRTC regs */ 629 uint32_t fb_start; 630 uint32_t crtc_cfg; 631 uint32_t cursor_cfg; 632 uint32_t gpio_ext; 633 uint32_t crtc_830; 634 uint32_t crtc_834; 635 uint32_t crtc_850; 636 uint32_t crtc_eng_ctrl; 637 638 /* PRAMDAC regs */ 639 uint32_t nv10_cursync; 640 struct nouveau_pll_vals pllvals; 641 uint32_t ramdac_gen_ctrl; 642 uint32_t ramdac_630; 643 uint32_t ramdac_634; 644 uint32_t tv_setup; 645 uint32_t tv_vtotal; 646 uint32_t tv_vskew; 647 uint32_t tv_vsync_delay; 648 uint32_t tv_htotal; 649 uint32_t tv_hskew; 650 uint32_t tv_hsync_delay; 651 uint32_t tv_hsync_delay2; 652 uint32_t fp_horiz_regs[7]; 653 uint32_t fp_vert_regs[7]; 654 uint32_t dither; 655 uint32_t fp_control; 656 uint32_t dither_regs[6]; 657 uint32_t fp_debug_0; 658 uint32_t fp_debug_1; 659 uint32_t fp_debug_2; 660 uint32_t fp_margin_color; 661 uint32_t ramdac_8c0; 662 uint32_t ramdac_a20; 663 uint32_t ramdac_a24; 664 uint32_t ramdac_a34; 665 uint32_t ctv_regs[38]; 666}; 667 668struct nv04_output_reg { 669 uint32_t output; 670 int head; 671}; 672 673struct nv04_mode_state { 674 struct nv04_crtc_reg crtc_reg[2]; 675 uint32_t pllsel; 676 uint32_t sel_clk; 677}; 678 679enum nouveau_card_type { 680 NV_04 = 0x00, 681 NV_10 = 0x10, 682 NV_20 = 0x20, 683 NV_30 = 0x30, 684 NV_40 = 0x40, 685 NV_50 = 0x50, 686 NV_C0 = 0xc0, 687 NV_D0 = 0xd0 688}; 689 690struct drm_nouveau_private { 691 struct drm_device *dev; 692 bool noaccel; 693 694 /* the card type, takes NV_* as values */ 695 enum nouveau_card_type card_type; 696 /* exact chipset, derived from NV_PMC_BOOT_0 */ 697 int chipset; 698 int flags; 699 u32 crystal; 700 701 void __iomem *mmio; 702 703 spinlock_t ramin_lock; 704 void __iomem *ramin; 705 u32 ramin_size; 706 u32 ramin_base; 707 bool ramin_available; 708 struct drm_mm ramin_heap; 709 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 710 struct list_head gpuobj_list; 711 struct list_head classes; 712 713 struct nouveau_bo *vga_ram; 714 715 /* interrupt handling */ 716 void (*irq_handler[32])(struct drm_device *); 717 bool msi_enabled; 718 719 struct list_head vbl_waiting; 720 721 struct { 722 struct drm_global_reference mem_global_ref; 723 struct ttm_bo_global_ref bo_global_ref; 724 struct ttm_bo_device bdev; 725 atomic_t validate_sequence; 726 } ttm; 727 728 struct { 729 spinlock_t lock; 730 struct drm_mm heap; 731 struct nouveau_bo *bo; 732 } fence; 733 734 struct { 735 spinlock_t lock; 736 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 737 } channels; 738 739 struct nouveau_engine engine; 740 struct nouveau_channel *channel; 741 742 /* For PFIFO and PGRAPH. */ 743 spinlock_t context_switch_lock; 744 745 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 746 spinlock_t vm_lock; 747 748 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 749 struct nouveau_ramht *ramht; 750 struct nouveau_gpuobj *ramfc; 751 struct nouveau_gpuobj *ramro; 752 753 uint32_t ramin_rsvd_vram; 754 755 struct { 756 enum { 757 NOUVEAU_GART_NONE = 0, 758 NOUVEAU_GART_AGP, /* AGP */ 759 NOUVEAU_GART_PDMA, /* paged dma object */ 760 NOUVEAU_GART_HW /* on-chip gart/vm */ 761 } type; 762 uint64_t aper_base; 763 uint64_t aper_size; 764 uint64_t aper_free; 765 766 struct ttm_backend_func *func; 767 768 struct { 769 struct page *page; 770 dma_addr_t addr; 771 } dummy; 772 773 struct nouveau_gpuobj *sg_ctxdma; 774 } gart_info; 775 776 /* nv10-nv40 tiling regions */ 777 struct { 778 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 779 spinlock_t lock; 780 } tile; 781 782 /* VRAM/fb configuration */ 783 uint64_t vram_size; 784 uint64_t vram_sys_base; 785 786 uint64_t fb_available_size; 787 uint64_t fb_mappable_pages; 788 uint64_t fb_aper_free; 789 int fb_mtrr; 790 791 /* BAR control (NV50-) */ 792 struct nouveau_vm *bar1_vm; 793 struct nouveau_vm *bar3_vm; 794 795 /* G8x/G9x virtual address space */ 796 struct nouveau_vm *chan_vm; 797 798 struct nvbios vbios; 799 800 struct nv04_mode_state mode_reg; 801 struct nv04_mode_state saved_reg; 802 uint32_t saved_vga_font[4][16384]; 803 uint32_t crtc_owner; 804 uint32_t dac_users[4]; 805 806 struct backlight_device *backlight; 807 808 struct { 809 struct dentry *channel_root; 810 } debugfs; 811 812 struct nouveau_fbdev *nfbdev; 813 struct apertures_struct *apertures; 814}; 815 816static inline struct drm_nouveau_private * 817nouveau_private(struct drm_device *dev) 818{ 819 return dev->dev_private; 820} 821 822static inline struct drm_nouveau_private * 823nouveau_bdev(struct ttm_bo_device *bd) 824{ 825 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 826} 827 828static inline int 829nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 830{ 831 struct nouveau_bo *prev; 832 833 if (!pnvbo) 834 return -EINVAL; 835 prev = *pnvbo; 836 837 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 838 if (prev) { 839 struct ttm_buffer_object *bo = &prev->bo; 840 841 ttm_bo_unref(&bo); 842 } 843 844 return 0; 845} 846 847/* nouveau_drv.c */ 848extern int nouveau_modeset; 849extern int nouveau_agpmode; 850extern int nouveau_duallink; 851extern int nouveau_uscript_lvds; 852extern int nouveau_uscript_tmds; 853extern int nouveau_vram_pushbuf; 854extern int nouveau_vram_notify; 855extern int nouveau_fbpercrtc; 856extern int nouveau_tv_disable; 857extern char *nouveau_tv_norm; 858extern int nouveau_reg_debug; 859extern char *nouveau_vbios; 860extern int nouveau_ignorelid; 861extern int nouveau_nofbaccel; 862extern int nouveau_noaccel; 863extern int nouveau_force_post; 864extern int nouveau_override_conntype; 865extern char *nouveau_perflvl; 866extern int nouveau_perflvl_wr; 867extern int nouveau_msi; 868extern int nouveau_ctxfw; 869 870extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 871extern int nouveau_pci_resume(struct pci_dev *pdev); 872 873/* nouveau_state.c */ 874extern int nouveau_open(struct drm_device *, struct drm_file *); 875extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 876extern void nouveau_postclose(struct drm_device *, struct drm_file *); 877extern int nouveau_load(struct drm_device *, unsigned long flags); 878extern int nouveau_firstopen(struct drm_device *); 879extern void nouveau_lastclose(struct drm_device *); 880extern int nouveau_unload(struct drm_device *); 881extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 882 struct drm_file *); 883extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 884 struct drm_file *); 885extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 886 uint32_t reg, uint32_t mask, uint32_t val); 887extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 888 uint32_t reg, uint32_t mask, uint32_t val); 889extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 890 bool (*cond)(void *), void *); 891extern bool nouveau_wait_for_idle(struct drm_device *); 892extern int nouveau_card_init(struct drm_device *); 893 894/* nouveau_mem.c */ 895extern int nouveau_mem_vram_init(struct drm_device *); 896extern void nouveau_mem_vram_fini(struct drm_device *); 897extern int nouveau_mem_gart_init(struct drm_device *); 898extern void nouveau_mem_gart_fini(struct drm_device *); 899extern int nouveau_mem_init_agp(struct drm_device *); 900extern int nouveau_mem_reset_agp(struct drm_device *); 901extern void nouveau_mem_close(struct drm_device *); 902extern int nouveau_mem_detect(struct drm_device *); 903extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 904extern struct nouveau_tile_reg *nv10_mem_set_tiling( 905 struct drm_device *dev, uint32_t addr, uint32_t size, 906 uint32_t pitch, uint32_t flags); 907extern void nv10_mem_put_tile_region(struct drm_device *dev, 908 struct nouveau_tile_reg *tile, 909 struct nouveau_fence *fence); 910extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 911extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 912 913/* nouveau_notifier.c */ 914extern int nouveau_notifier_init_channel(struct nouveau_channel *); 915extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 916extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 917 int cout, uint32_t start, uint32_t end, 918 uint32_t *offset); 919extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 920extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 921 struct drm_file *); 922extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 923 struct drm_file *); 924 925/* nouveau_channel.c */ 926extern struct drm_ioctl_desc nouveau_ioctls[]; 927extern int nouveau_max_ioctl; 928extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 929extern int nouveau_channel_alloc(struct drm_device *dev, 930 struct nouveau_channel **chan, 931 struct drm_file *file_priv, 932 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 933extern struct nouveau_channel * 934nouveau_channel_get_unlocked(struct nouveau_channel *); 935extern struct nouveau_channel * 936nouveau_channel_get(struct drm_file *, int id); 937extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 938extern void nouveau_channel_put(struct nouveau_channel **); 939extern void nouveau_channel_ref(struct nouveau_channel *chan, 940 struct nouveau_channel **pchan); 941extern void nouveau_channel_idle(struct nouveau_channel *chan); 942 943/* nouveau_object.c */ 944#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 945 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 946 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 947} while (0) 948 949#define NVOBJ_ENGINE_DEL(d, e) do { \ 950 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 951 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 952} while (0) 953 954#define NVOBJ_CLASS(d, c, e) do { \ 955 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 956 if (ret) \ 957 return ret; \ 958} while (0) 959 960#define NVOBJ_MTHD(d, c, m, e) do { \ 961 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 962 if (ret) \ 963 return ret; \ 964} while (0) 965 966extern int nouveau_gpuobj_early_init(struct drm_device *); 967extern int nouveau_gpuobj_init(struct drm_device *); 968extern void nouveau_gpuobj_takedown(struct drm_device *); 969extern int nouveau_gpuobj_suspend(struct drm_device *dev); 970extern void nouveau_gpuobj_resume(struct drm_device *dev); 971extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 972extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 973 int (*exec)(struct nouveau_channel *, 974 u32 class, u32 mthd, u32 data)); 975extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 976extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 977extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 978 uint32_t vram_h, uint32_t tt_h); 979extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 980extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 981 uint32_t size, int align, uint32_t flags, 982 struct nouveau_gpuobj **); 983extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 984 struct nouveau_gpuobj **); 985extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 986 u32 size, u32 flags, 987 struct nouveau_gpuobj **); 988extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 989 uint64_t offset, uint64_t size, int access, 990 int target, struct nouveau_gpuobj **); 991extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 992extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 993 u64 size, int target, int access, u32 type, 994 u32 comp, struct nouveau_gpuobj **pobj); 995extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 996 int class, u64 base, u64 size, int target, 997 int access, u32 type, u32 comp); 998extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 999 struct drm_file *); 1000extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1001 struct drm_file *); 1002 1003/* nouveau_irq.c */ 1004extern int nouveau_irq_init(struct drm_device *); 1005extern void nouveau_irq_fini(struct drm_device *); 1006extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1007extern void nouveau_irq_register(struct drm_device *, int status_bit, 1008 void (*)(struct drm_device *)); 1009extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1010extern void nouveau_irq_preinstall(struct drm_device *); 1011extern int nouveau_irq_postinstall(struct drm_device *); 1012extern void nouveau_irq_uninstall(struct drm_device *); 1013 1014/* nouveau_sgdma.c */ 1015extern int nouveau_sgdma_init(struct drm_device *); 1016extern void nouveau_sgdma_takedown(struct drm_device *); 1017extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1018 uint32_t offset); 1019extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1020 unsigned long size, 1021 uint32_t page_flags, 1022 struct page *dummy_read_page); 1023 1024/* nouveau_debugfs.c */ 1025#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1026extern int nouveau_debugfs_init(struct drm_minor *); 1027extern void nouveau_debugfs_takedown(struct drm_minor *); 1028extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1029extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1030#else 1031static inline int 1032nouveau_debugfs_init(struct drm_minor *minor) 1033{ 1034 return 0; 1035} 1036 1037static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1038{ 1039} 1040 1041static inline int 1042nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1043{ 1044 return 0; 1045} 1046 1047static inline void 1048nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1049{ 1050} 1051#endif 1052 1053/* nouveau_dma.c */ 1054extern void nouveau_dma_pre_init(struct nouveau_channel *); 1055extern int nouveau_dma_init(struct nouveau_channel *); 1056extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1057 1058/* nouveau_acpi.c */ 1059#define ROM_BIOS_PAGE 4096 1060#if defined(CONFIG_ACPI) 1061void nouveau_register_dsm_handler(void); 1062void nouveau_unregister_dsm_handler(void); 1063int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1064bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1065int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1066#else 1067static inline void nouveau_register_dsm_handler(void) {} 1068static inline void nouveau_unregister_dsm_handler(void) {} 1069static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1070static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1071static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1072#endif 1073 1074/* nouveau_backlight.c */ 1075#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1076extern int nouveau_backlight_init(struct drm_device *); 1077extern void nouveau_backlight_exit(struct drm_device *); 1078#else 1079static inline int nouveau_backlight_init(struct drm_device *dev) 1080{ 1081 return 0; 1082} 1083 1084static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1085#endif 1086 1087/* nouveau_bios.c */ 1088extern int nouveau_bios_init(struct drm_device *); 1089extern void nouveau_bios_takedown(struct drm_device *dev); 1090extern int nouveau_run_vbios_init(struct drm_device *); 1091extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1092 struct dcb_entry *, int crtc); 1093extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1094extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1095 enum dcb_gpio_tag); 1096extern struct dcb_connector_table_entry * 1097nouveau_bios_connector_entry(struct drm_device *, int index); 1098extern u32 get_pll_register(struct drm_device *, enum pll_types); 1099extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1100 struct pll_lims *); 1101extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1102 struct dcb_entry *, int crtc); 1103extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1104extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1105extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1106 bool *dl, bool *if_is_24bit); 1107extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1108 int head, int pxclk); 1109extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1110 enum LVDS_script, int pxclk); 1111bool bios_encoder_match(struct dcb_entry *, u32 hash); 1112 1113/* nouveau_ttm.c */ 1114int nouveau_ttm_global_init(struct drm_nouveau_private *); 1115void nouveau_ttm_global_release(struct drm_nouveau_private *); 1116int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1117 1118/* nouveau_hdmi.c */ 1119void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1120 1121/* nouveau_dp.c */ 1122int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1123 uint8_t *data, int data_nr); 1124bool nouveau_dp_detect(struct drm_encoder *); 1125bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1126void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1127u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1128 1129/* nv04_fb.c */ 1130extern int nv04_fb_init(struct drm_device *); 1131extern void nv04_fb_takedown(struct drm_device *); 1132 1133/* nv10_fb.c */ 1134extern int nv10_fb_init(struct drm_device *); 1135extern void nv10_fb_takedown(struct drm_device *); 1136extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1137 uint32_t addr, uint32_t size, 1138 uint32_t pitch, uint32_t flags); 1139extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1140extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1141 1142/* nv30_fb.c */ 1143extern int nv30_fb_init(struct drm_device *); 1144extern void nv30_fb_takedown(struct drm_device *); 1145extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1146 uint32_t addr, uint32_t size, 1147 uint32_t pitch, uint32_t flags); 1148extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1149 1150/* nv40_fb.c */ 1151extern int nv40_fb_init(struct drm_device *); 1152extern void nv40_fb_takedown(struct drm_device *); 1153extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1154 1155/* nv50_fb.c */ 1156extern int nv50_fb_init(struct drm_device *); 1157extern void nv50_fb_takedown(struct drm_device *); 1158extern void nv50_fb_vm_trap(struct drm_device *, int display); 1159 1160/* nvc0_fb.c */ 1161extern int nvc0_fb_init(struct drm_device *); 1162extern void nvc0_fb_takedown(struct drm_device *); 1163 1164/* nv04_fifo.c */ 1165extern int nv04_fifo_init(struct drm_device *); 1166extern void nv04_fifo_fini(struct drm_device *); 1167extern void nv04_fifo_disable(struct drm_device *); 1168extern void nv04_fifo_enable(struct drm_device *); 1169extern bool nv04_fifo_reassign(struct drm_device *, bool); 1170extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1171extern int nv04_fifo_channel_id(struct drm_device *); 1172extern int nv04_fifo_create_context(struct nouveau_channel *); 1173extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1174extern int nv04_fifo_load_context(struct nouveau_channel *); 1175extern int nv04_fifo_unload_context(struct drm_device *); 1176extern void nv04_fifo_isr(struct drm_device *); 1177 1178/* nv10_fifo.c */ 1179extern int nv10_fifo_init(struct drm_device *); 1180extern int nv10_fifo_channel_id(struct drm_device *); 1181extern int nv10_fifo_create_context(struct nouveau_channel *); 1182extern int nv10_fifo_load_context(struct nouveau_channel *); 1183extern int nv10_fifo_unload_context(struct drm_device *); 1184 1185/* nv40_fifo.c */ 1186extern int nv40_fifo_init(struct drm_device *); 1187extern int nv40_fifo_create_context(struct nouveau_channel *); 1188extern int nv40_fifo_load_context(struct nouveau_channel *); 1189extern int nv40_fifo_unload_context(struct drm_device *); 1190 1191/* nv50_fifo.c */ 1192extern int nv50_fifo_init(struct drm_device *); 1193extern void nv50_fifo_takedown(struct drm_device *); 1194extern int nv50_fifo_channel_id(struct drm_device *); 1195extern int nv50_fifo_create_context(struct nouveau_channel *); 1196extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1197extern int nv50_fifo_load_context(struct nouveau_channel *); 1198extern int nv50_fifo_unload_context(struct drm_device *); 1199extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1200 1201/* nvc0_fifo.c */ 1202extern int nvc0_fifo_init(struct drm_device *); 1203extern void nvc0_fifo_takedown(struct drm_device *); 1204extern void nvc0_fifo_disable(struct drm_device *); 1205extern void nvc0_fifo_enable(struct drm_device *); 1206extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1207extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1208extern int nvc0_fifo_channel_id(struct drm_device *); 1209extern int nvc0_fifo_create_context(struct nouveau_channel *); 1210extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1211extern int nvc0_fifo_load_context(struct nouveau_channel *); 1212extern int nvc0_fifo_unload_context(struct drm_device *); 1213 1214/* nv04_graph.c */ 1215extern int nv04_graph_create(struct drm_device *); 1216extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1217extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1218 u32 class, u32 mthd, u32 data); 1219extern struct nouveau_bitfield nv04_graph_nsource[]; 1220 1221/* nv10_graph.c */ 1222extern int nv10_graph_create(struct drm_device *); 1223extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1224extern struct nouveau_bitfield nv10_graph_intr[]; 1225extern struct nouveau_bitfield nv10_graph_nstatus[]; 1226 1227/* nv20_graph.c */ 1228extern int nv20_graph_create(struct drm_device *); 1229 1230/* nv40_graph.c */ 1231extern int nv40_graph_create(struct drm_device *); 1232extern void nv40_grctx_init(struct nouveau_grctx *); 1233 1234/* nv50_graph.c */ 1235extern int nv50_graph_create(struct drm_device *); 1236extern int nv50_grctx_init(struct nouveau_grctx *); 1237extern struct nouveau_enum nv50_data_error_names[]; 1238extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1239 1240/* nvc0_graph.c */ 1241extern int nvc0_graph_create(struct drm_device *); 1242extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1243 1244/* nv84_crypt.c */ 1245extern int nv84_crypt_create(struct drm_device *); 1246 1247/* nv98_crypt.c */ 1248extern int nv98_crypt_create(struct drm_device *dev); 1249 1250/* nva3_copy.c */ 1251extern int nva3_copy_create(struct drm_device *dev); 1252 1253/* nvc0_copy.c */ 1254extern int nvc0_copy_create(struct drm_device *dev, int engine); 1255 1256/* nv31_mpeg.c */ 1257extern int nv31_mpeg_create(struct drm_device *dev); 1258 1259/* nv50_mpeg.c */ 1260extern int nv50_mpeg_create(struct drm_device *dev); 1261 1262/* nv84_bsp.c */ 1263/* nv98_bsp.c */ 1264extern int nv84_bsp_create(struct drm_device *dev); 1265 1266/* nv84_vp.c */ 1267/* nv98_vp.c */ 1268extern int nv84_vp_create(struct drm_device *dev); 1269 1270/* nv98_ppp.c */ 1271extern int nv98_ppp_create(struct drm_device *dev); 1272 1273/* nv04_instmem.c */ 1274extern int nv04_instmem_init(struct drm_device *); 1275extern void nv04_instmem_takedown(struct drm_device *); 1276extern int nv04_instmem_suspend(struct drm_device *); 1277extern void nv04_instmem_resume(struct drm_device *); 1278extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1279 u32 size, u32 align); 1280extern void nv04_instmem_put(struct nouveau_gpuobj *); 1281extern int nv04_instmem_map(struct nouveau_gpuobj *); 1282extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1283extern void nv04_instmem_flush(struct drm_device *); 1284 1285/* nv50_instmem.c */ 1286extern int nv50_instmem_init(struct drm_device *); 1287extern void nv50_instmem_takedown(struct drm_device *); 1288extern int nv50_instmem_suspend(struct drm_device *); 1289extern void nv50_instmem_resume(struct drm_device *); 1290extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1291 u32 size, u32 align); 1292extern void nv50_instmem_put(struct nouveau_gpuobj *); 1293extern int nv50_instmem_map(struct nouveau_gpuobj *); 1294extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1295extern void nv50_instmem_flush(struct drm_device *); 1296extern void nv84_instmem_flush(struct drm_device *); 1297 1298/* nvc0_instmem.c */ 1299extern int nvc0_instmem_init(struct drm_device *); 1300extern void nvc0_instmem_takedown(struct drm_device *); 1301extern int nvc0_instmem_suspend(struct drm_device *); 1302extern void nvc0_instmem_resume(struct drm_device *); 1303 1304/* nv04_mc.c */ 1305extern int nv04_mc_init(struct drm_device *); 1306extern void nv04_mc_takedown(struct drm_device *); 1307 1308/* nv40_mc.c */ 1309extern int nv40_mc_init(struct drm_device *); 1310extern void nv40_mc_takedown(struct drm_device *); 1311 1312/* nv50_mc.c */ 1313extern int nv50_mc_init(struct drm_device *); 1314extern void nv50_mc_takedown(struct drm_device *); 1315 1316/* nv04_timer.c */ 1317extern int nv04_timer_init(struct drm_device *); 1318extern uint64_t nv04_timer_read(struct drm_device *); 1319extern void nv04_timer_takedown(struct drm_device *); 1320 1321extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1322 unsigned long arg); 1323 1324/* nv04_dac.c */ 1325extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1326extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1327extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1328extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1329extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1330 1331/* nv04_dfp.c */ 1332extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1333extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1334extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1335 int head, bool dl); 1336extern void nv04_dfp_disable(struct drm_device *dev, int head); 1337extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1338 1339/* nv04_tv.c */ 1340extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1341extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1342 1343/* nv17_tv.c */ 1344extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1345 1346/* nv04_display.c */ 1347extern int nv04_display_early_init(struct drm_device *); 1348extern void nv04_display_late_takedown(struct drm_device *); 1349extern int nv04_display_create(struct drm_device *); 1350extern int nv04_display_init(struct drm_device *); 1351extern void nv04_display_destroy(struct drm_device *); 1352 1353/* nvd0_display.c */ 1354extern int nvd0_display_create(struct drm_device *); 1355extern int nvd0_display_init(struct drm_device *); 1356extern void nvd0_display_destroy(struct drm_device *); 1357 1358/* nv04_crtc.c */ 1359extern int nv04_crtc_create(struct drm_device *, int index); 1360 1361/* nouveau_bo.c */ 1362extern struct ttm_bo_driver nouveau_bo_driver; 1363extern int nouveau_bo_new(struct drm_device *, int size, int align, 1364 uint32_t flags, uint32_t tile_mode, 1365 uint32_t tile_flags, struct nouveau_bo **); 1366extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1367extern int nouveau_bo_unpin(struct nouveau_bo *); 1368extern int nouveau_bo_map(struct nouveau_bo *); 1369extern void nouveau_bo_unmap(struct nouveau_bo *); 1370extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1371 uint32_t busy); 1372extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1373extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1374extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1375extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1376extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1377extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1378 bool no_wait_reserve, bool no_wait_gpu); 1379 1380extern struct nouveau_vma * 1381nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1382extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1383 struct nouveau_vma *); 1384extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1385 1386/* nouveau_fence.c */ 1387struct nouveau_fence; 1388extern int nouveau_fence_init(struct drm_device *); 1389extern void nouveau_fence_fini(struct drm_device *); 1390extern int nouveau_fence_channel_init(struct nouveau_channel *); 1391extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1392extern void nouveau_fence_update(struct nouveau_channel *); 1393extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1394 bool emit); 1395extern int nouveau_fence_emit(struct nouveau_fence *); 1396extern void nouveau_fence_work(struct nouveau_fence *fence, 1397 void (*work)(void *priv, bool signalled), 1398 void *priv); 1399struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1400 1401extern bool __nouveau_fence_signalled(void *obj, void *arg); 1402extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1403extern int __nouveau_fence_flush(void *obj, void *arg); 1404extern void __nouveau_fence_unref(void **obj); 1405extern void *__nouveau_fence_ref(void *obj); 1406 1407static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1408{ 1409 return __nouveau_fence_signalled(obj, NULL); 1410} 1411static inline int 1412nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1413{ 1414 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1415} 1416extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1417static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1418{ 1419 return __nouveau_fence_flush(obj, NULL); 1420} 1421static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1422{ 1423 __nouveau_fence_unref((void **)obj); 1424} 1425static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1426{ 1427 return __nouveau_fence_ref(obj); 1428} 1429 1430/* nouveau_gem.c */ 1431extern int nouveau_gem_new(struct drm_device *, int size, int align, 1432 uint32_t domain, uint32_t tile_mode, 1433 uint32_t tile_flags, struct nouveau_bo **); 1434extern int nouveau_gem_object_new(struct drm_gem_object *); 1435extern void nouveau_gem_object_del(struct drm_gem_object *); 1436extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1437extern void nouveau_gem_object_close(struct drm_gem_object *, 1438 struct drm_file *); 1439extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1440 struct drm_file *); 1441extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1442 struct drm_file *); 1443extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1444 struct drm_file *); 1445extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1446 struct drm_file *); 1447extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1448 struct drm_file *); 1449 1450/* nouveau_display.c */ 1451int nouveau_display_create(struct drm_device *dev); 1452void nouveau_display_destroy(struct drm_device *dev); 1453int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1454void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1455int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1456 struct drm_pending_vblank_event *event); 1457int nouveau_finish_page_flip(struct nouveau_channel *, 1458 struct nouveau_page_flip_state *); 1459int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1460 struct drm_mode_create_dumb *args); 1461int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1462 uint32_t handle, uint64_t *offset); 1463int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1464 uint32_t handle); 1465 1466/* nv10_gpio.c */ 1467int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1468int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1469 1470/* nv50_gpio.c */ 1471int nv50_gpio_init(struct drm_device *dev); 1472void nv50_gpio_fini(struct drm_device *dev); 1473int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1474int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1475int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1476int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1477int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1478 void (*)(void *, int), void *); 1479void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1480 void (*)(void *, int), void *); 1481bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1482 1483/* nv50_calc. */ 1484int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1485 int *N1, int *M1, int *N2, int *M2, int *P); 1486int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1487 int clk, int *N, int *fN, int *M, int *P); 1488 1489#ifndef ioread32_native 1490#ifdef __BIG_ENDIAN 1491#define ioread16_native ioread16be 1492#define iowrite16_native iowrite16be 1493#define ioread32_native ioread32be 1494#define iowrite32_native iowrite32be 1495#else /* def __BIG_ENDIAN */ 1496#define ioread16_native ioread16 1497#define iowrite16_native iowrite16 1498#define ioread32_native ioread32 1499#define iowrite32_native iowrite32 1500#endif /* def __BIG_ENDIAN else */ 1501#endif /* !ioread32_native */ 1502 1503/* channel control reg access */ 1504static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1505{ 1506 return ioread32_native(chan->user + reg); 1507} 1508 1509static inline void nvchan_wr32(struct nouveau_channel *chan, 1510 unsigned reg, u32 val) 1511{ 1512 iowrite32_native(val, chan->user + reg); 1513} 1514 1515/* register access */ 1516static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1517{ 1518 struct drm_nouveau_private *dev_priv = dev->dev_private; 1519 return ioread32_native(dev_priv->mmio + reg); 1520} 1521 1522static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1523{ 1524 struct drm_nouveau_private *dev_priv = dev->dev_private; 1525 iowrite32_native(val, dev_priv->mmio + reg); 1526} 1527 1528static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1529{ 1530 u32 tmp = nv_rd32(dev, reg); 1531 nv_wr32(dev, reg, (tmp & ~mask) | val); 1532 return tmp; 1533} 1534 1535static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1536{ 1537 struct drm_nouveau_private *dev_priv = dev->dev_private; 1538 return ioread8(dev_priv->mmio + reg); 1539} 1540 1541static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1542{ 1543 struct drm_nouveau_private *dev_priv = dev->dev_private; 1544 iowrite8(val, dev_priv->mmio + reg); 1545} 1546 1547#define nv_wait(dev, reg, mask, val) \ 1548 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1549#define nv_wait_ne(dev, reg, mask, val) \ 1550 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1551#define nv_wait_cb(dev, func, data) \ 1552 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1553 1554/* PRAMIN access */ 1555static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1556{ 1557 struct drm_nouveau_private *dev_priv = dev->dev_private; 1558 return ioread32_native(dev_priv->ramin + offset); 1559} 1560 1561static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1562{ 1563 struct drm_nouveau_private *dev_priv = dev->dev_private; 1564 iowrite32_native(val, dev_priv->ramin + offset); 1565} 1566 1567/* object access */ 1568extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1569extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1570 1571/* 1572 * Logging 1573 * Argument d is (struct drm_device *). 1574 */ 1575#define NV_PRINTK(level, d, fmt, arg...) \ 1576 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1577 pci_name(d->pdev), ##arg) 1578#ifndef NV_DEBUG_NOTRACE 1579#define NV_DEBUG(d, fmt, arg...) do { \ 1580 if (drm_debug & DRM_UT_DRIVER) { \ 1581 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1582 __LINE__, ##arg); \ 1583 } \ 1584} while (0) 1585#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1586 if (drm_debug & DRM_UT_KMS) { \ 1587 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1588 __LINE__, ##arg); \ 1589 } \ 1590} while (0) 1591#else 1592#define NV_DEBUG(d, fmt, arg...) do { \ 1593 if (drm_debug & DRM_UT_DRIVER) \ 1594 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1595} while (0) 1596#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1597 if (drm_debug & DRM_UT_KMS) \ 1598 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1599} while (0) 1600#endif 1601#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1602#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1603#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1604#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1605#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1606 1607/* nouveau_reg_debug bitmask */ 1608enum { 1609 NOUVEAU_REG_DEBUG_MC = 0x1, 1610 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1611 NOUVEAU_REG_DEBUG_FB = 0x4, 1612 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1613 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1614 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1615 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1616 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1617 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1618 NOUVEAU_REG_DEBUG_EVO = 0x200, 1619 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1620}; 1621 1622#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1623 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1624 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1625} while (0) 1626 1627static inline bool 1628nv_two_heads(struct drm_device *dev) 1629{ 1630 struct drm_nouveau_private *dev_priv = dev->dev_private; 1631 const int impl = dev->pci_device & 0x0ff0; 1632 1633 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1634 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1635 return true; 1636 1637 return false; 1638} 1639 1640static inline bool 1641nv_gf4_disp_arch(struct drm_device *dev) 1642{ 1643 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1644} 1645 1646static inline bool 1647nv_two_reg_pll(struct drm_device *dev) 1648{ 1649 struct drm_nouveau_private *dev_priv = dev->dev_private; 1650 const int impl = dev->pci_device & 0x0ff0; 1651 1652 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1653 return true; 1654 return false; 1655} 1656 1657static inline bool 1658nv_match_device(struct drm_device *dev, unsigned device, 1659 unsigned sub_vendor, unsigned sub_device) 1660{ 1661 return dev->pdev->device == device && 1662 dev->pdev->subsystem_vendor == sub_vendor && 1663 dev->pdev->subsystem_device == sub_device; 1664} 1665 1666static inline void * 1667nv_engine(struct drm_device *dev, int engine) 1668{ 1669 struct drm_nouveau_private *dev_priv = dev->dev_private; 1670 return (void *)dev_priv->eng[engine]; 1671} 1672 1673/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1674 * helpful to determine a number of other hardware features 1675 */ 1676static inline int 1677nv44_graph_class(struct drm_device *dev) 1678{ 1679 struct drm_nouveau_private *dev_priv = dev->dev_private; 1680 1681 if ((dev_priv->chipset & 0xf0) == 0x60) 1682 return 1; 1683 1684 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1685} 1686 1687/* memory type/access flags, do not match hardware values */ 1688#define NV_MEM_ACCESS_RO 1 1689#define NV_MEM_ACCESS_WO 2 1690#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1691#define NV_MEM_ACCESS_SYS 4 1692#define NV_MEM_ACCESS_VM 8 1693 1694#define NV_MEM_TARGET_VRAM 0 1695#define NV_MEM_TARGET_PCI 1 1696#define NV_MEM_TARGET_PCI_NOSNOOP 2 1697#define NV_MEM_TARGET_VM 3 1698#define NV_MEM_TARGET_GART 4 1699 1700#define NV_MEM_TYPE_VM 0x7f 1701#define NV_MEM_COMP_VM 0x03 1702 1703/* NV_SW object class */ 1704#define NV_SW 0x0000506e 1705#define NV_SW_DMA_SEMAPHORE 0x00000060 1706#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1707#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1708#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1709#define NV_SW_YIELD 0x00000080 1710#define NV_SW_DMA_VBLSEM 0x0000018c 1711#define NV_SW_VBLSEM_OFFSET 0x00000400 1712#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1713#define NV_SW_VBLSEM_RELEASE 0x00000408 1714#define NV_SW_PAGE_FLIP 0x00000500 1715 1716#endif /* __NOUVEAU_DRV_H__ */ 1717