nouveau_drv.h revision ddb2005516949dc50d117cb8381d7a3f8f0614b0
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_get_hi; 236 uint32_t user_put; 237 238 /* Fencing */ 239 struct { 240 /* lock protects the pending list only */ 241 spinlock_t lock; 242 struct list_head pending; 243 uint32_t sequence; 244 uint32_t sequence_ack; 245 atomic_t last_sequence_irq; 246 struct nouveau_vma vma; 247 } fence; 248 249 /* DMA push buffer */ 250 struct nouveau_gpuobj *pushbuf; 251 struct nouveau_bo *pushbuf_bo; 252 struct nouveau_vma pushbuf_vma; 253 uint64_t pushbuf_base; 254 255 /* Notifier memory */ 256 struct nouveau_bo *notifier_bo; 257 struct nouveau_vma notifier_vma; 258 struct drm_mm notifier_heap; 259 260 /* PFIFO context */ 261 struct nouveau_gpuobj *ramfc; 262 struct nouveau_gpuobj *cache; 263 void *fifo_priv; 264 265 /* Execution engine contexts */ 266 void *engctx[NVOBJ_ENGINE_NR]; 267 268 /* NV50 VM */ 269 struct nouveau_vm *vm; 270 struct nouveau_gpuobj *vm_pd; 271 272 /* Objects */ 273 struct nouveau_gpuobj *ramin; /* Private instmem */ 274 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 275 struct nouveau_ramht *ramht; /* Hash table */ 276 277 /* GPU object info for stuff used in-kernel (mm_enabled) */ 278 uint32_t m2mf_ntfy; 279 uint32_t vram_handle; 280 uint32_t gart_handle; 281 bool accel_done; 282 283 /* Push buffer state (only for drm's channel on !mm_enabled) */ 284 struct { 285 int max; 286 int free; 287 int cur; 288 int put; 289 /* access via pushbuf_bo */ 290 291 int ib_base; 292 int ib_max; 293 int ib_free; 294 int ib_put; 295 } dma; 296 297 uint32_t sw_subchannel[8]; 298 299 struct nouveau_vma dispc_vma[2]; 300 struct { 301 struct nouveau_gpuobj *vblsem; 302 uint32_t vblsem_head; 303 uint32_t vblsem_offset; 304 uint32_t vblsem_rval; 305 struct list_head vbl_wait; 306 struct list_head flip; 307 } nvsw; 308 309 struct { 310 bool active; 311 char name[32]; 312 struct drm_info_list info; 313 } debugfs; 314}; 315 316struct nouveau_exec_engine { 317 void (*destroy)(struct drm_device *, int engine); 318 int (*init)(struct drm_device *, int engine); 319 int (*fini)(struct drm_device *, int engine, bool suspend); 320 int (*context_new)(struct nouveau_channel *, int engine); 321 void (*context_del)(struct nouveau_channel *, int engine); 322 int (*object_new)(struct nouveau_channel *, int engine, 323 u32 handle, u16 class); 324 void (*set_tile_region)(struct drm_device *dev, int i); 325 void (*tlb_flush)(struct drm_device *, int engine); 326}; 327 328struct nouveau_instmem_engine { 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 int (*suspend)(struct drm_device *dev); 334 void (*resume)(struct drm_device *dev); 335 336 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 337 u32 size, u32 align); 338 void (*put)(struct nouveau_gpuobj *); 339 int (*map)(struct nouveau_gpuobj *); 340 void (*unmap)(struct nouveau_gpuobj *); 341 342 void (*flush)(struct drm_device *); 343}; 344 345struct nouveau_mc_engine { 346 int (*init)(struct drm_device *dev); 347 void (*takedown)(struct drm_device *dev); 348}; 349 350struct nouveau_timer_engine { 351 int (*init)(struct drm_device *dev); 352 void (*takedown)(struct drm_device *dev); 353 uint64_t (*read)(struct drm_device *dev); 354}; 355 356struct nouveau_fb_engine { 357 int num_tiles; 358 struct drm_mm tag_heap; 359 void *priv; 360 361 int (*init)(struct drm_device *dev); 362 void (*takedown)(struct drm_device *dev); 363 364 void (*init_tile_region)(struct drm_device *dev, int i, 365 uint32_t addr, uint32_t size, 366 uint32_t pitch, uint32_t flags); 367 void (*set_tile_region)(struct drm_device *dev, int i); 368 void (*free_tile_region)(struct drm_device *dev, int i); 369}; 370 371struct nouveau_fifo_engine { 372 void *priv; 373 int channels; 374 375 struct nouveau_gpuobj *playlist[2]; 376 int cur_playlist; 377 378 int (*init)(struct drm_device *); 379 void (*takedown)(struct drm_device *); 380 381 void (*disable)(struct drm_device *); 382 void (*enable)(struct drm_device *); 383 bool (*reassign)(struct drm_device *, bool enable); 384 bool (*cache_pull)(struct drm_device *dev, bool enable); 385 386 int (*channel_id)(struct drm_device *); 387 388 int (*create_context)(struct nouveau_channel *); 389 void (*destroy_context)(struct nouveau_channel *); 390 int (*load_context)(struct nouveau_channel *); 391 int (*unload_context)(struct drm_device *); 392 void (*tlb_flush)(struct drm_device *dev); 393}; 394 395struct nouveau_display_engine { 396 void *priv; 397 int (*early_init)(struct drm_device *); 398 void (*late_takedown)(struct drm_device *); 399 int (*create)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 int (*init)(struct drm_device *); 402 void (*fini)(struct drm_device *); 403 404 struct drm_property *dithering_mode; 405 struct drm_property *dithering_depth; 406 struct drm_property *underscan_property; 407 struct drm_property *underscan_hborder_property; 408 struct drm_property *underscan_vborder_property; 409}; 410 411struct nouveau_gpio_engine { 412 spinlock_t lock; 413 struct list_head isr; 414 int (*init)(struct drm_device *); 415 void (*fini)(struct drm_device *); 416 int (*drive)(struct drm_device *, int line, int dir, int out); 417 int (*sense)(struct drm_device *, int line); 418 void (*irq_enable)(struct drm_device *, int line, bool); 419}; 420 421struct nouveau_pm_voltage_level { 422 u32 voltage; /* microvolts */ 423 u8 vid; 424}; 425 426struct nouveau_pm_voltage { 427 bool supported; 428 u8 version; 429 u8 vid_mask; 430 431 struct nouveau_pm_voltage_level *level; 432 int nr_level; 433}; 434 435struct nouveau_pm_memtiming { 436 int id; 437 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 438 u32 reg_1; 439 u32 reg_2; 440 u32 reg_3; 441 u32 reg_4; 442 u32 reg_5; 443 u32 reg_6; 444 u32 reg_7; 445 u32 reg_8; 446 /* To be written to 0x1002c0 */ 447 u8 CL; 448 u8 WR; 449}; 450 451struct nouveau_pm_tbl_header { 452 u8 version; 453 u8 header_len; 454 u8 entry_cnt; 455 u8 entry_len; 456}; 457 458struct nouveau_pm_tbl_entry { 459 u8 tWR; 460 u8 tUNK_1; 461 u8 tCL; 462 u8 tRP; /* Byte 3 */ 463 u8 empty_4; 464 u8 tRAS; /* Byte 5 */ 465 u8 empty_6; 466 u8 tRFC; /* Byte 7 */ 467 u8 empty_8; 468 u8 tRC; /* Byte 9 */ 469 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 470 u8 empty_15,empty_16,empty_17; 471 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 472}; 473 474#define NOUVEAU_PM_MAX_LEVEL 8 475struct nouveau_pm_level { 476 struct device_attribute dev_attr; 477 char name[32]; 478 int id; 479 480 u32 core; 481 u32 memory; 482 u32 shader; 483 u32 rop; 484 u32 copy; 485 u32 daemon; 486 u32 vdec; 487 u32 dom6; 488 u32 unka0; /* nva3:nvc0 */ 489 u32 hub01; /* nvc0- */ 490 u32 hub06; /* nvc0- */ 491 u32 hub07; /* nvc0- */ 492 493 u32 volt_min; /* microvolts */ 494 u32 volt_max; 495 u8 fanspeed; 496 497 u16 memscript; 498 struct nouveau_pm_memtiming *timing; 499}; 500 501struct nouveau_pm_temp_sensor_constants { 502 u16 offset_constant; 503 s16 offset_mult; 504 s16 offset_div; 505 s16 slope_mult; 506 s16 slope_div; 507}; 508 509struct nouveau_pm_threshold_temp { 510 s16 critical; 511 s16 down_clock; 512 s16 fan_boost; 513}; 514 515struct nouveau_pm_memtimings { 516 bool supported; 517 struct nouveau_pm_memtiming *timing; 518 int nr_timing; 519}; 520 521struct nouveau_pm_fan { 522 u32 min_duty; 523 u32 max_duty; 524 u32 pwm_freq; 525}; 526 527struct nouveau_pm_engine { 528 struct nouveau_pm_voltage voltage; 529 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 530 int nr_perflvl; 531 struct nouveau_pm_memtimings memtimings; 532 struct nouveau_pm_temp_sensor_constants sensor_constants; 533 struct nouveau_pm_threshold_temp threshold_temp; 534 struct nouveau_pm_fan fan; 535 u32 pwm_divisor; 536 537 struct nouveau_pm_level boot; 538 struct nouveau_pm_level *cur; 539 540 struct device *hwmon; 541 struct notifier_block acpi_nb; 542 543 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 544 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 545 int (*clocks_set)(struct drm_device *, void *); 546 547 int (*voltage_get)(struct drm_device *); 548 int (*voltage_set)(struct drm_device *, int voltage); 549 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 550 int (*pwm_set)(struct drm_device *, int line, u32, u32); 551 int (*temp_get)(struct drm_device *); 552}; 553 554struct nouveau_vram_engine { 555 struct nouveau_mm mm; 556 557 int (*init)(struct drm_device *); 558 void (*takedown)(struct drm_device *dev); 559 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 560 u32 type, struct nouveau_mem **); 561 void (*put)(struct drm_device *, struct nouveau_mem **); 562 563 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 564}; 565 566struct nouveau_engine { 567 struct nouveau_instmem_engine instmem; 568 struct nouveau_mc_engine mc; 569 struct nouveau_timer_engine timer; 570 struct nouveau_fb_engine fb; 571 struct nouveau_fifo_engine fifo; 572 struct nouveau_display_engine display; 573 struct nouveau_gpio_engine gpio; 574 struct nouveau_pm_engine pm; 575 struct nouveau_vram_engine vram; 576}; 577 578struct nouveau_pll_vals { 579 union { 580 struct { 581#ifdef __BIG_ENDIAN 582 uint8_t N1, M1, N2, M2; 583#else 584 uint8_t M1, N1, M2, N2; 585#endif 586 }; 587 struct { 588 uint16_t NM1, NM2; 589 } __attribute__((packed)); 590 }; 591 int log2P; 592 593 int refclk; 594}; 595 596enum nv04_fp_display_regs { 597 FP_DISPLAY_END, 598 FP_TOTAL, 599 FP_CRTC, 600 FP_SYNC_START, 601 FP_SYNC_END, 602 FP_VALID_START, 603 FP_VALID_END 604}; 605 606struct nv04_crtc_reg { 607 unsigned char MiscOutReg; 608 uint8_t CRTC[0xa0]; 609 uint8_t CR58[0x10]; 610 uint8_t Sequencer[5]; 611 uint8_t Graphics[9]; 612 uint8_t Attribute[21]; 613 unsigned char DAC[768]; 614 615 /* PCRTC regs */ 616 uint32_t fb_start; 617 uint32_t crtc_cfg; 618 uint32_t cursor_cfg; 619 uint32_t gpio_ext; 620 uint32_t crtc_830; 621 uint32_t crtc_834; 622 uint32_t crtc_850; 623 uint32_t crtc_eng_ctrl; 624 625 /* PRAMDAC regs */ 626 uint32_t nv10_cursync; 627 struct nouveau_pll_vals pllvals; 628 uint32_t ramdac_gen_ctrl; 629 uint32_t ramdac_630; 630 uint32_t ramdac_634; 631 uint32_t tv_setup; 632 uint32_t tv_vtotal; 633 uint32_t tv_vskew; 634 uint32_t tv_vsync_delay; 635 uint32_t tv_htotal; 636 uint32_t tv_hskew; 637 uint32_t tv_hsync_delay; 638 uint32_t tv_hsync_delay2; 639 uint32_t fp_horiz_regs[7]; 640 uint32_t fp_vert_regs[7]; 641 uint32_t dither; 642 uint32_t fp_control; 643 uint32_t dither_regs[6]; 644 uint32_t fp_debug_0; 645 uint32_t fp_debug_1; 646 uint32_t fp_debug_2; 647 uint32_t fp_margin_color; 648 uint32_t ramdac_8c0; 649 uint32_t ramdac_a20; 650 uint32_t ramdac_a24; 651 uint32_t ramdac_a34; 652 uint32_t ctv_regs[38]; 653}; 654 655struct nv04_output_reg { 656 uint32_t output; 657 int head; 658}; 659 660struct nv04_mode_state { 661 struct nv04_crtc_reg crtc_reg[2]; 662 uint32_t pllsel; 663 uint32_t sel_clk; 664}; 665 666enum nouveau_card_type { 667 NV_04 = 0x00, 668 NV_10 = 0x10, 669 NV_20 = 0x20, 670 NV_30 = 0x30, 671 NV_40 = 0x40, 672 NV_50 = 0x50, 673 NV_C0 = 0xc0, 674 NV_D0 = 0xd0 675}; 676 677struct drm_nouveau_private { 678 struct drm_device *dev; 679 bool noaccel; 680 681 /* the card type, takes NV_* as values */ 682 enum nouveau_card_type card_type; 683 /* exact chipset, derived from NV_PMC_BOOT_0 */ 684 int chipset; 685 int flags; 686 u32 crystal; 687 688 void __iomem *mmio; 689 690 spinlock_t ramin_lock; 691 void __iomem *ramin; 692 u32 ramin_size; 693 u32 ramin_base; 694 bool ramin_available; 695 struct drm_mm ramin_heap; 696 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 697 struct list_head gpuobj_list; 698 struct list_head classes; 699 700 struct nouveau_bo *vga_ram; 701 702 /* interrupt handling */ 703 void (*irq_handler[32])(struct drm_device *); 704 bool msi_enabled; 705 706 struct list_head vbl_waiting; 707 708 struct { 709 struct drm_global_reference mem_global_ref; 710 struct ttm_bo_global_ref bo_global_ref; 711 struct ttm_bo_device bdev; 712 atomic_t validate_sequence; 713 } ttm; 714 715 struct { 716 spinlock_t lock; 717 struct drm_mm heap; 718 struct nouveau_bo *bo; 719 } fence; 720 721 struct { 722 spinlock_t lock; 723 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 724 } channels; 725 726 struct nouveau_engine engine; 727 struct nouveau_channel *channel; 728 729 /* For PFIFO and PGRAPH. */ 730 spinlock_t context_switch_lock; 731 732 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 733 spinlock_t vm_lock; 734 735 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 736 struct nouveau_ramht *ramht; 737 struct nouveau_gpuobj *ramfc; 738 struct nouveau_gpuobj *ramro; 739 740 uint32_t ramin_rsvd_vram; 741 742 struct { 743 enum { 744 NOUVEAU_GART_NONE = 0, 745 NOUVEAU_GART_AGP, /* AGP */ 746 NOUVEAU_GART_PDMA, /* paged dma object */ 747 NOUVEAU_GART_HW /* on-chip gart/vm */ 748 } type; 749 uint64_t aper_base; 750 uint64_t aper_size; 751 uint64_t aper_free; 752 753 struct ttm_backend_func *func; 754 755 struct { 756 struct page *page; 757 dma_addr_t addr; 758 } dummy; 759 760 struct nouveau_gpuobj *sg_ctxdma; 761 } gart_info; 762 763 /* nv10-nv40 tiling regions */ 764 struct { 765 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 766 spinlock_t lock; 767 } tile; 768 769 /* VRAM/fb configuration */ 770 enum { 771 NV_MEM_TYPE_UNKNOWN = 0, 772 NV_MEM_TYPE_STOLEN, 773 NV_MEM_TYPE_SGRAM, 774 NV_MEM_TYPE_SDRAM, 775 NV_MEM_TYPE_DDR1, 776 NV_MEM_TYPE_DDR2, 777 NV_MEM_TYPE_DDR3, 778 NV_MEM_TYPE_GDDR2, 779 NV_MEM_TYPE_GDDR3, 780 NV_MEM_TYPE_GDDR4, 781 NV_MEM_TYPE_GDDR5 782 } vram_type; 783 uint64_t vram_size; 784 uint64_t vram_sys_base; 785 786 uint64_t fb_available_size; 787 uint64_t fb_mappable_pages; 788 uint64_t fb_aper_free; 789 int fb_mtrr; 790 791 /* BAR control (NV50-) */ 792 struct nouveau_vm *bar1_vm; 793 struct nouveau_vm *bar3_vm; 794 795 /* G8x/G9x virtual address space */ 796 struct nouveau_vm *chan_vm; 797 798 struct nvbios vbios; 799 u8 *mxms; 800 struct list_head i2c_ports; 801 802 struct nv04_mode_state mode_reg; 803 struct nv04_mode_state saved_reg; 804 uint32_t saved_vga_font[4][16384]; 805 uint32_t crtc_owner; 806 uint32_t dac_users[4]; 807 808 struct backlight_device *backlight; 809 810 struct { 811 struct dentry *channel_root; 812 } debugfs; 813 814 struct nouveau_fbdev *nfbdev; 815 struct apertures_struct *apertures; 816}; 817 818static inline struct drm_nouveau_private * 819nouveau_private(struct drm_device *dev) 820{ 821 return dev->dev_private; 822} 823 824static inline struct drm_nouveau_private * 825nouveau_bdev(struct ttm_bo_device *bd) 826{ 827 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 828} 829 830static inline int 831nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 832{ 833 struct nouveau_bo *prev; 834 835 if (!pnvbo) 836 return -EINVAL; 837 prev = *pnvbo; 838 839 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 840 if (prev) { 841 struct ttm_buffer_object *bo = &prev->bo; 842 843 ttm_bo_unref(&bo); 844 } 845 846 return 0; 847} 848 849/* nouveau_drv.c */ 850extern int nouveau_modeset; 851extern int nouveau_agpmode; 852extern int nouveau_duallink; 853extern int nouveau_uscript_lvds; 854extern int nouveau_uscript_tmds; 855extern int nouveau_vram_pushbuf; 856extern int nouveau_vram_notify; 857extern char *nouveau_vram_type; 858extern int nouveau_fbpercrtc; 859extern int nouveau_tv_disable; 860extern char *nouveau_tv_norm; 861extern int nouveau_reg_debug; 862extern char *nouveau_vbios; 863extern int nouveau_ignorelid; 864extern int nouveau_nofbaccel; 865extern int nouveau_noaccel; 866extern int nouveau_force_post; 867extern int nouveau_override_conntype; 868extern char *nouveau_perflvl; 869extern int nouveau_perflvl_wr; 870extern int nouveau_msi; 871extern int nouveau_ctxfw; 872extern int nouveau_mxmdcb; 873 874extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 875extern int nouveau_pci_resume(struct pci_dev *pdev); 876 877/* nouveau_state.c */ 878extern int nouveau_open(struct drm_device *, struct drm_file *); 879extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 880extern void nouveau_postclose(struct drm_device *, struct drm_file *); 881extern int nouveau_load(struct drm_device *, unsigned long flags); 882extern int nouveau_firstopen(struct drm_device *); 883extern void nouveau_lastclose(struct drm_device *); 884extern int nouveau_unload(struct drm_device *); 885extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 886 struct drm_file *); 887extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 888 struct drm_file *); 889extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 890 uint32_t reg, uint32_t mask, uint32_t val); 891extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 892 uint32_t reg, uint32_t mask, uint32_t val); 893extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 894 bool (*cond)(void *), void *); 895extern bool nouveau_wait_for_idle(struct drm_device *); 896extern int nouveau_card_init(struct drm_device *); 897 898/* nouveau_mem.c */ 899extern int nouveau_mem_vram_init(struct drm_device *); 900extern void nouveau_mem_vram_fini(struct drm_device *); 901extern int nouveau_mem_gart_init(struct drm_device *); 902extern void nouveau_mem_gart_fini(struct drm_device *); 903extern int nouveau_mem_init_agp(struct drm_device *); 904extern int nouveau_mem_reset_agp(struct drm_device *); 905extern void nouveau_mem_close(struct drm_device *); 906extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 907extern int nouveau_mem_vbios_type(struct drm_device *); 908extern struct nouveau_tile_reg *nv10_mem_set_tiling( 909 struct drm_device *dev, uint32_t addr, uint32_t size, 910 uint32_t pitch, uint32_t flags); 911extern void nv10_mem_put_tile_region(struct drm_device *dev, 912 struct nouveau_tile_reg *tile, 913 struct nouveau_fence *fence); 914extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 915extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 916void nv30_mem_timing_entry(struct drm_device *dev, 917 struct nouveau_pm_tbl_header *hdr, 918 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 919 struct nouveau_pm_memtiming *timing); 920 921/* nouveau_notifier.c */ 922extern int nouveau_notifier_init_channel(struct nouveau_channel *); 923extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 924extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 925 int cout, uint32_t start, uint32_t end, 926 uint32_t *offset); 927extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 928extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 929 struct drm_file *); 930extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 931 struct drm_file *); 932 933/* nouveau_channel.c */ 934extern struct drm_ioctl_desc nouveau_ioctls[]; 935extern int nouveau_max_ioctl; 936extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 937extern int nouveau_channel_alloc(struct drm_device *dev, 938 struct nouveau_channel **chan, 939 struct drm_file *file_priv, 940 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 941extern struct nouveau_channel * 942nouveau_channel_get_unlocked(struct nouveau_channel *); 943extern struct nouveau_channel * 944nouveau_channel_get(struct drm_file *, int id); 945extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 946extern void nouveau_channel_put(struct nouveau_channel **); 947extern void nouveau_channel_ref(struct nouveau_channel *chan, 948 struct nouveau_channel **pchan); 949extern void nouveau_channel_idle(struct nouveau_channel *chan); 950 951/* nouveau_object.c */ 952#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 953 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 954 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 955} while (0) 956 957#define NVOBJ_ENGINE_DEL(d, e) do { \ 958 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 959 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 960} while (0) 961 962#define NVOBJ_CLASS(d, c, e) do { \ 963 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 964 if (ret) \ 965 return ret; \ 966} while (0) 967 968#define NVOBJ_MTHD(d, c, m, e) do { \ 969 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 970 if (ret) \ 971 return ret; \ 972} while (0) 973 974extern int nouveau_gpuobj_early_init(struct drm_device *); 975extern int nouveau_gpuobj_init(struct drm_device *); 976extern void nouveau_gpuobj_takedown(struct drm_device *); 977extern int nouveau_gpuobj_suspend(struct drm_device *dev); 978extern void nouveau_gpuobj_resume(struct drm_device *dev); 979extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 980extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 981 int (*exec)(struct nouveau_channel *, 982 u32 class, u32 mthd, u32 data)); 983extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 984extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 985extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 986 uint32_t vram_h, uint32_t tt_h); 987extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 988extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 989 uint32_t size, int align, uint32_t flags, 990 struct nouveau_gpuobj **); 991extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 992 struct nouveau_gpuobj **); 993extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 994 u32 size, u32 flags, 995 struct nouveau_gpuobj **); 996extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 997 uint64_t offset, uint64_t size, int access, 998 int target, struct nouveau_gpuobj **); 999extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 1000extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 1001 u64 size, int target, int access, u32 type, 1002 u32 comp, struct nouveau_gpuobj **pobj); 1003extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 1004 int class, u64 base, u64 size, int target, 1005 int access, u32 type, u32 comp); 1006extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 1007 struct drm_file *); 1008extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 1009 struct drm_file *); 1010 1011/* nouveau_irq.c */ 1012extern int nouveau_irq_init(struct drm_device *); 1013extern void nouveau_irq_fini(struct drm_device *); 1014extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1015extern void nouveau_irq_register(struct drm_device *, int status_bit, 1016 void (*)(struct drm_device *)); 1017extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1018extern void nouveau_irq_preinstall(struct drm_device *); 1019extern int nouveau_irq_postinstall(struct drm_device *); 1020extern void nouveau_irq_uninstall(struct drm_device *); 1021 1022/* nouveau_sgdma.c */ 1023extern int nouveau_sgdma_init(struct drm_device *); 1024extern void nouveau_sgdma_takedown(struct drm_device *); 1025extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1026 uint32_t offset); 1027extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1028 unsigned long size, 1029 uint32_t page_flags, 1030 struct page *dummy_read_page); 1031 1032/* nouveau_debugfs.c */ 1033#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1034extern int nouveau_debugfs_init(struct drm_minor *); 1035extern void nouveau_debugfs_takedown(struct drm_minor *); 1036extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1037extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1038#else 1039static inline int 1040nouveau_debugfs_init(struct drm_minor *minor) 1041{ 1042 return 0; 1043} 1044 1045static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1046{ 1047} 1048 1049static inline int 1050nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1051{ 1052 return 0; 1053} 1054 1055static inline void 1056nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1057{ 1058} 1059#endif 1060 1061/* nouveau_dma.c */ 1062extern void nouveau_dma_pre_init(struct nouveau_channel *); 1063extern int nouveau_dma_init(struct nouveau_channel *); 1064extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1065 1066/* nouveau_acpi.c */ 1067#define ROM_BIOS_PAGE 4096 1068#if defined(CONFIG_ACPI) 1069void nouveau_register_dsm_handler(void); 1070void nouveau_unregister_dsm_handler(void); 1071void nouveau_switcheroo_optimus_dsm(void); 1072int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1073bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1074int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1075#else 1076static inline void nouveau_register_dsm_handler(void) {} 1077static inline void nouveau_unregister_dsm_handler(void) {} 1078static inline void nouveau_switcheroo_optimus_dsm(void) {} 1079static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1080static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1081static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1082#endif 1083 1084/* nouveau_backlight.c */ 1085#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1086extern int nouveau_backlight_init(struct drm_device *); 1087extern void nouveau_backlight_exit(struct drm_device *); 1088#else 1089static inline int nouveau_backlight_init(struct drm_device *dev) 1090{ 1091 return 0; 1092} 1093 1094static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1095#endif 1096 1097/* nouveau_bios.c */ 1098extern int nouveau_bios_init(struct drm_device *); 1099extern void nouveau_bios_takedown(struct drm_device *dev); 1100extern int nouveau_run_vbios_init(struct drm_device *); 1101extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1102 struct dcb_entry *, int crtc); 1103extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1104extern struct dcb_connector_table_entry * 1105nouveau_bios_connector_entry(struct drm_device *, int index); 1106extern u32 get_pll_register(struct drm_device *, enum pll_types); 1107extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1108 struct pll_lims *); 1109extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1110 struct dcb_entry *, int crtc); 1111extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1112extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1113extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1114 bool *dl, bool *if_is_24bit); 1115extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1116 int head, int pxclk); 1117extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1118 enum LVDS_script, int pxclk); 1119bool bios_encoder_match(struct dcb_entry *, u32 hash); 1120 1121/* nouveau_mxm.c */ 1122int nouveau_mxm_init(struct drm_device *dev); 1123void nouveau_mxm_fini(struct drm_device *dev); 1124 1125/* nouveau_ttm.c */ 1126int nouveau_ttm_global_init(struct drm_nouveau_private *); 1127void nouveau_ttm_global_release(struct drm_nouveau_private *); 1128int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1129 1130/* nouveau_hdmi.c */ 1131void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1132 1133/* nouveau_dp.c */ 1134int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1135 uint8_t *data, int data_nr); 1136bool nouveau_dp_detect(struct drm_encoder *); 1137bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1138void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1139u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1140 1141/* nv04_fb.c */ 1142extern int nv04_fb_vram_init(struct drm_device *); 1143extern int nv04_fb_init(struct drm_device *); 1144extern void nv04_fb_takedown(struct drm_device *); 1145 1146/* nv10_fb.c */ 1147extern int nv10_fb_vram_init(struct drm_device *dev); 1148extern int nv1a_fb_vram_init(struct drm_device *dev); 1149extern int nv10_fb_init(struct drm_device *); 1150extern void nv10_fb_takedown(struct drm_device *); 1151extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1152 uint32_t addr, uint32_t size, 1153 uint32_t pitch, uint32_t flags); 1154extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1155extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1156 1157/* nv20_fb.c */ 1158extern int nv20_fb_vram_init(struct drm_device *dev); 1159extern int nv20_fb_init(struct drm_device *); 1160extern void nv20_fb_takedown(struct drm_device *); 1161extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1162 uint32_t addr, uint32_t size, 1163 uint32_t pitch, uint32_t flags); 1164extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1165extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1166 1167/* nv30_fb.c */ 1168extern int nv30_fb_init(struct drm_device *); 1169extern void nv30_fb_takedown(struct drm_device *); 1170extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1171 uint32_t addr, uint32_t size, 1172 uint32_t pitch, uint32_t flags); 1173extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1174 1175/* nv40_fb.c */ 1176extern int nv40_fb_vram_init(struct drm_device *dev); 1177extern int nv40_fb_init(struct drm_device *); 1178extern void nv40_fb_takedown(struct drm_device *); 1179extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1180 1181/* nv50_fb.c */ 1182extern int nv50_fb_init(struct drm_device *); 1183extern void nv50_fb_takedown(struct drm_device *); 1184extern void nv50_fb_vm_trap(struct drm_device *, int display); 1185 1186/* nvc0_fb.c */ 1187extern int nvc0_fb_init(struct drm_device *); 1188extern void nvc0_fb_takedown(struct drm_device *); 1189 1190/* nv04_fifo.c */ 1191extern int nv04_fifo_init(struct drm_device *); 1192extern void nv04_fifo_fini(struct drm_device *); 1193extern void nv04_fifo_disable(struct drm_device *); 1194extern void nv04_fifo_enable(struct drm_device *); 1195extern bool nv04_fifo_reassign(struct drm_device *, bool); 1196extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1197extern int nv04_fifo_channel_id(struct drm_device *); 1198extern int nv04_fifo_create_context(struct nouveau_channel *); 1199extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1200extern int nv04_fifo_load_context(struct nouveau_channel *); 1201extern int nv04_fifo_unload_context(struct drm_device *); 1202extern void nv04_fifo_isr(struct drm_device *); 1203 1204/* nv10_fifo.c */ 1205extern int nv10_fifo_init(struct drm_device *); 1206extern int nv10_fifo_channel_id(struct drm_device *); 1207extern int nv10_fifo_create_context(struct nouveau_channel *); 1208extern int nv10_fifo_load_context(struct nouveau_channel *); 1209extern int nv10_fifo_unload_context(struct drm_device *); 1210 1211/* nv40_fifo.c */ 1212extern int nv40_fifo_init(struct drm_device *); 1213extern int nv40_fifo_create_context(struct nouveau_channel *); 1214extern int nv40_fifo_load_context(struct nouveau_channel *); 1215extern int nv40_fifo_unload_context(struct drm_device *); 1216 1217/* nv50_fifo.c */ 1218extern int nv50_fifo_init(struct drm_device *); 1219extern void nv50_fifo_takedown(struct drm_device *); 1220extern int nv50_fifo_channel_id(struct drm_device *); 1221extern int nv50_fifo_create_context(struct nouveau_channel *); 1222extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1223extern int nv50_fifo_load_context(struct nouveau_channel *); 1224extern int nv50_fifo_unload_context(struct drm_device *); 1225extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1226 1227/* nvc0_fifo.c */ 1228extern int nvc0_fifo_init(struct drm_device *); 1229extern void nvc0_fifo_takedown(struct drm_device *); 1230extern void nvc0_fifo_disable(struct drm_device *); 1231extern void nvc0_fifo_enable(struct drm_device *); 1232extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1233extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1234extern int nvc0_fifo_channel_id(struct drm_device *); 1235extern int nvc0_fifo_create_context(struct nouveau_channel *); 1236extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1237extern int nvc0_fifo_load_context(struct nouveau_channel *); 1238extern int nvc0_fifo_unload_context(struct drm_device *); 1239 1240/* nv04_graph.c */ 1241extern int nv04_graph_create(struct drm_device *); 1242extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1243extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1244 u32 class, u32 mthd, u32 data); 1245extern struct nouveau_bitfield nv04_graph_nsource[]; 1246 1247/* nv10_graph.c */ 1248extern int nv10_graph_create(struct drm_device *); 1249extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1250extern struct nouveau_bitfield nv10_graph_intr[]; 1251extern struct nouveau_bitfield nv10_graph_nstatus[]; 1252 1253/* nv20_graph.c */ 1254extern int nv20_graph_create(struct drm_device *); 1255 1256/* nv40_graph.c */ 1257extern int nv40_graph_create(struct drm_device *); 1258extern void nv40_grctx_init(struct nouveau_grctx *); 1259 1260/* nv50_graph.c */ 1261extern int nv50_graph_create(struct drm_device *); 1262extern int nv50_grctx_init(struct nouveau_grctx *); 1263extern struct nouveau_enum nv50_data_error_names[]; 1264extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1265 1266/* nvc0_graph.c */ 1267extern int nvc0_graph_create(struct drm_device *); 1268extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1269 1270/* nv84_crypt.c */ 1271extern int nv84_crypt_create(struct drm_device *); 1272 1273/* nv98_crypt.c */ 1274extern int nv98_crypt_create(struct drm_device *dev); 1275 1276/* nva3_copy.c */ 1277extern int nva3_copy_create(struct drm_device *dev); 1278 1279/* nvc0_copy.c */ 1280extern int nvc0_copy_create(struct drm_device *dev, int engine); 1281 1282/* nv31_mpeg.c */ 1283extern int nv31_mpeg_create(struct drm_device *dev); 1284 1285/* nv50_mpeg.c */ 1286extern int nv50_mpeg_create(struct drm_device *dev); 1287 1288/* nv84_bsp.c */ 1289/* nv98_bsp.c */ 1290extern int nv84_bsp_create(struct drm_device *dev); 1291 1292/* nv84_vp.c */ 1293/* nv98_vp.c */ 1294extern int nv84_vp_create(struct drm_device *dev); 1295 1296/* nv98_ppp.c */ 1297extern int nv98_ppp_create(struct drm_device *dev); 1298 1299/* nv04_instmem.c */ 1300extern int nv04_instmem_init(struct drm_device *); 1301extern void nv04_instmem_takedown(struct drm_device *); 1302extern int nv04_instmem_suspend(struct drm_device *); 1303extern void nv04_instmem_resume(struct drm_device *); 1304extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1305 u32 size, u32 align); 1306extern void nv04_instmem_put(struct nouveau_gpuobj *); 1307extern int nv04_instmem_map(struct nouveau_gpuobj *); 1308extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1309extern void nv04_instmem_flush(struct drm_device *); 1310 1311/* nv50_instmem.c */ 1312extern int nv50_instmem_init(struct drm_device *); 1313extern void nv50_instmem_takedown(struct drm_device *); 1314extern int nv50_instmem_suspend(struct drm_device *); 1315extern void nv50_instmem_resume(struct drm_device *); 1316extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1317 u32 size, u32 align); 1318extern void nv50_instmem_put(struct nouveau_gpuobj *); 1319extern int nv50_instmem_map(struct nouveau_gpuobj *); 1320extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1321extern void nv50_instmem_flush(struct drm_device *); 1322extern void nv84_instmem_flush(struct drm_device *); 1323 1324/* nvc0_instmem.c */ 1325extern int nvc0_instmem_init(struct drm_device *); 1326extern void nvc0_instmem_takedown(struct drm_device *); 1327extern int nvc0_instmem_suspend(struct drm_device *); 1328extern void nvc0_instmem_resume(struct drm_device *); 1329 1330/* nv04_mc.c */ 1331extern int nv04_mc_init(struct drm_device *); 1332extern void nv04_mc_takedown(struct drm_device *); 1333 1334/* nv40_mc.c */ 1335extern int nv40_mc_init(struct drm_device *); 1336extern void nv40_mc_takedown(struct drm_device *); 1337 1338/* nv50_mc.c */ 1339extern int nv50_mc_init(struct drm_device *); 1340extern void nv50_mc_takedown(struct drm_device *); 1341 1342/* nv04_timer.c */ 1343extern int nv04_timer_init(struct drm_device *); 1344extern uint64_t nv04_timer_read(struct drm_device *); 1345extern void nv04_timer_takedown(struct drm_device *); 1346 1347extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1348 unsigned long arg); 1349 1350/* nv04_dac.c */ 1351extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1352extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1353extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1354extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1355extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1356 1357/* nv04_dfp.c */ 1358extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1359extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1360extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1361 int head, bool dl); 1362extern void nv04_dfp_disable(struct drm_device *dev, int head); 1363extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1364 1365/* nv04_tv.c */ 1366extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1367extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1368 1369/* nv17_tv.c */ 1370extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1371 1372/* nv04_display.c */ 1373extern int nv04_display_early_init(struct drm_device *); 1374extern void nv04_display_late_takedown(struct drm_device *); 1375extern int nv04_display_create(struct drm_device *); 1376extern void nv04_display_destroy(struct drm_device *); 1377extern int nv04_display_init(struct drm_device *); 1378extern void nv04_display_fini(struct drm_device *); 1379 1380/* nvd0_display.c */ 1381extern int nvd0_display_create(struct drm_device *); 1382extern void nvd0_display_destroy(struct drm_device *); 1383extern int nvd0_display_init(struct drm_device *); 1384extern void nvd0_display_fini(struct drm_device *); 1385struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1386void nvd0_display_flip_stop(struct drm_crtc *); 1387int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1388 struct nouveau_channel *, u32 swap_interval); 1389 1390/* nv04_crtc.c */ 1391extern int nv04_crtc_create(struct drm_device *, int index); 1392 1393/* nouveau_bo.c */ 1394extern struct ttm_bo_driver nouveau_bo_driver; 1395extern int nouveau_bo_new(struct drm_device *, int size, int align, 1396 uint32_t flags, uint32_t tile_mode, 1397 uint32_t tile_flags, struct nouveau_bo **); 1398extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1399extern int nouveau_bo_unpin(struct nouveau_bo *); 1400extern int nouveau_bo_map(struct nouveau_bo *); 1401extern void nouveau_bo_unmap(struct nouveau_bo *); 1402extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1403 uint32_t busy); 1404extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1405extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1406extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1407extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1408extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1409extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1410 bool no_wait_reserve, bool no_wait_gpu); 1411 1412extern struct nouveau_vma * 1413nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1414extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1415 struct nouveau_vma *); 1416extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1417 1418/* nouveau_fence.c */ 1419struct nouveau_fence; 1420extern int nouveau_fence_init(struct drm_device *); 1421extern void nouveau_fence_fini(struct drm_device *); 1422extern int nouveau_fence_channel_init(struct nouveau_channel *); 1423extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1424extern void nouveau_fence_update(struct nouveau_channel *); 1425extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1426 bool emit); 1427extern int nouveau_fence_emit(struct nouveau_fence *); 1428extern void nouveau_fence_work(struct nouveau_fence *fence, 1429 void (*work)(void *priv, bool signalled), 1430 void *priv); 1431struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1432 1433extern bool __nouveau_fence_signalled(void *obj, void *arg); 1434extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1435extern int __nouveau_fence_flush(void *obj, void *arg); 1436extern void __nouveau_fence_unref(void **obj); 1437extern void *__nouveau_fence_ref(void *obj); 1438 1439static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1440{ 1441 return __nouveau_fence_signalled(obj, NULL); 1442} 1443static inline int 1444nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1445{ 1446 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1447} 1448extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1449static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1450{ 1451 return __nouveau_fence_flush(obj, NULL); 1452} 1453static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1454{ 1455 __nouveau_fence_unref((void **)obj); 1456} 1457static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1458{ 1459 return __nouveau_fence_ref(obj); 1460} 1461 1462/* nouveau_gem.c */ 1463extern int nouveau_gem_new(struct drm_device *, int size, int align, 1464 uint32_t domain, uint32_t tile_mode, 1465 uint32_t tile_flags, struct nouveau_bo **); 1466extern int nouveau_gem_object_new(struct drm_gem_object *); 1467extern void nouveau_gem_object_del(struct drm_gem_object *); 1468extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1469extern void nouveau_gem_object_close(struct drm_gem_object *, 1470 struct drm_file *); 1471extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1472 struct drm_file *); 1473extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1474 struct drm_file *); 1475extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1476 struct drm_file *); 1477extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1478 struct drm_file *); 1479extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1480 struct drm_file *); 1481 1482/* nouveau_display.c */ 1483int nouveau_display_create(struct drm_device *dev); 1484void nouveau_display_destroy(struct drm_device *dev); 1485int nouveau_display_init(struct drm_device *dev); 1486void nouveau_display_fini(struct drm_device *dev); 1487int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1488void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1489int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1490 struct drm_pending_vblank_event *event); 1491int nouveau_finish_page_flip(struct nouveau_channel *, 1492 struct nouveau_page_flip_state *); 1493int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1494 struct drm_mode_create_dumb *args); 1495int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1496 uint32_t handle, uint64_t *offset); 1497int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1498 uint32_t handle); 1499 1500/* nv10_gpio.c */ 1501int nv10_gpio_init(struct drm_device *dev); 1502void nv10_gpio_fini(struct drm_device *dev); 1503int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1504int nv10_gpio_sense(struct drm_device *dev, int line); 1505void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1506 1507/* nv50_gpio.c */ 1508int nv50_gpio_init(struct drm_device *dev); 1509void nv50_gpio_fini(struct drm_device *dev); 1510int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1511int nv50_gpio_sense(struct drm_device *dev, int line); 1512void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1513int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1514int nvd0_gpio_sense(struct drm_device *dev, int line); 1515 1516/* nv50_calc.c */ 1517int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1518 int *N1, int *M1, int *N2, int *M2, int *P); 1519int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1520 int clk, int *N, int *fN, int *M, int *P); 1521 1522#ifndef ioread32_native 1523#ifdef __BIG_ENDIAN 1524#define ioread16_native ioread16be 1525#define iowrite16_native iowrite16be 1526#define ioread32_native ioread32be 1527#define iowrite32_native iowrite32be 1528#else /* def __BIG_ENDIAN */ 1529#define ioread16_native ioread16 1530#define iowrite16_native iowrite16 1531#define ioread32_native ioread32 1532#define iowrite32_native iowrite32 1533#endif /* def __BIG_ENDIAN else */ 1534#endif /* !ioread32_native */ 1535 1536/* channel control reg access */ 1537static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1538{ 1539 return ioread32_native(chan->user + reg); 1540} 1541 1542static inline void nvchan_wr32(struct nouveau_channel *chan, 1543 unsigned reg, u32 val) 1544{ 1545 iowrite32_native(val, chan->user + reg); 1546} 1547 1548/* register access */ 1549static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1550{ 1551 struct drm_nouveau_private *dev_priv = dev->dev_private; 1552 return ioread32_native(dev_priv->mmio + reg); 1553} 1554 1555static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1556{ 1557 struct drm_nouveau_private *dev_priv = dev->dev_private; 1558 iowrite32_native(val, dev_priv->mmio + reg); 1559} 1560 1561static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1562{ 1563 u32 tmp = nv_rd32(dev, reg); 1564 nv_wr32(dev, reg, (tmp & ~mask) | val); 1565 return tmp; 1566} 1567 1568static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1569{ 1570 struct drm_nouveau_private *dev_priv = dev->dev_private; 1571 return ioread8(dev_priv->mmio + reg); 1572} 1573 1574static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1575{ 1576 struct drm_nouveau_private *dev_priv = dev->dev_private; 1577 iowrite8(val, dev_priv->mmio + reg); 1578} 1579 1580#define nv_wait(dev, reg, mask, val) \ 1581 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1582#define nv_wait_ne(dev, reg, mask, val) \ 1583 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1584#define nv_wait_cb(dev, func, data) \ 1585 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1586 1587/* PRAMIN access */ 1588static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1589{ 1590 struct drm_nouveau_private *dev_priv = dev->dev_private; 1591 return ioread32_native(dev_priv->ramin + offset); 1592} 1593 1594static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1595{ 1596 struct drm_nouveau_private *dev_priv = dev->dev_private; 1597 iowrite32_native(val, dev_priv->ramin + offset); 1598} 1599 1600/* object access */ 1601extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1602extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1603 1604/* 1605 * Logging 1606 * Argument d is (struct drm_device *). 1607 */ 1608#define NV_PRINTK(level, d, fmt, arg...) \ 1609 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1610 pci_name(d->pdev), ##arg) 1611#ifndef NV_DEBUG_NOTRACE 1612#define NV_DEBUG(d, fmt, arg...) do { \ 1613 if (drm_debug & DRM_UT_DRIVER) { \ 1614 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1615 __LINE__, ##arg); \ 1616 } \ 1617} while (0) 1618#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1619 if (drm_debug & DRM_UT_KMS) { \ 1620 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1621 __LINE__, ##arg); \ 1622 } \ 1623} while (0) 1624#else 1625#define NV_DEBUG(d, fmt, arg...) do { \ 1626 if (drm_debug & DRM_UT_DRIVER) \ 1627 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1628} while (0) 1629#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1630 if (drm_debug & DRM_UT_KMS) \ 1631 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1632} while (0) 1633#endif 1634#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1635#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1636#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1637#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1638#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1639#define NV_WARNONCE(d, fmt, arg...) do { \ 1640 static int _warned = 0; \ 1641 if (!_warned) { \ 1642 NV_WARN(d, fmt, ##arg); \ 1643 _warned = 1; \ 1644 } \ 1645} while(0) 1646 1647/* nouveau_reg_debug bitmask */ 1648enum { 1649 NOUVEAU_REG_DEBUG_MC = 0x1, 1650 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1651 NOUVEAU_REG_DEBUG_FB = 0x4, 1652 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1653 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1654 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1655 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1656 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1657 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1658 NOUVEAU_REG_DEBUG_EVO = 0x200, 1659 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1660}; 1661 1662#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1663 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1664 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1665} while (0) 1666 1667static inline bool 1668nv_two_heads(struct drm_device *dev) 1669{ 1670 struct drm_nouveau_private *dev_priv = dev->dev_private; 1671 const int impl = dev->pci_device & 0x0ff0; 1672 1673 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1674 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1675 return true; 1676 1677 return false; 1678} 1679 1680static inline bool 1681nv_gf4_disp_arch(struct drm_device *dev) 1682{ 1683 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1684} 1685 1686static inline bool 1687nv_two_reg_pll(struct drm_device *dev) 1688{ 1689 struct drm_nouveau_private *dev_priv = dev->dev_private; 1690 const int impl = dev->pci_device & 0x0ff0; 1691 1692 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1693 return true; 1694 return false; 1695} 1696 1697static inline bool 1698nv_match_device(struct drm_device *dev, unsigned device, 1699 unsigned sub_vendor, unsigned sub_device) 1700{ 1701 return dev->pdev->device == device && 1702 dev->pdev->subsystem_vendor == sub_vendor && 1703 dev->pdev->subsystem_device == sub_device; 1704} 1705 1706static inline void * 1707nv_engine(struct drm_device *dev, int engine) 1708{ 1709 struct drm_nouveau_private *dev_priv = dev->dev_private; 1710 return (void *)dev_priv->eng[engine]; 1711} 1712 1713/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1714 * helpful to determine a number of other hardware features 1715 */ 1716static inline int 1717nv44_graph_class(struct drm_device *dev) 1718{ 1719 struct drm_nouveau_private *dev_priv = dev->dev_private; 1720 1721 if ((dev_priv->chipset & 0xf0) == 0x60) 1722 return 1; 1723 1724 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1725} 1726 1727/* memory type/access flags, do not match hardware values */ 1728#define NV_MEM_ACCESS_RO 1 1729#define NV_MEM_ACCESS_WO 2 1730#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1731#define NV_MEM_ACCESS_SYS 4 1732#define NV_MEM_ACCESS_VM 8 1733 1734#define NV_MEM_TARGET_VRAM 0 1735#define NV_MEM_TARGET_PCI 1 1736#define NV_MEM_TARGET_PCI_NOSNOOP 2 1737#define NV_MEM_TARGET_VM 3 1738#define NV_MEM_TARGET_GART 4 1739 1740#define NV_MEM_TYPE_VM 0x7f 1741#define NV_MEM_COMP_VM 0x03 1742 1743/* NV_SW object class */ 1744#define NV_SW 0x0000506e 1745#define NV_SW_DMA_SEMAPHORE 0x00000060 1746#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1747#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1748#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1749#define NV_SW_YIELD 0x00000080 1750#define NV_SW_DMA_VBLSEM 0x0000018c 1751#define NV_SW_VBLSEM_OFFSET 0x00000400 1752#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1753#define NV_SW_VBLSEM_RELEASE 0x00000408 1754#define NV_SW_PAGE_FLIP 0x00000500 1755 1756#endif /* __NOUVEAU_DRV_H__ */ 1757