nouveau_drv.h revision de3a6c0a3b642c0c350414d63298a1b19a009290
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 138#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 139#define NVOBJ_FLAG_FAKE (1 << 3) 140struct nouveau_gpuobj { 141 struct drm_device *dev; 142 struct list_head list; 143 144 struct nouveau_channel *im_channel; 145 struct drm_mm_node *im_pramin; 146 struct nouveau_bo *im_backing; 147 uint32_t im_backing_start; 148 uint32_t *im_backing_suspend; 149 int im_bound; 150 151 uint32_t flags; 152 int refcount; 153 154 u32 pinst; 155 u32 cinst; 156 u64 vinst; 157 158 uint32_t engine; 159 uint32_t class; 160 161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 162 void *priv; 163}; 164 165struct nouveau_gpuobj_ref { 166 struct list_head list; 167 168 struct nouveau_gpuobj *gpuobj; 169 uint32_t instance; 170 171 struct nouveau_channel *channel; 172 int handle; 173}; 174 175struct nouveau_channel { 176 struct drm_device *dev; 177 int id; 178 179 /* owner of this fifo */ 180 struct drm_file *file_priv; 181 /* mapping of the fifo itself */ 182 struct drm_local_map *map; 183 184 /* mapping of the regs controling the fifo */ 185 void __iomem *user; 186 uint32_t user_get; 187 uint32_t user_put; 188 189 /* Fencing */ 190 struct { 191 /* lock protects the pending list only */ 192 spinlock_t lock; 193 struct list_head pending; 194 uint32_t sequence; 195 uint32_t sequence_ack; 196 atomic_t last_sequence_irq; 197 } fence; 198 199 /* DMA push buffer */ 200 struct nouveau_gpuobj_ref *pushbuf; 201 struct nouveau_bo *pushbuf_bo; 202 uint32_t pushbuf_base; 203 204 /* Notifier memory */ 205 struct nouveau_bo *notifier_bo; 206 struct drm_mm notifier_heap; 207 208 /* PFIFO context */ 209 struct nouveau_gpuobj_ref *ramfc; 210 struct nouveau_gpuobj_ref *cache; 211 212 /* PGRAPH context */ 213 /* XXX may be merge 2 pointers as private data ??? */ 214 struct nouveau_gpuobj_ref *ramin_grctx; 215 void *pgraph_ctx; 216 217 /* NV50 VM */ 218 struct nouveau_gpuobj *vm_pd; 219 struct nouveau_gpuobj_ref *vm_gart_pt; 220 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 221 222 /* Objects */ 223 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 224 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 225 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 226 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 227 228 /* GPU object info for stuff used in-kernel (mm_enabled) */ 229 uint32_t m2mf_ntfy; 230 uint32_t vram_handle; 231 uint32_t gart_handle; 232 bool accel_done; 233 234 /* Push buffer state (only for drm's channel on !mm_enabled) */ 235 struct { 236 int max; 237 int free; 238 int cur; 239 int put; 240 /* access via pushbuf_bo */ 241 242 int ib_base; 243 int ib_max; 244 int ib_free; 245 int ib_put; 246 } dma; 247 248 uint32_t sw_subchannel[8]; 249 250 struct { 251 struct nouveau_gpuobj *vblsem; 252 uint32_t vblsem_offset; 253 uint32_t vblsem_rval; 254 struct list_head vbl_wait; 255 } nvsw; 256 257 struct { 258 bool active; 259 char name[32]; 260 struct drm_info_list info; 261 } debugfs; 262}; 263 264struct nouveau_instmem_engine { 265 void *priv; 266 267 int (*init)(struct drm_device *dev); 268 void (*takedown)(struct drm_device *dev); 269 int (*suspend)(struct drm_device *dev); 270 void (*resume)(struct drm_device *dev); 271 272 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 273 uint32_t *size); 274 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 275 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 276 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 277 void (*flush)(struct drm_device *); 278}; 279 280struct nouveau_mc_engine { 281 int (*init)(struct drm_device *dev); 282 void (*takedown)(struct drm_device *dev); 283}; 284 285struct nouveau_timer_engine { 286 int (*init)(struct drm_device *dev); 287 void (*takedown)(struct drm_device *dev); 288 uint64_t (*read)(struct drm_device *dev); 289}; 290 291struct nouveau_fb_engine { 292 int num_tiles; 293 294 int (*init)(struct drm_device *dev); 295 void (*takedown)(struct drm_device *dev); 296 297 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 298 uint32_t size, uint32_t pitch); 299}; 300 301struct nouveau_fifo_engine { 302 int channels; 303 304 struct nouveau_gpuobj_ref *playlist[2]; 305 int cur_playlist; 306 307 int (*init)(struct drm_device *); 308 void (*takedown)(struct drm_device *); 309 310 void (*disable)(struct drm_device *); 311 void (*enable)(struct drm_device *); 312 bool (*reassign)(struct drm_device *, bool enable); 313 bool (*cache_flush)(struct drm_device *dev); 314 bool (*cache_pull)(struct drm_device *dev, bool enable); 315 316 int (*channel_id)(struct drm_device *); 317 318 int (*create_context)(struct nouveau_channel *); 319 void (*destroy_context)(struct nouveau_channel *); 320 int (*load_context)(struct nouveau_channel *); 321 int (*unload_context)(struct drm_device *); 322}; 323 324struct nouveau_pgraph_object_method { 325 int id; 326 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 327 uint32_t data); 328}; 329 330struct nouveau_pgraph_object_class { 331 int id; 332 bool software; 333 struct nouveau_pgraph_object_method *methods; 334}; 335 336struct nouveau_pgraph_engine { 337 struct nouveau_pgraph_object_class *grclass; 338 bool accel_blocked; 339 int grctx_size; 340 341 /* NV2x/NV3x context table (0x400780) */ 342 struct nouveau_gpuobj_ref *ctx_table; 343 344 int (*init)(struct drm_device *); 345 void (*takedown)(struct drm_device *); 346 347 void (*fifo_access)(struct drm_device *, bool); 348 349 struct nouveau_channel *(*channel)(struct drm_device *); 350 int (*create_context)(struct nouveau_channel *); 351 void (*destroy_context)(struct nouveau_channel *); 352 int (*load_context)(struct nouveau_channel *); 353 int (*unload_context)(struct drm_device *); 354 355 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 356 uint32_t size, uint32_t pitch); 357}; 358 359struct nouveau_display_engine { 360 int (*early_init)(struct drm_device *); 361 void (*late_takedown)(struct drm_device *); 362 int (*create)(struct drm_device *); 363 int (*init)(struct drm_device *); 364 void (*destroy)(struct drm_device *); 365}; 366 367struct nouveau_gpio_engine { 368 int (*init)(struct drm_device *); 369 void (*takedown)(struct drm_device *); 370 371 int (*get)(struct drm_device *, enum dcb_gpio_tag); 372 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 373 374 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 375}; 376 377struct nouveau_engine { 378 struct nouveau_instmem_engine instmem; 379 struct nouveau_mc_engine mc; 380 struct nouveau_timer_engine timer; 381 struct nouveau_fb_engine fb; 382 struct nouveau_pgraph_engine graph; 383 struct nouveau_fifo_engine fifo; 384 struct nouveau_display_engine display; 385 struct nouveau_gpio_engine gpio; 386}; 387 388struct nouveau_pll_vals { 389 union { 390 struct { 391#ifdef __BIG_ENDIAN 392 uint8_t N1, M1, N2, M2; 393#else 394 uint8_t M1, N1, M2, N2; 395#endif 396 }; 397 struct { 398 uint16_t NM1, NM2; 399 } __attribute__((packed)); 400 }; 401 int log2P; 402 403 int refclk; 404}; 405 406enum nv04_fp_display_regs { 407 FP_DISPLAY_END, 408 FP_TOTAL, 409 FP_CRTC, 410 FP_SYNC_START, 411 FP_SYNC_END, 412 FP_VALID_START, 413 FP_VALID_END 414}; 415 416struct nv04_crtc_reg { 417 unsigned char MiscOutReg; /* */ 418 uint8_t CRTC[0xa0]; 419 uint8_t CR58[0x10]; 420 uint8_t Sequencer[5]; 421 uint8_t Graphics[9]; 422 uint8_t Attribute[21]; 423 unsigned char DAC[768]; /* Internal Colorlookuptable */ 424 425 /* PCRTC regs */ 426 uint32_t fb_start; 427 uint32_t crtc_cfg; 428 uint32_t cursor_cfg; 429 uint32_t gpio_ext; 430 uint32_t crtc_830; 431 uint32_t crtc_834; 432 uint32_t crtc_850; 433 uint32_t crtc_eng_ctrl; 434 435 /* PRAMDAC regs */ 436 uint32_t nv10_cursync; 437 struct nouveau_pll_vals pllvals; 438 uint32_t ramdac_gen_ctrl; 439 uint32_t ramdac_630; 440 uint32_t ramdac_634; 441 uint32_t tv_setup; 442 uint32_t tv_vtotal; 443 uint32_t tv_vskew; 444 uint32_t tv_vsync_delay; 445 uint32_t tv_htotal; 446 uint32_t tv_hskew; 447 uint32_t tv_hsync_delay; 448 uint32_t tv_hsync_delay2; 449 uint32_t fp_horiz_regs[7]; 450 uint32_t fp_vert_regs[7]; 451 uint32_t dither; 452 uint32_t fp_control; 453 uint32_t dither_regs[6]; 454 uint32_t fp_debug_0; 455 uint32_t fp_debug_1; 456 uint32_t fp_debug_2; 457 uint32_t fp_margin_color; 458 uint32_t ramdac_8c0; 459 uint32_t ramdac_a20; 460 uint32_t ramdac_a24; 461 uint32_t ramdac_a34; 462 uint32_t ctv_regs[38]; 463}; 464 465struct nv04_output_reg { 466 uint32_t output; 467 int head; 468}; 469 470struct nv04_mode_state { 471 uint32_t bpp; 472 uint32_t width; 473 uint32_t height; 474 uint32_t interlace; 475 uint32_t repaint0; 476 uint32_t repaint1; 477 uint32_t screen; 478 uint32_t scale; 479 uint32_t dither; 480 uint32_t extra; 481 uint32_t fifo; 482 uint32_t pixel; 483 uint32_t horiz; 484 int arbitration0; 485 int arbitration1; 486 uint32_t pll; 487 uint32_t pllB; 488 uint32_t vpll; 489 uint32_t vpll2; 490 uint32_t vpllB; 491 uint32_t vpll2B; 492 uint32_t pllsel; 493 uint32_t sel_clk; 494 uint32_t general; 495 uint32_t crtcOwner; 496 uint32_t head; 497 uint32_t head2; 498 uint32_t cursorConfig; 499 uint32_t cursor0; 500 uint32_t cursor1; 501 uint32_t cursor2; 502 uint32_t timingH; 503 uint32_t timingV; 504 uint32_t displayV; 505 uint32_t crtcSync; 506 507 struct nv04_crtc_reg crtc_reg[2]; 508}; 509 510enum nouveau_card_type { 511 NV_04 = 0x00, 512 NV_10 = 0x10, 513 NV_20 = 0x20, 514 NV_30 = 0x30, 515 NV_40 = 0x40, 516 NV_50 = 0x50, 517 NV_C0 = 0xc0, 518}; 519 520struct drm_nouveau_private { 521 struct drm_device *dev; 522 523 /* the card type, takes NV_* as values */ 524 enum nouveau_card_type card_type; 525 /* exact chipset, derived from NV_PMC_BOOT_0 */ 526 int chipset; 527 int flags; 528 529 void __iomem *mmio; 530 void __iomem *ramin; 531 uint32_t ramin_size; 532 533 struct nouveau_bo *vga_ram; 534 535 struct workqueue_struct *wq; 536 struct work_struct irq_work; 537 struct work_struct hpd_work; 538 539 struct list_head vbl_waiting; 540 541 struct { 542 struct drm_global_reference mem_global_ref; 543 struct ttm_bo_global_ref bo_global_ref; 544 struct ttm_bo_device bdev; 545 atomic_t validate_sequence; 546 } ttm; 547 548 int fifo_alloc_count; 549 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 550 551 struct nouveau_engine engine; 552 struct nouveau_channel *channel; 553 554 /* For PFIFO and PGRAPH. */ 555 spinlock_t context_switch_lock; 556 557 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 558 struct nouveau_gpuobj *ramht; 559 uint32_t ramin_rsvd_vram; 560 uint32_t ramht_offset; 561 uint32_t ramht_size; 562 uint32_t ramht_bits; 563 uint32_t ramfc_offset; 564 uint32_t ramfc_size; 565 uint32_t ramro_offset; 566 uint32_t ramro_size; 567 568 struct { 569 enum { 570 NOUVEAU_GART_NONE = 0, 571 NOUVEAU_GART_AGP, 572 NOUVEAU_GART_SGDMA 573 } type; 574 uint64_t aper_base; 575 uint64_t aper_size; 576 uint64_t aper_free; 577 578 struct nouveau_gpuobj *sg_ctxdma; 579 struct page *sg_dummy_page; 580 dma_addr_t sg_dummy_bus; 581 } gart_info; 582 583 /* nv10-nv40 tiling regions */ 584 struct { 585 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 586 spinlock_t lock; 587 } tile; 588 589 /* VRAM/fb configuration */ 590 uint64_t vram_size; 591 uint64_t vram_sys_base; 592 593 uint64_t fb_phys; 594 uint64_t fb_available_size; 595 uint64_t fb_mappable_pages; 596 uint64_t fb_aper_free; 597 int fb_mtrr; 598 599 /* G8x/G9x virtual address space */ 600 uint64_t vm_gart_base; 601 uint64_t vm_gart_size; 602 uint64_t vm_vram_base; 603 uint64_t vm_vram_size; 604 uint64_t vm_end; 605 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 606 int vm_vram_pt_nr; 607 608 struct drm_mm ramin_heap; 609 610 struct list_head gpuobj_list; 611 612 struct nvbios vbios; 613 614 struct nv04_mode_state mode_reg; 615 struct nv04_mode_state saved_reg; 616 uint32_t saved_vga_font[4][16384]; 617 uint32_t crtc_owner; 618 uint32_t dac_users[4]; 619 620 struct nouveau_suspend_resume { 621 uint32_t *ramin_copy; 622 } susres; 623 624 struct backlight_device *backlight; 625 626 struct nouveau_channel *evo; 627 struct { 628 struct dcb_entry *dcb; 629 u16 script; 630 u32 pclk; 631 } evo_irq; 632 633 struct { 634 struct dentry *channel_root; 635 } debugfs; 636 637 struct nouveau_fbdev *nfbdev; 638 struct apertures_struct *apertures; 639}; 640 641static inline struct drm_nouveau_private * 642nouveau_bdev(struct ttm_bo_device *bd) 643{ 644 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 645} 646 647static inline int 648nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 649{ 650 struct nouveau_bo *prev; 651 652 if (!pnvbo) 653 return -EINVAL; 654 prev = *pnvbo; 655 656 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 657 if (prev) { 658 struct ttm_buffer_object *bo = &prev->bo; 659 660 ttm_bo_unref(&bo); 661 } 662 663 return 0; 664} 665 666#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 667 struct drm_nouveau_private *nv = dev->dev_private; \ 668 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 669 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 670 DRM_CURRENTPID, (id)); \ 671 return -EPERM; \ 672 } \ 673 (ch) = nv->fifos[(id)]; \ 674} while (0) 675 676/* nouveau_drv.c */ 677extern int nouveau_noagp; 678extern int nouveau_duallink; 679extern int nouveau_uscript_lvds; 680extern int nouveau_uscript_tmds; 681extern int nouveau_vram_pushbuf; 682extern int nouveau_vram_notify; 683extern int nouveau_fbpercrtc; 684extern int nouveau_tv_disable; 685extern char *nouveau_tv_norm; 686extern int nouveau_reg_debug; 687extern char *nouveau_vbios; 688extern int nouveau_ignorelid; 689extern int nouveau_nofbaccel; 690extern int nouveau_noaccel; 691extern int nouveau_override_conntype; 692 693extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 694extern int nouveau_pci_resume(struct pci_dev *pdev); 695 696/* nouveau_state.c */ 697extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 698extern int nouveau_load(struct drm_device *, unsigned long flags); 699extern int nouveau_firstopen(struct drm_device *); 700extern void nouveau_lastclose(struct drm_device *); 701extern int nouveau_unload(struct drm_device *); 702extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 703 struct drm_file *); 704extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 705 struct drm_file *); 706extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 707 uint32_t reg, uint32_t mask, uint32_t val); 708extern bool nouveau_wait_for_idle(struct drm_device *); 709extern int nouveau_card_init(struct drm_device *); 710 711/* nouveau_mem.c */ 712extern int nouveau_mem_detect(struct drm_device *dev); 713extern int nouveau_mem_init(struct drm_device *); 714extern int nouveau_mem_init_agp(struct drm_device *); 715extern int nouveau_mem_reset_agp(struct drm_device *); 716extern void nouveau_mem_close(struct drm_device *); 717extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 718 uint32_t addr, 719 uint32_t size, 720 uint32_t pitch); 721extern void nv10_mem_expire_tiling(struct drm_device *dev, 722 struct nouveau_tile_reg *tile, 723 struct nouveau_fence *fence); 724extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 725 uint32_t size, uint32_t flags, 726 uint64_t phys); 727extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 728 uint32_t size); 729 730/* nouveau_notifier.c */ 731extern int nouveau_notifier_init_channel(struct nouveau_channel *); 732extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 733extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 734 int cout, uint32_t *offset); 735extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 736extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 737 struct drm_file *); 738extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 739 struct drm_file *); 740 741/* nouveau_channel.c */ 742extern struct drm_ioctl_desc nouveau_ioctls[]; 743extern int nouveau_max_ioctl; 744extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 745extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 746 int channel); 747extern int nouveau_channel_alloc(struct drm_device *dev, 748 struct nouveau_channel **chan, 749 struct drm_file *file_priv, 750 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 751extern void nouveau_channel_free(struct nouveau_channel *); 752 753/* nouveau_object.c */ 754extern int nouveau_gpuobj_early_init(struct drm_device *); 755extern int nouveau_gpuobj_init(struct drm_device *); 756extern void nouveau_gpuobj_takedown(struct drm_device *); 757extern void nouveau_gpuobj_late_takedown(struct drm_device *); 758extern int nouveau_gpuobj_suspend(struct drm_device *dev); 759extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 760extern void nouveau_gpuobj_resume(struct drm_device *dev); 761extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 762 uint32_t vram_h, uint32_t tt_h); 763extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 764extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 765 uint32_t size, int align, uint32_t flags, 766 struct nouveau_gpuobj **); 767extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 768extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 769 uint32_t handle, struct nouveau_gpuobj *, 770 struct nouveau_gpuobj_ref **); 771extern int nouveau_gpuobj_ref_del(struct drm_device *, 772 struct nouveau_gpuobj_ref **); 773extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 774 struct nouveau_gpuobj_ref **ref_ret); 775extern int nouveau_gpuobj_new_ref(struct drm_device *, 776 struct nouveau_channel *alloc_chan, 777 struct nouveau_channel *ref_chan, 778 uint32_t handle, uint32_t size, int align, 779 uint32_t flags, struct nouveau_gpuobj_ref **); 780extern int nouveau_gpuobj_new_fake(struct drm_device *, 781 uint32_t p_offset, uint32_t b_offset, 782 uint32_t size, uint32_t flags, 783 struct nouveau_gpuobj **, 784 struct nouveau_gpuobj_ref**); 785extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 786 uint64_t offset, uint64_t size, int access, 787 int target, struct nouveau_gpuobj **); 788extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 789 uint64_t offset, uint64_t size, 790 int access, struct nouveau_gpuobj **, 791 uint32_t *o_ret); 792extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 793 struct nouveau_gpuobj **); 794extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 795 struct nouveau_gpuobj **); 796extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 797 struct drm_file *); 798extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 799 struct drm_file *); 800 801/* nouveau_irq.c */ 802extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 803extern void nouveau_irq_preinstall(struct drm_device *); 804extern int nouveau_irq_postinstall(struct drm_device *); 805extern void nouveau_irq_uninstall(struct drm_device *); 806 807/* nouveau_sgdma.c */ 808extern int nouveau_sgdma_init(struct drm_device *); 809extern void nouveau_sgdma_takedown(struct drm_device *); 810extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 811 uint32_t *page); 812extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 813 814/* nouveau_debugfs.c */ 815#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 816extern int nouveau_debugfs_init(struct drm_minor *); 817extern void nouveau_debugfs_takedown(struct drm_minor *); 818extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 819extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 820#else 821static inline int 822nouveau_debugfs_init(struct drm_minor *minor) 823{ 824 return 0; 825} 826 827static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 828{ 829} 830 831static inline int 832nouveau_debugfs_channel_init(struct nouveau_channel *chan) 833{ 834 return 0; 835} 836 837static inline void 838nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 839{ 840} 841#endif 842 843/* nouveau_dma.c */ 844extern void nouveau_dma_pre_init(struct nouveau_channel *); 845extern int nouveau_dma_init(struct nouveau_channel *); 846extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 847 848/* nouveau_acpi.c */ 849#define ROM_BIOS_PAGE 4096 850#if defined(CONFIG_ACPI) 851void nouveau_register_dsm_handler(void); 852void nouveau_unregister_dsm_handler(void); 853int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 854bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 855int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 856#else 857static inline void nouveau_register_dsm_handler(void) {} 858static inline void nouveau_unregister_dsm_handler(void) {} 859static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 860static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 861static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 862#endif 863 864/* nouveau_backlight.c */ 865#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 866extern int nouveau_backlight_init(struct drm_device *); 867extern void nouveau_backlight_exit(struct drm_device *); 868#else 869static inline int nouveau_backlight_init(struct drm_device *dev) 870{ 871 return 0; 872} 873 874static inline void nouveau_backlight_exit(struct drm_device *dev) { } 875#endif 876 877/* nouveau_bios.c */ 878extern int nouveau_bios_init(struct drm_device *); 879extern void nouveau_bios_takedown(struct drm_device *dev); 880extern int nouveau_run_vbios_init(struct drm_device *); 881extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 882 struct dcb_entry *); 883extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 884 enum dcb_gpio_tag); 885extern struct dcb_connector_table_entry * 886nouveau_bios_connector_entry(struct drm_device *, int index); 887extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 888 struct pll_lims *); 889extern int nouveau_bios_run_display_table(struct drm_device *, 890 struct dcb_entry *, 891 uint32_t script, int pxclk); 892extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 893 int *length); 894extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 895extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 896extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 897 bool *dl, bool *if_is_24bit); 898extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 899 int head, int pxclk); 900extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 901 enum LVDS_script, int pxclk); 902 903/* nouveau_ttm.c */ 904int nouveau_ttm_global_init(struct drm_nouveau_private *); 905void nouveau_ttm_global_release(struct drm_nouveau_private *); 906int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 907 908/* nouveau_dp.c */ 909int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 910 uint8_t *data, int data_nr); 911bool nouveau_dp_detect(struct drm_encoder *); 912bool nouveau_dp_link_train(struct drm_encoder *); 913 914/* nv04_fb.c */ 915extern int nv04_fb_init(struct drm_device *); 916extern void nv04_fb_takedown(struct drm_device *); 917 918/* nv10_fb.c */ 919extern int nv10_fb_init(struct drm_device *); 920extern void nv10_fb_takedown(struct drm_device *); 921extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 922 uint32_t, uint32_t); 923 924/* nv30_fb.c */ 925extern int nv30_fb_init(struct drm_device *); 926extern void nv30_fb_takedown(struct drm_device *); 927 928/* nv40_fb.c */ 929extern int nv40_fb_init(struct drm_device *); 930extern void nv40_fb_takedown(struct drm_device *); 931extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 932 uint32_t, uint32_t); 933 934/* nv50_fb.c */ 935extern int nv50_fb_init(struct drm_device *); 936extern void nv50_fb_takedown(struct drm_device *); 937 938/* nvc0_fb.c */ 939extern int nvc0_fb_init(struct drm_device *); 940extern void nvc0_fb_takedown(struct drm_device *); 941 942/* nv04_fifo.c */ 943extern int nv04_fifo_init(struct drm_device *); 944extern void nv04_fifo_disable(struct drm_device *); 945extern void nv04_fifo_enable(struct drm_device *); 946extern bool nv04_fifo_reassign(struct drm_device *, bool); 947extern bool nv04_fifo_cache_flush(struct drm_device *); 948extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 949extern int nv04_fifo_channel_id(struct drm_device *); 950extern int nv04_fifo_create_context(struct nouveau_channel *); 951extern void nv04_fifo_destroy_context(struct nouveau_channel *); 952extern int nv04_fifo_load_context(struct nouveau_channel *); 953extern int nv04_fifo_unload_context(struct drm_device *); 954 955/* nv10_fifo.c */ 956extern int nv10_fifo_init(struct drm_device *); 957extern int nv10_fifo_channel_id(struct drm_device *); 958extern int nv10_fifo_create_context(struct nouveau_channel *); 959extern void nv10_fifo_destroy_context(struct nouveau_channel *); 960extern int nv10_fifo_load_context(struct nouveau_channel *); 961extern int nv10_fifo_unload_context(struct drm_device *); 962 963/* nv40_fifo.c */ 964extern int nv40_fifo_init(struct drm_device *); 965extern int nv40_fifo_create_context(struct nouveau_channel *); 966extern void nv40_fifo_destroy_context(struct nouveau_channel *); 967extern int nv40_fifo_load_context(struct nouveau_channel *); 968extern int nv40_fifo_unload_context(struct drm_device *); 969 970/* nv50_fifo.c */ 971extern int nv50_fifo_init(struct drm_device *); 972extern void nv50_fifo_takedown(struct drm_device *); 973extern int nv50_fifo_channel_id(struct drm_device *); 974extern int nv50_fifo_create_context(struct nouveau_channel *); 975extern void nv50_fifo_destroy_context(struct nouveau_channel *); 976extern int nv50_fifo_load_context(struct nouveau_channel *); 977extern int nv50_fifo_unload_context(struct drm_device *); 978 979/* nvc0_fifo.c */ 980extern int nvc0_fifo_init(struct drm_device *); 981extern void nvc0_fifo_takedown(struct drm_device *); 982extern void nvc0_fifo_disable(struct drm_device *); 983extern void nvc0_fifo_enable(struct drm_device *); 984extern bool nvc0_fifo_reassign(struct drm_device *, bool); 985extern bool nvc0_fifo_cache_flush(struct drm_device *); 986extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 987extern int nvc0_fifo_channel_id(struct drm_device *); 988extern int nvc0_fifo_create_context(struct nouveau_channel *); 989extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 990extern int nvc0_fifo_load_context(struct nouveau_channel *); 991extern int nvc0_fifo_unload_context(struct drm_device *); 992 993/* nv04_graph.c */ 994extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 995extern int nv04_graph_init(struct drm_device *); 996extern void nv04_graph_takedown(struct drm_device *); 997extern void nv04_graph_fifo_access(struct drm_device *, bool); 998extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 999extern int nv04_graph_create_context(struct nouveau_channel *); 1000extern void nv04_graph_destroy_context(struct nouveau_channel *); 1001extern int nv04_graph_load_context(struct nouveau_channel *); 1002extern int nv04_graph_unload_context(struct drm_device *); 1003extern void nv04_graph_context_switch(struct drm_device *); 1004 1005/* nv10_graph.c */ 1006extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1007extern int nv10_graph_init(struct drm_device *); 1008extern void nv10_graph_takedown(struct drm_device *); 1009extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1010extern int nv10_graph_create_context(struct nouveau_channel *); 1011extern void nv10_graph_destroy_context(struct nouveau_channel *); 1012extern int nv10_graph_load_context(struct nouveau_channel *); 1013extern int nv10_graph_unload_context(struct drm_device *); 1014extern void nv10_graph_context_switch(struct drm_device *); 1015extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1016 uint32_t, uint32_t); 1017 1018/* nv20_graph.c */ 1019extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1020extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1021extern int nv20_graph_create_context(struct nouveau_channel *); 1022extern void nv20_graph_destroy_context(struct nouveau_channel *); 1023extern int nv20_graph_load_context(struct nouveau_channel *); 1024extern int nv20_graph_unload_context(struct drm_device *); 1025extern int nv20_graph_init(struct drm_device *); 1026extern void nv20_graph_takedown(struct drm_device *); 1027extern int nv30_graph_init(struct drm_device *); 1028extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1029 uint32_t, uint32_t); 1030 1031/* nv40_graph.c */ 1032extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1033extern int nv40_graph_init(struct drm_device *); 1034extern void nv40_graph_takedown(struct drm_device *); 1035extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1036extern int nv40_graph_create_context(struct nouveau_channel *); 1037extern void nv40_graph_destroy_context(struct nouveau_channel *); 1038extern int nv40_graph_load_context(struct nouveau_channel *); 1039extern int nv40_graph_unload_context(struct drm_device *); 1040extern void nv40_grctx_init(struct nouveau_grctx *); 1041extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1042 uint32_t, uint32_t); 1043 1044/* nv50_graph.c */ 1045extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1046extern int nv50_graph_init(struct drm_device *); 1047extern void nv50_graph_takedown(struct drm_device *); 1048extern void nv50_graph_fifo_access(struct drm_device *, bool); 1049extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1050extern int nv50_graph_create_context(struct nouveau_channel *); 1051extern void nv50_graph_destroy_context(struct nouveau_channel *); 1052extern int nv50_graph_load_context(struct nouveau_channel *); 1053extern int nv50_graph_unload_context(struct drm_device *); 1054extern void nv50_graph_context_switch(struct drm_device *); 1055extern int nv50_grctx_init(struct nouveau_grctx *); 1056 1057/* nvc0_graph.c */ 1058extern int nvc0_graph_init(struct drm_device *); 1059extern void nvc0_graph_takedown(struct drm_device *); 1060extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1061extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1062extern int nvc0_graph_create_context(struct nouveau_channel *); 1063extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1064extern int nvc0_graph_load_context(struct nouveau_channel *); 1065extern int nvc0_graph_unload_context(struct drm_device *); 1066 1067/* nv04_instmem.c */ 1068extern int nv04_instmem_init(struct drm_device *); 1069extern void nv04_instmem_takedown(struct drm_device *); 1070extern int nv04_instmem_suspend(struct drm_device *); 1071extern void nv04_instmem_resume(struct drm_device *); 1072extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1073 uint32_t *size); 1074extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1075extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1076extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1077extern void nv04_instmem_flush(struct drm_device *); 1078 1079/* nv50_instmem.c */ 1080extern int nv50_instmem_init(struct drm_device *); 1081extern void nv50_instmem_takedown(struct drm_device *); 1082extern int nv50_instmem_suspend(struct drm_device *); 1083extern void nv50_instmem_resume(struct drm_device *); 1084extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1085 uint32_t *size); 1086extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1087extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1088extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1089extern void nv50_instmem_flush(struct drm_device *); 1090extern void nv84_instmem_flush(struct drm_device *); 1091extern void nv50_vm_flush(struct drm_device *, int engine); 1092 1093/* nvc0_instmem.c */ 1094extern int nvc0_instmem_init(struct drm_device *); 1095extern void nvc0_instmem_takedown(struct drm_device *); 1096extern int nvc0_instmem_suspend(struct drm_device *); 1097extern void nvc0_instmem_resume(struct drm_device *); 1098extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1099 uint32_t *size); 1100extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1101extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1102extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1103extern void nvc0_instmem_flush(struct drm_device *); 1104 1105/* nv04_mc.c */ 1106extern int nv04_mc_init(struct drm_device *); 1107extern void nv04_mc_takedown(struct drm_device *); 1108 1109/* nv40_mc.c */ 1110extern int nv40_mc_init(struct drm_device *); 1111extern void nv40_mc_takedown(struct drm_device *); 1112 1113/* nv50_mc.c */ 1114extern int nv50_mc_init(struct drm_device *); 1115extern void nv50_mc_takedown(struct drm_device *); 1116 1117/* nv04_timer.c */ 1118extern int nv04_timer_init(struct drm_device *); 1119extern uint64_t nv04_timer_read(struct drm_device *); 1120extern void nv04_timer_takedown(struct drm_device *); 1121 1122extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1123 unsigned long arg); 1124 1125/* nv04_dac.c */ 1126extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1127extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1128extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1129extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1130extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1131 1132/* nv04_dfp.c */ 1133extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1134extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1135extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1136 int head, bool dl); 1137extern void nv04_dfp_disable(struct drm_device *dev, int head); 1138extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1139 1140/* nv04_tv.c */ 1141extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1142extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1143 1144/* nv17_tv.c */ 1145extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1146 1147/* nv04_display.c */ 1148extern int nv04_display_early_init(struct drm_device *); 1149extern void nv04_display_late_takedown(struct drm_device *); 1150extern int nv04_display_create(struct drm_device *); 1151extern int nv04_display_init(struct drm_device *); 1152extern void nv04_display_destroy(struct drm_device *); 1153 1154/* nv04_crtc.c */ 1155extern int nv04_crtc_create(struct drm_device *, int index); 1156 1157/* nouveau_bo.c */ 1158extern struct ttm_bo_driver nouveau_bo_driver; 1159extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1160 int size, int align, uint32_t flags, 1161 uint32_t tile_mode, uint32_t tile_flags, 1162 bool no_vm, bool mappable, struct nouveau_bo **); 1163extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1164extern int nouveau_bo_unpin(struct nouveau_bo *); 1165extern int nouveau_bo_map(struct nouveau_bo *); 1166extern void nouveau_bo_unmap(struct nouveau_bo *); 1167extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1168 uint32_t busy); 1169extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1170extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1171extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1172extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1173extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *); 1174 1175/* nouveau_fence.c */ 1176struct nouveau_fence; 1177extern int nouveau_fence_init(struct nouveau_channel *); 1178extern void nouveau_fence_fini(struct nouveau_channel *); 1179extern void nouveau_fence_update(struct nouveau_channel *); 1180extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1181 bool emit); 1182extern int nouveau_fence_emit(struct nouveau_fence *); 1183struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1184extern bool nouveau_fence_signalled(void *obj, void *arg); 1185extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1186extern int nouveau_fence_flush(void *obj, void *arg); 1187extern void nouveau_fence_unref(void **obj); 1188extern void *nouveau_fence_ref(void *obj); 1189 1190/* nouveau_gem.c */ 1191extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1192 int size, int align, uint32_t flags, 1193 uint32_t tile_mode, uint32_t tile_flags, 1194 bool no_vm, bool mappable, struct nouveau_bo **); 1195extern int nouveau_gem_object_new(struct drm_gem_object *); 1196extern void nouveau_gem_object_del(struct drm_gem_object *); 1197extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1198 struct drm_file *); 1199extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1200 struct drm_file *); 1201extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1202 struct drm_file *); 1203extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1204 struct drm_file *); 1205extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1206 struct drm_file *); 1207 1208/* nv10_gpio.c */ 1209int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1210int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1211 1212/* nv50_gpio.c */ 1213int nv50_gpio_init(struct drm_device *dev); 1214int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1215int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1216void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1217 1218/* nv50_calc. */ 1219int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1220 int *N1, int *M1, int *N2, int *M2, int *P); 1221int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1222 int clk, int *N, int *fN, int *M, int *P); 1223 1224#ifndef ioread32_native 1225#ifdef __BIG_ENDIAN 1226#define ioread16_native ioread16be 1227#define iowrite16_native iowrite16be 1228#define ioread32_native ioread32be 1229#define iowrite32_native iowrite32be 1230#else /* def __BIG_ENDIAN */ 1231#define ioread16_native ioread16 1232#define iowrite16_native iowrite16 1233#define ioread32_native ioread32 1234#define iowrite32_native iowrite32 1235#endif /* def __BIG_ENDIAN else */ 1236#endif /* !ioread32_native */ 1237 1238/* channel control reg access */ 1239static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1240{ 1241 return ioread32_native(chan->user + reg); 1242} 1243 1244static inline void nvchan_wr32(struct nouveau_channel *chan, 1245 unsigned reg, u32 val) 1246{ 1247 iowrite32_native(val, chan->user + reg); 1248} 1249 1250/* register access */ 1251static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1252{ 1253 struct drm_nouveau_private *dev_priv = dev->dev_private; 1254 return ioread32_native(dev_priv->mmio + reg); 1255} 1256 1257static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1258{ 1259 struct drm_nouveau_private *dev_priv = dev->dev_private; 1260 iowrite32_native(val, dev_priv->mmio + reg); 1261} 1262 1263static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1264{ 1265 u32 tmp = nv_rd32(dev, reg); 1266 nv_wr32(dev, reg, (tmp & ~mask) | val); 1267 return tmp; 1268} 1269 1270static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1271{ 1272 struct drm_nouveau_private *dev_priv = dev->dev_private; 1273 return ioread8(dev_priv->mmio + reg); 1274} 1275 1276static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1277{ 1278 struct drm_nouveau_private *dev_priv = dev->dev_private; 1279 iowrite8(val, dev_priv->mmio + reg); 1280} 1281 1282#define nv_wait(reg, mask, val) \ 1283 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1284 1285/* PRAMIN access */ 1286static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1287{ 1288 struct drm_nouveau_private *dev_priv = dev->dev_private; 1289 return ioread32_native(dev_priv->ramin + offset); 1290} 1291 1292static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1293{ 1294 struct drm_nouveau_private *dev_priv = dev->dev_private; 1295 iowrite32_native(val, dev_priv->ramin + offset); 1296} 1297 1298/* object access */ 1299extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1300extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1301 1302/* 1303 * Logging 1304 * Argument d is (struct drm_device *). 1305 */ 1306#define NV_PRINTK(level, d, fmt, arg...) \ 1307 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1308 pci_name(d->pdev), ##arg) 1309#ifndef NV_DEBUG_NOTRACE 1310#define NV_DEBUG(d, fmt, arg...) do { \ 1311 if (drm_debug & DRM_UT_DRIVER) { \ 1312 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1313 __LINE__, ##arg); \ 1314 } \ 1315} while (0) 1316#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1317 if (drm_debug & DRM_UT_KMS) { \ 1318 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1319 __LINE__, ##arg); \ 1320 } \ 1321} while (0) 1322#else 1323#define NV_DEBUG(d, fmt, arg...) do { \ 1324 if (drm_debug & DRM_UT_DRIVER) \ 1325 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1326} while (0) 1327#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1328 if (drm_debug & DRM_UT_KMS) \ 1329 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1330} while (0) 1331#endif 1332#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1333#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1334#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1335#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1336#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1337 1338/* nouveau_reg_debug bitmask */ 1339enum { 1340 NOUVEAU_REG_DEBUG_MC = 0x1, 1341 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1342 NOUVEAU_REG_DEBUG_FB = 0x4, 1343 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1344 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1345 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1346 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1347 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1348 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1349 NOUVEAU_REG_DEBUG_EVO = 0x200, 1350}; 1351 1352#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1353 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1354 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1355} while (0) 1356 1357static inline bool 1358nv_two_heads(struct drm_device *dev) 1359{ 1360 struct drm_nouveau_private *dev_priv = dev->dev_private; 1361 const int impl = dev->pci_device & 0x0ff0; 1362 1363 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1364 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1365 return true; 1366 1367 return false; 1368} 1369 1370static inline bool 1371nv_gf4_disp_arch(struct drm_device *dev) 1372{ 1373 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1374} 1375 1376static inline bool 1377nv_two_reg_pll(struct drm_device *dev) 1378{ 1379 struct drm_nouveau_private *dev_priv = dev->dev_private; 1380 const int impl = dev->pci_device & 0x0ff0; 1381 1382 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1383 return true; 1384 return false; 1385} 1386 1387static inline bool 1388nv_match_device(struct drm_device *dev, unsigned device, 1389 unsigned sub_vendor, unsigned sub_device) 1390{ 1391 return dev->pdev->device == device && 1392 dev->pdev->subsystem_vendor == sub_vendor && 1393 dev->pdev->subsystem_device == sub_device; 1394} 1395 1396#define NV_SW 0x0000506e 1397#define NV_SW_DMA_SEMAPHORE 0x00000060 1398#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1399#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1400#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1401#define NV_SW_DMA_VBLSEM 0x0000018c 1402#define NV_SW_VBLSEM_OFFSET 0x00000400 1403#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1404#define NV_SW_VBLSEM_RELEASE 0x00000408 1405 1406#endif /* __NOUVEAU_DRV_H__ */ 1407