nouveau_drv.h revision ec91db269e6a3c7f45b96169ccf5dbd1fde8fce8
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103static inline struct nouveau_bo * 104nouveau_bo(struct ttm_buffer_object *bo) 105{ 106 return container_of(bo, struct nouveau_bo, bo); 107} 108 109static inline struct nouveau_bo * 110nouveau_gem_object(struct drm_gem_object *gem) 111{ 112 return gem ? gem->driver_private : NULL; 113} 114 115/* TODO: submit equivalent to TTM generic API upstream? */ 116static inline void __iomem * 117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 118{ 119 bool is_iomem; 120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 121 &nvbo->kmap, &is_iomem); 122 WARN_ON_ONCE(ioptr && !is_iomem); 123 return ioptr; 124} 125 126enum nouveau_flags { 127 NV_NFORCE = 0x10000000, 128 NV_NFORCE2 = 0x20000000 129}; 130 131#define NVOBJ_ENGINE_SW 0 132#define NVOBJ_ENGINE_GR 1 133#define NVOBJ_ENGINE_DISPLAY 2 134#define NVOBJ_ENGINE_INT 0xdeadbeef 135 136#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) 137#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 138#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 139#define NVOBJ_FLAG_FAKE (1 << 3) 140struct nouveau_gpuobj { 141 struct list_head list; 142 143 struct nouveau_channel *im_channel; 144 struct drm_mm_node *im_pramin; 145 struct nouveau_bo *im_backing; 146 uint32_t im_backing_start; 147 uint32_t *im_backing_suspend; 148 int im_bound; 149 150 uint32_t flags; 151 int refcount; 152 153 uint32_t engine; 154 uint32_t class; 155 156 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 157 void *priv; 158}; 159 160struct nouveau_gpuobj_ref { 161 struct list_head list; 162 163 struct nouveau_gpuobj *gpuobj; 164 uint32_t instance; 165 166 struct nouveau_channel *channel; 167 int handle; 168}; 169 170struct nouveau_channel { 171 struct drm_device *dev; 172 int id; 173 174 /* owner of this fifo */ 175 struct drm_file *file_priv; 176 /* mapping of the fifo itself */ 177 struct drm_local_map *map; 178 179 /* mapping of the regs controling the fifo */ 180 void __iomem *user; 181 uint32_t user_get; 182 uint32_t user_put; 183 184 /* Fencing */ 185 struct { 186 /* lock protects the pending list only */ 187 spinlock_t lock; 188 struct list_head pending; 189 uint32_t sequence; 190 uint32_t sequence_ack; 191 uint32_t last_sequence_irq; 192 } fence; 193 194 /* DMA push buffer */ 195 struct nouveau_gpuobj_ref *pushbuf; 196 struct nouveau_bo *pushbuf_bo; 197 uint32_t pushbuf_base; 198 199 /* Notifier memory */ 200 struct nouveau_bo *notifier_bo; 201 struct drm_mm notifier_heap; 202 203 /* PFIFO context */ 204 struct nouveau_gpuobj_ref *ramfc; 205 struct nouveau_gpuobj_ref *cache; 206 207 /* PGRAPH context */ 208 /* XXX may be merge 2 pointers as private data ??? */ 209 struct nouveau_gpuobj_ref *ramin_grctx; 210 void *pgraph_ctx; 211 212 /* NV50 VM */ 213 struct nouveau_gpuobj *vm_pd; 214 struct nouveau_gpuobj_ref *vm_gart_pt; 215 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; 216 217 /* Objects */ 218 struct nouveau_gpuobj_ref *ramin; /* Private instmem */ 219 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 220 struct nouveau_gpuobj_ref *ramht; /* Hash table */ 221 struct list_head ramht_refs; /* Objects referenced by RAMHT */ 222 223 /* GPU object info for stuff used in-kernel (mm_enabled) */ 224 uint32_t m2mf_ntfy; 225 uint32_t vram_handle; 226 uint32_t gart_handle; 227 bool accel_done; 228 229 /* Push buffer state (only for drm's channel on !mm_enabled) */ 230 struct { 231 int max; 232 int free; 233 int cur; 234 int put; 235 /* access via pushbuf_bo */ 236 237 int ib_base; 238 int ib_max; 239 int ib_free; 240 int ib_put; 241 } dma; 242 243 uint32_t sw_subchannel[8]; 244 245 struct { 246 struct nouveau_gpuobj *vblsem; 247 uint32_t vblsem_offset; 248 uint32_t vblsem_rval; 249 struct list_head vbl_wait; 250 } nvsw; 251 252 struct { 253 bool active; 254 char name[32]; 255 struct drm_info_list info; 256 } debugfs; 257}; 258 259struct nouveau_instmem_engine { 260 void *priv; 261 262 int (*init)(struct drm_device *dev); 263 void (*takedown)(struct drm_device *dev); 264 int (*suspend)(struct drm_device *dev); 265 void (*resume)(struct drm_device *dev); 266 267 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 268 uint32_t *size); 269 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 270 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 271 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 272 void (*flush)(struct drm_device *); 273}; 274 275struct nouveau_mc_engine { 276 int (*init)(struct drm_device *dev); 277 void (*takedown)(struct drm_device *dev); 278}; 279 280struct nouveau_timer_engine { 281 int (*init)(struct drm_device *dev); 282 void (*takedown)(struct drm_device *dev); 283 uint64_t (*read)(struct drm_device *dev); 284}; 285 286struct nouveau_fb_engine { 287 int num_tiles; 288 289 int (*init)(struct drm_device *dev); 290 void (*takedown)(struct drm_device *dev); 291 292 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 293 uint32_t size, uint32_t pitch); 294}; 295 296struct nouveau_fifo_engine { 297 void *priv; 298 299 int channels; 300 301 int (*init)(struct drm_device *); 302 void (*takedown)(struct drm_device *); 303 304 void (*disable)(struct drm_device *); 305 void (*enable)(struct drm_device *); 306 bool (*reassign)(struct drm_device *, bool enable); 307 bool (*cache_flush)(struct drm_device *dev); 308 bool (*cache_pull)(struct drm_device *dev, bool enable); 309 310 int (*channel_id)(struct drm_device *); 311 312 int (*create_context)(struct nouveau_channel *); 313 void (*destroy_context)(struct nouveau_channel *); 314 int (*load_context)(struct nouveau_channel *); 315 int (*unload_context)(struct drm_device *); 316}; 317 318struct nouveau_pgraph_object_method { 319 int id; 320 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 321 uint32_t data); 322}; 323 324struct nouveau_pgraph_object_class { 325 int id; 326 bool software; 327 struct nouveau_pgraph_object_method *methods; 328}; 329 330struct nouveau_pgraph_engine { 331 struct nouveau_pgraph_object_class *grclass; 332 bool accel_blocked; 333 int grctx_size; 334 335 int (*init)(struct drm_device *); 336 void (*takedown)(struct drm_device *); 337 338 void (*fifo_access)(struct drm_device *, bool); 339 340 struct nouveau_channel *(*channel)(struct drm_device *); 341 int (*create_context)(struct nouveau_channel *); 342 void (*destroy_context)(struct nouveau_channel *); 343 int (*load_context)(struct nouveau_channel *); 344 int (*unload_context)(struct drm_device *); 345 346 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 347 uint32_t size, uint32_t pitch); 348}; 349 350struct nouveau_engine { 351 struct nouveau_instmem_engine instmem; 352 struct nouveau_mc_engine mc; 353 struct nouveau_timer_engine timer; 354 struct nouveau_fb_engine fb; 355 struct nouveau_pgraph_engine graph; 356 struct nouveau_fifo_engine fifo; 357}; 358 359struct nouveau_pll_vals { 360 union { 361 struct { 362#ifdef __BIG_ENDIAN 363 uint8_t N1, M1, N2, M2; 364#else 365 uint8_t M1, N1, M2, N2; 366#endif 367 }; 368 struct { 369 uint16_t NM1, NM2; 370 } __attribute__((packed)); 371 }; 372 int log2P; 373 374 int refclk; 375}; 376 377enum nv04_fp_display_regs { 378 FP_DISPLAY_END, 379 FP_TOTAL, 380 FP_CRTC, 381 FP_SYNC_START, 382 FP_SYNC_END, 383 FP_VALID_START, 384 FP_VALID_END 385}; 386 387struct nv04_crtc_reg { 388 unsigned char MiscOutReg; /* */ 389 uint8_t CRTC[0x9f]; 390 uint8_t CR58[0x10]; 391 uint8_t Sequencer[5]; 392 uint8_t Graphics[9]; 393 uint8_t Attribute[21]; 394 unsigned char DAC[768]; /* Internal Colorlookuptable */ 395 396 /* PCRTC regs */ 397 uint32_t fb_start; 398 uint32_t crtc_cfg; 399 uint32_t cursor_cfg; 400 uint32_t gpio_ext; 401 uint32_t crtc_830; 402 uint32_t crtc_834; 403 uint32_t crtc_850; 404 uint32_t crtc_eng_ctrl; 405 406 /* PRAMDAC regs */ 407 uint32_t nv10_cursync; 408 struct nouveau_pll_vals pllvals; 409 uint32_t ramdac_gen_ctrl; 410 uint32_t ramdac_630; 411 uint32_t ramdac_634; 412 uint32_t tv_setup; 413 uint32_t tv_vtotal; 414 uint32_t tv_vskew; 415 uint32_t tv_vsync_delay; 416 uint32_t tv_htotal; 417 uint32_t tv_hskew; 418 uint32_t tv_hsync_delay; 419 uint32_t tv_hsync_delay2; 420 uint32_t fp_horiz_regs[7]; 421 uint32_t fp_vert_regs[7]; 422 uint32_t dither; 423 uint32_t fp_control; 424 uint32_t dither_regs[6]; 425 uint32_t fp_debug_0; 426 uint32_t fp_debug_1; 427 uint32_t fp_debug_2; 428 uint32_t fp_margin_color; 429 uint32_t ramdac_8c0; 430 uint32_t ramdac_a20; 431 uint32_t ramdac_a24; 432 uint32_t ramdac_a34; 433 uint32_t ctv_regs[38]; 434}; 435 436struct nv04_output_reg { 437 uint32_t output; 438 int head; 439}; 440 441struct nv04_mode_state { 442 uint32_t bpp; 443 uint32_t width; 444 uint32_t height; 445 uint32_t interlace; 446 uint32_t repaint0; 447 uint32_t repaint1; 448 uint32_t screen; 449 uint32_t scale; 450 uint32_t dither; 451 uint32_t extra; 452 uint32_t fifo; 453 uint32_t pixel; 454 uint32_t horiz; 455 int arbitration0; 456 int arbitration1; 457 uint32_t pll; 458 uint32_t pllB; 459 uint32_t vpll; 460 uint32_t vpll2; 461 uint32_t vpllB; 462 uint32_t vpll2B; 463 uint32_t pllsel; 464 uint32_t sel_clk; 465 uint32_t general; 466 uint32_t crtcOwner; 467 uint32_t head; 468 uint32_t head2; 469 uint32_t cursorConfig; 470 uint32_t cursor0; 471 uint32_t cursor1; 472 uint32_t cursor2; 473 uint32_t timingH; 474 uint32_t timingV; 475 uint32_t displayV; 476 uint32_t crtcSync; 477 478 struct nv04_crtc_reg crtc_reg[2]; 479}; 480 481enum nouveau_card_type { 482 NV_04 = 0x00, 483 NV_10 = 0x10, 484 NV_20 = 0x20, 485 NV_30 = 0x30, 486 NV_40 = 0x40, 487 NV_50 = 0x50, 488}; 489 490struct drm_nouveau_private { 491 struct drm_device *dev; 492 493 /* the card type, takes NV_* as values */ 494 enum nouveau_card_type card_type; 495 /* exact chipset, derived from NV_PMC_BOOT_0 */ 496 int chipset; 497 int flags; 498 499 void __iomem *mmio; 500 void __iomem *ramin; 501 uint32_t ramin_size; 502 503 struct nouveau_bo *vga_ram; 504 505 struct workqueue_struct *wq; 506 struct work_struct irq_work; 507 struct work_struct hpd_work; 508 509 struct list_head vbl_waiting; 510 511 struct { 512 struct ttm_global_reference mem_global_ref; 513 struct ttm_bo_global_ref bo_global_ref; 514 struct ttm_bo_device bdev; 515 spinlock_t bo_list_lock; 516 struct list_head bo_list; 517 atomic_t validate_sequence; 518 } ttm; 519 520 struct fb_info *fbdev_info; 521 522 int fifo_alloc_count; 523 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 524 525 struct nouveau_engine engine; 526 struct nouveau_channel *channel; 527 528 /* For PFIFO and PGRAPH. */ 529 spinlock_t context_switch_lock; 530 531 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 532 struct nouveau_gpuobj *ramht; 533 uint32_t ramin_rsvd_vram; 534 uint32_t ramht_offset; 535 uint32_t ramht_size; 536 uint32_t ramht_bits; 537 uint32_t ramfc_offset; 538 uint32_t ramfc_size; 539 uint32_t ramro_offset; 540 uint32_t ramro_size; 541 542 struct { 543 enum { 544 NOUVEAU_GART_NONE = 0, 545 NOUVEAU_GART_AGP, 546 NOUVEAU_GART_SGDMA 547 } type; 548 uint64_t aper_base; 549 uint64_t aper_size; 550 uint64_t aper_free; 551 552 struct nouveau_gpuobj *sg_ctxdma; 553 struct page *sg_dummy_page; 554 dma_addr_t sg_dummy_bus; 555 } gart_info; 556 557 /* nv10-nv40 tiling regions */ 558 struct { 559 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 560 spinlock_t lock; 561 } tile; 562 563 /* VRAM/fb configuration */ 564 uint64_t vram_size; 565 uint64_t vram_sys_base; 566 567 uint64_t fb_phys; 568 uint64_t fb_available_size; 569 uint64_t fb_mappable_pages; 570 uint64_t fb_aper_free; 571 int fb_mtrr; 572 573 /* G8x/G9x virtual address space */ 574 uint64_t vm_gart_base; 575 uint64_t vm_gart_size; 576 uint64_t vm_vram_base; 577 uint64_t vm_vram_size; 578 uint64_t vm_end; 579 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 580 int vm_vram_pt_nr; 581 582 struct drm_mm ramin_heap; 583 584 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */ 585 uint32_t ctx_table_size; 586 struct nouveau_gpuobj_ref *ctx_table; 587 588 struct list_head gpuobj_list; 589 590 struct nvbios vbios; 591 592 struct nv04_mode_state mode_reg; 593 struct nv04_mode_state saved_reg; 594 uint32_t saved_vga_font[4][16384]; 595 uint32_t crtc_owner; 596 uint32_t dac_users[4]; 597 598 struct nouveau_suspend_resume { 599 uint32_t *ramin_copy; 600 } susres; 601 602 struct backlight_device *backlight; 603 604 struct nouveau_channel *evo; 605 struct { 606 struct dcb_entry *dcb; 607 u16 script; 608 u32 pclk; 609 } evo_irq; 610 611 struct { 612 struct dentry *channel_root; 613 } debugfs; 614 615 struct nouveau_fbdev *nfbdev; 616 struct apertures_struct *apertures; 617}; 618 619static inline struct drm_nouveau_private * 620nouveau_bdev(struct ttm_bo_device *bd) 621{ 622 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 623} 624 625static inline int 626nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 627{ 628 struct nouveau_bo *prev; 629 630 if (!pnvbo) 631 return -EINVAL; 632 prev = *pnvbo; 633 634 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 635 if (prev) { 636 struct ttm_buffer_object *bo = &prev->bo; 637 638 ttm_bo_unref(&bo); 639 } 640 641 return 0; 642} 643 644#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 645 struct drm_nouveau_private *nv = dev->dev_private; \ 646 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 647 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 648 DRM_CURRENTPID, (id)); \ 649 return -EPERM; \ 650 } \ 651 (ch) = nv->fifos[(id)]; \ 652} while (0) 653 654/* nouveau_drv.c */ 655extern int nouveau_noagp; 656extern int nouveau_duallink; 657extern int nouveau_uscript_lvds; 658extern int nouveau_uscript_tmds; 659extern int nouveau_vram_pushbuf; 660extern int nouveau_vram_notify; 661extern int nouveau_fbpercrtc; 662extern int nouveau_tv_disable; 663extern char *nouveau_tv_norm; 664extern int nouveau_reg_debug; 665extern char *nouveau_vbios; 666extern int nouveau_ignorelid; 667extern int nouveau_nofbaccel; 668extern int nouveau_noaccel; 669extern int nouveau_override_conntype; 670 671extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 672extern int nouveau_pci_resume(struct pci_dev *pdev); 673 674/* nouveau_state.c */ 675extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 676extern int nouveau_load(struct drm_device *, unsigned long flags); 677extern int nouveau_firstopen(struct drm_device *); 678extern void nouveau_lastclose(struct drm_device *); 679extern int nouveau_unload(struct drm_device *); 680extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 681 struct drm_file *); 682extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 683 struct drm_file *); 684extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 685 uint32_t reg, uint32_t mask, uint32_t val); 686extern bool nouveau_wait_for_idle(struct drm_device *); 687extern int nouveau_card_init(struct drm_device *); 688 689/* nouveau_mem.c */ 690extern int nouveau_mem_detect(struct drm_device *dev); 691extern int nouveau_mem_init(struct drm_device *); 692extern int nouveau_mem_init_agp(struct drm_device *); 693extern void nouveau_mem_close(struct drm_device *); 694extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 695 uint32_t addr, 696 uint32_t size, 697 uint32_t pitch); 698extern void nv10_mem_expire_tiling(struct drm_device *dev, 699 struct nouveau_tile_reg *tile, 700 struct nouveau_fence *fence); 701extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 702 uint32_t size, uint32_t flags, 703 uint64_t phys); 704extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 705 uint32_t size); 706 707/* nouveau_notifier.c */ 708extern int nouveau_notifier_init_channel(struct nouveau_channel *); 709extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 710extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 711 int cout, uint32_t *offset); 712extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 713extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 714 struct drm_file *); 715extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 716 struct drm_file *); 717 718/* nouveau_channel.c */ 719extern struct drm_ioctl_desc nouveau_ioctls[]; 720extern int nouveau_max_ioctl; 721extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 722extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 723 int channel); 724extern int nouveau_channel_alloc(struct drm_device *dev, 725 struct nouveau_channel **chan, 726 struct drm_file *file_priv, 727 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 728extern void nouveau_channel_free(struct nouveau_channel *); 729 730/* nouveau_object.c */ 731extern int nouveau_gpuobj_early_init(struct drm_device *); 732extern int nouveau_gpuobj_init(struct drm_device *); 733extern void nouveau_gpuobj_takedown(struct drm_device *); 734extern void nouveau_gpuobj_late_takedown(struct drm_device *); 735extern int nouveau_gpuobj_suspend(struct drm_device *dev); 736extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 737extern void nouveau_gpuobj_resume(struct drm_device *dev); 738extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 739 uint32_t vram_h, uint32_t tt_h); 740extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 741extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 742 uint32_t size, int align, uint32_t flags, 743 struct nouveau_gpuobj **); 744extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); 745extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, 746 uint32_t handle, struct nouveau_gpuobj *, 747 struct nouveau_gpuobj_ref **); 748extern int nouveau_gpuobj_ref_del(struct drm_device *, 749 struct nouveau_gpuobj_ref **); 750extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, 751 struct nouveau_gpuobj_ref **ref_ret); 752extern int nouveau_gpuobj_new_ref(struct drm_device *, 753 struct nouveau_channel *alloc_chan, 754 struct nouveau_channel *ref_chan, 755 uint32_t handle, uint32_t size, int align, 756 uint32_t flags, struct nouveau_gpuobj_ref **); 757extern int nouveau_gpuobj_new_fake(struct drm_device *, 758 uint32_t p_offset, uint32_t b_offset, 759 uint32_t size, uint32_t flags, 760 struct nouveau_gpuobj **, 761 struct nouveau_gpuobj_ref**); 762extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 763 uint64_t offset, uint64_t size, int access, 764 int target, struct nouveau_gpuobj **); 765extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 766 uint64_t offset, uint64_t size, 767 int access, struct nouveau_gpuobj **, 768 uint32_t *o_ret); 769extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 770 struct nouveau_gpuobj **); 771extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 772 struct nouveau_gpuobj **); 773extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 774 struct drm_file *); 775extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 776 struct drm_file *); 777 778/* nouveau_irq.c */ 779extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 780extern void nouveau_irq_preinstall(struct drm_device *); 781extern int nouveau_irq_postinstall(struct drm_device *); 782extern void nouveau_irq_uninstall(struct drm_device *); 783 784/* nouveau_sgdma.c */ 785extern int nouveau_sgdma_init(struct drm_device *); 786extern void nouveau_sgdma_takedown(struct drm_device *); 787extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 788 uint32_t *page); 789extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 790 791/* nouveau_debugfs.c */ 792#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 793extern int nouveau_debugfs_init(struct drm_minor *); 794extern void nouveau_debugfs_takedown(struct drm_minor *); 795extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 796extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 797#else 798static inline int 799nouveau_debugfs_init(struct drm_minor *minor) 800{ 801 return 0; 802} 803 804static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 805{ 806} 807 808static inline int 809nouveau_debugfs_channel_init(struct nouveau_channel *chan) 810{ 811 return 0; 812} 813 814static inline void 815nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 816{ 817} 818#endif 819 820/* nouveau_dma.c */ 821extern void nouveau_dma_pre_init(struct nouveau_channel *); 822extern int nouveau_dma_init(struct nouveau_channel *); 823extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 824 825/* nouveau_acpi.c */ 826#define ROM_BIOS_PAGE 4096 827#if defined(CONFIG_ACPI) 828void nouveau_register_dsm_handler(void); 829void nouveau_unregister_dsm_handler(void); 830int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 831bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 832#else 833static inline void nouveau_register_dsm_handler(void) {} 834static inline void nouveau_unregister_dsm_handler(void) {} 835static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 836static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 837#endif 838 839/* nouveau_backlight.c */ 840#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 841extern int nouveau_backlight_init(struct drm_device *); 842extern void nouveau_backlight_exit(struct drm_device *); 843#else 844static inline int nouveau_backlight_init(struct drm_device *dev) 845{ 846 return 0; 847} 848 849static inline void nouveau_backlight_exit(struct drm_device *dev) { } 850#endif 851 852/* nouveau_bios.c */ 853extern int nouveau_bios_init(struct drm_device *); 854extern void nouveau_bios_takedown(struct drm_device *dev); 855extern int nouveau_run_vbios_init(struct drm_device *); 856extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 857 struct dcb_entry *); 858extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 859 enum dcb_gpio_tag); 860extern struct dcb_connector_table_entry * 861nouveau_bios_connector_entry(struct drm_device *, int index); 862extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 863 struct pll_lims *); 864extern int nouveau_bios_run_display_table(struct drm_device *, 865 struct dcb_entry *, 866 uint32_t script, int pxclk); 867extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 868 int *length); 869extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 870extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 871extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 872 bool *dl, bool *if_is_24bit); 873extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 874 int head, int pxclk); 875extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 876 enum LVDS_script, int pxclk); 877 878/* nouveau_ttm.c */ 879int nouveau_ttm_global_init(struct drm_nouveau_private *); 880void nouveau_ttm_global_release(struct drm_nouveau_private *); 881int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 882 883/* nouveau_dp.c */ 884int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 885 uint8_t *data, int data_nr); 886bool nouveau_dp_detect(struct drm_encoder *); 887bool nouveau_dp_link_train(struct drm_encoder *); 888 889/* nv04_fb.c */ 890extern int nv04_fb_init(struct drm_device *); 891extern void nv04_fb_takedown(struct drm_device *); 892 893/* nv10_fb.c */ 894extern int nv10_fb_init(struct drm_device *); 895extern void nv10_fb_takedown(struct drm_device *); 896extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 897 uint32_t, uint32_t); 898 899/* nv40_fb.c */ 900extern int nv40_fb_init(struct drm_device *); 901extern void nv40_fb_takedown(struct drm_device *); 902extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 903 uint32_t, uint32_t); 904 905/* nv50_fb.c */ 906extern int nv50_fb_init(struct drm_device *); 907extern void nv50_fb_takedown(struct drm_device *); 908 909/* nv04_fifo.c */ 910extern int nv04_fifo_init(struct drm_device *); 911extern void nv04_fifo_disable(struct drm_device *); 912extern void nv04_fifo_enable(struct drm_device *); 913extern bool nv04_fifo_reassign(struct drm_device *, bool); 914extern bool nv04_fifo_cache_flush(struct drm_device *); 915extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 916extern int nv04_fifo_channel_id(struct drm_device *); 917extern int nv04_fifo_create_context(struct nouveau_channel *); 918extern void nv04_fifo_destroy_context(struct nouveau_channel *); 919extern int nv04_fifo_load_context(struct nouveau_channel *); 920extern int nv04_fifo_unload_context(struct drm_device *); 921 922/* nv10_fifo.c */ 923extern int nv10_fifo_init(struct drm_device *); 924extern int nv10_fifo_channel_id(struct drm_device *); 925extern int nv10_fifo_create_context(struct nouveau_channel *); 926extern void nv10_fifo_destroy_context(struct nouveau_channel *); 927extern int nv10_fifo_load_context(struct nouveau_channel *); 928extern int nv10_fifo_unload_context(struct drm_device *); 929 930/* nv40_fifo.c */ 931extern int nv40_fifo_init(struct drm_device *); 932extern int nv40_fifo_create_context(struct nouveau_channel *); 933extern void nv40_fifo_destroy_context(struct nouveau_channel *); 934extern int nv40_fifo_load_context(struct nouveau_channel *); 935extern int nv40_fifo_unload_context(struct drm_device *); 936 937/* nv50_fifo.c */ 938extern int nv50_fifo_init(struct drm_device *); 939extern void nv50_fifo_takedown(struct drm_device *); 940extern int nv50_fifo_channel_id(struct drm_device *); 941extern int nv50_fifo_create_context(struct nouveau_channel *); 942extern void nv50_fifo_destroy_context(struct nouveau_channel *); 943extern int nv50_fifo_load_context(struct nouveau_channel *); 944extern int nv50_fifo_unload_context(struct drm_device *); 945 946/* nv04_graph.c */ 947extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 948extern int nv04_graph_init(struct drm_device *); 949extern void nv04_graph_takedown(struct drm_device *); 950extern void nv04_graph_fifo_access(struct drm_device *, bool); 951extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 952extern int nv04_graph_create_context(struct nouveau_channel *); 953extern void nv04_graph_destroy_context(struct nouveau_channel *); 954extern int nv04_graph_load_context(struct nouveau_channel *); 955extern int nv04_graph_unload_context(struct drm_device *); 956extern void nv04_graph_context_switch(struct drm_device *); 957 958/* nv10_graph.c */ 959extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 960extern int nv10_graph_init(struct drm_device *); 961extern void nv10_graph_takedown(struct drm_device *); 962extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 963extern int nv10_graph_create_context(struct nouveau_channel *); 964extern void nv10_graph_destroy_context(struct nouveau_channel *); 965extern int nv10_graph_load_context(struct nouveau_channel *); 966extern int nv10_graph_unload_context(struct drm_device *); 967extern void nv10_graph_context_switch(struct drm_device *); 968extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 969 uint32_t, uint32_t); 970 971/* nv20_graph.c */ 972extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 973extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 974extern int nv20_graph_create_context(struct nouveau_channel *); 975extern void nv20_graph_destroy_context(struct nouveau_channel *); 976extern int nv20_graph_load_context(struct nouveau_channel *); 977extern int nv20_graph_unload_context(struct drm_device *); 978extern int nv20_graph_init(struct drm_device *); 979extern void nv20_graph_takedown(struct drm_device *); 980extern int nv30_graph_init(struct drm_device *); 981extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 982 uint32_t, uint32_t); 983 984/* nv40_graph.c */ 985extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 986extern int nv40_graph_init(struct drm_device *); 987extern void nv40_graph_takedown(struct drm_device *); 988extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 989extern int nv40_graph_create_context(struct nouveau_channel *); 990extern void nv40_graph_destroy_context(struct nouveau_channel *); 991extern int nv40_graph_load_context(struct nouveau_channel *); 992extern int nv40_graph_unload_context(struct drm_device *); 993extern void nv40_grctx_init(struct nouveau_grctx *); 994extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 995 uint32_t, uint32_t); 996 997/* nv50_graph.c */ 998extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 999extern int nv50_graph_init(struct drm_device *); 1000extern void nv50_graph_takedown(struct drm_device *); 1001extern void nv50_graph_fifo_access(struct drm_device *, bool); 1002extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1003extern int nv50_graph_create_context(struct nouveau_channel *); 1004extern void nv50_graph_destroy_context(struct nouveau_channel *); 1005extern int nv50_graph_load_context(struct nouveau_channel *); 1006extern int nv50_graph_unload_context(struct drm_device *); 1007extern void nv50_graph_context_switch(struct drm_device *); 1008extern int nv50_grctx_init(struct nouveau_grctx *); 1009 1010/* nv04_instmem.c */ 1011extern int nv04_instmem_init(struct drm_device *); 1012extern void nv04_instmem_takedown(struct drm_device *); 1013extern int nv04_instmem_suspend(struct drm_device *); 1014extern void nv04_instmem_resume(struct drm_device *); 1015extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1016 uint32_t *size); 1017extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1018extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1019extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1020extern void nv04_instmem_flush(struct drm_device *); 1021 1022/* nv50_instmem.c */ 1023extern int nv50_instmem_init(struct drm_device *); 1024extern void nv50_instmem_takedown(struct drm_device *); 1025extern int nv50_instmem_suspend(struct drm_device *); 1026extern void nv50_instmem_resume(struct drm_device *); 1027extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1028 uint32_t *size); 1029extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1030extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1031extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1032extern void nv50_instmem_flush(struct drm_device *); 1033extern void nv50_vm_flush(struct drm_device *, int engine); 1034 1035/* nv04_mc.c */ 1036extern int nv04_mc_init(struct drm_device *); 1037extern void nv04_mc_takedown(struct drm_device *); 1038 1039/* nv40_mc.c */ 1040extern int nv40_mc_init(struct drm_device *); 1041extern void nv40_mc_takedown(struct drm_device *); 1042 1043/* nv50_mc.c */ 1044extern int nv50_mc_init(struct drm_device *); 1045extern void nv50_mc_takedown(struct drm_device *); 1046 1047/* nv04_timer.c */ 1048extern int nv04_timer_init(struct drm_device *); 1049extern uint64_t nv04_timer_read(struct drm_device *); 1050extern void nv04_timer_takedown(struct drm_device *); 1051 1052extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1053 unsigned long arg); 1054 1055/* nv04_dac.c */ 1056extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1057extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1058extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1059extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1060extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1061 1062/* nv04_dfp.c */ 1063extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1064extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1065extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1066 int head, bool dl); 1067extern void nv04_dfp_disable(struct drm_device *dev, int head); 1068extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1069 1070/* nv04_tv.c */ 1071extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1072extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1073 1074/* nv17_tv.c */ 1075extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1076 1077/* nv04_display.c */ 1078extern int nv04_display_create(struct drm_device *); 1079extern void nv04_display_destroy(struct drm_device *); 1080extern void nv04_display_restore(struct drm_device *); 1081 1082/* nv04_crtc.c */ 1083extern int nv04_crtc_create(struct drm_device *, int index); 1084 1085/* nouveau_bo.c */ 1086extern struct ttm_bo_driver nouveau_bo_driver; 1087extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1088 int size, int align, uint32_t flags, 1089 uint32_t tile_mode, uint32_t tile_flags, 1090 bool no_vm, bool mappable, struct nouveau_bo **); 1091extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1092extern int nouveau_bo_unpin(struct nouveau_bo *); 1093extern int nouveau_bo_map(struct nouveau_bo *); 1094extern void nouveau_bo_unmap(struct nouveau_bo *); 1095extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1096 uint32_t busy); 1097extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1098extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1099extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1100extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1101 1102/* nouveau_fence.c */ 1103struct nouveau_fence; 1104extern int nouveau_fence_init(struct nouveau_channel *); 1105extern void nouveau_fence_fini(struct nouveau_channel *); 1106extern void nouveau_fence_update(struct nouveau_channel *); 1107extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1108 bool emit); 1109extern int nouveau_fence_emit(struct nouveau_fence *); 1110struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1111extern bool nouveau_fence_signalled(void *obj, void *arg); 1112extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1113extern int nouveau_fence_flush(void *obj, void *arg); 1114extern void nouveau_fence_unref(void **obj); 1115extern void *nouveau_fence_ref(void *obj); 1116extern void nouveau_fence_handler(struct drm_device *dev, int channel); 1117 1118/* nouveau_gem.c */ 1119extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1120 int size, int align, uint32_t flags, 1121 uint32_t tile_mode, uint32_t tile_flags, 1122 bool no_vm, bool mappable, struct nouveau_bo **); 1123extern int nouveau_gem_object_new(struct drm_gem_object *); 1124extern void nouveau_gem_object_del(struct drm_gem_object *); 1125extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1126 struct drm_file *); 1127extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1128 struct drm_file *); 1129extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1130 struct drm_file *); 1131extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1132 struct drm_file *); 1133extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1134 struct drm_file *); 1135 1136/* nv17_gpio.c */ 1137int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1138int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1139 1140/* nv50_gpio.c */ 1141int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1142int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1143 1144/* nv50_calc. */ 1145int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1146 int *N1, int *M1, int *N2, int *M2, int *P); 1147int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1148 int clk, int *N, int *fN, int *M, int *P); 1149 1150#ifndef ioread32_native 1151#ifdef __BIG_ENDIAN 1152#define ioread16_native ioread16be 1153#define iowrite16_native iowrite16be 1154#define ioread32_native ioread32be 1155#define iowrite32_native iowrite32be 1156#else /* def __BIG_ENDIAN */ 1157#define ioread16_native ioread16 1158#define iowrite16_native iowrite16 1159#define ioread32_native ioread32 1160#define iowrite32_native iowrite32 1161#endif /* def __BIG_ENDIAN else */ 1162#endif /* !ioread32_native */ 1163 1164/* channel control reg access */ 1165static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1166{ 1167 return ioread32_native(chan->user + reg); 1168} 1169 1170static inline void nvchan_wr32(struct nouveau_channel *chan, 1171 unsigned reg, u32 val) 1172{ 1173 iowrite32_native(val, chan->user + reg); 1174} 1175 1176/* register access */ 1177static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1178{ 1179 struct drm_nouveau_private *dev_priv = dev->dev_private; 1180 return ioread32_native(dev_priv->mmio + reg); 1181} 1182 1183static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1184{ 1185 struct drm_nouveau_private *dev_priv = dev->dev_private; 1186 iowrite32_native(val, dev_priv->mmio + reg); 1187} 1188 1189static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1190{ 1191 struct drm_nouveau_private *dev_priv = dev->dev_private; 1192 return ioread8(dev_priv->mmio + reg); 1193} 1194 1195static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1196{ 1197 struct drm_nouveau_private *dev_priv = dev->dev_private; 1198 iowrite8(val, dev_priv->mmio + reg); 1199} 1200 1201#define nv_wait(reg, mask, val) \ 1202 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1203 1204/* PRAMIN access */ 1205static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1206{ 1207 struct drm_nouveau_private *dev_priv = dev->dev_private; 1208 return ioread32_native(dev_priv->ramin + offset); 1209} 1210 1211static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1212{ 1213 struct drm_nouveau_private *dev_priv = dev->dev_private; 1214 iowrite32_native(val, dev_priv->ramin + offset); 1215} 1216 1217/* object access */ 1218static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1219 unsigned index) 1220{ 1221 return nv_ri32(dev, obj->im_pramin->start + index * 4); 1222} 1223 1224static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, 1225 unsigned index, u32 val) 1226{ 1227 nv_wi32(dev, obj->im_pramin->start + index * 4, val); 1228} 1229 1230/* 1231 * Logging 1232 * Argument d is (struct drm_device *). 1233 */ 1234#define NV_PRINTK(level, d, fmt, arg...) \ 1235 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1236 pci_name(d->pdev), ##arg) 1237#ifndef NV_DEBUG_NOTRACE 1238#define NV_DEBUG(d, fmt, arg...) do { \ 1239 if (drm_debug & DRM_UT_DRIVER) { \ 1240 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1241 __LINE__, ##arg); \ 1242 } \ 1243} while (0) 1244#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1245 if (drm_debug & DRM_UT_KMS) { \ 1246 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1247 __LINE__, ##arg); \ 1248 } \ 1249} while (0) 1250#else 1251#define NV_DEBUG(d, fmt, arg...) do { \ 1252 if (drm_debug & DRM_UT_DRIVER) \ 1253 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1254} while (0) 1255#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1256 if (drm_debug & DRM_UT_KMS) \ 1257 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1258} while (0) 1259#endif 1260#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1261#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1262#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1263#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1264#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1265 1266/* nouveau_reg_debug bitmask */ 1267enum { 1268 NOUVEAU_REG_DEBUG_MC = 0x1, 1269 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1270 NOUVEAU_REG_DEBUG_FB = 0x4, 1271 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1272 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1273 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1274 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1275 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1276 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1277 NOUVEAU_REG_DEBUG_EVO = 0x200, 1278}; 1279 1280#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1281 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1282 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1283} while (0) 1284 1285static inline bool 1286nv_two_heads(struct drm_device *dev) 1287{ 1288 struct drm_nouveau_private *dev_priv = dev->dev_private; 1289 const int impl = dev->pci_device & 0x0ff0; 1290 1291 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1292 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1293 return true; 1294 1295 return false; 1296} 1297 1298static inline bool 1299nv_gf4_disp_arch(struct drm_device *dev) 1300{ 1301 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1302} 1303 1304static inline bool 1305nv_two_reg_pll(struct drm_device *dev) 1306{ 1307 struct drm_nouveau_private *dev_priv = dev->dev_private; 1308 const int impl = dev->pci_device & 0x0ff0; 1309 1310 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1311 return true; 1312 return false; 1313} 1314 1315#define NV_SW 0x0000506e 1316#define NV_SW_DMA_SEMAPHORE 0x00000060 1317#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1318#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1319#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1320#define NV_SW_DMA_VBLSEM 0x0000018c 1321#define NV_SW_VBLSEM_OFFSET 0x00000400 1322#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1323#define NV_SW_VBLSEM_RELEASE 0x00000408 1324 1325#endif /* __NOUVEAU_DRV_H__ */ 1326