nouveau_drv.h revision f13b32630dda7e583a84a8c535880cff7e4a9bdd
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57struct nouveau_grctx; 58 59#define MAX_NUM_DCB_ENTRIES 16 60 61#define NOUVEAU_MAX_CHANNEL_NR 128 62#define NOUVEAU_MAX_TILE_NR 15 63 64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 65#define NV50_VM_BLOCK (512*1024*1024ULL) 66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 67 68struct nouveau_tile_reg { 69 struct nouveau_fence *fence; 70 uint32_t addr; 71 uint32_t size; 72 bool used; 73}; 74 75struct nouveau_bo { 76 struct ttm_buffer_object bo; 77 struct ttm_placement placement; 78 u32 placements[3]; 79 u32 busy_placements[3]; 80 struct ttm_bo_kmap_obj kmap; 81 struct list_head head; 82 83 /* protected by ttm_bo_reserve() */ 84 struct drm_file *reserved_by; 85 struct list_head entry; 86 int pbbo_index; 87 bool validate_mapped; 88 89 struct nouveau_channel *channel; 90 91 bool mappable; 92 bool no_vm; 93 94 uint32_t tile_mode; 95 uint32_t tile_flags; 96 struct nouveau_tile_reg *tile; 97 98 struct drm_gem_object *gem; 99 struct drm_file *cpu_filp; 100 int pin_refcnt; 101}; 102 103#define nouveau_bo_tile_layout(nvbo) \ 104 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 105 106static inline struct nouveau_bo * 107nouveau_bo(struct ttm_buffer_object *bo) 108{ 109 return container_of(bo, struct nouveau_bo, bo); 110} 111 112static inline struct nouveau_bo * 113nouveau_gem_object(struct drm_gem_object *gem) 114{ 115 return gem ? gem->driver_private : NULL; 116} 117 118/* TODO: submit equivalent to TTM generic API upstream? */ 119static inline void __iomem * 120nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 121{ 122 bool is_iomem; 123 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 124 &nvbo->kmap, &is_iomem); 125 WARN_ON_ONCE(ioptr && !is_iomem); 126 return ioptr; 127} 128 129enum nouveau_flags { 130 NV_NFORCE = 0x10000000, 131 NV_NFORCE2 = 0x20000000 132}; 133 134#define NVOBJ_ENGINE_SW 0 135#define NVOBJ_ENGINE_GR 1 136#define NVOBJ_ENGINE_DISPLAY 2 137#define NVOBJ_ENGINE_INT 0xdeadbeef 138 139#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 140#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 141struct nouveau_gpuobj { 142 struct drm_device *dev; 143 struct kref refcount; 144 struct list_head list; 145 146 struct drm_mm_node *im_pramin; 147 struct nouveau_bo *im_backing; 148 uint32_t *im_backing_suspend; 149 int im_bound; 150 151 uint32_t flags; 152 153 u32 size; 154 u32 pinst; 155 u32 cinst; 156 u64 vinst; 157 158 uint32_t engine; 159 uint32_t class; 160 161 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 162 void *priv; 163}; 164 165struct nouveau_channel { 166 struct drm_device *dev; 167 int id; 168 169 /* owner of this fifo */ 170 struct drm_file *file_priv; 171 /* mapping of the fifo itself */ 172 struct drm_local_map *map; 173 174 /* mapping of the regs controling the fifo */ 175 void __iomem *user; 176 uint32_t user_get; 177 uint32_t user_put; 178 179 /* Fencing */ 180 struct { 181 /* lock protects the pending list only */ 182 spinlock_t lock; 183 struct list_head pending; 184 uint32_t sequence; 185 uint32_t sequence_ack; 186 atomic_t last_sequence_irq; 187 } fence; 188 189 /* DMA push buffer */ 190 struct nouveau_gpuobj *pushbuf; 191 struct nouveau_bo *pushbuf_bo; 192 uint32_t pushbuf_base; 193 194 /* Notifier memory */ 195 struct nouveau_bo *notifier_bo; 196 struct drm_mm notifier_heap; 197 198 /* PFIFO context */ 199 struct nouveau_gpuobj *ramfc; 200 struct nouveau_gpuobj *cache; 201 202 /* PGRAPH context */ 203 /* XXX may be merge 2 pointers as private data ??? */ 204 struct nouveau_gpuobj *ramin_grctx; 205 void *pgraph_ctx; 206 207 /* NV50 VM */ 208 struct nouveau_gpuobj *vm_pd; 209 struct nouveau_gpuobj *vm_gart_pt; 210 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 211 212 /* Objects */ 213 struct nouveau_gpuobj *ramin; /* Private instmem */ 214 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 215 struct nouveau_ramht *ramht; /* Hash table */ 216 217 /* GPU object info for stuff used in-kernel (mm_enabled) */ 218 uint32_t m2mf_ntfy; 219 uint32_t vram_handle; 220 uint32_t gart_handle; 221 bool accel_done; 222 223 /* Push buffer state (only for drm's channel on !mm_enabled) */ 224 struct { 225 int max; 226 int free; 227 int cur; 228 int put; 229 /* access via pushbuf_bo */ 230 231 int ib_base; 232 int ib_max; 233 int ib_free; 234 int ib_put; 235 } dma; 236 237 uint32_t sw_subchannel[8]; 238 239 struct { 240 struct nouveau_gpuobj *vblsem; 241 uint32_t vblsem_offset; 242 uint32_t vblsem_rval; 243 struct list_head vbl_wait; 244 } nvsw; 245 246 struct { 247 bool active; 248 char name[32]; 249 struct drm_info_list info; 250 } debugfs; 251}; 252 253struct nouveau_instmem_engine { 254 void *priv; 255 256 int (*init)(struct drm_device *dev); 257 void (*takedown)(struct drm_device *dev); 258 int (*suspend)(struct drm_device *dev); 259 void (*resume)(struct drm_device *dev); 260 261 int (*populate)(struct drm_device *, struct nouveau_gpuobj *, 262 uint32_t *size); 263 void (*clear)(struct drm_device *, struct nouveau_gpuobj *); 264 int (*bind)(struct drm_device *, struct nouveau_gpuobj *); 265 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); 266 void (*flush)(struct drm_device *); 267}; 268 269struct nouveau_mc_engine { 270 int (*init)(struct drm_device *dev); 271 void (*takedown)(struct drm_device *dev); 272}; 273 274struct nouveau_timer_engine { 275 int (*init)(struct drm_device *dev); 276 void (*takedown)(struct drm_device *dev); 277 uint64_t (*read)(struct drm_device *dev); 278}; 279 280struct nouveau_fb_engine { 281 int num_tiles; 282 283 int (*init)(struct drm_device *dev); 284 void (*takedown)(struct drm_device *dev); 285 286 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 287 uint32_t size, uint32_t pitch); 288}; 289 290struct nouveau_fifo_engine { 291 int channels; 292 293 struct nouveau_gpuobj *playlist[2]; 294 int cur_playlist; 295 296 int (*init)(struct drm_device *); 297 void (*takedown)(struct drm_device *); 298 299 void (*disable)(struct drm_device *); 300 void (*enable)(struct drm_device *); 301 bool (*reassign)(struct drm_device *, bool enable); 302 bool (*cache_pull)(struct drm_device *dev, bool enable); 303 304 int (*channel_id)(struct drm_device *); 305 306 int (*create_context)(struct nouveau_channel *); 307 void (*destroy_context)(struct nouveau_channel *); 308 int (*load_context)(struct nouveau_channel *); 309 int (*unload_context)(struct drm_device *); 310}; 311 312struct nouveau_pgraph_object_method { 313 int id; 314 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, 315 uint32_t data); 316}; 317 318struct nouveau_pgraph_object_class { 319 int id; 320 bool software; 321 struct nouveau_pgraph_object_method *methods; 322}; 323 324struct nouveau_pgraph_engine { 325 struct nouveau_pgraph_object_class *grclass; 326 bool accel_blocked; 327 int grctx_size; 328 329 /* NV2x/NV3x context table (0x400780) */ 330 struct nouveau_gpuobj *ctx_table; 331 332 int (*init)(struct drm_device *); 333 void (*takedown)(struct drm_device *); 334 335 void (*fifo_access)(struct drm_device *, bool); 336 337 struct nouveau_channel *(*channel)(struct drm_device *); 338 int (*create_context)(struct nouveau_channel *); 339 void (*destroy_context)(struct nouveau_channel *); 340 int (*load_context)(struct nouveau_channel *); 341 int (*unload_context)(struct drm_device *); 342 343 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, 344 uint32_t size, uint32_t pitch); 345}; 346 347struct nouveau_display_engine { 348 int (*early_init)(struct drm_device *); 349 void (*late_takedown)(struct drm_device *); 350 int (*create)(struct drm_device *); 351 int (*init)(struct drm_device *); 352 void (*destroy)(struct drm_device *); 353}; 354 355struct nouveau_gpio_engine { 356 int (*init)(struct drm_device *); 357 void (*takedown)(struct drm_device *); 358 359 int (*get)(struct drm_device *, enum dcb_gpio_tag); 360 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 361 362 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 363}; 364 365struct nouveau_pm_voltage_level { 366 u8 voltage; 367 u8 vid; 368}; 369 370struct nouveau_pm_voltage { 371 bool supported; 372 u8 vid_mask; 373 374 struct nouveau_pm_voltage_level *level; 375 int nr_level; 376}; 377 378#define NOUVEAU_PM_MAX_LEVEL 8 379struct nouveau_pm_level { 380 struct device_attribute dev_attr; 381 char name[32]; 382 int id; 383 384 u32 core; 385 u32 memory; 386 u32 shader; 387 u32 unk05; 388 389 u8 voltage; 390 u8 fanspeed; 391 392 u16 memscript; 393}; 394 395struct nouveau_pm_temp_sensor_constants { 396 u16 offset_constant; 397 s16 offset_mult; 398 u16 offset_div; 399 u16 slope_mult; 400 u16 slope_div; 401}; 402 403struct nouveau_pm_threshold_temp { 404 s16 critical; 405 s16 down_clock; 406 s16 fan_boost; 407}; 408 409struct nouveau_pm_memtiming { 410 u32 reg_100220; 411 u32 reg_100224; 412 u32 reg_100228; 413 u32 reg_10022c; 414 u32 reg_100230; 415 u32 reg_100234; 416 u32 reg_100238; 417 u32 reg_10023c; 418}; 419 420struct nouveau_pm_memtimings { 421 bool supported; 422 struct nouveau_pm_memtiming *timing; 423 int nr_timing; 424}; 425 426struct nouveau_pm_engine { 427 struct nouveau_pm_voltage voltage; 428 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 429 int nr_perflvl; 430 struct nouveau_pm_memtimings memtimings; 431 struct nouveau_pm_temp_sensor_constants sensor_constants; 432 struct nouveau_pm_threshold_temp threshold_temp; 433 434 struct nouveau_pm_level boot; 435 struct nouveau_pm_level *cur; 436 437 struct device *hwmon; 438 439 int (*clock_get)(struct drm_device *, u32 id); 440 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 441 u32 id, int khz); 442 void (*clock_set)(struct drm_device *, void *); 443 int (*voltage_get)(struct drm_device *); 444 int (*voltage_set)(struct drm_device *, int voltage); 445 int (*fanspeed_get)(struct drm_device *); 446 int (*fanspeed_set)(struct drm_device *, int fanspeed); 447 int (*temp_get)(struct drm_device *); 448}; 449 450struct nouveau_engine { 451 struct nouveau_instmem_engine instmem; 452 struct nouveau_mc_engine mc; 453 struct nouveau_timer_engine timer; 454 struct nouveau_fb_engine fb; 455 struct nouveau_pgraph_engine graph; 456 struct nouveau_fifo_engine fifo; 457 struct nouveau_display_engine display; 458 struct nouveau_gpio_engine gpio; 459 struct nouveau_pm_engine pm; 460}; 461 462struct nouveau_pll_vals { 463 union { 464 struct { 465#ifdef __BIG_ENDIAN 466 uint8_t N1, M1, N2, M2; 467#else 468 uint8_t M1, N1, M2, N2; 469#endif 470 }; 471 struct { 472 uint16_t NM1, NM2; 473 } __attribute__((packed)); 474 }; 475 int log2P; 476 477 int refclk; 478}; 479 480enum nv04_fp_display_regs { 481 FP_DISPLAY_END, 482 FP_TOTAL, 483 FP_CRTC, 484 FP_SYNC_START, 485 FP_SYNC_END, 486 FP_VALID_START, 487 FP_VALID_END 488}; 489 490struct nv04_crtc_reg { 491 unsigned char MiscOutReg; 492 uint8_t CRTC[0xa0]; 493 uint8_t CR58[0x10]; 494 uint8_t Sequencer[5]; 495 uint8_t Graphics[9]; 496 uint8_t Attribute[21]; 497 unsigned char DAC[768]; 498 499 /* PCRTC regs */ 500 uint32_t fb_start; 501 uint32_t crtc_cfg; 502 uint32_t cursor_cfg; 503 uint32_t gpio_ext; 504 uint32_t crtc_830; 505 uint32_t crtc_834; 506 uint32_t crtc_850; 507 uint32_t crtc_eng_ctrl; 508 509 /* PRAMDAC regs */ 510 uint32_t nv10_cursync; 511 struct nouveau_pll_vals pllvals; 512 uint32_t ramdac_gen_ctrl; 513 uint32_t ramdac_630; 514 uint32_t ramdac_634; 515 uint32_t tv_setup; 516 uint32_t tv_vtotal; 517 uint32_t tv_vskew; 518 uint32_t tv_vsync_delay; 519 uint32_t tv_htotal; 520 uint32_t tv_hskew; 521 uint32_t tv_hsync_delay; 522 uint32_t tv_hsync_delay2; 523 uint32_t fp_horiz_regs[7]; 524 uint32_t fp_vert_regs[7]; 525 uint32_t dither; 526 uint32_t fp_control; 527 uint32_t dither_regs[6]; 528 uint32_t fp_debug_0; 529 uint32_t fp_debug_1; 530 uint32_t fp_debug_2; 531 uint32_t fp_margin_color; 532 uint32_t ramdac_8c0; 533 uint32_t ramdac_a20; 534 uint32_t ramdac_a24; 535 uint32_t ramdac_a34; 536 uint32_t ctv_regs[38]; 537}; 538 539struct nv04_output_reg { 540 uint32_t output; 541 int head; 542}; 543 544struct nv04_mode_state { 545 struct nv04_crtc_reg crtc_reg[2]; 546 uint32_t pllsel; 547 uint32_t sel_clk; 548}; 549 550enum nouveau_card_type { 551 NV_04 = 0x00, 552 NV_10 = 0x10, 553 NV_20 = 0x20, 554 NV_30 = 0x30, 555 NV_40 = 0x40, 556 NV_50 = 0x50, 557 NV_C0 = 0xc0, 558}; 559 560struct drm_nouveau_private { 561 struct drm_device *dev; 562 563 /* the card type, takes NV_* as values */ 564 enum nouveau_card_type card_type; 565 /* exact chipset, derived from NV_PMC_BOOT_0 */ 566 int chipset; 567 int flags; 568 569 void __iomem *mmio; 570 571 spinlock_t ramin_lock; 572 void __iomem *ramin; 573 u32 ramin_size; 574 u32 ramin_base; 575 bool ramin_available; 576 struct drm_mm ramin_heap; 577 struct list_head gpuobj_list; 578 579 struct nouveau_bo *vga_ram; 580 581 struct workqueue_struct *wq; 582 struct work_struct irq_work; 583 struct work_struct hpd_work; 584 585 struct list_head vbl_waiting; 586 587 struct { 588 struct drm_global_reference mem_global_ref; 589 struct ttm_bo_global_ref bo_global_ref; 590 struct ttm_bo_device bdev; 591 atomic_t validate_sequence; 592 } ttm; 593 594 struct { 595 spinlock_t lock; 596 struct drm_mm heap; 597 struct nouveau_bo *bo; 598 } fence; 599 600 int fifo_alloc_count; 601 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; 602 603 struct nouveau_engine engine; 604 struct nouveau_channel *channel; 605 606 /* For PFIFO and PGRAPH. */ 607 spinlock_t context_switch_lock; 608 609 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 610 struct nouveau_ramht *ramht; 611 struct nouveau_gpuobj *ramfc; 612 struct nouveau_gpuobj *ramro; 613 614 uint32_t ramin_rsvd_vram; 615 616 struct { 617 enum { 618 NOUVEAU_GART_NONE = 0, 619 NOUVEAU_GART_AGP, 620 NOUVEAU_GART_SGDMA 621 } type; 622 uint64_t aper_base; 623 uint64_t aper_size; 624 uint64_t aper_free; 625 626 struct nouveau_gpuobj *sg_ctxdma; 627 struct page *sg_dummy_page; 628 dma_addr_t sg_dummy_bus; 629 } gart_info; 630 631 /* nv10-nv40 tiling regions */ 632 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR]; 633 634 /* VRAM/fb configuration */ 635 uint64_t vram_size; 636 uint64_t vram_sys_base; 637 u32 vram_rblock_size; 638 639 uint64_t fb_phys; 640 uint64_t fb_available_size; 641 uint64_t fb_mappable_pages; 642 uint64_t fb_aper_free; 643 int fb_mtrr; 644 645 /* G8x/G9x virtual address space */ 646 uint64_t vm_gart_base; 647 uint64_t vm_gart_size; 648 uint64_t vm_vram_base; 649 uint64_t vm_vram_size; 650 uint64_t vm_end; 651 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 652 int vm_vram_pt_nr; 653 654 struct nvbios vbios; 655 656 struct nv04_mode_state mode_reg; 657 struct nv04_mode_state saved_reg; 658 uint32_t saved_vga_font[4][16384]; 659 uint32_t crtc_owner; 660 uint32_t dac_users[4]; 661 662 struct nouveau_suspend_resume { 663 uint32_t *ramin_copy; 664 } susres; 665 666 struct backlight_device *backlight; 667 668 struct nouveau_channel *evo; 669 struct { 670 struct dcb_entry *dcb; 671 u16 script; 672 u32 pclk; 673 } evo_irq; 674 675 struct { 676 struct dentry *channel_root; 677 } debugfs; 678 679 struct nouveau_fbdev *nfbdev; 680 struct apertures_struct *apertures; 681}; 682 683static inline struct drm_nouveau_private * 684nouveau_private(struct drm_device *dev) 685{ 686 return dev->dev_private; 687} 688 689static inline struct drm_nouveau_private * 690nouveau_bdev(struct ttm_bo_device *bd) 691{ 692 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 693} 694 695static inline int 696nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 697{ 698 struct nouveau_bo *prev; 699 700 if (!pnvbo) 701 return -EINVAL; 702 prev = *pnvbo; 703 704 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 705 if (prev) { 706 struct ttm_buffer_object *bo = &prev->bo; 707 708 ttm_bo_unref(&bo); 709 } 710 711 return 0; 712} 713 714#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ 715 struct drm_nouveau_private *nv = dev->dev_private; \ 716 if (!nouveau_channel_owner(dev, (cl), (id))) { \ 717 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ 718 DRM_CURRENTPID, (id)); \ 719 return -EPERM; \ 720 } \ 721 (ch) = nv->fifos[(id)]; \ 722} while (0) 723 724/* nouveau_drv.c */ 725extern int nouveau_agpmode; 726extern int nouveau_duallink; 727extern int nouveau_uscript_lvds; 728extern int nouveau_uscript_tmds; 729extern int nouveau_vram_pushbuf; 730extern int nouveau_vram_notify; 731extern int nouveau_fbpercrtc; 732extern int nouveau_tv_disable; 733extern char *nouveau_tv_norm; 734extern int nouveau_reg_debug; 735extern char *nouveau_vbios; 736extern int nouveau_ignorelid; 737extern int nouveau_nofbaccel; 738extern int nouveau_noaccel; 739extern int nouveau_force_post; 740extern int nouveau_override_conntype; 741extern char *nouveau_perflvl; 742extern int nouveau_perflvl_wr; 743 744extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 745extern int nouveau_pci_resume(struct pci_dev *pdev); 746 747/* nouveau_state.c */ 748extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 749extern int nouveau_load(struct drm_device *, unsigned long flags); 750extern int nouveau_firstopen(struct drm_device *); 751extern void nouveau_lastclose(struct drm_device *); 752extern int nouveau_unload(struct drm_device *); 753extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 754 struct drm_file *); 755extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 756 struct drm_file *); 757extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, 758 uint32_t reg, uint32_t mask, uint32_t val); 759extern bool nouveau_wait_for_idle(struct drm_device *); 760extern int nouveau_card_init(struct drm_device *); 761 762/* nouveau_mem.c */ 763extern int nouveau_mem_vram_init(struct drm_device *); 764extern void nouveau_mem_vram_fini(struct drm_device *); 765extern int nouveau_mem_gart_init(struct drm_device *); 766extern void nouveau_mem_gart_fini(struct drm_device *); 767extern int nouveau_mem_init_agp(struct drm_device *); 768extern int nouveau_mem_reset_agp(struct drm_device *); 769extern void nouveau_mem_close(struct drm_device *); 770extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, 771 uint32_t addr, 772 uint32_t size, 773 uint32_t pitch); 774extern void nv10_mem_expire_tiling(struct drm_device *dev, 775 struct nouveau_tile_reg *tile, 776 struct nouveau_fence *fence); 777extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 778 uint32_t size, uint32_t flags, 779 uint64_t phys); 780extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 781 uint32_t size); 782 783/* nouveau_notifier.c */ 784extern int nouveau_notifier_init_channel(struct nouveau_channel *); 785extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 786extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 787 int cout, uint32_t *offset); 788extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 789extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 790 struct drm_file *); 791extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 792 struct drm_file *); 793 794/* nouveau_channel.c */ 795extern struct drm_ioctl_desc nouveau_ioctls[]; 796extern int nouveau_max_ioctl; 797extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 798extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, 799 int channel); 800extern int nouveau_channel_alloc(struct drm_device *dev, 801 struct nouveau_channel **chan, 802 struct drm_file *file_priv, 803 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 804extern void nouveau_channel_free(struct nouveau_channel *); 805 806/* nouveau_object.c */ 807extern int nouveau_gpuobj_early_init(struct drm_device *); 808extern int nouveau_gpuobj_init(struct drm_device *); 809extern void nouveau_gpuobj_takedown(struct drm_device *); 810extern int nouveau_gpuobj_suspend(struct drm_device *dev); 811extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); 812extern void nouveau_gpuobj_resume(struct drm_device *dev); 813extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 814 uint32_t vram_h, uint32_t tt_h); 815extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 816extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 817 uint32_t size, int align, uint32_t flags, 818 struct nouveau_gpuobj **); 819extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 820 struct nouveau_gpuobj **); 821extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 822 u32 size, u32 flags, 823 struct nouveau_gpuobj **); 824extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 825 uint64_t offset, uint64_t size, int access, 826 int target, struct nouveau_gpuobj **); 827extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, 828 uint64_t offset, uint64_t size, 829 int access, struct nouveau_gpuobj **, 830 uint32_t *o_ret); 831extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, 832 struct nouveau_gpuobj **); 833extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, 834 struct nouveau_gpuobj **); 835extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 836 struct drm_file *); 837extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 838 struct drm_file *); 839 840/* nouveau_irq.c */ 841extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 842extern void nouveau_irq_preinstall(struct drm_device *); 843extern int nouveau_irq_postinstall(struct drm_device *); 844extern void nouveau_irq_uninstall(struct drm_device *); 845 846/* nouveau_sgdma.c */ 847extern int nouveau_sgdma_init(struct drm_device *); 848extern void nouveau_sgdma_takedown(struct drm_device *); 849extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 850 uint32_t *page); 851extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 852 853/* nouveau_debugfs.c */ 854#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 855extern int nouveau_debugfs_init(struct drm_minor *); 856extern void nouveau_debugfs_takedown(struct drm_minor *); 857extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 858extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 859#else 860static inline int 861nouveau_debugfs_init(struct drm_minor *minor) 862{ 863 return 0; 864} 865 866static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 867{ 868} 869 870static inline int 871nouveau_debugfs_channel_init(struct nouveau_channel *chan) 872{ 873 return 0; 874} 875 876static inline void 877nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 878{ 879} 880#endif 881 882/* nouveau_dma.c */ 883extern void nouveau_dma_pre_init(struct nouveau_channel *); 884extern int nouveau_dma_init(struct nouveau_channel *); 885extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 886 887/* nouveau_acpi.c */ 888#define ROM_BIOS_PAGE 4096 889#if defined(CONFIG_ACPI) 890void nouveau_register_dsm_handler(void); 891void nouveau_unregister_dsm_handler(void); 892int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 893bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 894int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 895#else 896static inline void nouveau_register_dsm_handler(void) {} 897static inline void nouveau_unregister_dsm_handler(void) {} 898static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 899static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 900static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 901#endif 902 903/* nouveau_backlight.c */ 904#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 905extern int nouveau_backlight_init(struct drm_device *); 906extern void nouveau_backlight_exit(struct drm_device *); 907#else 908static inline int nouveau_backlight_init(struct drm_device *dev) 909{ 910 return 0; 911} 912 913static inline void nouveau_backlight_exit(struct drm_device *dev) { } 914#endif 915 916/* nouveau_bios.c */ 917extern int nouveau_bios_init(struct drm_device *); 918extern void nouveau_bios_takedown(struct drm_device *dev); 919extern int nouveau_run_vbios_init(struct drm_device *); 920extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 921 struct dcb_entry *); 922extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 923 enum dcb_gpio_tag); 924extern struct dcb_connector_table_entry * 925nouveau_bios_connector_entry(struct drm_device *, int index); 926extern u32 get_pll_register(struct drm_device *, enum pll_types); 927extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 928 struct pll_lims *); 929extern int nouveau_bios_run_display_table(struct drm_device *, 930 struct dcb_entry *, 931 uint32_t script, int pxclk); 932extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 933 int *length); 934extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 935extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 936extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 937 bool *dl, bool *if_is_24bit); 938extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 939 int head, int pxclk); 940extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 941 enum LVDS_script, int pxclk); 942 943/* nouveau_ttm.c */ 944int nouveau_ttm_global_init(struct drm_nouveau_private *); 945void nouveau_ttm_global_release(struct drm_nouveau_private *); 946int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 947 948/* nouveau_dp.c */ 949int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 950 uint8_t *data, int data_nr); 951bool nouveau_dp_detect(struct drm_encoder *); 952bool nouveau_dp_link_train(struct drm_encoder *); 953 954/* nv04_fb.c */ 955extern int nv04_fb_init(struct drm_device *); 956extern void nv04_fb_takedown(struct drm_device *); 957 958/* nv10_fb.c */ 959extern int nv10_fb_init(struct drm_device *); 960extern void nv10_fb_takedown(struct drm_device *); 961extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, 962 uint32_t, uint32_t); 963 964/* nv30_fb.c */ 965extern int nv30_fb_init(struct drm_device *); 966extern void nv30_fb_takedown(struct drm_device *); 967 968/* nv40_fb.c */ 969extern int nv40_fb_init(struct drm_device *); 970extern void nv40_fb_takedown(struct drm_device *); 971extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, 972 uint32_t, uint32_t); 973/* nv50_fb.c */ 974extern int nv50_fb_init(struct drm_device *); 975extern void nv50_fb_takedown(struct drm_device *); 976extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 977 978/* nvc0_fb.c */ 979extern int nvc0_fb_init(struct drm_device *); 980extern void nvc0_fb_takedown(struct drm_device *); 981 982/* nv04_fifo.c */ 983extern int nv04_fifo_init(struct drm_device *); 984extern void nv04_fifo_disable(struct drm_device *); 985extern void nv04_fifo_enable(struct drm_device *); 986extern bool nv04_fifo_reassign(struct drm_device *, bool); 987extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 988extern int nv04_fifo_channel_id(struct drm_device *); 989extern int nv04_fifo_create_context(struct nouveau_channel *); 990extern void nv04_fifo_destroy_context(struct nouveau_channel *); 991extern int nv04_fifo_load_context(struct nouveau_channel *); 992extern int nv04_fifo_unload_context(struct drm_device *); 993 994/* nv10_fifo.c */ 995extern int nv10_fifo_init(struct drm_device *); 996extern int nv10_fifo_channel_id(struct drm_device *); 997extern int nv10_fifo_create_context(struct nouveau_channel *); 998extern void nv10_fifo_destroy_context(struct nouveau_channel *); 999extern int nv10_fifo_load_context(struct nouveau_channel *); 1000extern int nv10_fifo_unload_context(struct drm_device *); 1001 1002/* nv40_fifo.c */ 1003extern int nv40_fifo_init(struct drm_device *); 1004extern int nv40_fifo_create_context(struct nouveau_channel *); 1005extern void nv40_fifo_destroy_context(struct nouveau_channel *); 1006extern int nv40_fifo_load_context(struct nouveau_channel *); 1007extern int nv40_fifo_unload_context(struct drm_device *); 1008 1009/* nv50_fifo.c */ 1010extern int nv50_fifo_init(struct drm_device *); 1011extern void nv50_fifo_takedown(struct drm_device *); 1012extern int nv50_fifo_channel_id(struct drm_device *); 1013extern int nv50_fifo_create_context(struct nouveau_channel *); 1014extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1015extern int nv50_fifo_load_context(struct nouveau_channel *); 1016extern int nv50_fifo_unload_context(struct drm_device *); 1017 1018/* nvc0_fifo.c */ 1019extern int nvc0_fifo_init(struct drm_device *); 1020extern void nvc0_fifo_takedown(struct drm_device *); 1021extern void nvc0_fifo_disable(struct drm_device *); 1022extern void nvc0_fifo_enable(struct drm_device *); 1023extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1024extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1025extern int nvc0_fifo_channel_id(struct drm_device *); 1026extern int nvc0_fifo_create_context(struct nouveau_channel *); 1027extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1028extern int nvc0_fifo_load_context(struct nouveau_channel *); 1029extern int nvc0_fifo_unload_context(struct drm_device *); 1030 1031/* nv04_graph.c */ 1032extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; 1033extern int nv04_graph_init(struct drm_device *); 1034extern void nv04_graph_takedown(struct drm_device *); 1035extern void nv04_graph_fifo_access(struct drm_device *, bool); 1036extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1037extern int nv04_graph_create_context(struct nouveau_channel *); 1038extern void nv04_graph_destroy_context(struct nouveau_channel *); 1039extern int nv04_graph_load_context(struct nouveau_channel *); 1040extern int nv04_graph_unload_context(struct drm_device *); 1041extern void nv04_graph_context_switch(struct drm_device *); 1042 1043/* nv10_graph.c */ 1044extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; 1045extern int nv10_graph_init(struct drm_device *); 1046extern void nv10_graph_takedown(struct drm_device *); 1047extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1048extern int nv10_graph_create_context(struct nouveau_channel *); 1049extern void nv10_graph_destroy_context(struct nouveau_channel *); 1050extern int nv10_graph_load_context(struct nouveau_channel *); 1051extern int nv10_graph_unload_context(struct drm_device *); 1052extern void nv10_graph_context_switch(struct drm_device *); 1053extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1054 uint32_t, uint32_t); 1055 1056/* nv20_graph.c */ 1057extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; 1058extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; 1059extern int nv20_graph_create_context(struct nouveau_channel *); 1060extern void nv20_graph_destroy_context(struct nouveau_channel *); 1061extern int nv20_graph_load_context(struct nouveau_channel *); 1062extern int nv20_graph_unload_context(struct drm_device *); 1063extern int nv20_graph_init(struct drm_device *); 1064extern void nv20_graph_takedown(struct drm_device *); 1065extern int nv30_graph_init(struct drm_device *); 1066extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1067 uint32_t, uint32_t); 1068 1069/* nv40_graph.c */ 1070extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; 1071extern int nv40_graph_init(struct drm_device *); 1072extern void nv40_graph_takedown(struct drm_device *); 1073extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1074extern int nv40_graph_create_context(struct nouveau_channel *); 1075extern void nv40_graph_destroy_context(struct nouveau_channel *); 1076extern int nv40_graph_load_context(struct nouveau_channel *); 1077extern int nv40_graph_unload_context(struct drm_device *); 1078extern void nv40_grctx_init(struct nouveau_grctx *); 1079extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, 1080 uint32_t, uint32_t); 1081 1082/* nv50_graph.c */ 1083extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; 1084extern int nv50_graph_init(struct drm_device *); 1085extern void nv50_graph_takedown(struct drm_device *); 1086extern void nv50_graph_fifo_access(struct drm_device *, bool); 1087extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1088extern int nv50_graph_create_context(struct nouveau_channel *); 1089extern void nv50_graph_destroy_context(struct nouveau_channel *); 1090extern int nv50_graph_load_context(struct nouveau_channel *); 1091extern int nv50_graph_unload_context(struct drm_device *); 1092extern void nv50_graph_context_switch(struct drm_device *); 1093extern int nv50_grctx_init(struct nouveau_grctx *); 1094 1095/* nvc0_graph.c */ 1096extern int nvc0_graph_init(struct drm_device *); 1097extern void nvc0_graph_takedown(struct drm_device *); 1098extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1099extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1100extern int nvc0_graph_create_context(struct nouveau_channel *); 1101extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1102extern int nvc0_graph_load_context(struct nouveau_channel *); 1103extern int nvc0_graph_unload_context(struct drm_device *); 1104 1105/* nv04_instmem.c */ 1106extern int nv04_instmem_init(struct drm_device *); 1107extern void nv04_instmem_takedown(struct drm_device *); 1108extern int nv04_instmem_suspend(struct drm_device *); 1109extern void nv04_instmem_resume(struct drm_device *); 1110extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1111 uint32_t *size); 1112extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1113extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1114extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1115extern void nv04_instmem_flush(struct drm_device *); 1116 1117/* nv50_instmem.c */ 1118extern int nv50_instmem_init(struct drm_device *); 1119extern void nv50_instmem_takedown(struct drm_device *); 1120extern int nv50_instmem_suspend(struct drm_device *); 1121extern void nv50_instmem_resume(struct drm_device *); 1122extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1123 uint32_t *size); 1124extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1125extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1126extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1127extern void nv50_instmem_flush(struct drm_device *); 1128extern void nv84_instmem_flush(struct drm_device *); 1129extern void nv50_vm_flush(struct drm_device *, int engine); 1130 1131/* nvc0_instmem.c */ 1132extern int nvc0_instmem_init(struct drm_device *); 1133extern void nvc0_instmem_takedown(struct drm_device *); 1134extern int nvc0_instmem_suspend(struct drm_device *); 1135extern void nvc0_instmem_resume(struct drm_device *); 1136extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 1137 uint32_t *size); 1138extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); 1139extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); 1140extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); 1141extern void nvc0_instmem_flush(struct drm_device *); 1142 1143/* nv04_mc.c */ 1144extern int nv04_mc_init(struct drm_device *); 1145extern void nv04_mc_takedown(struct drm_device *); 1146 1147/* nv40_mc.c */ 1148extern int nv40_mc_init(struct drm_device *); 1149extern void nv40_mc_takedown(struct drm_device *); 1150 1151/* nv50_mc.c */ 1152extern int nv50_mc_init(struct drm_device *); 1153extern void nv50_mc_takedown(struct drm_device *); 1154 1155/* nv04_timer.c */ 1156extern int nv04_timer_init(struct drm_device *); 1157extern uint64_t nv04_timer_read(struct drm_device *); 1158extern void nv04_timer_takedown(struct drm_device *); 1159 1160extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1161 unsigned long arg); 1162 1163/* nv04_dac.c */ 1164extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1165extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1166extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1167extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1168extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1169 1170/* nv04_dfp.c */ 1171extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1172extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1173extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1174 int head, bool dl); 1175extern void nv04_dfp_disable(struct drm_device *dev, int head); 1176extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1177 1178/* nv04_tv.c */ 1179extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1180extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1181 1182/* nv17_tv.c */ 1183extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1184 1185/* nv04_display.c */ 1186extern int nv04_display_early_init(struct drm_device *); 1187extern void nv04_display_late_takedown(struct drm_device *); 1188extern int nv04_display_create(struct drm_device *); 1189extern int nv04_display_init(struct drm_device *); 1190extern void nv04_display_destroy(struct drm_device *); 1191 1192/* nv04_crtc.c */ 1193extern int nv04_crtc_create(struct drm_device *, int index); 1194 1195/* nouveau_bo.c */ 1196extern struct ttm_bo_driver nouveau_bo_driver; 1197extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1198 int size, int align, uint32_t flags, 1199 uint32_t tile_mode, uint32_t tile_flags, 1200 bool no_vm, bool mappable, struct nouveau_bo **); 1201extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1202extern int nouveau_bo_unpin(struct nouveau_bo *); 1203extern int nouveau_bo_map(struct nouveau_bo *); 1204extern void nouveau_bo_unmap(struct nouveau_bo *); 1205extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1206 uint32_t busy); 1207extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1208extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1209extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1210extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1211 1212/* nouveau_fence.c */ 1213struct nouveau_fence; 1214extern int nouveau_fence_init(struct drm_device *); 1215extern void nouveau_fence_fini(struct drm_device *); 1216extern int nouveau_fence_channel_init(struct nouveau_channel *); 1217extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1218extern void nouveau_fence_update(struct nouveau_channel *); 1219extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1220 bool emit); 1221extern int nouveau_fence_emit(struct nouveau_fence *); 1222extern void nouveau_fence_work(struct nouveau_fence *fence, 1223 void (*work)(void *priv, bool signalled), 1224 void *priv); 1225struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1226extern bool nouveau_fence_signalled(void *obj, void *arg); 1227extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1228extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1229extern int nouveau_fence_flush(void *obj, void *arg); 1230extern void nouveau_fence_unref(void **obj); 1231extern void *nouveau_fence_ref(void *obj); 1232 1233/* nouveau_gem.c */ 1234extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1235 int size, int align, uint32_t flags, 1236 uint32_t tile_mode, uint32_t tile_flags, 1237 bool no_vm, bool mappable, struct nouveau_bo **); 1238extern int nouveau_gem_object_new(struct drm_gem_object *); 1239extern void nouveau_gem_object_del(struct drm_gem_object *); 1240extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1241 struct drm_file *); 1242extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1243 struct drm_file *); 1244extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1245 struct drm_file *); 1246extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1247 struct drm_file *); 1248extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1249 struct drm_file *); 1250 1251/* nv10_gpio.c */ 1252int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1253int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1254 1255/* nv50_gpio.c */ 1256int nv50_gpio_init(struct drm_device *dev); 1257int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1258int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1259void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1260 1261/* nv50_calc. */ 1262int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1263 int *N1, int *M1, int *N2, int *M2, int *P); 1264int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1265 int clk, int *N, int *fN, int *M, int *P); 1266 1267#ifndef ioread32_native 1268#ifdef __BIG_ENDIAN 1269#define ioread16_native ioread16be 1270#define iowrite16_native iowrite16be 1271#define ioread32_native ioread32be 1272#define iowrite32_native iowrite32be 1273#else /* def __BIG_ENDIAN */ 1274#define ioread16_native ioread16 1275#define iowrite16_native iowrite16 1276#define ioread32_native ioread32 1277#define iowrite32_native iowrite32 1278#endif /* def __BIG_ENDIAN else */ 1279#endif /* !ioread32_native */ 1280 1281/* channel control reg access */ 1282static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1283{ 1284 return ioread32_native(chan->user + reg); 1285} 1286 1287static inline void nvchan_wr32(struct nouveau_channel *chan, 1288 unsigned reg, u32 val) 1289{ 1290 iowrite32_native(val, chan->user + reg); 1291} 1292 1293/* register access */ 1294static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1295{ 1296 struct drm_nouveau_private *dev_priv = dev->dev_private; 1297 return ioread32_native(dev_priv->mmio + reg); 1298} 1299 1300static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1301{ 1302 struct drm_nouveau_private *dev_priv = dev->dev_private; 1303 iowrite32_native(val, dev_priv->mmio + reg); 1304} 1305 1306static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1307{ 1308 u32 tmp = nv_rd32(dev, reg); 1309 nv_wr32(dev, reg, (tmp & ~mask) | val); 1310 return tmp; 1311} 1312 1313static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1314{ 1315 struct drm_nouveau_private *dev_priv = dev->dev_private; 1316 return ioread8(dev_priv->mmio + reg); 1317} 1318 1319static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1320{ 1321 struct drm_nouveau_private *dev_priv = dev->dev_private; 1322 iowrite8(val, dev_priv->mmio + reg); 1323} 1324 1325#define nv_wait(dev, reg, mask, val) \ 1326 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) 1327 1328/* PRAMIN access */ 1329static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1330{ 1331 struct drm_nouveau_private *dev_priv = dev->dev_private; 1332 return ioread32_native(dev_priv->ramin + offset); 1333} 1334 1335static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1336{ 1337 struct drm_nouveau_private *dev_priv = dev->dev_private; 1338 iowrite32_native(val, dev_priv->ramin + offset); 1339} 1340 1341/* object access */ 1342extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1343extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1344 1345/* 1346 * Logging 1347 * Argument d is (struct drm_device *). 1348 */ 1349#define NV_PRINTK(level, d, fmt, arg...) \ 1350 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1351 pci_name(d->pdev), ##arg) 1352#ifndef NV_DEBUG_NOTRACE 1353#define NV_DEBUG(d, fmt, arg...) do { \ 1354 if (drm_debug & DRM_UT_DRIVER) { \ 1355 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1356 __LINE__, ##arg); \ 1357 } \ 1358} while (0) 1359#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1360 if (drm_debug & DRM_UT_KMS) { \ 1361 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1362 __LINE__, ##arg); \ 1363 } \ 1364} while (0) 1365#else 1366#define NV_DEBUG(d, fmt, arg...) do { \ 1367 if (drm_debug & DRM_UT_DRIVER) \ 1368 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1369} while (0) 1370#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1371 if (drm_debug & DRM_UT_KMS) \ 1372 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1373} while (0) 1374#endif 1375#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1376#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1377#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1378#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1379#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1380 1381/* nouveau_reg_debug bitmask */ 1382enum { 1383 NOUVEAU_REG_DEBUG_MC = 0x1, 1384 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1385 NOUVEAU_REG_DEBUG_FB = 0x4, 1386 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1387 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1388 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1389 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1390 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1391 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1392 NOUVEAU_REG_DEBUG_EVO = 0x200, 1393}; 1394 1395#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1396 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1397 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1398} while (0) 1399 1400static inline bool 1401nv_two_heads(struct drm_device *dev) 1402{ 1403 struct drm_nouveau_private *dev_priv = dev->dev_private; 1404 const int impl = dev->pci_device & 0x0ff0; 1405 1406 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1407 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1408 return true; 1409 1410 return false; 1411} 1412 1413static inline bool 1414nv_gf4_disp_arch(struct drm_device *dev) 1415{ 1416 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1417} 1418 1419static inline bool 1420nv_two_reg_pll(struct drm_device *dev) 1421{ 1422 struct drm_nouveau_private *dev_priv = dev->dev_private; 1423 const int impl = dev->pci_device & 0x0ff0; 1424 1425 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1426 return true; 1427 return false; 1428} 1429 1430static inline bool 1431nv_match_device(struct drm_device *dev, unsigned device, 1432 unsigned sub_vendor, unsigned sub_device) 1433{ 1434 return dev->pdev->device == device && 1435 dev->pdev->subsystem_vendor == sub_vendor && 1436 dev->pdev->subsystem_device == sub_device; 1437} 1438 1439#define NV_SW 0x0000506e 1440#define NV_SW_DMA_SEMAPHORE 0x00000060 1441#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1442#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1443#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1444#define NV_SW_YIELD 0x00000080 1445#define NV_SW_DMA_VBLSEM 0x0000018c 1446#define NV_SW_VBLSEM_OFFSET 0x00000400 1447#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1448#define NV_SW_VBLSEM_RELEASE 0x00000408 1449 1450#endif /* __NOUVEAU_DRV_H__ */ 1451