nouveau_drv.h revision f13e435c59573aa0ac398210777cc0406c476593
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78}; 79 80struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88}; 89 90struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 bool mappable; 108 bool no_vm; 109 110 uint32_t tile_mode; 111 uint32_t tile_flags; 112 struct nouveau_tile_reg *tile; 113 114 struct drm_gem_object *gem; 115 int pin_refcnt; 116}; 117 118#define nouveau_bo_tile_layout(nvbo) \ 119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 120 121static inline struct nouveau_bo * 122nouveau_bo(struct ttm_buffer_object *bo) 123{ 124 return container_of(bo, struct nouveau_bo, bo); 125} 126 127static inline struct nouveau_bo * 128nouveau_gem_object(struct drm_gem_object *gem) 129{ 130 return gem ? gem->driver_private : NULL; 131} 132 133/* TODO: submit equivalent to TTM generic API upstream? */ 134static inline void __iomem * 135nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 136{ 137 bool is_iomem; 138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 139 &nvbo->kmap, &is_iomem); 140 WARN_ON_ONCE(ioptr && !is_iomem); 141 return ioptr; 142} 143 144enum nouveau_flags { 145 NV_NFORCE = 0x10000000, 146 NV_NFORCE2 = 0x20000000 147}; 148 149#define NVOBJ_ENGINE_SW 0 150#define NVOBJ_ENGINE_GR 1 151#define NVOBJ_ENGINE_PPP 2 152#define NVOBJ_ENGINE_COPY 3 153#define NVOBJ_ENGINE_VP 4 154#define NVOBJ_ENGINE_CRYPT 5 155#define NVOBJ_ENGINE_BSP 6 156#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 157#define NVOBJ_ENGINE_INT 0xdeadbeef 158 159#define NVOBJ_FLAG_DONT_MAP (1 << 0) 160#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 161#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 162#define NVOBJ_FLAG_VM (1 << 3) 163#define NVOBJ_FLAG_VM_USER (1 << 4) 164 165#define NVOBJ_CINST_GLOBAL 0xdeadbeef 166 167struct nouveau_gpuobj { 168 struct drm_device *dev; 169 struct kref refcount; 170 struct list_head list; 171 172 void *node; 173 u32 *suspend; 174 175 uint32_t flags; 176 177 u32 size; 178 u32 pinst; 179 u32 cinst; 180 u64 vinst; 181 182 uint32_t engine; 183 uint32_t class; 184 185 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 186 void *priv; 187}; 188 189struct nouveau_page_flip_state { 190 struct list_head head; 191 struct drm_pending_vblank_event *event; 192 int crtc, bpp, pitch, x, y; 193 uint64_t offset; 194}; 195 196enum nouveau_channel_mutex_class { 197 NOUVEAU_UCHANNEL_MUTEX, 198 NOUVEAU_KCHANNEL_MUTEX 199}; 200 201struct nouveau_channel { 202 struct drm_device *dev; 203 int id; 204 205 /* references to the channel data structure */ 206 struct kref ref; 207 /* users of the hardware channel resources, the hardware 208 * context will be kicked off when it reaches zero. */ 209 atomic_t users; 210 struct mutex mutex; 211 212 /* owner of this fifo */ 213 struct drm_file *file_priv; 214 /* mapping of the fifo itself */ 215 struct drm_local_map *map; 216 217 /* mapping of the regs controling the fifo */ 218 void __iomem *user; 219 uint32_t user_get; 220 uint32_t user_put; 221 222 /* Fencing */ 223 struct { 224 /* lock protects the pending list only */ 225 spinlock_t lock; 226 struct list_head pending; 227 uint32_t sequence; 228 uint32_t sequence_ack; 229 atomic_t last_sequence_irq; 230 } fence; 231 232 /* DMA push buffer */ 233 struct nouveau_gpuobj *pushbuf; 234 struct nouveau_bo *pushbuf_bo; 235 uint32_t pushbuf_base; 236 237 /* Notifier memory */ 238 struct nouveau_bo *notifier_bo; 239 struct drm_mm notifier_heap; 240 241 /* PFIFO context */ 242 struct nouveau_gpuobj *ramfc; 243 struct nouveau_gpuobj *cache; 244 void *fifo_priv; 245 246 /* PGRAPH context */ 247 /* XXX may be merge 2 pointers as private data ??? */ 248 struct nouveau_gpuobj *ramin_grctx; 249 struct nouveau_gpuobj *crypt_ctx; 250 void *pgraph_ctx; 251 252 /* NV50 VM */ 253 struct nouveau_vm *vm; 254 struct nouveau_gpuobj *vm_pd; 255 256 /* Objects */ 257 struct nouveau_gpuobj *ramin; /* Private instmem */ 258 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 259 struct nouveau_ramht *ramht; /* Hash table */ 260 261 /* GPU object info for stuff used in-kernel (mm_enabled) */ 262 uint32_t m2mf_ntfy; 263 uint32_t vram_handle; 264 uint32_t gart_handle; 265 bool accel_done; 266 267 /* Push buffer state (only for drm's channel on !mm_enabled) */ 268 struct { 269 int max; 270 int free; 271 int cur; 272 int put; 273 /* access via pushbuf_bo */ 274 275 int ib_base; 276 int ib_max; 277 int ib_free; 278 int ib_put; 279 } dma; 280 281 uint32_t sw_subchannel[8]; 282 283 struct { 284 struct nouveau_gpuobj *vblsem; 285 uint32_t vblsem_head; 286 uint32_t vblsem_offset; 287 uint32_t vblsem_rval; 288 struct list_head vbl_wait; 289 struct list_head flip; 290 } nvsw; 291 292 struct { 293 bool active; 294 char name[32]; 295 struct drm_info_list info; 296 } debugfs; 297}; 298 299struct nouveau_instmem_engine { 300 void *priv; 301 302 int (*init)(struct drm_device *dev); 303 void (*takedown)(struct drm_device *dev); 304 int (*suspend)(struct drm_device *dev); 305 void (*resume)(struct drm_device *dev); 306 307 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 308 void (*put)(struct nouveau_gpuobj *); 309 int (*map)(struct nouveau_gpuobj *); 310 void (*unmap)(struct nouveau_gpuobj *); 311 312 void (*flush)(struct drm_device *); 313}; 314 315struct nouveau_mc_engine { 316 int (*init)(struct drm_device *dev); 317 void (*takedown)(struct drm_device *dev); 318}; 319 320struct nouveau_timer_engine { 321 int (*init)(struct drm_device *dev); 322 void (*takedown)(struct drm_device *dev); 323 uint64_t (*read)(struct drm_device *dev); 324}; 325 326struct nouveau_fb_engine { 327 int num_tiles; 328 struct drm_mm tag_heap; 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 334 void (*init_tile_region)(struct drm_device *dev, int i, 335 uint32_t addr, uint32_t size, 336 uint32_t pitch, uint32_t flags); 337 void (*set_tile_region)(struct drm_device *dev, int i); 338 void (*free_tile_region)(struct drm_device *dev, int i); 339}; 340 341struct nouveau_fifo_engine { 342 void *priv; 343 int channels; 344 345 struct nouveau_gpuobj *playlist[2]; 346 int cur_playlist; 347 348 int (*init)(struct drm_device *); 349 void (*takedown)(struct drm_device *); 350 351 void (*disable)(struct drm_device *); 352 void (*enable)(struct drm_device *); 353 bool (*reassign)(struct drm_device *, bool enable); 354 bool (*cache_pull)(struct drm_device *dev, bool enable); 355 356 int (*channel_id)(struct drm_device *); 357 358 int (*create_context)(struct nouveau_channel *); 359 void (*destroy_context)(struct nouveau_channel *); 360 int (*load_context)(struct nouveau_channel *); 361 int (*unload_context)(struct drm_device *); 362 void (*tlb_flush)(struct drm_device *dev); 363}; 364 365struct nouveau_pgraph_engine { 366 bool accel_blocked; 367 bool registered; 368 int grctx_size; 369 void *priv; 370 371 /* NV2x/NV3x context table (0x400780) */ 372 struct nouveau_gpuobj *ctx_table; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*fifo_access)(struct drm_device *, bool); 378 379 struct nouveau_channel *(*channel)(struct drm_device *); 380 int (*create_context)(struct nouveau_channel *); 381 void (*destroy_context)(struct nouveau_channel *); 382 int (*load_context)(struct nouveau_channel *); 383 int (*unload_context)(struct drm_device *); 384 void (*tlb_flush)(struct drm_device *dev); 385 386 void (*set_tile_region)(struct drm_device *dev, int i); 387}; 388 389struct nouveau_display_engine { 390 void *priv; 391 int (*early_init)(struct drm_device *); 392 void (*late_takedown)(struct drm_device *); 393 int (*create)(struct drm_device *); 394 int (*init)(struct drm_device *); 395 void (*destroy)(struct drm_device *); 396}; 397 398struct nouveau_gpio_engine { 399 void *priv; 400 401 int (*init)(struct drm_device *); 402 void (*takedown)(struct drm_device *); 403 404 int (*get)(struct drm_device *, enum dcb_gpio_tag); 405 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 406 407 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 408 void (*)(void *, int), void *); 409 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 412}; 413 414struct nouveau_pm_voltage_level { 415 u8 voltage; 416 u8 vid; 417}; 418 419struct nouveau_pm_voltage { 420 bool supported; 421 u8 vid_mask; 422 423 struct nouveau_pm_voltage_level *level; 424 int nr_level; 425}; 426 427#define NOUVEAU_PM_MAX_LEVEL 8 428struct nouveau_pm_level { 429 struct device_attribute dev_attr; 430 char name[32]; 431 int id; 432 433 u32 core; 434 u32 memory; 435 u32 shader; 436 u32 unk05; 437 438 u8 voltage; 439 u8 fanspeed; 440 441 u16 memscript; 442}; 443 444struct nouveau_pm_temp_sensor_constants { 445 u16 offset_constant; 446 s16 offset_mult; 447 u16 offset_div; 448 u16 slope_mult; 449 u16 slope_div; 450}; 451 452struct nouveau_pm_threshold_temp { 453 s16 critical; 454 s16 down_clock; 455 s16 fan_boost; 456}; 457 458struct nouveau_pm_memtiming { 459 u32 reg_100220; 460 u32 reg_100224; 461 u32 reg_100228; 462 u32 reg_10022c; 463 u32 reg_100230; 464 u32 reg_100234; 465 u32 reg_100238; 466 u32 reg_10023c; 467}; 468 469struct nouveau_pm_memtimings { 470 bool supported; 471 struct nouveau_pm_memtiming *timing; 472 int nr_timing; 473}; 474 475struct nouveau_pm_engine { 476 struct nouveau_pm_voltage voltage; 477 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 478 int nr_perflvl; 479 struct nouveau_pm_memtimings memtimings; 480 struct nouveau_pm_temp_sensor_constants sensor_constants; 481 struct nouveau_pm_threshold_temp threshold_temp; 482 483 struct nouveau_pm_level boot; 484 struct nouveau_pm_level *cur; 485 486 struct device *hwmon; 487 struct notifier_block acpi_nb; 488 489 int (*clock_get)(struct drm_device *, u32 id); 490 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 491 u32 id, int khz); 492 void (*clock_set)(struct drm_device *, void *); 493 int (*voltage_get)(struct drm_device *); 494 int (*voltage_set)(struct drm_device *, int voltage); 495 int (*fanspeed_get)(struct drm_device *); 496 int (*fanspeed_set)(struct drm_device *, int fanspeed); 497 int (*temp_get)(struct drm_device *); 498}; 499 500struct nouveau_crypt_engine { 501 bool registered; 502 503 int (*init)(struct drm_device *); 504 void (*takedown)(struct drm_device *); 505 int (*create_context)(struct nouveau_channel *); 506 void (*destroy_context)(struct nouveau_channel *); 507 void (*tlb_flush)(struct drm_device *dev); 508}; 509 510struct nouveau_vram_engine { 511 int (*init)(struct drm_device *); 512 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 513 u32 type, struct nouveau_vram **); 514 void (*put)(struct drm_device *, struct nouveau_vram **); 515 516 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 517}; 518 519struct nouveau_engine { 520 struct nouveau_instmem_engine instmem; 521 struct nouveau_mc_engine mc; 522 struct nouveau_timer_engine timer; 523 struct nouveau_fb_engine fb; 524 struct nouveau_pgraph_engine graph; 525 struct nouveau_fifo_engine fifo; 526 struct nouveau_display_engine display; 527 struct nouveau_gpio_engine gpio; 528 struct nouveau_pm_engine pm; 529 struct nouveau_crypt_engine crypt; 530 struct nouveau_vram_engine vram; 531}; 532 533struct nouveau_pll_vals { 534 union { 535 struct { 536#ifdef __BIG_ENDIAN 537 uint8_t N1, M1, N2, M2; 538#else 539 uint8_t M1, N1, M2, N2; 540#endif 541 }; 542 struct { 543 uint16_t NM1, NM2; 544 } __attribute__((packed)); 545 }; 546 int log2P; 547 548 int refclk; 549}; 550 551enum nv04_fp_display_regs { 552 FP_DISPLAY_END, 553 FP_TOTAL, 554 FP_CRTC, 555 FP_SYNC_START, 556 FP_SYNC_END, 557 FP_VALID_START, 558 FP_VALID_END 559}; 560 561struct nv04_crtc_reg { 562 unsigned char MiscOutReg; 563 uint8_t CRTC[0xa0]; 564 uint8_t CR58[0x10]; 565 uint8_t Sequencer[5]; 566 uint8_t Graphics[9]; 567 uint8_t Attribute[21]; 568 unsigned char DAC[768]; 569 570 /* PCRTC regs */ 571 uint32_t fb_start; 572 uint32_t crtc_cfg; 573 uint32_t cursor_cfg; 574 uint32_t gpio_ext; 575 uint32_t crtc_830; 576 uint32_t crtc_834; 577 uint32_t crtc_850; 578 uint32_t crtc_eng_ctrl; 579 580 /* PRAMDAC regs */ 581 uint32_t nv10_cursync; 582 struct nouveau_pll_vals pllvals; 583 uint32_t ramdac_gen_ctrl; 584 uint32_t ramdac_630; 585 uint32_t ramdac_634; 586 uint32_t tv_setup; 587 uint32_t tv_vtotal; 588 uint32_t tv_vskew; 589 uint32_t tv_vsync_delay; 590 uint32_t tv_htotal; 591 uint32_t tv_hskew; 592 uint32_t tv_hsync_delay; 593 uint32_t tv_hsync_delay2; 594 uint32_t fp_horiz_regs[7]; 595 uint32_t fp_vert_regs[7]; 596 uint32_t dither; 597 uint32_t fp_control; 598 uint32_t dither_regs[6]; 599 uint32_t fp_debug_0; 600 uint32_t fp_debug_1; 601 uint32_t fp_debug_2; 602 uint32_t fp_margin_color; 603 uint32_t ramdac_8c0; 604 uint32_t ramdac_a20; 605 uint32_t ramdac_a24; 606 uint32_t ramdac_a34; 607 uint32_t ctv_regs[38]; 608}; 609 610struct nv04_output_reg { 611 uint32_t output; 612 int head; 613}; 614 615struct nv04_mode_state { 616 struct nv04_crtc_reg crtc_reg[2]; 617 uint32_t pllsel; 618 uint32_t sel_clk; 619}; 620 621enum nouveau_card_type { 622 NV_04 = 0x00, 623 NV_10 = 0x10, 624 NV_20 = 0x20, 625 NV_30 = 0x30, 626 NV_40 = 0x40, 627 NV_50 = 0x50, 628 NV_C0 = 0xc0, 629}; 630 631struct drm_nouveau_private { 632 struct drm_device *dev; 633 634 /* the card type, takes NV_* as values */ 635 enum nouveau_card_type card_type; 636 /* exact chipset, derived from NV_PMC_BOOT_0 */ 637 int chipset; 638 int flags; 639 640 void __iomem *mmio; 641 642 spinlock_t ramin_lock; 643 void __iomem *ramin; 644 u32 ramin_size; 645 u32 ramin_base; 646 bool ramin_available; 647 struct drm_mm ramin_heap; 648 struct list_head gpuobj_list; 649 struct list_head classes; 650 651 struct nouveau_bo *vga_ram; 652 653 /* interrupt handling */ 654 void (*irq_handler[32])(struct drm_device *); 655 bool msi_enabled; 656 657 struct list_head vbl_waiting; 658 659 struct { 660 struct drm_global_reference mem_global_ref; 661 struct ttm_bo_global_ref bo_global_ref; 662 struct ttm_bo_device bdev; 663 atomic_t validate_sequence; 664 } ttm; 665 666 struct { 667 spinlock_t lock; 668 struct drm_mm heap; 669 struct nouveau_bo *bo; 670 } fence; 671 672 struct { 673 spinlock_t lock; 674 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 675 } channels; 676 677 struct nouveau_engine engine; 678 struct nouveau_channel *channel; 679 680 /* For PFIFO and PGRAPH. */ 681 spinlock_t context_switch_lock; 682 683 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 684 struct nouveau_ramht *ramht; 685 struct nouveau_gpuobj *ramfc; 686 struct nouveau_gpuobj *ramro; 687 688 uint32_t ramin_rsvd_vram; 689 690 struct { 691 enum { 692 NOUVEAU_GART_NONE = 0, 693 NOUVEAU_GART_AGP, /* AGP */ 694 NOUVEAU_GART_PDMA, /* paged dma object */ 695 NOUVEAU_GART_HW /* on-chip gart/vm */ 696 } type; 697 uint64_t aper_base; 698 uint64_t aper_size; 699 uint64_t aper_free; 700 701 struct ttm_backend_func *func; 702 703 struct { 704 struct page *page; 705 dma_addr_t addr; 706 } dummy; 707 708 struct nouveau_gpuobj *sg_ctxdma; 709 struct nouveau_vma vma; 710 } gart_info; 711 712 /* nv10-nv40 tiling regions */ 713 struct { 714 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 715 spinlock_t lock; 716 } tile; 717 718 /* VRAM/fb configuration */ 719 uint64_t vram_size; 720 uint64_t vram_sys_base; 721 u32 vram_rblock_size; 722 723 uint64_t fb_phys; 724 uint64_t fb_available_size; 725 uint64_t fb_mappable_pages; 726 uint64_t fb_aper_free; 727 int fb_mtrr; 728 729 /* BAR control (NV50-) */ 730 struct nouveau_vm *bar1_vm; 731 struct nouveau_vm *bar3_vm; 732 733 /* G8x/G9x virtual address space */ 734 struct nouveau_vm *chan_vm; 735 736 struct nvbios vbios; 737 738 struct nv04_mode_state mode_reg; 739 struct nv04_mode_state saved_reg; 740 uint32_t saved_vga_font[4][16384]; 741 uint32_t crtc_owner; 742 uint32_t dac_users[4]; 743 744 struct nouveau_suspend_resume { 745 uint32_t *ramin_copy; 746 } susres; 747 748 struct backlight_device *backlight; 749 750 struct { 751 struct dentry *channel_root; 752 } debugfs; 753 754 struct nouveau_fbdev *nfbdev; 755 struct apertures_struct *apertures; 756 757 bool powered_down; 758}; 759 760static inline struct drm_nouveau_private * 761nouveau_private(struct drm_device *dev) 762{ 763 return dev->dev_private; 764} 765 766static inline struct drm_nouveau_private * 767nouveau_bdev(struct ttm_bo_device *bd) 768{ 769 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 770} 771 772static inline int 773nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 774{ 775 struct nouveau_bo *prev; 776 777 if (!pnvbo) 778 return -EINVAL; 779 prev = *pnvbo; 780 781 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 782 if (prev) { 783 struct ttm_buffer_object *bo = &prev->bo; 784 785 ttm_bo_unref(&bo); 786 } 787 788 return 0; 789} 790 791/* nouveau_drv.c */ 792extern int nouveau_agpmode; 793extern int nouveau_duallink; 794extern int nouveau_uscript_lvds; 795extern int nouveau_uscript_tmds; 796extern int nouveau_vram_pushbuf; 797extern int nouveau_vram_notify; 798extern int nouveau_fbpercrtc; 799extern int nouveau_tv_disable; 800extern char *nouveau_tv_norm; 801extern int nouveau_reg_debug; 802extern char *nouveau_vbios; 803extern int nouveau_ignorelid; 804extern int nouveau_nofbaccel; 805extern int nouveau_noaccel; 806extern int nouveau_force_post; 807extern int nouveau_override_conntype; 808extern char *nouveau_perflvl; 809extern int nouveau_perflvl_wr; 810extern int nouveau_msi; 811 812extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 813extern int nouveau_pci_resume(struct pci_dev *pdev); 814 815/* nouveau_state.c */ 816extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 817extern int nouveau_load(struct drm_device *, unsigned long flags); 818extern int nouveau_firstopen(struct drm_device *); 819extern void nouveau_lastclose(struct drm_device *); 820extern int nouveau_unload(struct drm_device *); 821extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 822 struct drm_file *); 823extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 824 struct drm_file *); 825extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 826 uint32_t reg, uint32_t mask, uint32_t val); 827extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 828 uint32_t reg, uint32_t mask, uint32_t val); 829extern bool nouveau_wait_for_idle(struct drm_device *); 830extern int nouveau_card_init(struct drm_device *); 831 832/* nouveau_mem.c */ 833extern int nouveau_mem_vram_init(struct drm_device *); 834extern void nouveau_mem_vram_fini(struct drm_device *); 835extern int nouveau_mem_gart_init(struct drm_device *); 836extern void nouveau_mem_gart_fini(struct drm_device *); 837extern int nouveau_mem_init_agp(struct drm_device *); 838extern int nouveau_mem_reset_agp(struct drm_device *); 839extern void nouveau_mem_close(struct drm_device *); 840extern int nouveau_mem_detect(struct drm_device *); 841extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 842extern struct nouveau_tile_reg *nv10_mem_set_tiling( 843 struct drm_device *dev, uint32_t addr, uint32_t size, 844 uint32_t pitch, uint32_t flags); 845extern void nv10_mem_put_tile_region(struct drm_device *dev, 846 struct nouveau_tile_reg *tile, 847 struct nouveau_fence *fence); 848extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 849 850/* nouveau_notifier.c */ 851extern int nouveau_notifier_init_channel(struct nouveau_channel *); 852extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 853extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 854 int cout, uint32_t *offset); 855extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 856extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 857 struct drm_file *); 858extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 859 struct drm_file *); 860 861/* nouveau_channel.c */ 862extern struct drm_ioctl_desc nouveau_ioctls[]; 863extern int nouveau_max_ioctl; 864extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 865extern int nouveau_channel_alloc(struct drm_device *dev, 866 struct nouveau_channel **chan, 867 struct drm_file *file_priv, 868 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 869extern struct nouveau_channel * 870nouveau_channel_get_unlocked(struct nouveau_channel *); 871extern struct nouveau_channel * 872nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 873extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 874extern void nouveau_channel_put(struct nouveau_channel **); 875extern void nouveau_channel_ref(struct nouveau_channel *chan, 876 struct nouveau_channel **pchan); 877extern void nouveau_channel_idle(struct nouveau_channel *chan); 878 879/* nouveau_object.c */ 880#define NVOBJ_CLASS(d,c,e) do { \ 881 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 882 if (ret) \ 883 return ret; \ 884} while(0) 885 886#define NVOBJ_MTHD(d,c,m,e) do { \ 887 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 888 if (ret) \ 889 return ret; \ 890} while(0) 891 892extern int nouveau_gpuobj_early_init(struct drm_device *); 893extern int nouveau_gpuobj_init(struct drm_device *); 894extern void nouveau_gpuobj_takedown(struct drm_device *); 895extern int nouveau_gpuobj_suspend(struct drm_device *dev); 896extern void nouveau_gpuobj_resume(struct drm_device *dev); 897extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 898extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 899 int (*exec)(struct nouveau_channel *, 900 u32 class, u32 mthd, u32 data)); 901extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 902extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 903extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 904 uint32_t vram_h, uint32_t tt_h); 905extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 906extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 907 uint32_t size, int align, uint32_t flags, 908 struct nouveau_gpuobj **); 909extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 910 struct nouveau_gpuobj **); 911extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 912 u32 size, u32 flags, 913 struct nouveau_gpuobj **); 914extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 915 uint64_t offset, uint64_t size, int access, 916 int target, struct nouveau_gpuobj **); 917extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 918extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 919 u64 size, int target, int access, u32 type, 920 u32 comp, struct nouveau_gpuobj **pobj); 921extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 922 int class, u64 base, u64 size, int target, 923 int access, u32 type, u32 comp); 924extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 925 struct drm_file *); 926extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 927 struct drm_file *); 928 929/* nouveau_irq.c */ 930extern int nouveau_irq_init(struct drm_device *); 931extern void nouveau_irq_fini(struct drm_device *); 932extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 933extern void nouveau_irq_register(struct drm_device *, int status_bit, 934 void (*)(struct drm_device *)); 935extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 936extern void nouveau_irq_preinstall(struct drm_device *); 937extern int nouveau_irq_postinstall(struct drm_device *); 938extern void nouveau_irq_uninstall(struct drm_device *); 939 940/* nouveau_sgdma.c */ 941extern int nouveau_sgdma_init(struct drm_device *); 942extern void nouveau_sgdma_takedown(struct drm_device *); 943extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 944 uint32_t offset); 945extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 946 947/* nouveau_debugfs.c */ 948#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 949extern int nouveau_debugfs_init(struct drm_minor *); 950extern void nouveau_debugfs_takedown(struct drm_minor *); 951extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 952extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 953#else 954static inline int 955nouveau_debugfs_init(struct drm_minor *minor) 956{ 957 return 0; 958} 959 960static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 961{ 962} 963 964static inline int 965nouveau_debugfs_channel_init(struct nouveau_channel *chan) 966{ 967 return 0; 968} 969 970static inline void 971nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 972{ 973} 974#endif 975 976/* nouveau_dma.c */ 977extern void nouveau_dma_pre_init(struct nouveau_channel *); 978extern int nouveau_dma_init(struct nouveau_channel *); 979extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 980 981/* nouveau_acpi.c */ 982#define ROM_BIOS_PAGE 4096 983#if defined(CONFIG_ACPI) 984void nouveau_register_dsm_handler(void); 985void nouveau_unregister_dsm_handler(void); 986int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 987bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 988int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 989#else 990static inline void nouveau_register_dsm_handler(void) {} 991static inline void nouveau_unregister_dsm_handler(void) {} 992static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 993static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 994static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 995#endif 996 997/* nouveau_backlight.c */ 998#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 999extern int nouveau_backlight_init(struct drm_device *); 1000extern void nouveau_backlight_exit(struct drm_device *); 1001#else 1002static inline int nouveau_backlight_init(struct drm_device *dev) 1003{ 1004 return 0; 1005} 1006 1007static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1008#endif 1009 1010/* nouveau_bios.c */ 1011extern int nouveau_bios_init(struct drm_device *); 1012extern void nouveau_bios_takedown(struct drm_device *dev); 1013extern int nouveau_run_vbios_init(struct drm_device *); 1014extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1015 struct dcb_entry *); 1016extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1017 enum dcb_gpio_tag); 1018extern struct dcb_connector_table_entry * 1019nouveau_bios_connector_entry(struct drm_device *, int index); 1020extern u32 get_pll_register(struct drm_device *, enum pll_types); 1021extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1022 struct pll_lims *); 1023extern int nouveau_bios_run_display_table(struct drm_device *, 1024 struct dcb_entry *, 1025 uint32_t script, int pxclk); 1026extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1027 int *length); 1028extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1029extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1030extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1031 bool *dl, bool *if_is_24bit); 1032extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1033 int head, int pxclk); 1034extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1035 enum LVDS_script, int pxclk); 1036 1037/* nouveau_ttm.c */ 1038int nouveau_ttm_global_init(struct drm_nouveau_private *); 1039void nouveau_ttm_global_release(struct drm_nouveau_private *); 1040int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1041 1042/* nouveau_dp.c */ 1043int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1044 uint8_t *data, int data_nr); 1045bool nouveau_dp_detect(struct drm_encoder *); 1046bool nouveau_dp_link_train(struct drm_encoder *); 1047 1048/* nv04_fb.c */ 1049extern int nv04_fb_init(struct drm_device *); 1050extern void nv04_fb_takedown(struct drm_device *); 1051 1052/* nv10_fb.c */ 1053extern int nv10_fb_init(struct drm_device *); 1054extern void nv10_fb_takedown(struct drm_device *); 1055extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1056 uint32_t addr, uint32_t size, 1057 uint32_t pitch, uint32_t flags); 1058extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1059extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1060 1061/* nv30_fb.c */ 1062extern int nv30_fb_init(struct drm_device *); 1063extern void nv30_fb_takedown(struct drm_device *); 1064extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1065 uint32_t addr, uint32_t size, 1066 uint32_t pitch, uint32_t flags); 1067extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1068 1069/* nv40_fb.c */ 1070extern int nv40_fb_init(struct drm_device *); 1071extern void nv40_fb_takedown(struct drm_device *); 1072extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1073 1074/* nv50_fb.c */ 1075extern int nv50_fb_init(struct drm_device *); 1076extern void nv50_fb_takedown(struct drm_device *); 1077extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1078 1079/* nvc0_fb.c */ 1080extern int nvc0_fb_init(struct drm_device *); 1081extern void nvc0_fb_takedown(struct drm_device *); 1082 1083/* nv04_fifo.c */ 1084extern int nv04_fifo_init(struct drm_device *); 1085extern void nv04_fifo_fini(struct drm_device *); 1086extern void nv04_fifo_disable(struct drm_device *); 1087extern void nv04_fifo_enable(struct drm_device *); 1088extern bool nv04_fifo_reassign(struct drm_device *, bool); 1089extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1090extern int nv04_fifo_channel_id(struct drm_device *); 1091extern int nv04_fifo_create_context(struct nouveau_channel *); 1092extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1093extern int nv04_fifo_load_context(struct nouveau_channel *); 1094extern int nv04_fifo_unload_context(struct drm_device *); 1095extern void nv04_fifo_isr(struct drm_device *); 1096 1097/* nv10_fifo.c */ 1098extern int nv10_fifo_init(struct drm_device *); 1099extern int nv10_fifo_channel_id(struct drm_device *); 1100extern int nv10_fifo_create_context(struct nouveau_channel *); 1101extern int nv10_fifo_load_context(struct nouveau_channel *); 1102extern int nv10_fifo_unload_context(struct drm_device *); 1103 1104/* nv40_fifo.c */ 1105extern int nv40_fifo_init(struct drm_device *); 1106extern int nv40_fifo_create_context(struct nouveau_channel *); 1107extern int nv40_fifo_load_context(struct nouveau_channel *); 1108extern int nv40_fifo_unload_context(struct drm_device *); 1109 1110/* nv50_fifo.c */ 1111extern int nv50_fifo_init(struct drm_device *); 1112extern void nv50_fifo_takedown(struct drm_device *); 1113extern int nv50_fifo_channel_id(struct drm_device *); 1114extern int nv50_fifo_create_context(struct nouveau_channel *); 1115extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1116extern int nv50_fifo_load_context(struct nouveau_channel *); 1117extern int nv50_fifo_unload_context(struct drm_device *); 1118extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1119 1120/* nvc0_fifo.c */ 1121extern int nvc0_fifo_init(struct drm_device *); 1122extern void nvc0_fifo_takedown(struct drm_device *); 1123extern void nvc0_fifo_disable(struct drm_device *); 1124extern void nvc0_fifo_enable(struct drm_device *); 1125extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1126extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1127extern int nvc0_fifo_channel_id(struct drm_device *); 1128extern int nvc0_fifo_create_context(struct nouveau_channel *); 1129extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1130extern int nvc0_fifo_load_context(struct nouveau_channel *); 1131extern int nvc0_fifo_unload_context(struct drm_device *); 1132 1133/* nv04_graph.c */ 1134extern int nv04_graph_init(struct drm_device *); 1135extern void nv04_graph_takedown(struct drm_device *); 1136extern void nv04_graph_fifo_access(struct drm_device *, bool); 1137extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1138extern int nv04_graph_create_context(struct nouveau_channel *); 1139extern void nv04_graph_destroy_context(struct nouveau_channel *); 1140extern int nv04_graph_load_context(struct nouveau_channel *); 1141extern int nv04_graph_unload_context(struct drm_device *); 1142extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1143 u32 class, u32 mthd, u32 data); 1144extern struct nouveau_bitfield nv04_graph_nsource[]; 1145 1146/* nv10_graph.c */ 1147extern int nv10_graph_init(struct drm_device *); 1148extern void nv10_graph_takedown(struct drm_device *); 1149extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1150extern int nv10_graph_create_context(struct nouveau_channel *); 1151extern void nv10_graph_destroy_context(struct nouveau_channel *); 1152extern int nv10_graph_load_context(struct nouveau_channel *); 1153extern int nv10_graph_unload_context(struct drm_device *); 1154extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1155extern struct nouveau_bitfield nv10_graph_intr[]; 1156extern struct nouveau_bitfield nv10_graph_nstatus[]; 1157 1158/* nv20_graph.c */ 1159extern int nv20_graph_create_context(struct nouveau_channel *); 1160extern void nv20_graph_destroy_context(struct nouveau_channel *); 1161extern int nv20_graph_load_context(struct nouveau_channel *); 1162extern int nv20_graph_unload_context(struct drm_device *); 1163extern int nv20_graph_init(struct drm_device *); 1164extern void nv20_graph_takedown(struct drm_device *); 1165extern int nv30_graph_init(struct drm_device *); 1166extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1167 1168/* nv40_graph.c */ 1169extern int nv40_graph_init(struct drm_device *); 1170extern void nv40_graph_takedown(struct drm_device *); 1171extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1172extern int nv40_graph_create_context(struct nouveau_channel *); 1173extern void nv40_graph_destroy_context(struct nouveau_channel *); 1174extern int nv40_graph_load_context(struct nouveau_channel *); 1175extern int nv40_graph_unload_context(struct drm_device *); 1176extern void nv40_grctx_init(struct nouveau_grctx *); 1177extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1178 1179/* nv50_graph.c */ 1180extern int nv50_graph_init(struct drm_device *); 1181extern void nv50_graph_takedown(struct drm_device *); 1182extern void nv50_graph_fifo_access(struct drm_device *, bool); 1183extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1184extern int nv50_graph_create_context(struct nouveau_channel *); 1185extern void nv50_graph_destroy_context(struct nouveau_channel *); 1186extern int nv50_graph_load_context(struct nouveau_channel *); 1187extern int nv50_graph_unload_context(struct drm_device *); 1188extern int nv50_grctx_init(struct nouveau_grctx *); 1189extern void nv50_graph_tlb_flush(struct drm_device *dev); 1190extern void nv86_graph_tlb_flush(struct drm_device *dev); 1191extern struct nouveau_enum nv50_data_error_names[]; 1192 1193/* nvc0_graph.c */ 1194extern int nvc0_graph_init(struct drm_device *); 1195extern void nvc0_graph_takedown(struct drm_device *); 1196extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1197extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1198extern int nvc0_graph_create_context(struct nouveau_channel *); 1199extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1200extern int nvc0_graph_load_context(struct nouveau_channel *); 1201extern int nvc0_graph_unload_context(struct drm_device *); 1202 1203/* nv84_crypt.c */ 1204extern int nv84_crypt_init(struct drm_device *dev); 1205extern void nv84_crypt_fini(struct drm_device *dev); 1206extern int nv84_crypt_create_context(struct nouveau_channel *); 1207extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1208extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1209 1210/* nv04_instmem.c */ 1211extern int nv04_instmem_init(struct drm_device *); 1212extern void nv04_instmem_takedown(struct drm_device *); 1213extern int nv04_instmem_suspend(struct drm_device *); 1214extern void nv04_instmem_resume(struct drm_device *); 1215extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1216extern void nv04_instmem_put(struct nouveau_gpuobj *); 1217extern int nv04_instmem_map(struct nouveau_gpuobj *); 1218extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1219extern void nv04_instmem_flush(struct drm_device *); 1220 1221/* nv50_instmem.c */ 1222extern int nv50_instmem_init(struct drm_device *); 1223extern void nv50_instmem_takedown(struct drm_device *); 1224extern int nv50_instmem_suspend(struct drm_device *); 1225extern void nv50_instmem_resume(struct drm_device *); 1226extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1227extern void nv50_instmem_put(struct nouveau_gpuobj *); 1228extern int nv50_instmem_map(struct nouveau_gpuobj *); 1229extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1230extern void nv50_instmem_flush(struct drm_device *); 1231extern void nv84_instmem_flush(struct drm_device *); 1232 1233/* nvc0_instmem.c */ 1234extern int nvc0_instmem_init(struct drm_device *); 1235extern void nvc0_instmem_takedown(struct drm_device *); 1236extern int nvc0_instmem_suspend(struct drm_device *); 1237extern void nvc0_instmem_resume(struct drm_device *); 1238 1239/* nv04_mc.c */ 1240extern int nv04_mc_init(struct drm_device *); 1241extern void nv04_mc_takedown(struct drm_device *); 1242 1243/* nv40_mc.c */ 1244extern int nv40_mc_init(struct drm_device *); 1245extern void nv40_mc_takedown(struct drm_device *); 1246 1247/* nv50_mc.c */ 1248extern int nv50_mc_init(struct drm_device *); 1249extern void nv50_mc_takedown(struct drm_device *); 1250 1251/* nv04_timer.c */ 1252extern int nv04_timer_init(struct drm_device *); 1253extern uint64_t nv04_timer_read(struct drm_device *); 1254extern void nv04_timer_takedown(struct drm_device *); 1255 1256extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1257 unsigned long arg); 1258 1259/* nv04_dac.c */ 1260extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1261extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1262extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1263extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1264extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1265 1266/* nv04_dfp.c */ 1267extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1268extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1269extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1270 int head, bool dl); 1271extern void nv04_dfp_disable(struct drm_device *dev, int head); 1272extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1273 1274/* nv04_tv.c */ 1275extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1276extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1277 1278/* nv17_tv.c */ 1279extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1280 1281/* nv04_display.c */ 1282extern int nv04_display_early_init(struct drm_device *); 1283extern void nv04_display_late_takedown(struct drm_device *); 1284extern int nv04_display_create(struct drm_device *); 1285extern int nv04_display_init(struct drm_device *); 1286extern void nv04_display_destroy(struct drm_device *); 1287 1288/* nv04_crtc.c */ 1289extern int nv04_crtc_create(struct drm_device *, int index); 1290 1291/* nouveau_bo.c */ 1292extern struct ttm_bo_driver nouveau_bo_driver; 1293extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1294 int size, int align, uint32_t flags, 1295 uint32_t tile_mode, uint32_t tile_flags, 1296 bool no_vm, bool mappable, struct nouveau_bo **); 1297extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1298extern int nouveau_bo_unpin(struct nouveau_bo *); 1299extern int nouveau_bo_map(struct nouveau_bo *); 1300extern void nouveau_bo_unmap(struct nouveau_bo *); 1301extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1302 uint32_t busy); 1303extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1304extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1305extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1306extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1307extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1308extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1309 bool no_wait_reserve, bool no_wait_gpu); 1310 1311/* nouveau_fence.c */ 1312struct nouveau_fence; 1313extern int nouveau_fence_init(struct drm_device *); 1314extern void nouveau_fence_fini(struct drm_device *); 1315extern int nouveau_fence_channel_init(struct nouveau_channel *); 1316extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1317extern void nouveau_fence_update(struct nouveau_channel *); 1318extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1319 bool emit); 1320extern int nouveau_fence_emit(struct nouveau_fence *); 1321extern void nouveau_fence_work(struct nouveau_fence *fence, 1322 void (*work)(void *priv, bool signalled), 1323 void *priv); 1324struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1325 1326extern bool __nouveau_fence_signalled(void *obj, void *arg); 1327extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1328extern int __nouveau_fence_flush(void *obj, void *arg); 1329extern void __nouveau_fence_unref(void **obj); 1330extern void *__nouveau_fence_ref(void *obj); 1331 1332static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1333{ 1334 return __nouveau_fence_signalled(obj, NULL); 1335} 1336static inline int 1337nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1338{ 1339 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1340} 1341extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1342static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1343{ 1344 return __nouveau_fence_flush(obj, NULL); 1345} 1346static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1347{ 1348 __nouveau_fence_unref((void **)obj); 1349} 1350static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1351{ 1352 return __nouveau_fence_ref(obj); 1353} 1354 1355/* nouveau_gem.c */ 1356extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1357 int size, int align, uint32_t flags, 1358 uint32_t tile_mode, uint32_t tile_flags, 1359 bool no_vm, bool mappable, struct nouveau_bo **); 1360extern int nouveau_gem_object_new(struct drm_gem_object *); 1361extern void nouveau_gem_object_del(struct drm_gem_object *); 1362extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1363 struct drm_file *); 1364extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1365 struct drm_file *); 1366extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1367 struct drm_file *); 1368extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1369 struct drm_file *); 1370extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1371 struct drm_file *); 1372 1373/* nouveau_display.c */ 1374int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1375void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1376int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1377 struct drm_pending_vblank_event *event); 1378int nouveau_finish_page_flip(struct nouveau_channel *, 1379 struct nouveau_page_flip_state *); 1380 1381/* nv10_gpio.c */ 1382int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1383int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1384 1385/* nv50_gpio.c */ 1386int nv50_gpio_init(struct drm_device *dev); 1387void nv50_gpio_fini(struct drm_device *dev); 1388int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1389int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1390int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1391 void (*)(void *, int), void *); 1392void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1393 void (*)(void *, int), void *); 1394bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1395 1396/* nv50_calc. */ 1397int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1398 int *N1, int *M1, int *N2, int *M2, int *P); 1399int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1400 int clk, int *N, int *fN, int *M, int *P); 1401 1402#ifndef ioread32_native 1403#ifdef __BIG_ENDIAN 1404#define ioread16_native ioread16be 1405#define iowrite16_native iowrite16be 1406#define ioread32_native ioread32be 1407#define iowrite32_native iowrite32be 1408#else /* def __BIG_ENDIAN */ 1409#define ioread16_native ioread16 1410#define iowrite16_native iowrite16 1411#define ioread32_native ioread32 1412#define iowrite32_native iowrite32 1413#endif /* def __BIG_ENDIAN else */ 1414#endif /* !ioread32_native */ 1415 1416/* channel control reg access */ 1417static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1418{ 1419 return ioread32_native(chan->user + reg); 1420} 1421 1422static inline void nvchan_wr32(struct nouveau_channel *chan, 1423 unsigned reg, u32 val) 1424{ 1425 iowrite32_native(val, chan->user + reg); 1426} 1427 1428/* register access */ 1429static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1430{ 1431 struct drm_nouveau_private *dev_priv = dev->dev_private; 1432 return ioread32_native(dev_priv->mmio + reg); 1433} 1434 1435static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1436{ 1437 struct drm_nouveau_private *dev_priv = dev->dev_private; 1438 iowrite32_native(val, dev_priv->mmio + reg); 1439} 1440 1441static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1442{ 1443 u32 tmp = nv_rd32(dev, reg); 1444 nv_wr32(dev, reg, (tmp & ~mask) | val); 1445 return tmp; 1446} 1447 1448static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1449{ 1450 struct drm_nouveau_private *dev_priv = dev->dev_private; 1451 return ioread8(dev_priv->mmio + reg); 1452} 1453 1454static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1455{ 1456 struct drm_nouveau_private *dev_priv = dev->dev_private; 1457 iowrite8(val, dev_priv->mmio + reg); 1458} 1459 1460#define nv_wait(dev, reg, mask, val) \ 1461 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1462#define nv_wait_ne(dev, reg, mask, val) \ 1463 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1464 1465/* PRAMIN access */ 1466static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1467{ 1468 struct drm_nouveau_private *dev_priv = dev->dev_private; 1469 return ioread32_native(dev_priv->ramin + offset); 1470} 1471 1472static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1473{ 1474 struct drm_nouveau_private *dev_priv = dev->dev_private; 1475 iowrite32_native(val, dev_priv->ramin + offset); 1476} 1477 1478/* object access */ 1479extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1480extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1481 1482/* 1483 * Logging 1484 * Argument d is (struct drm_device *). 1485 */ 1486#define NV_PRINTK(level, d, fmt, arg...) \ 1487 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1488 pci_name(d->pdev), ##arg) 1489#ifndef NV_DEBUG_NOTRACE 1490#define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) { \ 1492 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1493 __LINE__, ##arg); \ 1494 } \ 1495} while (0) 1496#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1497 if (drm_debug & DRM_UT_KMS) { \ 1498 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1499 __LINE__, ##arg); \ 1500 } \ 1501} while (0) 1502#else 1503#define NV_DEBUG(d, fmt, arg...) do { \ 1504 if (drm_debug & DRM_UT_DRIVER) \ 1505 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1506} while (0) 1507#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1508 if (drm_debug & DRM_UT_KMS) \ 1509 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1510} while (0) 1511#endif 1512#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1513#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1514#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1515#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1516#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1517 1518/* nouveau_reg_debug bitmask */ 1519enum { 1520 NOUVEAU_REG_DEBUG_MC = 0x1, 1521 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1522 NOUVEAU_REG_DEBUG_FB = 0x4, 1523 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1524 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1525 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1526 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1527 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1528 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1529 NOUVEAU_REG_DEBUG_EVO = 0x200, 1530}; 1531 1532#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1533 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1534 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1535} while (0) 1536 1537static inline bool 1538nv_two_heads(struct drm_device *dev) 1539{ 1540 struct drm_nouveau_private *dev_priv = dev->dev_private; 1541 const int impl = dev->pci_device & 0x0ff0; 1542 1543 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1544 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1545 return true; 1546 1547 return false; 1548} 1549 1550static inline bool 1551nv_gf4_disp_arch(struct drm_device *dev) 1552{ 1553 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1554} 1555 1556static inline bool 1557nv_two_reg_pll(struct drm_device *dev) 1558{ 1559 struct drm_nouveau_private *dev_priv = dev->dev_private; 1560 const int impl = dev->pci_device & 0x0ff0; 1561 1562 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1563 return true; 1564 return false; 1565} 1566 1567static inline bool 1568nv_match_device(struct drm_device *dev, unsigned device, 1569 unsigned sub_vendor, unsigned sub_device) 1570{ 1571 return dev->pdev->device == device && 1572 dev->pdev->subsystem_vendor == sub_vendor && 1573 dev->pdev->subsystem_device == sub_device; 1574} 1575 1576/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1577 * helpful to determine a number of other hardware features 1578 */ 1579static inline int 1580nv44_graph_class(struct drm_device *dev) 1581{ 1582 struct drm_nouveau_private *dev_priv = dev->dev_private; 1583 1584 if ((dev_priv->chipset & 0xf0) == 0x60) 1585 return 1; 1586 1587 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1588} 1589 1590/* memory type/access flags, do not match hardware values */ 1591#define NV_MEM_ACCESS_RO 1 1592#define NV_MEM_ACCESS_WO 2 1593#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1594#define NV_MEM_ACCESS_SYS 4 1595#define NV_MEM_ACCESS_VM 8 1596 1597#define NV_MEM_TARGET_VRAM 0 1598#define NV_MEM_TARGET_PCI 1 1599#define NV_MEM_TARGET_PCI_NOSNOOP 2 1600#define NV_MEM_TARGET_VM 3 1601#define NV_MEM_TARGET_GART 4 1602 1603#define NV_MEM_TYPE_VM 0x7f 1604#define NV_MEM_COMP_VM 0x03 1605 1606/* NV_SW object class */ 1607#define NV_SW 0x0000506e 1608#define NV_SW_DMA_SEMAPHORE 0x00000060 1609#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1610#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1611#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1612#define NV_SW_YIELD 0x00000080 1613#define NV_SW_DMA_VBLSEM 0x0000018c 1614#define NV_SW_VBLSEM_OFFSET 0x00000400 1615#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1616#define NV_SW_VBLSEM_RELEASE 0x00000408 1617#define NV_SW_PAGE_FLIP 0x00000500 1618 1619#endif /* __NOUVEAU_DRV_H__ */ 1620