nouveau_drv.h revision f62b27db6b5479efe376b408802a081a834ef50e
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 void (*destroy)(struct drm_device *); 400 int (*init)(struct drm_device *); 401 void (*fini)(struct drm_device *); 402 403 struct drm_property *dithering_mode; 404 struct drm_property *dithering_depth; 405 struct drm_property *underscan_property; 406 struct drm_property *underscan_hborder_property; 407 struct drm_property *underscan_vborder_property; 408}; 409 410struct nouveau_gpio_engine { 411 void *priv; 412 413 int (*init)(struct drm_device *); 414 void (*takedown)(struct drm_device *); 415 416 int (*get)(struct drm_device *, enum dcb_gpio_tag); 417 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 418 419 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 420 void (*)(void *, int), void *); 421 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 422 void (*)(void *, int), void *); 423 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 424}; 425 426struct nouveau_pm_voltage_level { 427 u32 voltage; /* microvolts */ 428 u8 vid; 429}; 430 431struct nouveau_pm_voltage { 432 bool supported; 433 u8 version; 434 u8 vid_mask; 435 436 struct nouveau_pm_voltage_level *level; 437 int nr_level; 438}; 439 440struct nouveau_pm_memtiming { 441 int id; 442 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 443 u32 reg_1; 444 u32 reg_2; 445 u32 reg_3; 446 u32 reg_4; 447 u32 reg_5; 448 u32 reg_6; 449 u32 reg_7; 450 u32 reg_8; 451 /* To be written to 0x1002c0 */ 452 u8 CL; 453 u8 WR; 454}; 455 456struct nouveau_pm_tbl_header{ 457 u8 version; 458 u8 header_len; 459 u8 entry_cnt; 460 u8 entry_len; 461}; 462 463struct nouveau_pm_tbl_entry{ 464 u8 tWR; 465 u8 tUNK_1; 466 u8 tCL; 467 u8 tRP; /* Byte 3 */ 468 u8 empty_4; 469 u8 tRAS; /* Byte 5 */ 470 u8 empty_6; 471 u8 tRFC; /* Byte 7 */ 472 u8 empty_8; 473 u8 tRC; /* Byte 9 */ 474 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 475 u8 empty_15,empty_16,empty_17; 476 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 477}; 478 479/* nouveau_mem.c */ 480void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 481 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 482 struct nouveau_pm_memtiming *timing); 483 484#define NOUVEAU_PM_MAX_LEVEL 8 485struct nouveau_pm_level { 486 struct device_attribute dev_attr; 487 char name[32]; 488 int id; 489 490 u32 core; 491 u32 memory; 492 u32 shader; 493 u32 rop; 494 u32 copy; 495 u32 daemon; 496 u32 vdec; 497 u32 dom6; 498 u32 unka0; /* nva3:nvc0 */ 499 u32 hub01; /* nvc0- */ 500 u32 hub06; /* nvc0- */ 501 u32 hub07; /* nvc0- */ 502 503 u32 volt_min; /* microvolts */ 504 u32 volt_max; 505 u8 fanspeed; 506 507 u16 memscript; 508 struct nouveau_pm_memtiming *timing; 509}; 510 511struct nouveau_pm_temp_sensor_constants { 512 u16 offset_constant; 513 s16 offset_mult; 514 s16 offset_div; 515 s16 slope_mult; 516 s16 slope_div; 517}; 518 519struct nouveau_pm_threshold_temp { 520 s16 critical; 521 s16 down_clock; 522 s16 fan_boost; 523}; 524 525struct nouveau_pm_memtimings { 526 bool supported; 527 struct nouveau_pm_memtiming *timing; 528 int nr_timing; 529}; 530 531struct nouveau_pm_fan { 532 u32 min_duty; 533 u32 max_duty; 534 u32 pwm_freq; 535}; 536 537struct nouveau_pm_engine { 538 struct nouveau_pm_voltage voltage; 539 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 540 int nr_perflvl; 541 struct nouveau_pm_memtimings memtimings; 542 struct nouveau_pm_temp_sensor_constants sensor_constants; 543 struct nouveau_pm_threshold_temp threshold_temp; 544 struct nouveau_pm_fan fan; 545 u32 pwm_divisor; 546 547 struct nouveau_pm_level boot; 548 struct nouveau_pm_level *cur; 549 550 struct device *hwmon; 551 struct notifier_block acpi_nb; 552 553 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 554 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 555 int (*clocks_set)(struct drm_device *, void *); 556 557 int (*voltage_get)(struct drm_device *); 558 int (*voltage_set)(struct drm_device *, int voltage); 559 int (*pwm_get)(struct drm_device *, struct dcb_gpio_entry*, u32*, u32*); 560 int (*pwm_set)(struct drm_device *, struct dcb_gpio_entry*, u32, u32); 561 int (*temp_get)(struct drm_device *); 562}; 563 564struct nouveau_vram_engine { 565 struct nouveau_mm mm; 566 567 int (*init)(struct drm_device *); 568 void (*takedown)(struct drm_device *dev); 569 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 570 u32 type, struct nouveau_mem **); 571 void (*put)(struct drm_device *, struct nouveau_mem **); 572 573 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 574}; 575 576struct nouveau_engine { 577 struct nouveau_instmem_engine instmem; 578 struct nouveau_mc_engine mc; 579 struct nouveau_timer_engine timer; 580 struct nouveau_fb_engine fb; 581 struct nouveau_fifo_engine fifo; 582 struct nouveau_display_engine display; 583 struct nouveau_gpio_engine gpio; 584 struct nouveau_pm_engine pm; 585 struct nouveau_vram_engine vram; 586}; 587 588struct nouveau_pll_vals { 589 union { 590 struct { 591#ifdef __BIG_ENDIAN 592 uint8_t N1, M1, N2, M2; 593#else 594 uint8_t M1, N1, M2, N2; 595#endif 596 }; 597 struct { 598 uint16_t NM1, NM2; 599 } __attribute__((packed)); 600 }; 601 int log2P; 602 603 int refclk; 604}; 605 606enum nv04_fp_display_regs { 607 FP_DISPLAY_END, 608 FP_TOTAL, 609 FP_CRTC, 610 FP_SYNC_START, 611 FP_SYNC_END, 612 FP_VALID_START, 613 FP_VALID_END 614}; 615 616struct nv04_crtc_reg { 617 unsigned char MiscOutReg; 618 uint8_t CRTC[0xa0]; 619 uint8_t CR58[0x10]; 620 uint8_t Sequencer[5]; 621 uint8_t Graphics[9]; 622 uint8_t Attribute[21]; 623 unsigned char DAC[768]; 624 625 /* PCRTC regs */ 626 uint32_t fb_start; 627 uint32_t crtc_cfg; 628 uint32_t cursor_cfg; 629 uint32_t gpio_ext; 630 uint32_t crtc_830; 631 uint32_t crtc_834; 632 uint32_t crtc_850; 633 uint32_t crtc_eng_ctrl; 634 635 /* PRAMDAC regs */ 636 uint32_t nv10_cursync; 637 struct nouveau_pll_vals pllvals; 638 uint32_t ramdac_gen_ctrl; 639 uint32_t ramdac_630; 640 uint32_t ramdac_634; 641 uint32_t tv_setup; 642 uint32_t tv_vtotal; 643 uint32_t tv_vskew; 644 uint32_t tv_vsync_delay; 645 uint32_t tv_htotal; 646 uint32_t tv_hskew; 647 uint32_t tv_hsync_delay; 648 uint32_t tv_hsync_delay2; 649 uint32_t fp_horiz_regs[7]; 650 uint32_t fp_vert_regs[7]; 651 uint32_t dither; 652 uint32_t fp_control; 653 uint32_t dither_regs[6]; 654 uint32_t fp_debug_0; 655 uint32_t fp_debug_1; 656 uint32_t fp_debug_2; 657 uint32_t fp_margin_color; 658 uint32_t ramdac_8c0; 659 uint32_t ramdac_a20; 660 uint32_t ramdac_a24; 661 uint32_t ramdac_a34; 662 uint32_t ctv_regs[38]; 663}; 664 665struct nv04_output_reg { 666 uint32_t output; 667 int head; 668}; 669 670struct nv04_mode_state { 671 struct nv04_crtc_reg crtc_reg[2]; 672 uint32_t pllsel; 673 uint32_t sel_clk; 674}; 675 676enum nouveau_card_type { 677 NV_04 = 0x00, 678 NV_10 = 0x10, 679 NV_20 = 0x20, 680 NV_30 = 0x30, 681 NV_40 = 0x40, 682 NV_50 = 0x50, 683 NV_C0 = 0xc0, 684 NV_D0 = 0xd0 685}; 686 687struct drm_nouveau_private { 688 struct drm_device *dev; 689 bool noaccel; 690 691 /* the card type, takes NV_* as values */ 692 enum nouveau_card_type card_type; 693 /* exact chipset, derived from NV_PMC_BOOT_0 */ 694 int chipset; 695 int flags; 696 u32 crystal; 697 698 void __iomem *mmio; 699 700 spinlock_t ramin_lock; 701 void __iomem *ramin; 702 u32 ramin_size; 703 u32 ramin_base; 704 bool ramin_available; 705 struct drm_mm ramin_heap; 706 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 707 struct list_head gpuobj_list; 708 struct list_head classes; 709 710 struct nouveau_bo *vga_ram; 711 712 /* interrupt handling */ 713 void (*irq_handler[32])(struct drm_device *); 714 bool msi_enabled; 715 716 struct list_head vbl_waiting; 717 718 struct { 719 struct drm_global_reference mem_global_ref; 720 struct ttm_bo_global_ref bo_global_ref; 721 struct ttm_bo_device bdev; 722 atomic_t validate_sequence; 723 } ttm; 724 725 struct { 726 spinlock_t lock; 727 struct drm_mm heap; 728 struct nouveau_bo *bo; 729 } fence; 730 731 struct { 732 spinlock_t lock; 733 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 734 } channels; 735 736 struct nouveau_engine engine; 737 struct nouveau_channel *channel; 738 739 /* For PFIFO and PGRAPH. */ 740 spinlock_t context_switch_lock; 741 742 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 743 spinlock_t vm_lock; 744 745 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 746 struct nouveau_ramht *ramht; 747 struct nouveau_gpuobj *ramfc; 748 struct nouveau_gpuobj *ramro; 749 750 uint32_t ramin_rsvd_vram; 751 752 struct { 753 enum { 754 NOUVEAU_GART_NONE = 0, 755 NOUVEAU_GART_AGP, /* AGP */ 756 NOUVEAU_GART_PDMA, /* paged dma object */ 757 NOUVEAU_GART_HW /* on-chip gart/vm */ 758 } type; 759 uint64_t aper_base; 760 uint64_t aper_size; 761 uint64_t aper_free; 762 763 struct ttm_backend_func *func; 764 765 struct { 766 struct page *page; 767 dma_addr_t addr; 768 } dummy; 769 770 struct nouveau_gpuobj *sg_ctxdma; 771 } gart_info; 772 773 /* nv10-nv40 tiling regions */ 774 struct { 775 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 776 spinlock_t lock; 777 } tile; 778 779 /* VRAM/fb configuration */ 780 uint64_t vram_size; 781 uint64_t vram_sys_base; 782 783 uint64_t fb_available_size; 784 uint64_t fb_mappable_pages; 785 uint64_t fb_aper_free; 786 int fb_mtrr; 787 788 /* BAR control (NV50-) */ 789 struct nouveau_vm *bar1_vm; 790 struct nouveau_vm *bar3_vm; 791 792 /* G8x/G9x virtual address space */ 793 struct nouveau_vm *chan_vm; 794 795 struct nvbios vbios; 796 797 struct nv04_mode_state mode_reg; 798 struct nv04_mode_state saved_reg; 799 uint32_t saved_vga_font[4][16384]; 800 uint32_t crtc_owner; 801 uint32_t dac_users[4]; 802 803 struct backlight_device *backlight; 804 805 struct { 806 struct dentry *channel_root; 807 } debugfs; 808 809 struct nouveau_fbdev *nfbdev; 810 struct apertures_struct *apertures; 811}; 812 813static inline struct drm_nouveau_private * 814nouveau_private(struct drm_device *dev) 815{ 816 return dev->dev_private; 817} 818 819static inline struct drm_nouveau_private * 820nouveau_bdev(struct ttm_bo_device *bd) 821{ 822 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 823} 824 825static inline int 826nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 827{ 828 struct nouveau_bo *prev; 829 830 if (!pnvbo) 831 return -EINVAL; 832 prev = *pnvbo; 833 834 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 835 if (prev) { 836 struct ttm_buffer_object *bo = &prev->bo; 837 838 ttm_bo_unref(&bo); 839 } 840 841 return 0; 842} 843 844/* nouveau_drv.c */ 845extern int nouveau_modeset; 846extern int nouveau_agpmode; 847extern int nouveau_duallink; 848extern int nouveau_uscript_lvds; 849extern int nouveau_uscript_tmds; 850extern int nouveau_vram_pushbuf; 851extern int nouveau_vram_notify; 852extern int nouveau_fbpercrtc; 853extern int nouveau_tv_disable; 854extern char *nouveau_tv_norm; 855extern int nouveau_reg_debug; 856extern char *nouveau_vbios; 857extern int nouveau_ignorelid; 858extern int nouveau_nofbaccel; 859extern int nouveau_noaccel; 860extern int nouveau_force_post; 861extern int nouveau_override_conntype; 862extern char *nouveau_perflvl; 863extern int nouveau_perflvl_wr; 864extern int nouveau_msi; 865extern int nouveau_ctxfw; 866 867extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 868extern int nouveau_pci_resume(struct pci_dev *pdev); 869 870/* nouveau_state.c */ 871extern int nouveau_open(struct drm_device *, struct drm_file *); 872extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 873extern void nouveau_postclose(struct drm_device *, struct drm_file *); 874extern int nouveau_load(struct drm_device *, unsigned long flags); 875extern int nouveau_firstopen(struct drm_device *); 876extern void nouveau_lastclose(struct drm_device *); 877extern int nouveau_unload(struct drm_device *); 878extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 879 struct drm_file *); 880extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 881 struct drm_file *); 882extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 883 uint32_t reg, uint32_t mask, uint32_t val); 884extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 885 uint32_t reg, uint32_t mask, uint32_t val); 886extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 887 bool (*cond)(void *), void *); 888extern bool nouveau_wait_for_idle(struct drm_device *); 889extern int nouveau_card_init(struct drm_device *); 890 891/* nouveau_mem.c */ 892extern int nouveau_mem_vram_init(struct drm_device *); 893extern void nouveau_mem_vram_fini(struct drm_device *); 894extern int nouveau_mem_gart_init(struct drm_device *); 895extern void nouveau_mem_gart_fini(struct drm_device *); 896extern int nouveau_mem_init_agp(struct drm_device *); 897extern int nouveau_mem_reset_agp(struct drm_device *); 898extern void nouveau_mem_close(struct drm_device *); 899extern int nouveau_mem_detect(struct drm_device *); 900extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 901extern struct nouveau_tile_reg *nv10_mem_set_tiling( 902 struct drm_device *dev, uint32_t addr, uint32_t size, 903 uint32_t pitch, uint32_t flags); 904extern void nv10_mem_put_tile_region(struct drm_device *dev, 905 struct nouveau_tile_reg *tile, 906 struct nouveau_fence *fence); 907extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 908extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 909 910/* nouveau_notifier.c */ 911extern int nouveau_notifier_init_channel(struct nouveau_channel *); 912extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 913extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 914 int cout, uint32_t start, uint32_t end, 915 uint32_t *offset); 916extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 917extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 918 struct drm_file *); 919extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 920 struct drm_file *); 921 922/* nouveau_channel.c */ 923extern struct drm_ioctl_desc nouveau_ioctls[]; 924extern int nouveau_max_ioctl; 925extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 926extern int nouveau_channel_alloc(struct drm_device *dev, 927 struct nouveau_channel **chan, 928 struct drm_file *file_priv, 929 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 930extern struct nouveau_channel * 931nouveau_channel_get_unlocked(struct nouveau_channel *); 932extern struct nouveau_channel * 933nouveau_channel_get(struct drm_file *, int id); 934extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 935extern void nouveau_channel_put(struct nouveau_channel **); 936extern void nouveau_channel_ref(struct nouveau_channel *chan, 937 struct nouveau_channel **pchan); 938extern void nouveau_channel_idle(struct nouveau_channel *chan); 939 940/* nouveau_object.c */ 941#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 942 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 943 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 944} while (0) 945 946#define NVOBJ_ENGINE_DEL(d, e) do { \ 947 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 948 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 949} while (0) 950 951#define NVOBJ_CLASS(d, c, e) do { \ 952 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 953 if (ret) \ 954 return ret; \ 955} while (0) 956 957#define NVOBJ_MTHD(d, c, m, e) do { \ 958 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 959 if (ret) \ 960 return ret; \ 961} while (0) 962 963extern int nouveau_gpuobj_early_init(struct drm_device *); 964extern int nouveau_gpuobj_init(struct drm_device *); 965extern void nouveau_gpuobj_takedown(struct drm_device *); 966extern int nouveau_gpuobj_suspend(struct drm_device *dev); 967extern void nouveau_gpuobj_resume(struct drm_device *dev); 968extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 969extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 970 int (*exec)(struct nouveau_channel *, 971 u32 class, u32 mthd, u32 data)); 972extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 973extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 974extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 975 uint32_t vram_h, uint32_t tt_h); 976extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 977extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 978 uint32_t size, int align, uint32_t flags, 979 struct nouveau_gpuobj **); 980extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 981 struct nouveau_gpuobj **); 982extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 983 u32 size, u32 flags, 984 struct nouveau_gpuobj **); 985extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 986 uint64_t offset, uint64_t size, int access, 987 int target, struct nouveau_gpuobj **); 988extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 989extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 990 u64 size, int target, int access, u32 type, 991 u32 comp, struct nouveau_gpuobj **pobj); 992extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 993 int class, u64 base, u64 size, int target, 994 int access, u32 type, u32 comp); 995extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 996 struct drm_file *); 997extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 998 struct drm_file *); 999 1000/* nouveau_irq.c */ 1001extern int nouveau_irq_init(struct drm_device *); 1002extern void nouveau_irq_fini(struct drm_device *); 1003extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1004extern void nouveau_irq_register(struct drm_device *, int status_bit, 1005 void (*)(struct drm_device *)); 1006extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1007extern void nouveau_irq_preinstall(struct drm_device *); 1008extern int nouveau_irq_postinstall(struct drm_device *); 1009extern void nouveau_irq_uninstall(struct drm_device *); 1010 1011/* nouveau_sgdma.c */ 1012extern int nouveau_sgdma_init(struct drm_device *); 1013extern void nouveau_sgdma_takedown(struct drm_device *); 1014extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1015 uint32_t offset); 1016extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1017 unsigned long size, 1018 uint32_t page_flags, 1019 struct page *dummy_read_page); 1020 1021/* nouveau_debugfs.c */ 1022#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1023extern int nouveau_debugfs_init(struct drm_minor *); 1024extern void nouveau_debugfs_takedown(struct drm_minor *); 1025extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1026extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1027#else 1028static inline int 1029nouveau_debugfs_init(struct drm_minor *minor) 1030{ 1031 return 0; 1032} 1033 1034static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1035{ 1036} 1037 1038static inline int 1039nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1040{ 1041 return 0; 1042} 1043 1044static inline void 1045nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1046{ 1047} 1048#endif 1049 1050/* nouveau_dma.c */ 1051extern void nouveau_dma_pre_init(struct nouveau_channel *); 1052extern int nouveau_dma_init(struct nouveau_channel *); 1053extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1054 1055/* nouveau_acpi.c */ 1056#define ROM_BIOS_PAGE 4096 1057#if defined(CONFIG_ACPI) 1058void nouveau_register_dsm_handler(void); 1059void nouveau_unregister_dsm_handler(void); 1060int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1061bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1062int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1063#else 1064static inline void nouveau_register_dsm_handler(void) {} 1065static inline void nouveau_unregister_dsm_handler(void) {} 1066static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1067static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1068static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1069#endif 1070 1071/* nouveau_backlight.c */ 1072#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1073extern int nouveau_backlight_init(struct drm_device *); 1074extern void nouveau_backlight_exit(struct drm_device *); 1075#else 1076static inline int nouveau_backlight_init(struct drm_device *dev) 1077{ 1078 return 0; 1079} 1080 1081static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1082#endif 1083 1084/* nouveau_bios.c */ 1085extern int nouveau_bios_init(struct drm_device *); 1086extern void nouveau_bios_takedown(struct drm_device *dev); 1087extern int nouveau_run_vbios_init(struct drm_device *); 1088extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1089 struct dcb_entry *, int crtc); 1090extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1091extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1092 enum dcb_gpio_tag); 1093extern struct dcb_connector_table_entry * 1094nouveau_bios_connector_entry(struct drm_device *, int index); 1095extern u32 get_pll_register(struct drm_device *, enum pll_types); 1096extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1097 struct pll_lims *); 1098extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1099 struct dcb_entry *, int crtc); 1100extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1101extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1102extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1103 bool *dl, bool *if_is_24bit); 1104extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1105 int head, int pxclk); 1106extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1107 enum LVDS_script, int pxclk); 1108bool bios_encoder_match(struct dcb_entry *, u32 hash); 1109 1110/* nouveau_ttm.c */ 1111int nouveau_ttm_global_init(struct drm_nouveau_private *); 1112void nouveau_ttm_global_release(struct drm_nouveau_private *); 1113int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1114 1115/* nouveau_hdmi.c */ 1116void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1117 1118/* nouveau_dp.c */ 1119int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1120 uint8_t *data, int data_nr); 1121bool nouveau_dp_detect(struct drm_encoder *); 1122bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1123void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1124u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1125 1126/* nv04_fb.c */ 1127extern int nv04_fb_init(struct drm_device *); 1128extern void nv04_fb_takedown(struct drm_device *); 1129 1130/* nv10_fb.c */ 1131extern int nv10_fb_init(struct drm_device *); 1132extern void nv10_fb_takedown(struct drm_device *); 1133extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1134 uint32_t addr, uint32_t size, 1135 uint32_t pitch, uint32_t flags); 1136extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1137extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1138 1139/* nv30_fb.c */ 1140extern int nv30_fb_init(struct drm_device *); 1141extern void nv30_fb_takedown(struct drm_device *); 1142extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1143 uint32_t addr, uint32_t size, 1144 uint32_t pitch, uint32_t flags); 1145extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1146 1147/* nv40_fb.c */ 1148extern int nv40_fb_init(struct drm_device *); 1149extern void nv40_fb_takedown(struct drm_device *); 1150extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1151 1152/* nv50_fb.c */ 1153extern int nv50_fb_init(struct drm_device *); 1154extern void nv50_fb_takedown(struct drm_device *); 1155extern void nv50_fb_vm_trap(struct drm_device *, int display); 1156 1157/* nvc0_fb.c */ 1158extern int nvc0_fb_init(struct drm_device *); 1159extern void nvc0_fb_takedown(struct drm_device *); 1160 1161/* nv04_fifo.c */ 1162extern int nv04_fifo_init(struct drm_device *); 1163extern void nv04_fifo_fini(struct drm_device *); 1164extern void nv04_fifo_disable(struct drm_device *); 1165extern void nv04_fifo_enable(struct drm_device *); 1166extern bool nv04_fifo_reassign(struct drm_device *, bool); 1167extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1168extern int nv04_fifo_channel_id(struct drm_device *); 1169extern int nv04_fifo_create_context(struct nouveau_channel *); 1170extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1171extern int nv04_fifo_load_context(struct nouveau_channel *); 1172extern int nv04_fifo_unload_context(struct drm_device *); 1173extern void nv04_fifo_isr(struct drm_device *); 1174 1175/* nv10_fifo.c */ 1176extern int nv10_fifo_init(struct drm_device *); 1177extern int nv10_fifo_channel_id(struct drm_device *); 1178extern int nv10_fifo_create_context(struct nouveau_channel *); 1179extern int nv10_fifo_load_context(struct nouveau_channel *); 1180extern int nv10_fifo_unload_context(struct drm_device *); 1181 1182/* nv40_fifo.c */ 1183extern int nv40_fifo_init(struct drm_device *); 1184extern int nv40_fifo_create_context(struct nouveau_channel *); 1185extern int nv40_fifo_load_context(struct nouveau_channel *); 1186extern int nv40_fifo_unload_context(struct drm_device *); 1187 1188/* nv50_fifo.c */ 1189extern int nv50_fifo_init(struct drm_device *); 1190extern void nv50_fifo_takedown(struct drm_device *); 1191extern int nv50_fifo_channel_id(struct drm_device *); 1192extern int nv50_fifo_create_context(struct nouveau_channel *); 1193extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1194extern int nv50_fifo_load_context(struct nouveau_channel *); 1195extern int nv50_fifo_unload_context(struct drm_device *); 1196extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1197 1198/* nvc0_fifo.c */ 1199extern int nvc0_fifo_init(struct drm_device *); 1200extern void nvc0_fifo_takedown(struct drm_device *); 1201extern void nvc0_fifo_disable(struct drm_device *); 1202extern void nvc0_fifo_enable(struct drm_device *); 1203extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1204extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1205extern int nvc0_fifo_channel_id(struct drm_device *); 1206extern int nvc0_fifo_create_context(struct nouveau_channel *); 1207extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1208extern int nvc0_fifo_load_context(struct nouveau_channel *); 1209extern int nvc0_fifo_unload_context(struct drm_device *); 1210 1211/* nv04_graph.c */ 1212extern int nv04_graph_create(struct drm_device *); 1213extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1214extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1215 u32 class, u32 mthd, u32 data); 1216extern struct nouveau_bitfield nv04_graph_nsource[]; 1217 1218/* nv10_graph.c */ 1219extern int nv10_graph_create(struct drm_device *); 1220extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1221extern struct nouveau_bitfield nv10_graph_intr[]; 1222extern struct nouveau_bitfield nv10_graph_nstatus[]; 1223 1224/* nv20_graph.c */ 1225extern int nv20_graph_create(struct drm_device *); 1226 1227/* nv40_graph.c */ 1228extern int nv40_graph_create(struct drm_device *); 1229extern void nv40_grctx_init(struct nouveau_grctx *); 1230 1231/* nv50_graph.c */ 1232extern int nv50_graph_create(struct drm_device *); 1233extern int nv50_grctx_init(struct nouveau_grctx *); 1234extern struct nouveau_enum nv50_data_error_names[]; 1235extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1236 1237/* nvc0_graph.c */ 1238extern int nvc0_graph_create(struct drm_device *); 1239extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1240 1241/* nv84_crypt.c */ 1242extern int nv84_crypt_create(struct drm_device *); 1243 1244/* nv98_crypt.c */ 1245extern int nv98_crypt_create(struct drm_device *dev); 1246 1247/* nva3_copy.c */ 1248extern int nva3_copy_create(struct drm_device *dev); 1249 1250/* nvc0_copy.c */ 1251extern int nvc0_copy_create(struct drm_device *dev, int engine); 1252 1253/* nv31_mpeg.c */ 1254extern int nv31_mpeg_create(struct drm_device *dev); 1255 1256/* nv50_mpeg.c */ 1257extern int nv50_mpeg_create(struct drm_device *dev); 1258 1259/* nv84_bsp.c */ 1260/* nv98_bsp.c */ 1261extern int nv84_bsp_create(struct drm_device *dev); 1262 1263/* nv84_vp.c */ 1264/* nv98_vp.c */ 1265extern int nv84_vp_create(struct drm_device *dev); 1266 1267/* nv98_ppp.c */ 1268extern int nv98_ppp_create(struct drm_device *dev); 1269 1270/* nv04_instmem.c */ 1271extern int nv04_instmem_init(struct drm_device *); 1272extern void nv04_instmem_takedown(struct drm_device *); 1273extern int nv04_instmem_suspend(struct drm_device *); 1274extern void nv04_instmem_resume(struct drm_device *); 1275extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1276 u32 size, u32 align); 1277extern void nv04_instmem_put(struct nouveau_gpuobj *); 1278extern int nv04_instmem_map(struct nouveau_gpuobj *); 1279extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1280extern void nv04_instmem_flush(struct drm_device *); 1281 1282/* nv50_instmem.c */ 1283extern int nv50_instmem_init(struct drm_device *); 1284extern void nv50_instmem_takedown(struct drm_device *); 1285extern int nv50_instmem_suspend(struct drm_device *); 1286extern void nv50_instmem_resume(struct drm_device *); 1287extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1288 u32 size, u32 align); 1289extern void nv50_instmem_put(struct nouveau_gpuobj *); 1290extern int nv50_instmem_map(struct nouveau_gpuobj *); 1291extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1292extern void nv50_instmem_flush(struct drm_device *); 1293extern void nv84_instmem_flush(struct drm_device *); 1294 1295/* nvc0_instmem.c */ 1296extern int nvc0_instmem_init(struct drm_device *); 1297extern void nvc0_instmem_takedown(struct drm_device *); 1298extern int nvc0_instmem_suspend(struct drm_device *); 1299extern void nvc0_instmem_resume(struct drm_device *); 1300 1301/* nv04_mc.c */ 1302extern int nv04_mc_init(struct drm_device *); 1303extern void nv04_mc_takedown(struct drm_device *); 1304 1305/* nv40_mc.c */ 1306extern int nv40_mc_init(struct drm_device *); 1307extern void nv40_mc_takedown(struct drm_device *); 1308 1309/* nv50_mc.c */ 1310extern int nv50_mc_init(struct drm_device *); 1311extern void nv50_mc_takedown(struct drm_device *); 1312 1313/* nv04_timer.c */ 1314extern int nv04_timer_init(struct drm_device *); 1315extern uint64_t nv04_timer_read(struct drm_device *); 1316extern void nv04_timer_takedown(struct drm_device *); 1317 1318extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1319 unsigned long arg); 1320 1321/* nv04_dac.c */ 1322extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1323extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1324extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1325extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1326extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1327 1328/* nv04_dfp.c */ 1329extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1330extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1331extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1332 int head, bool dl); 1333extern void nv04_dfp_disable(struct drm_device *dev, int head); 1334extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1335 1336/* nv04_tv.c */ 1337extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1338extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1339 1340/* nv17_tv.c */ 1341extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1342 1343/* nv04_display.c */ 1344extern int nv04_display_early_init(struct drm_device *); 1345extern void nv04_display_late_takedown(struct drm_device *); 1346extern int nv04_display_create(struct drm_device *); 1347extern void nv04_display_destroy(struct drm_device *); 1348extern int nv04_display_init(struct drm_device *); 1349extern void nv04_display_fini(struct drm_device *); 1350 1351/* nvd0_display.c */ 1352extern int nvd0_display_create(struct drm_device *); 1353extern void nvd0_display_destroy(struct drm_device *); 1354extern int nvd0_display_init(struct drm_device *); 1355extern void nvd0_display_fini(struct drm_device *); 1356 1357/* nv04_crtc.c */ 1358extern int nv04_crtc_create(struct drm_device *, int index); 1359 1360/* nouveau_bo.c */ 1361extern struct ttm_bo_driver nouveau_bo_driver; 1362extern int nouveau_bo_new(struct drm_device *, int size, int align, 1363 uint32_t flags, uint32_t tile_mode, 1364 uint32_t tile_flags, struct nouveau_bo **); 1365extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1366extern int nouveau_bo_unpin(struct nouveau_bo *); 1367extern int nouveau_bo_map(struct nouveau_bo *); 1368extern void nouveau_bo_unmap(struct nouveau_bo *); 1369extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1370 uint32_t busy); 1371extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1372extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1373extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1374extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1375extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1376extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1377 bool no_wait_reserve, bool no_wait_gpu); 1378 1379extern struct nouveau_vma * 1380nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1381extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1382 struct nouveau_vma *); 1383extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1384 1385/* nouveau_fence.c */ 1386struct nouveau_fence; 1387extern int nouveau_fence_init(struct drm_device *); 1388extern void nouveau_fence_fini(struct drm_device *); 1389extern int nouveau_fence_channel_init(struct nouveau_channel *); 1390extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1391extern void nouveau_fence_update(struct nouveau_channel *); 1392extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1393 bool emit); 1394extern int nouveau_fence_emit(struct nouveau_fence *); 1395extern void nouveau_fence_work(struct nouveau_fence *fence, 1396 void (*work)(void *priv, bool signalled), 1397 void *priv); 1398struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1399 1400extern bool __nouveau_fence_signalled(void *obj, void *arg); 1401extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1402extern int __nouveau_fence_flush(void *obj, void *arg); 1403extern void __nouveau_fence_unref(void **obj); 1404extern void *__nouveau_fence_ref(void *obj); 1405 1406static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1407{ 1408 return __nouveau_fence_signalled(obj, NULL); 1409} 1410static inline int 1411nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1412{ 1413 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1414} 1415extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1416static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1417{ 1418 return __nouveau_fence_flush(obj, NULL); 1419} 1420static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1421{ 1422 __nouveau_fence_unref((void **)obj); 1423} 1424static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1425{ 1426 return __nouveau_fence_ref(obj); 1427} 1428 1429/* nouveau_gem.c */ 1430extern int nouveau_gem_new(struct drm_device *, int size, int align, 1431 uint32_t domain, uint32_t tile_mode, 1432 uint32_t tile_flags, struct nouveau_bo **); 1433extern int nouveau_gem_object_new(struct drm_gem_object *); 1434extern void nouveau_gem_object_del(struct drm_gem_object *); 1435extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1436extern void nouveau_gem_object_close(struct drm_gem_object *, 1437 struct drm_file *); 1438extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1439 struct drm_file *); 1440extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1441 struct drm_file *); 1442extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1443 struct drm_file *); 1444extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1445 struct drm_file *); 1446extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1447 struct drm_file *); 1448 1449/* nouveau_display.c */ 1450int nouveau_display_create(struct drm_device *dev); 1451void nouveau_display_destroy(struct drm_device *dev); 1452int nouveau_display_init(struct drm_device *dev); 1453void nouveau_display_fini(struct drm_device *dev); 1454int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1455void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1456int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1457 struct drm_pending_vblank_event *event); 1458int nouveau_finish_page_flip(struct nouveau_channel *, 1459 struct nouveau_page_flip_state *); 1460int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1461 struct drm_mode_create_dumb *args); 1462int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1463 uint32_t handle, uint64_t *offset); 1464int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1465 uint32_t handle); 1466 1467/* nv10_gpio.c */ 1468int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1469int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1470 1471/* nv50_gpio.c */ 1472int nv50_gpio_init(struct drm_device *dev); 1473void nv50_gpio_fini(struct drm_device *dev); 1474int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1475int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1476int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1477int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1478int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1479 void (*)(void *, int), void *); 1480void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1481 void (*)(void *, int), void *); 1482bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1483 1484/* nv50_calc. */ 1485int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1486 int *N1, int *M1, int *N2, int *M2, int *P); 1487int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1488 int clk, int *N, int *fN, int *M, int *P); 1489 1490#ifndef ioread32_native 1491#ifdef __BIG_ENDIAN 1492#define ioread16_native ioread16be 1493#define iowrite16_native iowrite16be 1494#define ioread32_native ioread32be 1495#define iowrite32_native iowrite32be 1496#else /* def __BIG_ENDIAN */ 1497#define ioread16_native ioread16 1498#define iowrite16_native iowrite16 1499#define ioread32_native ioread32 1500#define iowrite32_native iowrite32 1501#endif /* def __BIG_ENDIAN else */ 1502#endif /* !ioread32_native */ 1503 1504/* channel control reg access */ 1505static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1506{ 1507 return ioread32_native(chan->user + reg); 1508} 1509 1510static inline void nvchan_wr32(struct nouveau_channel *chan, 1511 unsigned reg, u32 val) 1512{ 1513 iowrite32_native(val, chan->user + reg); 1514} 1515 1516/* register access */ 1517static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1518{ 1519 struct drm_nouveau_private *dev_priv = dev->dev_private; 1520 return ioread32_native(dev_priv->mmio + reg); 1521} 1522 1523static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1524{ 1525 struct drm_nouveau_private *dev_priv = dev->dev_private; 1526 iowrite32_native(val, dev_priv->mmio + reg); 1527} 1528 1529static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1530{ 1531 u32 tmp = nv_rd32(dev, reg); 1532 nv_wr32(dev, reg, (tmp & ~mask) | val); 1533 return tmp; 1534} 1535 1536static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1537{ 1538 struct drm_nouveau_private *dev_priv = dev->dev_private; 1539 return ioread8(dev_priv->mmio + reg); 1540} 1541 1542static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1543{ 1544 struct drm_nouveau_private *dev_priv = dev->dev_private; 1545 iowrite8(val, dev_priv->mmio + reg); 1546} 1547 1548#define nv_wait(dev, reg, mask, val) \ 1549 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1550#define nv_wait_ne(dev, reg, mask, val) \ 1551 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1552#define nv_wait_cb(dev, func, data) \ 1553 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1554 1555/* PRAMIN access */ 1556static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1557{ 1558 struct drm_nouveau_private *dev_priv = dev->dev_private; 1559 return ioread32_native(dev_priv->ramin + offset); 1560} 1561 1562static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1563{ 1564 struct drm_nouveau_private *dev_priv = dev->dev_private; 1565 iowrite32_native(val, dev_priv->ramin + offset); 1566} 1567 1568/* object access */ 1569extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1570extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1571 1572/* 1573 * Logging 1574 * Argument d is (struct drm_device *). 1575 */ 1576#define NV_PRINTK(level, d, fmt, arg...) \ 1577 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1578 pci_name(d->pdev), ##arg) 1579#ifndef NV_DEBUG_NOTRACE 1580#define NV_DEBUG(d, fmt, arg...) do { \ 1581 if (drm_debug & DRM_UT_DRIVER) { \ 1582 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1583 __LINE__, ##arg); \ 1584 } \ 1585} while (0) 1586#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1587 if (drm_debug & DRM_UT_KMS) { \ 1588 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1589 __LINE__, ##arg); \ 1590 } \ 1591} while (0) 1592#else 1593#define NV_DEBUG(d, fmt, arg...) do { \ 1594 if (drm_debug & DRM_UT_DRIVER) \ 1595 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1596} while (0) 1597#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1598 if (drm_debug & DRM_UT_KMS) \ 1599 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1600} while (0) 1601#endif 1602#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1603#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1604#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1605#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1606#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1607 1608/* nouveau_reg_debug bitmask */ 1609enum { 1610 NOUVEAU_REG_DEBUG_MC = 0x1, 1611 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1612 NOUVEAU_REG_DEBUG_FB = 0x4, 1613 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1614 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1615 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1616 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1617 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1618 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1619 NOUVEAU_REG_DEBUG_EVO = 0x200, 1620 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1621}; 1622 1623#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1624 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1625 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1626} while (0) 1627 1628static inline bool 1629nv_two_heads(struct drm_device *dev) 1630{ 1631 struct drm_nouveau_private *dev_priv = dev->dev_private; 1632 const int impl = dev->pci_device & 0x0ff0; 1633 1634 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1635 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1636 return true; 1637 1638 return false; 1639} 1640 1641static inline bool 1642nv_gf4_disp_arch(struct drm_device *dev) 1643{ 1644 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1645} 1646 1647static inline bool 1648nv_two_reg_pll(struct drm_device *dev) 1649{ 1650 struct drm_nouveau_private *dev_priv = dev->dev_private; 1651 const int impl = dev->pci_device & 0x0ff0; 1652 1653 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1654 return true; 1655 return false; 1656} 1657 1658static inline bool 1659nv_match_device(struct drm_device *dev, unsigned device, 1660 unsigned sub_vendor, unsigned sub_device) 1661{ 1662 return dev->pdev->device == device && 1663 dev->pdev->subsystem_vendor == sub_vendor && 1664 dev->pdev->subsystem_device == sub_device; 1665} 1666 1667static inline void * 1668nv_engine(struct drm_device *dev, int engine) 1669{ 1670 struct drm_nouveau_private *dev_priv = dev->dev_private; 1671 return (void *)dev_priv->eng[engine]; 1672} 1673 1674/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1675 * helpful to determine a number of other hardware features 1676 */ 1677static inline int 1678nv44_graph_class(struct drm_device *dev) 1679{ 1680 struct drm_nouveau_private *dev_priv = dev->dev_private; 1681 1682 if ((dev_priv->chipset & 0xf0) == 0x60) 1683 return 1; 1684 1685 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1686} 1687 1688/* memory type/access flags, do not match hardware values */ 1689#define NV_MEM_ACCESS_RO 1 1690#define NV_MEM_ACCESS_WO 2 1691#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1692#define NV_MEM_ACCESS_SYS 4 1693#define NV_MEM_ACCESS_VM 8 1694 1695#define NV_MEM_TARGET_VRAM 0 1696#define NV_MEM_TARGET_PCI 1 1697#define NV_MEM_TARGET_PCI_NOSNOOP 2 1698#define NV_MEM_TARGET_VM 3 1699#define NV_MEM_TARGET_GART 4 1700 1701#define NV_MEM_TYPE_VM 0x7f 1702#define NV_MEM_COMP_VM 0x03 1703 1704/* NV_SW object class */ 1705#define NV_SW 0x0000506e 1706#define NV_SW_DMA_SEMAPHORE 0x00000060 1707#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1708#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1709#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1710#define NV_SW_YIELD 0x00000080 1711#define NV_SW_DMA_VBLSEM 0x0000018c 1712#define NV_SW_VBLSEM_OFFSET 0x00000400 1713#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1714#define NV_SW_VBLSEM_RELEASE 0x00000408 1715#define NV_SW_PAGE_FLIP 0x00000500 1716 1717#endif /* __NOUVEAU_DRV_H__ */ 1718