nouveau_drv.h revision f8522fc80f2e0392fc44b069f61721bd25907270
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_mem; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68struct nouveau_mem { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 struct nouveau_vma tmp_vma; 73 u8 page_shift; 74 75 struct drm_mm_node *tag; 76 struct list_head regions; 77 dma_addr_t *pages; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 valid_domains; 97 u32 placements[3]; 98 u32 busy_placements[3]; 99 struct ttm_bo_kmap_obj kmap; 100 struct list_head head; 101 102 /* protected by ttm_bo_reserve() */ 103 struct drm_file *reserved_by; 104 struct list_head entry; 105 int pbbo_index; 106 bool validate_mapped; 107 108 struct nouveau_channel *channel; 109 110 struct nouveau_vma vma; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_CRYPT 2 154#define NVOBJ_ENGINE_COPY0 3 155#define NVOBJ_ENGINE_COPY1 4 156#define NVOBJ_ENGINE_MPEG 5 157#define NVOBJ_ENGINE_DISPLAY 15 158#define NVOBJ_ENGINE_NR 16 159 160#define NVOBJ_FLAG_DONT_MAP (1 << 0) 161#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 162#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 163#define NVOBJ_FLAG_VM (1 << 3) 164#define NVOBJ_FLAG_VM_USER (1 << 4) 165 166#define NVOBJ_CINST_GLOBAL 0xdeadbeef 167 168struct nouveau_gpuobj { 169 struct drm_device *dev; 170 struct kref refcount; 171 struct list_head list; 172 173 void *node; 174 u32 *suspend; 175 176 uint32_t flags; 177 178 u32 size; 179 u32 pinst; /* PRAMIN BAR offset */ 180 u32 cinst; /* Channel offset */ 181 u64 vinst; /* VRAM address */ 182 u64 linst; /* VM address */ 183 184 uint32_t engine; 185 uint32_t class; 186 187 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 188 void *priv; 189}; 190 191struct nouveau_page_flip_state { 192 struct list_head head; 193 struct drm_pending_vblank_event *event; 194 int crtc, bpp, pitch, x, y; 195 uint64_t offset; 196}; 197 198enum nouveau_channel_mutex_class { 199 NOUVEAU_UCHANNEL_MUTEX, 200 NOUVEAU_KCHANNEL_MUTEX 201}; 202 203struct nouveau_channel { 204 struct drm_device *dev; 205 int id; 206 207 /* references to the channel data structure */ 208 struct kref ref; 209 /* users of the hardware channel resources, the hardware 210 * context will be kicked off when it reaches zero. */ 211 atomic_t users; 212 struct mutex mutex; 213 214 /* owner of this fifo */ 215 struct drm_file *file_priv; 216 /* mapping of the fifo itself */ 217 struct drm_local_map *map; 218 219 /* mapping of the regs controlling the fifo */ 220 void __iomem *user; 221 uint32_t user_get; 222 uint32_t user_put; 223 224 /* Fencing */ 225 struct { 226 /* lock protects the pending list only */ 227 spinlock_t lock; 228 struct list_head pending; 229 uint32_t sequence; 230 uint32_t sequence_ack; 231 atomic_t last_sequence_irq; 232 } fence; 233 234 /* DMA push buffer */ 235 struct nouveau_gpuobj *pushbuf; 236 struct nouveau_bo *pushbuf_bo; 237 uint32_t pushbuf_base; 238 239 /* Notifier memory */ 240 struct nouveau_bo *notifier_bo; 241 struct drm_mm notifier_heap; 242 243 /* PFIFO context */ 244 struct nouveau_gpuobj *ramfc; 245 struct nouveau_gpuobj *cache; 246 void *fifo_priv; 247 248 /* Execution engine contexts */ 249 void *engctx[NVOBJ_ENGINE_NR]; 250 251 /* NV50 VM */ 252 struct nouveau_vm *vm; 253 struct nouveau_gpuobj *vm_pd; 254 255 /* Objects */ 256 struct nouveau_gpuobj *ramin; /* Private instmem */ 257 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 258 struct nouveau_ramht *ramht; /* Hash table */ 259 260 /* GPU object info for stuff used in-kernel (mm_enabled) */ 261 uint32_t m2mf_ntfy; 262 uint32_t vram_handle; 263 uint32_t gart_handle; 264 bool accel_done; 265 266 /* Push buffer state (only for drm's channel on !mm_enabled) */ 267 struct { 268 int max; 269 int free; 270 int cur; 271 int put; 272 /* access via pushbuf_bo */ 273 274 int ib_base; 275 int ib_max; 276 int ib_free; 277 int ib_put; 278 } dma; 279 280 uint32_t sw_subchannel[8]; 281 282 struct { 283 struct nouveau_gpuobj *vblsem; 284 uint32_t vblsem_head; 285 uint32_t vblsem_offset; 286 uint32_t vblsem_rval; 287 struct list_head vbl_wait; 288 struct list_head flip; 289 } nvsw; 290 291 struct { 292 bool active; 293 char name[32]; 294 struct drm_info_list info; 295 } debugfs; 296}; 297 298struct nouveau_exec_engine { 299 void (*destroy)(struct drm_device *, int engine); 300 int (*init)(struct drm_device *, int engine); 301 int (*fini)(struct drm_device *, int engine); 302 int (*context_new)(struct nouveau_channel *, int engine); 303 void (*context_del)(struct nouveau_channel *, int engine); 304 int (*object_new)(struct nouveau_channel *, int engine, 305 u32 handle, u16 class); 306 void (*set_tile_region)(struct drm_device *dev, int i); 307 void (*tlb_flush)(struct drm_device *, int engine); 308}; 309 310struct nouveau_instmem_engine { 311 void *priv; 312 313 int (*init)(struct drm_device *dev); 314 void (*takedown)(struct drm_device *dev); 315 int (*suspend)(struct drm_device *dev); 316 void (*resume)(struct drm_device *dev); 317 318 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 319 void (*put)(struct nouveau_gpuobj *); 320 int (*map)(struct nouveau_gpuobj *); 321 void (*unmap)(struct nouveau_gpuobj *); 322 323 void (*flush)(struct drm_device *); 324}; 325 326struct nouveau_mc_engine { 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329}; 330 331struct nouveau_timer_engine { 332 int (*init)(struct drm_device *dev); 333 void (*takedown)(struct drm_device *dev); 334 uint64_t (*read)(struct drm_device *dev); 335}; 336 337struct nouveau_fb_engine { 338 int num_tiles; 339 struct drm_mm tag_heap; 340 void *priv; 341 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344 345 void (*init_tile_region)(struct drm_device *dev, int i, 346 uint32_t addr, uint32_t size, 347 uint32_t pitch, uint32_t flags); 348 void (*set_tile_region)(struct drm_device *dev, int i); 349 void (*free_tile_region)(struct drm_device *dev, int i); 350}; 351 352struct nouveau_fifo_engine { 353 void *priv; 354 int channels; 355 356 struct nouveau_gpuobj *playlist[2]; 357 int cur_playlist; 358 359 int (*init)(struct drm_device *); 360 void (*takedown)(struct drm_device *); 361 362 void (*disable)(struct drm_device *); 363 void (*enable)(struct drm_device *); 364 bool (*reassign)(struct drm_device *, bool enable); 365 bool (*cache_pull)(struct drm_device *dev, bool enable); 366 367 int (*channel_id)(struct drm_device *); 368 369 int (*create_context)(struct nouveau_channel *); 370 void (*destroy_context)(struct nouveau_channel *); 371 int (*load_context)(struct nouveau_channel *); 372 int (*unload_context)(struct drm_device *); 373 void (*tlb_flush)(struct drm_device *dev); 374}; 375 376struct nouveau_display_engine { 377 void *priv; 378 int (*early_init)(struct drm_device *); 379 void (*late_takedown)(struct drm_device *); 380 int (*create)(struct drm_device *); 381 int (*init)(struct drm_device *); 382 void (*destroy)(struct drm_device *); 383}; 384 385struct nouveau_gpio_engine { 386 void *priv; 387 388 int (*init)(struct drm_device *); 389 void (*takedown)(struct drm_device *); 390 391 int (*get)(struct drm_device *, enum dcb_gpio_tag); 392 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 393 394 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 395 void (*)(void *, int), void *); 396 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 397 void (*)(void *, int), void *); 398 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 399}; 400 401struct nouveau_pm_voltage_level { 402 u8 voltage; 403 u8 vid; 404}; 405 406struct nouveau_pm_voltage { 407 bool supported; 408 u8 vid_mask; 409 410 struct nouveau_pm_voltage_level *level; 411 int nr_level; 412}; 413 414struct nouveau_pm_memtiming { 415 int id; 416 u32 reg_100220; 417 u32 reg_100224; 418 u32 reg_100228; 419 u32 reg_10022c; 420 u32 reg_100230; 421 u32 reg_100234; 422 u32 reg_100238; 423 u32 reg_10023c; 424 u32 reg_100240; 425}; 426 427#define NOUVEAU_PM_MAX_LEVEL 8 428struct nouveau_pm_level { 429 struct device_attribute dev_attr; 430 char name[32]; 431 int id; 432 433 u32 core; 434 u32 memory; 435 u32 shader; 436 u32 unk05; 437 u32 unk0a; 438 439 u8 voltage; 440 u8 fanspeed; 441 442 u16 memscript; 443 struct nouveau_pm_memtiming *timing; 444}; 445 446struct nouveau_pm_temp_sensor_constants { 447 u16 offset_constant; 448 s16 offset_mult; 449 u16 offset_div; 450 u16 slope_mult; 451 u16 slope_div; 452}; 453 454struct nouveau_pm_threshold_temp { 455 s16 critical; 456 s16 down_clock; 457 s16 fan_boost; 458}; 459 460struct nouveau_pm_memtimings { 461 bool supported; 462 struct nouveau_pm_memtiming *timing; 463 int nr_timing; 464}; 465 466struct nouveau_pm_engine { 467 struct nouveau_pm_voltage voltage; 468 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 469 int nr_perflvl; 470 struct nouveau_pm_memtimings memtimings; 471 struct nouveau_pm_temp_sensor_constants sensor_constants; 472 struct nouveau_pm_threshold_temp threshold_temp; 473 474 struct nouveau_pm_level boot; 475 struct nouveau_pm_level *cur; 476 477 struct device *hwmon; 478 struct notifier_block acpi_nb; 479 480 int (*clock_get)(struct drm_device *, u32 id); 481 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 482 u32 id, int khz); 483 void (*clock_set)(struct drm_device *, void *); 484 int (*voltage_get)(struct drm_device *); 485 int (*voltage_set)(struct drm_device *, int voltage); 486 int (*fanspeed_get)(struct drm_device *); 487 int (*fanspeed_set)(struct drm_device *, int fanspeed); 488 int (*temp_get)(struct drm_device *); 489}; 490 491struct nouveau_vram_engine { 492 int (*init)(struct drm_device *); 493 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 494 u32 type, struct nouveau_mem **); 495 void (*put)(struct drm_device *, struct nouveau_mem **); 496 497 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 498}; 499 500struct nouveau_engine { 501 struct nouveau_instmem_engine instmem; 502 struct nouveau_mc_engine mc; 503 struct nouveau_timer_engine timer; 504 struct nouveau_fb_engine fb; 505 struct nouveau_fifo_engine fifo; 506 struct nouveau_display_engine display; 507 struct nouveau_gpio_engine gpio; 508 struct nouveau_pm_engine pm; 509 struct nouveau_vram_engine vram; 510}; 511 512struct nouveau_pll_vals { 513 union { 514 struct { 515#ifdef __BIG_ENDIAN 516 uint8_t N1, M1, N2, M2; 517#else 518 uint8_t M1, N1, M2, N2; 519#endif 520 }; 521 struct { 522 uint16_t NM1, NM2; 523 } __attribute__((packed)); 524 }; 525 int log2P; 526 527 int refclk; 528}; 529 530enum nv04_fp_display_regs { 531 FP_DISPLAY_END, 532 FP_TOTAL, 533 FP_CRTC, 534 FP_SYNC_START, 535 FP_SYNC_END, 536 FP_VALID_START, 537 FP_VALID_END 538}; 539 540struct nv04_crtc_reg { 541 unsigned char MiscOutReg; 542 uint8_t CRTC[0xa0]; 543 uint8_t CR58[0x10]; 544 uint8_t Sequencer[5]; 545 uint8_t Graphics[9]; 546 uint8_t Attribute[21]; 547 unsigned char DAC[768]; 548 549 /* PCRTC regs */ 550 uint32_t fb_start; 551 uint32_t crtc_cfg; 552 uint32_t cursor_cfg; 553 uint32_t gpio_ext; 554 uint32_t crtc_830; 555 uint32_t crtc_834; 556 uint32_t crtc_850; 557 uint32_t crtc_eng_ctrl; 558 559 /* PRAMDAC regs */ 560 uint32_t nv10_cursync; 561 struct nouveau_pll_vals pllvals; 562 uint32_t ramdac_gen_ctrl; 563 uint32_t ramdac_630; 564 uint32_t ramdac_634; 565 uint32_t tv_setup; 566 uint32_t tv_vtotal; 567 uint32_t tv_vskew; 568 uint32_t tv_vsync_delay; 569 uint32_t tv_htotal; 570 uint32_t tv_hskew; 571 uint32_t tv_hsync_delay; 572 uint32_t tv_hsync_delay2; 573 uint32_t fp_horiz_regs[7]; 574 uint32_t fp_vert_regs[7]; 575 uint32_t dither; 576 uint32_t fp_control; 577 uint32_t dither_regs[6]; 578 uint32_t fp_debug_0; 579 uint32_t fp_debug_1; 580 uint32_t fp_debug_2; 581 uint32_t fp_margin_color; 582 uint32_t ramdac_8c0; 583 uint32_t ramdac_a20; 584 uint32_t ramdac_a24; 585 uint32_t ramdac_a34; 586 uint32_t ctv_regs[38]; 587}; 588 589struct nv04_output_reg { 590 uint32_t output; 591 int head; 592}; 593 594struct nv04_mode_state { 595 struct nv04_crtc_reg crtc_reg[2]; 596 uint32_t pllsel; 597 uint32_t sel_clk; 598}; 599 600enum nouveau_card_type { 601 NV_04 = 0x00, 602 NV_10 = 0x10, 603 NV_20 = 0x20, 604 NV_30 = 0x30, 605 NV_40 = 0x40, 606 NV_50 = 0x50, 607 NV_C0 = 0xc0, 608}; 609 610struct drm_nouveau_private { 611 struct drm_device *dev; 612 bool noaccel; 613 614 /* the card type, takes NV_* as values */ 615 enum nouveau_card_type card_type; 616 /* exact chipset, derived from NV_PMC_BOOT_0 */ 617 int chipset; 618 int stepping; 619 int flags; 620 621 void __iomem *mmio; 622 623 spinlock_t ramin_lock; 624 void __iomem *ramin; 625 u32 ramin_size; 626 u32 ramin_base; 627 bool ramin_available; 628 struct drm_mm ramin_heap; 629 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 630 struct list_head gpuobj_list; 631 struct list_head classes; 632 633 struct nouveau_bo *vga_ram; 634 635 /* interrupt handling */ 636 void (*irq_handler[32])(struct drm_device *); 637 bool msi_enabled; 638 639 struct list_head vbl_waiting; 640 641 struct { 642 struct drm_global_reference mem_global_ref; 643 struct ttm_bo_global_ref bo_global_ref; 644 struct ttm_bo_device bdev; 645 atomic_t validate_sequence; 646 } ttm; 647 648 struct { 649 spinlock_t lock; 650 struct drm_mm heap; 651 struct nouveau_bo *bo; 652 } fence; 653 654 struct { 655 spinlock_t lock; 656 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 657 } channels; 658 659 struct nouveau_engine engine; 660 struct nouveau_channel *channel; 661 662 /* For PFIFO and PGRAPH. */ 663 spinlock_t context_switch_lock; 664 665 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 666 spinlock_t vm_lock; 667 668 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 669 struct nouveau_ramht *ramht; 670 struct nouveau_gpuobj *ramfc; 671 struct nouveau_gpuobj *ramro; 672 673 uint32_t ramin_rsvd_vram; 674 675 struct { 676 enum { 677 NOUVEAU_GART_NONE = 0, 678 NOUVEAU_GART_AGP, /* AGP */ 679 NOUVEAU_GART_PDMA, /* paged dma object */ 680 NOUVEAU_GART_HW /* on-chip gart/vm */ 681 } type; 682 uint64_t aper_base; 683 uint64_t aper_size; 684 uint64_t aper_free; 685 686 struct ttm_backend_func *func; 687 688 struct { 689 struct page *page; 690 dma_addr_t addr; 691 } dummy; 692 693 struct nouveau_gpuobj *sg_ctxdma; 694 } gart_info; 695 696 /* nv10-nv40 tiling regions */ 697 struct { 698 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 699 spinlock_t lock; 700 } tile; 701 702 /* VRAM/fb configuration */ 703 uint64_t vram_size; 704 uint64_t vram_sys_base; 705 u32 vram_rblock_size; 706 707 uint64_t fb_phys; 708 uint64_t fb_available_size; 709 uint64_t fb_mappable_pages; 710 uint64_t fb_aper_free; 711 int fb_mtrr; 712 713 /* BAR control (NV50-) */ 714 struct nouveau_vm *bar1_vm; 715 struct nouveau_vm *bar3_vm; 716 717 /* G8x/G9x virtual address space */ 718 struct nouveau_vm *chan_vm; 719 720 struct nvbios vbios; 721 722 struct nv04_mode_state mode_reg; 723 struct nv04_mode_state saved_reg; 724 uint32_t saved_vga_font[4][16384]; 725 uint32_t crtc_owner; 726 uint32_t dac_users[4]; 727 728 struct backlight_device *backlight; 729 730 struct { 731 struct dentry *channel_root; 732 } debugfs; 733 734 struct nouveau_fbdev *nfbdev; 735 struct apertures_struct *apertures; 736}; 737 738static inline struct drm_nouveau_private * 739nouveau_private(struct drm_device *dev) 740{ 741 return dev->dev_private; 742} 743 744static inline struct drm_nouveau_private * 745nouveau_bdev(struct ttm_bo_device *bd) 746{ 747 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 748} 749 750static inline int 751nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 752{ 753 struct nouveau_bo *prev; 754 755 if (!pnvbo) 756 return -EINVAL; 757 prev = *pnvbo; 758 759 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 760 if (prev) { 761 struct ttm_buffer_object *bo = &prev->bo; 762 763 ttm_bo_unref(&bo); 764 } 765 766 return 0; 767} 768 769/* nouveau_drv.c */ 770extern int nouveau_agpmode; 771extern int nouveau_duallink; 772extern int nouveau_uscript_lvds; 773extern int nouveau_uscript_tmds; 774extern int nouveau_vram_pushbuf; 775extern int nouveau_vram_notify; 776extern int nouveau_fbpercrtc; 777extern int nouveau_tv_disable; 778extern char *nouveau_tv_norm; 779extern int nouveau_reg_debug; 780extern char *nouveau_vbios; 781extern int nouveau_ignorelid; 782extern int nouveau_nofbaccel; 783extern int nouveau_noaccel; 784extern int nouveau_force_post; 785extern int nouveau_override_conntype; 786extern char *nouveau_perflvl; 787extern int nouveau_perflvl_wr; 788extern int nouveau_msi; 789 790extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 791extern int nouveau_pci_resume(struct pci_dev *pdev); 792 793/* nouveau_state.c */ 794extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 795extern int nouveau_load(struct drm_device *, unsigned long flags); 796extern int nouveau_firstopen(struct drm_device *); 797extern void nouveau_lastclose(struct drm_device *); 798extern int nouveau_unload(struct drm_device *); 799extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 800 struct drm_file *); 801extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 802 struct drm_file *); 803extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 804 uint32_t reg, uint32_t mask, uint32_t val); 805extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 806 uint32_t reg, uint32_t mask, uint32_t val); 807extern bool nouveau_wait_for_idle(struct drm_device *); 808extern int nouveau_card_init(struct drm_device *); 809 810/* nouveau_mem.c */ 811extern int nouveau_mem_vram_init(struct drm_device *); 812extern void nouveau_mem_vram_fini(struct drm_device *); 813extern int nouveau_mem_gart_init(struct drm_device *); 814extern void nouveau_mem_gart_fini(struct drm_device *); 815extern int nouveau_mem_init_agp(struct drm_device *); 816extern int nouveau_mem_reset_agp(struct drm_device *); 817extern void nouveau_mem_close(struct drm_device *); 818extern int nouveau_mem_detect(struct drm_device *); 819extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 820extern struct nouveau_tile_reg *nv10_mem_set_tiling( 821 struct drm_device *dev, uint32_t addr, uint32_t size, 822 uint32_t pitch, uint32_t flags); 823extern void nv10_mem_put_tile_region(struct drm_device *dev, 824 struct nouveau_tile_reg *tile, 825 struct nouveau_fence *fence); 826extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 827extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 828 829/* nouveau_notifier.c */ 830extern int nouveau_notifier_init_channel(struct nouveau_channel *); 831extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 832extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 833 int cout, uint32_t start, uint32_t end, 834 uint32_t *offset); 835extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 836extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 837 struct drm_file *); 838extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 839 struct drm_file *); 840 841/* nouveau_channel.c */ 842extern struct drm_ioctl_desc nouveau_ioctls[]; 843extern int nouveau_max_ioctl; 844extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 845extern int nouveau_channel_alloc(struct drm_device *dev, 846 struct nouveau_channel **chan, 847 struct drm_file *file_priv, 848 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 849extern struct nouveau_channel * 850nouveau_channel_get_unlocked(struct nouveau_channel *); 851extern struct nouveau_channel * 852nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 853extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 854extern void nouveau_channel_put(struct nouveau_channel **); 855extern void nouveau_channel_ref(struct nouveau_channel *chan, 856 struct nouveau_channel **pchan); 857extern void nouveau_channel_idle(struct nouveau_channel *chan); 858 859/* nouveau_object.c */ 860#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 861 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 862 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 863} while (0) 864 865#define NVOBJ_ENGINE_DEL(d, e) do { \ 866 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 867 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 868} while (0) 869 870#define NVOBJ_CLASS(d, c, e) do { \ 871 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 872 if (ret) \ 873 return ret; \ 874} while (0) 875 876#define NVOBJ_MTHD(d, c, m, e) do { \ 877 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 878 if (ret) \ 879 return ret; \ 880} while (0) 881 882extern int nouveau_gpuobj_early_init(struct drm_device *); 883extern int nouveau_gpuobj_init(struct drm_device *); 884extern void nouveau_gpuobj_takedown(struct drm_device *); 885extern int nouveau_gpuobj_suspend(struct drm_device *dev); 886extern void nouveau_gpuobj_resume(struct drm_device *dev); 887extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 888extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 889 int (*exec)(struct nouveau_channel *, 890 u32 class, u32 mthd, u32 data)); 891extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 892extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 893extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 894 uint32_t vram_h, uint32_t tt_h); 895extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 896extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 897 uint32_t size, int align, uint32_t flags, 898 struct nouveau_gpuobj **); 899extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 900 struct nouveau_gpuobj **); 901extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 902 u32 size, u32 flags, 903 struct nouveau_gpuobj **); 904extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 905 uint64_t offset, uint64_t size, int access, 906 int target, struct nouveau_gpuobj **); 907extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 908extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 909 u64 size, int target, int access, u32 type, 910 u32 comp, struct nouveau_gpuobj **pobj); 911extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 912 int class, u64 base, u64 size, int target, 913 int access, u32 type, u32 comp); 914extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 915 struct drm_file *); 916extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 917 struct drm_file *); 918 919/* nouveau_irq.c */ 920extern int nouveau_irq_init(struct drm_device *); 921extern void nouveau_irq_fini(struct drm_device *); 922extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 923extern void nouveau_irq_register(struct drm_device *, int status_bit, 924 void (*)(struct drm_device *)); 925extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 926extern void nouveau_irq_preinstall(struct drm_device *); 927extern int nouveau_irq_postinstall(struct drm_device *); 928extern void nouveau_irq_uninstall(struct drm_device *); 929 930/* nouveau_sgdma.c */ 931extern int nouveau_sgdma_init(struct drm_device *); 932extern void nouveau_sgdma_takedown(struct drm_device *); 933extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 934 uint32_t offset); 935extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 936 937/* nouveau_debugfs.c */ 938#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 939extern int nouveau_debugfs_init(struct drm_minor *); 940extern void nouveau_debugfs_takedown(struct drm_minor *); 941extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 942extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 943#else 944static inline int 945nouveau_debugfs_init(struct drm_minor *minor) 946{ 947 return 0; 948} 949 950static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 951{ 952} 953 954static inline int 955nouveau_debugfs_channel_init(struct nouveau_channel *chan) 956{ 957 return 0; 958} 959 960static inline void 961nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 962{ 963} 964#endif 965 966/* nouveau_dma.c */ 967extern void nouveau_dma_pre_init(struct nouveau_channel *); 968extern int nouveau_dma_init(struct nouveau_channel *); 969extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 970 971/* nouveau_acpi.c */ 972#define ROM_BIOS_PAGE 4096 973#if defined(CONFIG_ACPI) 974void nouveau_register_dsm_handler(void); 975void nouveau_unregister_dsm_handler(void); 976int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 977bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 978int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 979#else 980static inline void nouveau_register_dsm_handler(void) {} 981static inline void nouveau_unregister_dsm_handler(void) {} 982static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 983static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 984static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 985#endif 986 987/* nouveau_backlight.c */ 988#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 989extern int nouveau_backlight_init(struct drm_connector *); 990extern void nouveau_backlight_exit(struct drm_connector *); 991#else 992static inline int nouveau_backlight_init(struct drm_connector *dev) 993{ 994 return 0; 995} 996 997static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 998#endif 999 1000/* nouveau_bios.c */ 1001extern int nouveau_bios_init(struct drm_device *); 1002extern void nouveau_bios_takedown(struct drm_device *dev); 1003extern int nouveau_run_vbios_init(struct drm_device *); 1004extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1005 struct dcb_entry *); 1006extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1007 enum dcb_gpio_tag); 1008extern struct dcb_connector_table_entry * 1009nouveau_bios_connector_entry(struct drm_device *, int index); 1010extern u32 get_pll_register(struct drm_device *, enum pll_types); 1011extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1012 struct pll_lims *); 1013extern int nouveau_bios_run_display_table(struct drm_device *, 1014 struct dcb_entry *, 1015 uint32_t script, int pxclk); 1016extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1017 int *length); 1018extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1019extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1020extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1021 bool *dl, bool *if_is_24bit); 1022extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1023 int head, int pxclk); 1024extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1025 enum LVDS_script, int pxclk); 1026 1027/* nouveau_ttm.c */ 1028int nouveau_ttm_global_init(struct drm_nouveau_private *); 1029void nouveau_ttm_global_release(struct drm_nouveau_private *); 1030int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1031 1032/* nouveau_dp.c */ 1033int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1034 uint8_t *data, int data_nr); 1035bool nouveau_dp_detect(struct drm_encoder *); 1036bool nouveau_dp_link_train(struct drm_encoder *); 1037 1038/* nv04_fb.c */ 1039extern int nv04_fb_init(struct drm_device *); 1040extern void nv04_fb_takedown(struct drm_device *); 1041 1042/* nv10_fb.c */ 1043extern int nv10_fb_init(struct drm_device *); 1044extern void nv10_fb_takedown(struct drm_device *); 1045extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1046 uint32_t addr, uint32_t size, 1047 uint32_t pitch, uint32_t flags); 1048extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1049extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1050 1051/* nv30_fb.c */ 1052extern int nv30_fb_init(struct drm_device *); 1053extern void nv30_fb_takedown(struct drm_device *); 1054extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1055 uint32_t addr, uint32_t size, 1056 uint32_t pitch, uint32_t flags); 1057extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1058 1059/* nv40_fb.c */ 1060extern int nv40_fb_init(struct drm_device *); 1061extern void nv40_fb_takedown(struct drm_device *); 1062extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1063 1064/* nv50_fb.c */ 1065extern int nv50_fb_init(struct drm_device *); 1066extern void nv50_fb_takedown(struct drm_device *); 1067extern void nv50_fb_vm_trap(struct drm_device *, int display); 1068 1069/* nvc0_fb.c */ 1070extern int nvc0_fb_init(struct drm_device *); 1071extern void nvc0_fb_takedown(struct drm_device *); 1072 1073/* nv04_fifo.c */ 1074extern int nv04_fifo_init(struct drm_device *); 1075extern void nv04_fifo_fini(struct drm_device *); 1076extern void nv04_fifo_disable(struct drm_device *); 1077extern void nv04_fifo_enable(struct drm_device *); 1078extern bool nv04_fifo_reassign(struct drm_device *, bool); 1079extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1080extern int nv04_fifo_channel_id(struct drm_device *); 1081extern int nv04_fifo_create_context(struct nouveau_channel *); 1082extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1083extern int nv04_fifo_load_context(struct nouveau_channel *); 1084extern int nv04_fifo_unload_context(struct drm_device *); 1085extern void nv04_fifo_isr(struct drm_device *); 1086 1087/* nv10_fifo.c */ 1088extern int nv10_fifo_init(struct drm_device *); 1089extern int nv10_fifo_channel_id(struct drm_device *); 1090extern int nv10_fifo_create_context(struct nouveau_channel *); 1091extern int nv10_fifo_load_context(struct nouveau_channel *); 1092extern int nv10_fifo_unload_context(struct drm_device *); 1093 1094/* nv40_fifo.c */ 1095extern int nv40_fifo_init(struct drm_device *); 1096extern int nv40_fifo_create_context(struct nouveau_channel *); 1097extern int nv40_fifo_load_context(struct nouveau_channel *); 1098extern int nv40_fifo_unload_context(struct drm_device *); 1099 1100/* nv50_fifo.c */ 1101extern int nv50_fifo_init(struct drm_device *); 1102extern void nv50_fifo_takedown(struct drm_device *); 1103extern int nv50_fifo_channel_id(struct drm_device *); 1104extern int nv50_fifo_create_context(struct nouveau_channel *); 1105extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1106extern int nv50_fifo_load_context(struct nouveau_channel *); 1107extern int nv50_fifo_unload_context(struct drm_device *); 1108extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1109 1110/* nvc0_fifo.c */ 1111extern int nvc0_fifo_init(struct drm_device *); 1112extern void nvc0_fifo_takedown(struct drm_device *); 1113extern void nvc0_fifo_disable(struct drm_device *); 1114extern void nvc0_fifo_enable(struct drm_device *); 1115extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1116extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1117extern int nvc0_fifo_channel_id(struct drm_device *); 1118extern int nvc0_fifo_create_context(struct nouveau_channel *); 1119extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1120extern int nvc0_fifo_load_context(struct nouveau_channel *); 1121extern int nvc0_fifo_unload_context(struct drm_device *); 1122 1123/* nv04_graph.c */ 1124extern int nv04_graph_create(struct drm_device *); 1125extern void nv04_graph_fifo_access(struct drm_device *, bool); 1126extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1127extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1128 u32 class, u32 mthd, u32 data); 1129extern struct nouveau_bitfield nv04_graph_nsource[]; 1130 1131/* nv10_graph.c */ 1132extern int nv10_graph_create(struct drm_device *); 1133extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1134extern struct nouveau_bitfield nv10_graph_intr[]; 1135extern struct nouveau_bitfield nv10_graph_nstatus[]; 1136 1137/* nv20_graph.c */ 1138extern int nv20_graph_create(struct drm_device *); 1139 1140/* nv40_graph.c */ 1141extern int nv40_graph_create(struct drm_device *); 1142extern void nv40_grctx_init(struct nouveau_grctx *); 1143 1144/* nv50_graph.c */ 1145extern int nv50_graph_create(struct drm_device *); 1146extern int nv50_grctx_init(struct nouveau_grctx *); 1147extern struct nouveau_enum nv50_data_error_names[]; 1148extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1149 1150/* nvc0_graph.c */ 1151extern int nvc0_graph_create(struct drm_device *); 1152extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1153 1154/* nv84_crypt.c */ 1155extern int nv84_crypt_create(struct drm_device *); 1156 1157/* nva3_copy.c */ 1158extern int nva3_copy_create(struct drm_device *dev); 1159 1160/* nvc0_copy.c */ 1161extern int nvc0_copy_create(struct drm_device *dev, int engine); 1162 1163/* nv40_mpeg.c */ 1164extern int nv40_mpeg_create(struct drm_device *dev); 1165 1166/* nv50_mpeg.c */ 1167extern int nv50_mpeg_create(struct drm_device *dev); 1168 1169/* nv04_instmem.c */ 1170extern int nv04_instmem_init(struct drm_device *); 1171extern void nv04_instmem_takedown(struct drm_device *); 1172extern int nv04_instmem_suspend(struct drm_device *); 1173extern void nv04_instmem_resume(struct drm_device *); 1174extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1175extern void nv04_instmem_put(struct nouveau_gpuobj *); 1176extern int nv04_instmem_map(struct nouveau_gpuobj *); 1177extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1178extern void nv04_instmem_flush(struct drm_device *); 1179 1180/* nv50_instmem.c */ 1181extern int nv50_instmem_init(struct drm_device *); 1182extern void nv50_instmem_takedown(struct drm_device *); 1183extern int nv50_instmem_suspend(struct drm_device *); 1184extern void nv50_instmem_resume(struct drm_device *); 1185extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1186extern void nv50_instmem_put(struct nouveau_gpuobj *); 1187extern int nv50_instmem_map(struct nouveau_gpuobj *); 1188extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1189extern void nv50_instmem_flush(struct drm_device *); 1190extern void nv84_instmem_flush(struct drm_device *); 1191 1192/* nvc0_instmem.c */ 1193extern int nvc0_instmem_init(struct drm_device *); 1194extern void nvc0_instmem_takedown(struct drm_device *); 1195extern int nvc0_instmem_suspend(struct drm_device *); 1196extern void nvc0_instmem_resume(struct drm_device *); 1197 1198/* nv04_mc.c */ 1199extern int nv04_mc_init(struct drm_device *); 1200extern void nv04_mc_takedown(struct drm_device *); 1201 1202/* nv40_mc.c */ 1203extern int nv40_mc_init(struct drm_device *); 1204extern void nv40_mc_takedown(struct drm_device *); 1205 1206/* nv50_mc.c */ 1207extern int nv50_mc_init(struct drm_device *); 1208extern void nv50_mc_takedown(struct drm_device *); 1209 1210/* nv04_timer.c */ 1211extern int nv04_timer_init(struct drm_device *); 1212extern uint64_t nv04_timer_read(struct drm_device *); 1213extern void nv04_timer_takedown(struct drm_device *); 1214 1215extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1216 unsigned long arg); 1217 1218/* nv04_dac.c */ 1219extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1220extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1221extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1222extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1223extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1224 1225/* nv04_dfp.c */ 1226extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1227extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1228extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1229 int head, bool dl); 1230extern void nv04_dfp_disable(struct drm_device *dev, int head); 1231extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1232 1233/* nv04_tv.c */ 1234extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1235extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1236 1237/* nv17_tv.c */ 1238extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1239 1240/* nv04_display.c */ 1241extern int nv04_display_early_init(struct drm_device *); 1242extern void nv04_display_late_takedown(struct drm_device *); 1243extern int nv04_display_create(struct drm_device *); 1244extern int nv04_display_init(struct drm_device *); 1245extern void nv04_display_destroy(struct drm_device *); 1246 1247/* nv04_crtc.c */ 1248extern int nv04_crtc_create(struct drm_device *, int index); 1249 1250/* nouveau_bo.c */ 1251extern struct ttm_bo_driver nouveau_bo_driver; 1252extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1253 int size, int align, uint32_t flags, 1254 uint32_t tile_mode, uint32_t tile_flags, 1255 struct nouveau_bo **); 1256extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1257extern int nouveau_bo_unpin(struct nouveau_bo *); 1258extern int nouveau_bo_map(struct nouveau_bo *); 1259extern void nouveau_bo_unmap(struct nouveau_bo *); 1260extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1261 uint32_t busy); 1262extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1263extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1264extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1265extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1266extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1267extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1268 bool no_wait_reserve, bool no_wait_gpu); 1269 1270/* nouveau_fence.c */ 1271struct nouveau_fence; 1272extern int nouveau_fence_init(struct drm_device *); 1273extern void nouveau_fence_fini(struct drm_device *); 1274extern int nouveau_fence_channel_init(struct nouveau_channel *); 1275extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1276extern void nouveau_fence_update(struct nouveau_channel *); 1277extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1278 bool emit); 1279extern int nouveau_fence_emit(struct nouveau_fence *); 1280extern void nouveau_fence_work(struct nouveau_fence *fence, 1281 void (*work)(void *priv, bool signalled), 1282 void *priv); 1283struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1284 1285extern bool __nouveau_fence_signalled(void *obj, void *arg); 1286extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1287extern int __nouveau_fence_flush(void *obj, void *arg); 1288extern void __nouveau_fence_unref(void **obj); 1289extern void *__nouveau_fence_ref(void *obj); 1290 1291static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1292{ 1293 return __nouveau_fence_signalled(obj, NULL); 1294} 1295static inline int 1296nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1297{ 1298 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1299} 1300extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1301static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1302{ 1303 return __nouveau_fence_flush(obj, NULL); 1304} 1305static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1306{ 1307 __nouveau_fence_unref((void **)obj); 1308} 1309static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1310{ 1311 return __nouveau_fence_ref(obj); 1312} 1313 1314/* nouveau_gem.c */ 1315extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1316 int size, int align, uint32_t domain, 1317 uint32_t tile_mode, uint32_t tile_flags, 1318 struct nouveau_bo **); 1319extern int nouveau_gem_object_new(struct drm_gem_object *); 1320extern void nouveau_gem_object_del(struct drm_gem_object *); 1321extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1322 struct drm_file *); 1323extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1324 struct drm_file *); 1325extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1326 struct drm_file *); 1327extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1328 struct drm_file *); 1329extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1330 struct drm_file *); 1331 1332/* nouveau_display.c */ 1333int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1334void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1335int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1336 struct drm_pending_vblank_event *event); 1337int nouveau_finish_page_flip(struct nouveau_channel *, 1338 struct nouveau_page_flip_state *); 1339 1340/* nv10_gpio.c */ 1341int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1342int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1343 1344/* nv50_gpio.c */ 1345int nv50_gpio_init(struct drm_device *dev); 1346void nv50_gpio_fini(struct drm_device *dev); 1347int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1348int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1349int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1350 void (*)(void *, int), void *); 1351void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1352 void (*)(void *, int), void *); 1353bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1354 1355/* nv50_calc. */ 1356int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1357 int *N1, int *M1, int *N2, int *M2, int *P); 1358int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1359 int clk, int *N, int *fN, int *M, int *P); 1360 1361#ifndef ioread32_native 1362#ifdef __BIG_ENDIAN 1363#define ioread16_native ioread16be 1364#define iowrite16_native iowrite16be 1365#define ioread32_native ioread32be 1366#define iowrite32_native iowrite32be 1367#else /* def __BIG_ENDIAN */ 1368#define ioread16_native ioread16 1369#define iowrite16_native iowrite16 1370#define ioread32_native ioread32 1371#define iowrite32_native iowrite32 1372#endif /* def __BIG_ENDIAN else */ 1373#endif /* !ioread32_native */ 1374 1375/* channel control reg access */ 1376static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1377{ 1378 return ioread32_native(chan->user + reg); 1379} 1380 1381static inline void nvchan_wr32(struct nouveau_channel *chan, 1382 unsigned reg, u32 val) 1383{ 1384 iowrite32_native(val, chan->user + reg); 1385} 1386 1387/* register access */ 1388static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1389{ 1390 struct drm_nouveau_private *dev_priv = dev->dev_private; 1391 return ioread32_native(dev_priv->mmio + reg); 1392} 1393 1394static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1395{ 1396 struct drm_nouveau_private *dev_priv = dev->dev_private; 1397 iowrite32_native(val, dev_priv->mmio + reg); 1398} 1399 1400static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1401{ 1402 u32 tmp = nv_rd32(dev, reg); 1403 nv_wr32(dev, reg, (tmp & ~mask) | val); 1404 return tmp; 1405} 1406 1407static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1408{ 1409 struct drm_nouveau_private *dev_priv = dev->dev_private; 1410 return ioread8(dev_priv->mmio + reg); 1411} 1412 1413static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1414{ 1415 struct drm_nouveau_private *dev_priv = dev->dev_private; 1416 iowrite8(val, dev_priv->mmio + reg); 1417} 1418 1419#define nv_wait(dev, reg, mask, val) \ 1420 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1421#define nv_wait_ne(dev, reg, mask, val) \ 1422 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1423 1424/* PRAMIN access */ 1425static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1426{ 1427 struct drm_nouveau_private *dev_priv = dev->dev_private; 1428 return ioread32_native(dev_priv->ramin + offset); 1429} 1430 1431static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1432{ 1433 struct drm_nouveau_private *dev_priv = dev->dev_private; 1434 iowrite32_native(val, dev_priv->ramin + offset); 1435} 1436 1437/* object access */ 1438extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1439extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1440 1441/* 1442 * Logging 1443 * Argument d is (struct drm_device *). 1444 */ 1445#define NV_PRINTK(level, d, fmt, arg...) \ 1446 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1447 pci_name(d->pdev), ##arg) 1448#ifndef NV_DEBUG_NOTRACE 1449#define NV_DEBUG(d, fmt, arg...) do { \ 1450 if (drm_debug & DRM_UT_DRIVER) { \ 1451 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1452 __LINE__, ##arg); \ 1453 } \ 1454} while (0) 1455#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1456 if (drm_debug & DRM_UT_KMS) { \ 1457 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1458 __LINE__, ##arg); \ 1459 } \ 1460} while (0) 1461#else 1462#define NV_DEBUG(d, fmt, arg...) do { \ 1463 if (drm_debug & DRM_UT_DRIVER) \ 1464 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1465} while (0) 1466#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1467 if (drm_debug & DRM_UT_KMS) \ 1468 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1469} while (0) 1470#endif 1471#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1472#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1473#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1474#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1475#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1476 1477/* nouveau_reg_debug bitmask */ 1478enum { 1479 NOUVEAU_REG_DEBUG_MC = 0x1, 1480 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1481 NOUVEAU_REG_DEBUG_FB = 0x4, 1482 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1483 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1484 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1485 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1486 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1487 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1488 NOUVEAU_REG_DEBUG_EVO = 0x200, 1489}; 1490 1491#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1492 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1493 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1494} while (0) 1495 1496static inline bool 1497nv_two_heads(struct drm_device *dev) 1498{ 1499 struct drm_nouveau_private *dev_priv = dev->dev_private; 1500 const int impl = dev->pci_device & 0x0ff0; 1501 1502 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1503 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1504 return true; 1505 1506 return false; 1507} 1508 1509static inline bool 1510nv_gf4_disp_arch(struct drm_device *dev) 1511{ 1512 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1513} 1514 1515static inline bool 1516nv_two_reg_pll(struct drm_device *dev) 1517{ 1518 struct drm_nouveau_private *dev_priv = dev->dev_private; 1519 const int impl = dev->pci_device & 0x0ff0; 1520 1521 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1522 return true; 1523 return false; 1524} 1525 1526static inline bool 1527nv_match_device(struct drm_device *dev, unsigned device, 1528 unsigned sub_vendor, unsigned sub_device) 1529{ 1530 return dev->pdev->device == device && 1531 dev->pdev->subsystem_vendor == sub_vendor && 1532 dev->pdev->subsystem_device == sub_device; 1533} 1534 1535static inline void * 1536nv_engine(struct drm_device *dev, int engine) 1537{ 1538 struct drm_nouveau_private *dev_priv = dev->dev_private; 1539 return (void *)dev_priv->eng[engine]; 1540} 1541 1542/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1543 * helpful to determine a number of other hardware features 1544 */ 1545static inline int 1546nv44_graph_class(struct drm_device *dev) 1547{ 1548 struct drm_nouveau_private *dev_priv = dev->dev_private; 1549 1550 if ((dev_priv->chipset & 0xf0) == 0x60) 1551 return 1; 1552 1553 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1554} 1555 1556/* memory type/access flags, do not match hardware values */ 1557#define NV_MEM_ACCESS_RO 1 1558#define NV_MEM_ACCESS_WO 2 1559#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1560#define NV_MEM_ACCESS_SYS 4 1561#define NV_MEM_ACCESS_VM 8 1562 1563#define NV_MEM_TARGET_VRAM 0 1564#define NV_MEM_TARGET_PCI 1 1565#define NV_MEM_TARGET_PCI_NOSNOOP 2 1566#define NV_MEM_TARGET_VM 3 1567#define NV_MEM_TARGET_GART 4 1568 1569#define NV_MEM_TYPE_VM 0x7f 1570#define NV_MEM_COMP_VM 0x03 1571 1572/* NV_SW object class */ 1573#define NV_SW 0x0000506e 1574#define NV_SW_DMA_SEMAPHORE 0x00000060 1575#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1576#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1577#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1578#define NV_SW_YIELD 0x00000080 1579#define NV_SW_DMA_VBLSEM 0x0000018c 1580#define NV_SW_VBLSEM_OFFSET 0x00000400 1581#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1582#define NV_SW_VBLSEM_RELEASE 0x00000408 1583#define NV_SW_PAGE_FLIP 0x00000500 1584 1585#endif /* __NOUVEAU_DRV_H__ */ 1586