nouveau_drv.h revision f869ef882382a4b6cb42d259e399aeec3781d4bb
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50}; 51 52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54#include "nouveau_drm.h" 55#include "nouveau_reg.h" 56#include "nouveau_bios.h" 57#include "nouveau_util.h" 58 59struct nouveau_grctx; 60struct nouveau_vram; 61#include "nouveau_vm.h" 62 63#define MAX_NUM_DCB_ENTRIES 16 64 65#define NOUVEAU_MAX_CHANNEL_NR 128 66#define NOUVEAU_MAX_TILE_NR 15 67 68#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) 69#define NV50_VM_BLOCK (512*1024*1024ULL) 70#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) 71 72struct nouveau_vram { 73 struct drm_device *dev; 74 75 struct nouveau_vma bar_vma; 76 77 struct list_head regions; 78 u32 memtype; 79 u64 offset; 80 u64 size; 81}; 82 83struct nouveau_tile_reg { 84 bool used; 85 uint32_t addr; 86 uint32_t limit; 87 uint32_t pitch; 88 uint32_t zcomp; 89 struct drm_mm_node *tag_mem; 90 struct nouveau_fence *fence; 91}; 92 93struct nouveau_bo { 94 struct ttm_buffer_object bo; 95 struct ttm_placement placement; 96 u32 placements[3]; 97 u32 busy_placements[3]; 98 struct ttm_bo_kmap_obj kmap; 99 struct list_head head; 100 101 /* protected by ttm_bo_reserve() */ 102 struct drm_file *reserved_by; 103 struct list_head entry; 104 int pbbo_index; 105 bool validate_mapped; 106 107 struct nouveau_channel *channel; 108 109 bool mappable; 110 bool no_vm; 111 112 uint32_t tile_mode; 113 uint32_t tile_flags; 114 struct nouveau_tile_reg *tile; 115 116 struct drm_gem_object *gem; 117 int pin_refcnt; 118}; 119 120#define nouveau_bo_tile_layout(nvbo) \ 121 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 122 123static inline struct nouveau_bo * 124nouveau_bo(struct ttm_buffer_object *bo) 125{ 126 return container_of(bo, struct nouveau_bo, bo); 127} 128 129static inline struct nouveau_bo * 130nouveau_gem_object(struct drm_gem_object *gem) 131{ 132 return gem ? gem->driver_private : NULL; 133} 134 135/* TODO: submit equivalent to TTM generic API upstream? */ 136static inline void __iomem * 137nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 138{ 139 bool is_iomem; 140 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 141 &nvbo->kmap, &is_iomem); 142 WARN_ON_ONCE(ioptr && !is_iomem); 143 return ioptr; 144} 145 146enum nouveau_flags { 147 NV_NFORCE = 0x10000000, 148 NV_NFORCE2 = 0x20000000 149}; 150 151#define NVOBJ_ENGINE_SW 0 152#define NVOBJ_ENGINE_GR 1 153#define NVOBJ_ENGINE_PPP 2 154#define NVOBJ_ENGINE_COPY 3 155#define NVOBJ_ENGINE_VP 4 156#define NVOBJ_ENGINE_CRYPT 5 157#define NVOBJ_ENGINE_BSP 6 158#define NVOBJ_ENGINE_DISPLAY 0xcafe0001 159#define NVOBJ_ENGINE_INT 0xdeadbeef 160 161#define NVOBJ_FLAG_DONT_MAP (1 << 0) 162#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 163#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 164 165#define NVOBJ_CINST_GLOBAL 0xdeadbeef 166 167struct nouveau_gpuobj { 168 struct drm_device *dev; 169 struct kref refcount; 170 struct list_head list; 171 172 void *node; 173 u32 *suspend; 174 175 uint32_t flags; 176 177 u32 size; 178 u32 pinst; 179 u32 cinst; 180 u64 vinst; 181 182 uint32_t engine; 183 uint32_t class; 184 185 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 186 void *priv; 187}; 188 189struct nouveau_page_flip_state { 190 struct list_head head; 191 struct drm_pending_vblank_event *event; 192 int crtc, bpp, pitch, x, y; 193 uint64_t offset; 194}; 195 196enum nouveau_channel_mutex_class { 197 NOUVEAU_UCHANNEL_MUTEX, 198 NOUVEAU_KCHANNEL_MUTEX 199}; 200 201struct nouveau_channel { 202 struct drm_device *dev; 203 int id; 204 205 /* references to the channel data structure */ 206 struct kref ref; 207 /* users of the hardware channel resources, the hardware 208 * context will be kicked off when it reaches zero. */ 209 atomic_t users; 210 struct mutex mutex; 211 212 /* owner of this fifo */ 213 struct drm_file *file_priv; 214 /* mapping of the fifo itself */ 215 struct drm_local_map *map; 216 217 /* mapping of the regs controling the fifo */ 218 void __iomem *user; 219 uint32_t user_get; 220 uint32_t user_put; 221 222 /* Fencing */ 223 struct { 224 /* lock protects the pending list only */ 225 spinlock_t lock; 226 struct list_head pending; 227 uint32_t sequence; 228 uint32_t sequence_ack; 229 atomic_t last_sequence_irq; 230 } fence; 231 232 /* DMA push buffer */ 233 struct nouveau_gpuobj *pushbuf; 234 struct nouveau_bo *pushbuf_bo; 235 uint32_t pushbuf_base; 236 237 /* Notifier memory */ 238 struct nouveau_bo *notifier_bo; 239 struct drm_mm notifier_heap; 240 241 /* PFIFO context */ 242 struct nouveau_gpuobj *ramfc; 243 struct nouveau_gpuobj *cache; 244 245 /* PGRAPH context */ 246 /* XXX may be merge 2 pointers as private data ??? */ 247 struct nouveau_gpuobj *ramin_grctx; 248 struct nouveau_gpuobj *crypt_ctx; 249 void *pgraph_ctx; 250 251 /* NV50 VM */ 252 struct nouveau_vm *vm; 253 struct nouveau_gpuobj *vm_pd; 254 struct nouveau_gpuobj *vm_gart_pt; 255 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 256 257 /* Objects */ 258 struct nouveau_gpuobj *ramin; /* Private instmem */ 259 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 260 struct nouveau_ramht *ramht; /* Hash table */ 261 262 /* GPU object info for stuff used in-kernel (mm_enabled) */ 263 uint32_t m2mf_ntfy; 264 uint32_t vram_handle; 265 uint32_t gart_handle; 266 bool accel_done; 267 268 /* Push buffer state (only for drm's channel on !mm_enabled) */ 269 struct { 270 int max; 271 int free; 272 int cur; 273 int put; 274 /* access via pushbuf_bo */ 275 276 int ib_base; 277 int ib_max; 278 int ib_free; 279 int ib_put; 280 } dma; 281 282 uint32_t sw_subchannel[8]; 283 284 struct { 285 struct nouveau_gpuobj *vblsem; 286 uint32_t vblsem_head; 287 uint32_t vblsem_offset; 288 uint32_t vblsem_rval; 289 struct list_head vbl_wait; 290 struct list_head flip; 291 } nvsw; 292 293 struct { 294 bool active; 295 char name[32]; 296 struct drm_info_list info; 297 } debugfs; 298}; 299 300struct nouveau_instmem_engine { 301 void *priv; 302 303 int (*init)(struct drm_device *dev); 304 void (*takedown)(struct drm_device *dev); 305 int (*suspend)(struct drm_device *dev); 306 void (*resume)(struct drm_device *dev); 307 308 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 309 void (*put)(struct nouveau_gpuobj *); 310 int (*map)(struct nouveau_gpuobj *); 311 void (*unmap)(struct nouveau_gpuobj *); 312 313 void (*flush)(struct drm_device *); 314}; 315 316struct nouveau_mc_engine { 317 int (*init)(struct drm_device *dev); 318 void (*takedown)(struct drm_device *dev); 319}; 320 321struct nouveau_timer_engine { 322 int (*init)(struct drm_device *dev); 323 void (*takedown)(struct drm_device *dev); 324 uint64_t (*read)(struct drm_device *dev); 325}; 326 327struct nouveau_fb_engine { 328 int num_tiles; 329 struct drm_mm tag_heap; 330 void *priv; 331 332 int (*init)(struct drm_device *dev); 333 void (*takedown)(struct drm_device *dev); 334 335 void (*init_tile_region)(struct drm_device *dev, int i, 336 uint32_t addr, uint32_t size, 337 uint32_t pitch, uint32_t flags); 338 void (*set_tile_region)(struct drm_device *dev, int i); 339 void (*free_tile_region)(struct drm_device *dev, int i); 340}; 341 342struct nouveau_fifo_engine { 343 int channels; 344 345 struct nouveau_gpuobj *playlist[2]; 346 int cur_playlist; 347 348 int (*init)(struct drm_device *); 349 void (*takedown)(struct drm_device *); 350 351 void (*disable)(struct drm_device *); 352 void (*enable)(struct drm_device *); 353 bool (*reassign)(struct drm_device *, bool enable); 354 bool (*cache_pull)(struct drm_device *dev, bool enable); 355 356 int (*channel_id)(struct drm_device *); 357 358 int (*create_context)(struct nouveau_channel *); 359 void (*destroy_context)(struct nouveau_channel *); 360 int (*load_context)(struct nouveau_channel *); 361 int (*unload_context)(struct drm_device *); 362 void (*tlb_flush)(struct drm_device *dev); 363}; 364 365struct nouveau_pgraph_engine { 366 bool accel_blocked; 367 bool registered; 368 int grctx_size; 369 370 /* NV2x/NV3x context table (0x400780) */ 371 struct nouveau_gpuobj *ctx_table; 372 373 int (*init)(struct drm_device *); 374 void (*takedown)(struct drm_device *); 375 376 void (*fifo_access)(struct drm_device *, bool); 377 378 struct nouveau_channel *(*channel)(struct drm_device *); 379 int (*create_context)(struct nouveau_channel *); 380 void (*destroy_context)(struct nouveau_channel *); 381 int (*load_context)(struct nouveau_channel *); 382 int (*unload_context)(struct drm_device *); 383 void (*tlb_flush)(struct drm_device *dev); 384 385 void (*set_tile_region)(struct drm_device *dev, int i); 386}; 387 388struct nouveau_display_engine { 389 int (*early_init)(struct drm_device *); 390 void (*late_takedown)(struct drm_device *); 391 int (*create)(struct drm_device *); 392 int (*init)(struct drm_device *); 393 void (*destroy)(struct drm_device *); 394}; 395 396struct nouveau_gpio_engine { 397 void *priv; 398 399 int (*init)(struct drm_device *); 400 void (*takedown)(struct drm_device *); 401 402 int (*get)(struct drm_device *, enum dcb_gpio_tag); 403 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 404 405 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 406 void (*)(void *, int), void *); 407 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 408 void (*)(void *, int), void *); 409 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 410}; 411 412struct nouveau_pm_voltage_level { 413 u8 voltage; 414 u8 vid; 415}; 416 417struct nouveau_pm_voltage { 418 bool supported; 419 u8 vid_mask; 420 421 struct nouveau_pm_voltage_level *level; 422 int nr_level; 423}; 424 425#define NOUVEAU_PM_MAX_LEVEL 8 426struct nouveau_pm_level { 427 struct device_attribute dev_attr; 428 char name[32]; 429 int id; 430 431 u32 core; 432 u32 memory; 433 u32 shader; 434 u32 unk05; 435 436 u8 voltage; 437 u8 fanspeed; 438 439 u16 memscript; 440}; 441 442struct nouveau_pm_temp_sensor_constants { 443 u16 offset_constant; 444 s16 offset_mult; 445 u16 offset_div; 446 u16 slope_mult; 447 u16 slope_div; 448}; 449 450struct nouveau_pm_threshold_temp { 451 s16 critical; 452 s16 down_clock; 453 s16 fan_boost; 454}; 455 456struct nouveau_pm_memtiming { 457 u32 reg_100220; 458 u32 reg_100224; 459 u32 reg_100228; 460 u32 reg_10022c; 461 u32 reg_100230; 462 u32 reg_100234; 463 u32 reg_100238; 464 u32 reg_10023c; 465}; 466 467struct nouveau_pm_memtimings { 468 bool supported; 469 struct nouveau_pm_memtiming *timing; 470 int nr_timing; 471}; 472 473struct nouveau_pm_engine { 474 struct nouveau_pm_voltage voltage; 475 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 476 int nr_perflvl; 477 struct nouveau_pm_memtimings memtimings; 478 struct nouveau_pm_temp_sensor_constants sensor_constants; 479 struct nouveau_pm_threshold_temp threshold_temp; 480 481 struct nouveau_pm_level boot; 482 struct nouveau_pm_level *cur; 483 484 struct device *hwmon; 485 struct notifier_block acpi_nb; 486 487 int (*clock_get)(struct drm_device *, u32 id); 488 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 489 u32 id, int khz); 490 void (*clock_set)(struct drm_device *, void *); 491 int (*voltage_get)(struct drm_device *); 492 int (*voltage_set)(struct drm_device *, int voltage); 493 int (*fanspeed_get)(struct drm_device *); 494 int (*fanspeed_set)(struct drm_device *, int fanspeed); 495 int (*temp_get)(struct drm_device *); 496}; 497 498struct nouveau_crypt_engine { 499 bool registered; 500 501 int (*init)(struct drm_device *); 502 void (*takedown)(struct drm_device *); 503 int (*create_context)(struct nouveau_channel *); 504 void (*destroy_context)(struct nouveau_channel *); 505 void (*tlb_flush)(struct drm_device *dev); 506}; 507 508struct nouveau_engine { 509 struct nouveau_instmem_engine instmem; 510 struct nouveau_mc_engine mc; 511 struct nouveau_timer_engine timer; 512 struct nouveau_fb_engine fb; 513 struct nouveau_pgraph_engine graph; 514 struct nouveau_fifo_engine fifo; 515 struct nouveau_display_engine display; 516 struct nouveau_gpio_engine gpio; 517 struct nouveau_pm_engine pm; 518 struct nouveau_crypt_engine crypt; 519}; 520 521struct nouveau_pll_vals { 522 union { 523 struct { 524#ifdef __BIG_ENDIAN 525 uint8_t N1, M1, N2, M2; 526#else 527 uint8_t M1, N1, M2, N2; 528#endif 529 }; 530 struct { 531 uint16_t NM1, NM2; 532 } __attribute__((packed)); 533 }; 534 int log2P; 535 536 int refclk; 537}; 538 539enum nv04_fp_display_regs { 540 FP_DISPLAY_END, 541 FP_TOTAL, 542 FP_CRTC, 543 FP_SYNC_START, 544 FP_SYNC_END, 545 FP_VALID_START, 546 FP_VALID_END 547}; 548 549struct nv04_crtc_reg { 550 unsigned char MiscOutReg; 551 uint8_t CRTC[0xa0]; 552 uint8_t CR58[0x10]; 553 uint8_t Sequencer[5]; 554 uint8_t Graphics[9]; 555 uint8_t Attribute[21]; 556 unsigned char DAC[768]; 557 558 /* PCRTC regs */ 559 uint32_t fb_start; 560 uint32_t crtc_cfg; 561 uint32_t cursor_cfg; 562 uint32_t gpio_ext; 563 uint32_t crtc_830; 564 uint32_t crtc_834; 565 uint32_t crtc_850; 566 uint32_t crtc_eng_ctrl; 567 568 /* PRAMDAC regs */ 569 uint32_t nv10_cursync; 570 struct nouveau_pll_vals pllvals; 571 uint32_t ramdac_gen_ctrl; 572 uint32_t ramdac_630; 573 uint32_t ramdac_634; 574 uint32_t tv_setup; 575 uint32_t tv_vtotal; 576 uint32_t tv_vskew; 577 uint32_t tv_vsync_delay; 578 uint32_t tv_htotal; 579 uint32_t tv_hskew; 580 uint32_t tv_hsync_delay; 581 uint32_t tv_hsync_delay2; 582 uint32_t fp_horiz_regs[7]; 583 uint32_t fp_vert_regs[7]; 584 uint32_t dither; 585 uint32_t fp_control; 586 uint32_t dither_regs[6]; 587 uint32_t fp_debug_0; 588 uint32_t fp_debug_1; 589 uint32_t fp_debug_2; 590 uint32_t fp_margin_color; 591 uint32_t ramdac_8c0; 592 uint32_t ramdac_a20; 593 uint32_t ramdac_a24; 594 uint32_t ramdac_a34; 595 uint32_t ctv_regs[38]; 596}; 597 598struct nv04_output_reg { 599 uint32_t output; 600 int head; 601}; 602 603struct nv04_mode_state { 604 struct nv04_crtc_reg crtc_reg[2]; 605 uint32_t pllsel; 606 uint32_t sel_clk; 607}; 608 609enum nouveau_card_type { 610 NV_04 = 0x00, 611 NV_10 = 0x10, 612 NV_20 = 0x20, 613 NV_30 = 0x30, 614 NV_40 = 0x40, 615 NV_50 = 0x50, 616 NV_C0 = 0xc0, 617}; 618 619struct drm_nouveau_private { 620 struct drm_device *dev; 621 622 /* the card type, takes NV_* as values */ 623 enum nouveau_card_type card_type; 624 /* exact chipset, derived from NV_PMC_BOOT_0 */ 625 int chipset; 626 int flags; 627 628 void __iomem *mmio; 629 630 spinlock_t ramin_lock; 631 void __iomem *ramin; 632 u32 ramin_size; 633 u32 ramin_base; 634 bool ramin_available; 635 struct drm_mm ramin_heap; 636 struct list_head gpuobj_list; 637 struct list_head classes; 638 639 struct nouveau_bo *vga_ram; 640 641 /* interrupt handling */ 642 void (*irq_handler[32])(struct drm_device *); 643 bool msi_enabled; 644 struct workqueue_struct *wq; 645 struct work_struct irq_work; 646 647 struct list_head vbl_waiting; 648 649 struct { 650 struct drm_global_reference mem_global_ref; 651 struct ttm_bo_global_ref bo_global_ref; 652 struct ttm_bo_device bdev; 653 atomic_t validate_sequence; 654 } ttm; 655 656 struct { 657 spinlock_t lock; 658 struct drm_mm heap; 659 struct nouveau_bo *bo; 660 } fence; 661 662 struct { 663 spinlock_t lock; 664 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 665 } channels; 666 667 struct nouveau_engine engine; 668 struct nouveau_channel *channel; 669 670 /* For PFIFO and PGRAPH. */ 671 spinlock_t context_switch_lock; 672 673 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 674 struct nouveau_ramht *ramht; 675 struct nouveau_gpuobj *ramfc; 676 struct nouveau_gpuobj *ramro; 677 678 uint32_t ramin_rsvd_vram; 679 680 struct { 681 enum { 682 NOUVEAU_GART_NONE = 0, 683 NOUVEAU_GART_AGP, 684 NOUVEAU_GART_SGDMA 685 } type; 686 uint64_t aper_base; 687 uint64_t aper_size; 688 uint64_t aper_free; 689 690 struct nouveau_gpuobj *sg_ctxdma; 691 } gart_info; 692 693 /* nv10-nv40 tiling regions */ 694 struct { 695 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 696 spinlock_t lock; 697 } tile; 698 699 /* VRAM/fb configuration */ 700 uint64_t vram_size; 701 uint64_t vram_sys_base; 702 u32 vram_rblock_size; 703 704 uint64_t fb_phys; 705 uint64_t fb_available_size; 706 uint64_t fb_mappable_pages; 707 uint64_t fb_aper_free; 708 int fb_mtrr; 709 710 /* BAR control (NV50-) */ 711 struct nouveau_vm *bar1_vm; 712 struct nouveau_vm *bar3_vm; 713 714 /* G8x/G9x virtual address space */ 715 uint64_t vm_gart_base; 716 uint64_t vm_gart_size; 717 uint64_t vm_vram_base; 718 uint64_t vm_vram_size; 719 uint64_t vm_end; 720 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; 721 int vm_vram_pt_nr; 722 723 struct nvbios vbios; 724 725 struct nv04_mode_state mode_reg; 726 struct nv04_mode_state saved_reg; 727 uint32_t saved_vga_font[4][16384]; 728 uint32_t crtc_owner; 729 uint32_t dac_users[4]; 730 731 struct nouveau_suspend_resume { 732 uint32_t *ramin_copy; 733 } susres; 734 735 struct backlight_device *backlight; 736 737 struct nouveau_channel *evo; 738 u32 evo_alloc; 739 struct { 740 struct dcb_entry *dcb; 741 u16 script; 742 u32 pclk; 743 } evo_irq; 744 745 struct { 746 struct dentry *channel_root; 747 } debugfs; 748 749 struct nouveau_fbdev *nfbdev; 750 struct apertures_struct *apertures; 751}; 752 753static inline struct drm_nouveau_private * 754nouveau_private(struct drm_device *dev) 755{ 756 return dev->dev_private; 757} 758 759static inline struct drm_nouveau_private * 760nouveau_bdev(struct ttm_bo_device *bd) 761{ 762 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 763} 764 765static inline int 766nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 767{ 768 struct nouveau_bo *prev; 769 770 if (!pnvbo) 771 return -EINVAL; 772 prev = *pnvbo; 773 774 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 775 if (prev) { 776 struct ttm_buffer_object *bo = &prev->bo; 777 778 ttm_bo_unref(&bo); 779 } 780 781 return 0; 782} 783 784/* nouveau_drv.c */ 785extern int nouveau_agpmode; 786extern int nouveau_duallink; 787extern int nouveau_uscript_lvds; 788extern int nouveau_uscript_tmds; 789extern int nouveau_vram_pushbuf; 790extern int nouveau_vram_notify; 791extern int nouveau_fbpercrtc; 792extern int nouveau_tv_disable; 793extern char *nouveau_tv_norm; 794extern int nouveau_reg_debug; 795extern char *nouveau_vbios; 796extern int nouveau_ignorelid; 797extern int nouveau_nofbaccel; 798extern int nouveau_noaccel; 799extern int nouveau_force_post; 800extern int nouveau_override_conntype; 801extern char *nouveau_perflvl; 802extern int nouveau_perflvl_wr; 803extern int nouveau_msi; 804 805extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 806extern int nouveau_pci_resume(struct pci_dev *pdev); 807 808/* nouveau_state.c */ 809extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 810extern int nouveau_load(struct drm_device *, unsigned long flags); 811extern int nouveau_firstopen(struct drm_device *); 812extern void nouveau_lastclose(struct drm_device *); 813extern int nouveau_unload(struct drm_device *); 814extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 815 struct drm_file *); 816extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 817 struct drm_file *); 818extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 819 uint32_t reg, uint32_t mask, uint32_t val); 820extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 821 uint32_t reg, uint32_t mask, uint32_t val); 822extern bool nouveau_wait_for_idle(struct drm_device *); 823extern int nouveau_card_init(struct drm_device *); 824 825/* nouveau_mem.c */ 826extern int nouveau_mem_vram_init(struct drm_device *); 827extern void nouveau_mem_vram_fini(struct drm_device *); 828extern int nouveau_mem_gart_init(struct drm_device *); 829extern void nouveau_mem_gart_fini(struct drm_device *); 830extern int nouveau_mem_init_agp(struct drm_device *); 831extern int nouveau_mem_reset_agp(struct drm_device *); 832extern void nouveau_mem_close(struct drm_device *); 833extern struct nouveau_tile_reg *nv10_mem_set_tiling( 834 struct drm_device *dev, uint32_t addr, uint32_t size, 835 uint32_t pitch, uint32_t flags); 836extern void nv10_mem_put_tile_region(struct drm_device *dev, 837 struct nouveau_tile_reg *tile, 838 struct nouveau_fence *fence); 839extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, 840 uint32_t size, uint32_t flags, 841 uint64_t phys); 842extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, 843 uint32_t size); 844extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 845 846/* nouveau_notifier.c */ 847extern int nouveau_notifier_init_channel(struct nouveau_channel *); 848extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 849extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 850 int cout, uint32_t *offset); 851extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 852extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 853 struct drm_file *); 854extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 855 struct drm_file *); 856 857/* nouveau_channel.c */ 858extern struct drm_ioctl_desc nouveau_ioctls[]; 859extern int nouveau_max_ioctl; 860extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 861extern int nouveau_channel_alloc(struct drm_device *dev, 862 struct nouveau_channel **chan, 863 struct drm_file *file_priv, 864 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 865extern struct nouveau_channel * 866nouveau_channel_get_unlocked(struct nouveau_channel *); 867extern struct nouveau_channel * 868nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 869extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 870extern void nouveau_channel_put(struct nouveau_channel **); 871extern void nouveau_channel_ref(struct nouveau_channel *chan, 872 struct nouveau_channel **pchan); 873extern void nouveau_channel_idle(struct nouveau_channel *chan); 874 875/* nouveau_object.c */ 876#define NVOBJ_CLASS(d,c,e) do { \ 877 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 878 if (ret) \ 879 return ret; \ 880} while(0) 881 882#define NVOBJ_MTHD(d,c,m,e) do { \ 883 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 884 if (ret) \ 885 return ret; \ 886} while(0) 887 888extern int nouveau_gpuobj_early_init(struct drm_device *); 889extern int nouveau_gpuobj_init(struct drm_device *); 890extern void nouveau_gpuobj_takedown(struct drm_device *); 891extern int nouveau_gpuobj_suspend(struct drm_device *dev); 892extern void nouveau_gpuobj_resume(struct drm_device *dev); 893extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 894extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 895 int (*exec)(struct nouveau_channel *, 896 u32 class, u32 mthd, u32 data)); 897extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 898extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 899extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 900 uint32_t vram_h, uint32_t tt_h); 901extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 902extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 903 uint32_t size, int align, uint32_t flags, 904 struct nouveau_gpuobj **); 905extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 906 struct nouveau_gpuobj **); 907extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 908 u32 size, u32 flags, 909 struct nouveau_gpuobj **); 910extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 911 uint64_t offset, uint64_t size, int access, 912 int target, struct nouveau_gpuobj **); 913extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 914extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 915 u64 size, int target, int access, u32 type, 916 u32 comp, struct nouveau_gpuobj **pobj); 917extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 918 int class, u64 base, u64 size, int target, 919 int access, u32 type, u32 comp); 920extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 921 struct drm_file *); 922extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 923 struct drm_file *); 924 925/* nouveau_irq.c */ 926extern int nouveau_irq_init(struct drm_device *); 927extern void nouveau_irq_fini(struct drm_device *); 928extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 929extern void nouveau_irq_register(struct drm_device *, int status_bit, 930 void (*)(struct drm_device *)); 931extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 932extern void nouveau_irq_preinstall(struct drm_device *); 933extern int nouveau_irq_postinstall(struct drm_device *); 934extern void nouveau_irq_uninstall(struct drm_device *); 935 936/* nouveau_sgdma.c */ 937extern int nouveau_sgdma_init(struct drm_device *); 938extern void nouveau_sgdma_takedown(struct drm_device *); 939extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, 940 uint32_t *page); 941extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 942 943/* nouveau_debugfs.c */ 944#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 945extern int nouveau_debugfs_init(struct drm_minor *); 946extern void nouveau_debugfs_takedown(struct drm_minor *); 947extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 948extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 949#else 950static inline int 951nouveau_debugfs_init(struct drm_minor *minor) 952{ 953 return 0; 954} 955 956static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 957{ 958} 959 960static inline int 961nouveau_debugfs_channel_init(struct nouveau_channel *chan) 962{ 963 return 0; 964} 965 966static inline void 967nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 968{ 969} 970#endif 971 972/* nouveau_dma.c */ 973extern void nouveau_dma_pre_init(struct nouveau_channel *); 974extern int nouveau_dma_init(struct nouveau_channel *); 975extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 976 977/* nouveau_acpi.c */ 978#define ROM_BIOS_PAGE 4096 979#if defined(CONFIG_ACPI) 980void nouveau_register_dsm_handler(void); 981void nouveau_unregister_dsm_handler(void); 982int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 983bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 984int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 985#else 986static inline void nouveau_register_dsm_handler(void) {} 987static inline void nouveau_unregister_dsm_handler(void) {} 988static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 989static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 990static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 991#endif 992 993/* nouveau_backlight.c */ 994#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 995extern int nouveau_backlight_init(struct drm_device *); 996extern void nouveau_backlight_exit(struct drm_device *); 997#else 998static inline int nouveau_backlight_init(struct drm_device *dev) 999{ 1000 return 0; 1001} 1002 1003static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1004#endif 1005 1006/* nouveau_bios.c */ 1007extern int nouveau_bios_init(struct drm_device *); 1008extern void nouveau_bios_takedown(struct drm_device *dev); 1009extern int nouveau_run_vbios_init(struct drm_device *); 1010extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1011 struct dcb_entry *); 1012extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1013 enum dcb_gpio_tag); 1014extern struct dcb_connector_table_entry * 1015nouveau_bios_connector_entry(struct drm_device *, int index); 1016extern u32 get_pll_register(struct drm_device *, enum pll_types); 1017extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1018 struct pll_lims *); 1019extern int nouveau_bios_run_display_table(struct drm_device *, 1020 struct dcb_entry *, 1021 uint32_t script, int pxclk); 1022extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1023 int *length); 1024extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1025extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1026extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1027 bool *dl, bool *if_is_24bit); 1028extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1029 int head, int pxclk); 1030extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1031 enum LVDS_script, int pxclk); 1032 1033/* nouveau_ttm.c */ 1034int nouveau_ttm_global_init(struct drm_nouveau_private *); 1035void nouveau_ttm_global_release(struct drm_nouveau_private *); 1036int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1037 1038/* nouveau_dp.c */ 1039int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1040 uint8_t *data, int data_nr); 1041bool nouveau_dp_detect(struct drm_encoder *); 1042bool nouveau_dp_link_train(struct drm_encoder *); 1043 1044/* nv04_fb.c */ 1045extern int nv04_fb_init(struct drm_device *); 1046extern void nv04_fb_takedown(struct drm_device *); 1047 1048/* nv10_fb.c */ 1049extern int nv10_fb_init(struct drm_device *); 1050extern void nv10_fb_takedown(struct drm_device *); 1051extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1052 uint32_t addr, uint32_t size, 1053 uint32_t pitch, uint32_t flags); 1054extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1055extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1056 1057/* nv30_fb.c */ 1058extern int nv30_fb_init(struct drm_device *); 1059extern void nv30_fb_takedown(struct drm_device *); 1060extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1061 uint32_t addr, uint32_t size, 1062 uint32_t pitch, uint32_t flags); 1063extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1064 1065/* nv40_fb.c */ 1066extern int nv40_fb_init(struct drm_device *); 1067extern void nv40_fb_takedown(struct drm_device *); 1068extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1069 1070/* nv50_fb.c */ 1071extern int nv50_fb_init(struct drm_device *); 1072extern void nv50_fb_takedown(struct drm_device *); 1073extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1074 1075/* nvc0_fb.c */ 1076extern int nvc0_fb_init(struct drm_device *); 1077extern void nvc0_fb_takedown(struct drm_device *); 1078 1079/* nv04_fifo.c */ 1080extern int nv04_fifo_init(struct drm_device *); 1081extern void nv04_fifo_fini(struct drm_device *); 1082extern void nv04_fifo_disable(struct drm_device *); 1083extern void nv04_fifo_enable(struct drm_device *); 1084extern bool nv04_fifo_reassign(struct drm_device *, bool); 1085extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1086extern int nv04_fifo_channel_id(struct drm_device *); 1087extern int nv04_fifo_create_context(struct nouveau_channel *); 1088extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1089extern int nv04_fifo_load_context(struct nouveau_channel *); 1090extern int nv04_fifo_unload_context(struct drm_device *); 1091extern void nv04_fifo_isr(struct drm_device *); 1092 1093/* nv10_fifo.c */ 1094extern int nv10_fifo_init(struct drm_device *); 1095extern int nv10_fifo_channel_id(struct drm_device *); 1096extern int nv10_fifo_create_context(struct nouveau_channel *); 1097extern int nv10_fifo_load_context(struct nouveau_channel *); 1098extern int nv10_fifo_unload_context(struct drm_device *); 1099 1100/* nv40_fifo.c */ 1101extern int nv40_fifo_init(struct drm_device *); 1102extern int nv40_fifo_create_context(struct nouveau_channel *); 1103extern int nv40_fifo_load_context(struct nouveau_channel *); 1104extern int nv40_fifo_unload_context(struct drm_device *); 1105 1106/* nv50_fifo.c */ 1107extern int nv50_fifo_init(struct drm_device *); 1108extern void nv50_fifo_takedown(struct drm_device *); 1109extern int nv50_fifo_channel_id(struct drm_device *); 1110extern int nv50_fifo_create_context(struct nouveau_channel *); 1111extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1112extern int nv50_fifo_load_context(struct nouveau_channel *); 1113extern int nv50_fifo_unload_context(struct drm_device *); 1114extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1115 1116/* nvc0_fifo.c */ 1117extern int nvc0_fifo_init(struct drm_device *); 1118extern void nvc0_fifo_takedown(struct drm_device *); 1119extern void nvc0_fifo_disable(struct drm_device *); 1120extern void nvc0_fifo_enable(struct drm_device *); 1121extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1122extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1123extern int nvc0_fifo_channel_id(struct drm_device *); 1124extern int nvc0_fifo_create_context(struct nouveau_channel *); 1125extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1126extern int nvc0_fifo_load_context(struct nouveau_channel *); 1127extern int nvc0_fifo_unload_context(struct drm_device *); 1128 1129/* nv04_graph.c */ 1130extern int nv04_graph_init(struct drm_device *); 1131extern void nv04_graph_takedown(struct drm_device *); 1132extern void nv04_graph_fifo_access(struct drm_device *, bool); 1133extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1134extern int nv04_graph_create_context(struct nouveau_channel *); 1135extern void nv04_graph_destroy_context(struct nouveau_channel *); 1136extern int nv04_graph_load_context(struct nouveau_channel *); 1137extern int nv04_graph_unload_context(struct drm_device *); 1138extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1139 u32 class, u32 mthd, u32 data); 1140extern struct nouveau_bitfield nv04_graph_nsource[]; 1141 1142/* nv10_graph.c */ 1143extern int nv10_graph_init(struct drm_device *); 1144extern void nv10_graph_takedown(struct drm_device *); 1145extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1146extern int nv10_graph_create_context(struct nouveau_channel *); 1147extern void nv10_graph_destroy_context(struct nouveau_channel *); 1148extern int nv10_graph_load_context(struct nouveau_channel *); 1149extern int nv10_graph_unload_context(struct drm_device *); 1150extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1151extern struct nouveau_bitfield nv10_graph_intr[]; 1152extern struct nouveau_bitfield nv10_graph_nstatus[]; 1153 1154/* nv20_graph.c */ 1155extern int nv20_graph_create_context(struct nouveau_channel *); 1156extern void nv20_graph_destroy_context(struct nouveau_channel *); 1157extern int nv20_graph_load_context(struct nouveau_channel *); 1158extern int nv20_graph_unload_context(struct drm_device *); 1159extern int nv20_graph_init(struct drm_device *); 1160extern void nv20_graph_takedown(struct drm_device *); 1161extern int nv30_graph_init(struct drm_device *); 1162extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1163 1164/* nv40_graph.c */ 1165extern int nv40_graph_init(struct drm_device *); 1166extern void nv40_graph_takedown(struct drm_device *); 1167extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1168extern int nv40_graph_create_context(struct nouveau_channel *); 1169extern void nv40_graph_destroy_context(struct nouveau_channel *); 1170extern int nv40_graph_load_context(struct nouveau_channel *); 1171extern int nv40_graph_unload_context(struct drm_device *); 1172extern void nv40_grctx_init(struct nouveau_grctx *); 1173extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1174 1175/* nv50_graph.c */ 1176extern int nv50_graph_init(struct drm_device *); 1177extern void nv50_graph_takedown(struct drm_device *); 1178extern void nv50_graph_fifo_access(struct drm_device *, bool); 1179extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1180extern int nv50_graph_create_context(struct nouveau_channel *); 1181extern void nv50_graph_destroy_context(struct nouveau_channel *); 1182extern int nv50_graph_load_context(struct nouveau_channel *); 1183extern int nv50_graph_unload_context(struct drm_device *); 1184extern int nv50_grctx_init(struct nouveau_grctx *); 1185extern void nv50_graph_tlb_flush(struct drm_device *dev); 1186extern void nv86_graph_tlb_flush(struct drm_device *dev); 1187 1188/* nvc0_graph.c */ 1189extern int nvc0_graph_init(struct drm_device *); 1190extern void nvc0_graph_takedown(struct drm_device *); 1191extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1192extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1193extern int nvc0_graph_create_context(struct nouveau_channel *); 1194extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1195extern int nvc0_graph_load_context(struct nouveau_channel *); 1196extern int nvc0_graph_unload_context(struct drm_device *); 1197 1198/* nv84_crypt.c */ 1199extern int nv84_crypt_init(struct drm_device *dev); 1200extern void nv84_crypt_fini(struct drm_device *dev); 1201extern int nv84_crypt_create_context(struct nouveau_channel *); 1202extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1203extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1204 1205/* nv04_instmem.c */ 1206extern int nv04_instmem_init(struct drm_device *); 1207extern void nv04_instmem_takedown(struct drm_device *); 1208extern int nv04_instmem_suspend(struct drm_device *); 1209extern void nv04_instmem_resume(struct drm_device *); 1210extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1211extern void nv04_instmem_put(struct nouveau_gpuobj *); 1212extern int nv04_instmem_map(struct nouveau_gpuobj *); 1213extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1214extern void nv04_instmem_flush(struct drm_device *); 1215 1216/* nv50_instmem.c */ 1217extern int nv50_instmem_init(struct drm_device *); 1218extern void nv50_instmem_takedown(struct drm_device *); 1219extern int nv50_instmem_suspend(struct drm_device *); 1220extern void nv50_instmem_resume(struct drm_device *); 1221extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1222extern void nv50_instmem_put(struct nouveau_gpuobj *); 1223extern int nv50_instmem_map(struct nouveau_gpuobj *); 1224extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1225extern void nv50_instmem_flush(struct drm_device *); 1226extern void nv84_instmem_flush(struct drm_device *); 1227 1228/* nvc0_instmem.c */ 1229extern int nvc0_instmem_init(struct drm_device *); 1230extern void nvc0_instmem_takedown(struct drm_device *); 1231extern int nvc0_instmem_suspend(struct drm_device *); 1232extern void nvc0_instmem_resume(struct drm_device *); 1233extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1234extern void nvc0_instmem_put(struct nouveau_gpuobj *); 1235extern int nvc0_instmem_map(struct nouveau_gpuobj *); 1236extern void nvc0_instmem_unmap(struct nouveau_gpuobj *); 1237extern void nvc0_instmem_flush(struct drm_device *); 1238 1239/* nv04_mc.c */ 1240extern int nv04_mc_init(struct drm_device *); 1241extern void nv04_mc_takedown(struct drm_device *); 1242 1243/* nv40_mc.c */ 1244extern int nv40_mc_init(struct drm_device *); 1245extern void nv40_mc_takedown(struct drm_device *); 1246 1247/* nv50_mc.c */ 1248extern int nv50_mc_init(struct drm_device *); 1249extern void nv50_mc_takedown(struct drm_device *); 1250 1251/* nv04_timer.c */ 1252extern int nv04_timer_init(struct drm_device *); 1253extern uint64_t nv04_timer_read(struct drm_device *); 1254extern void nv04_timer_takedown(struct drm_device *); 1255 1256extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1257 unsigned long arg); 1258 1259/* nv04_dac.c */ 1260extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1261extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1262extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1263extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1264extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1265 1266/* nv04_dfp.c */ 1267extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1268extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1269extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1270 int head, bool dl); 1271extern void nv04_dfp_disable(struct drm_device *dev, int head); 1272extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1273 1274/* nv04_tv.c */ 1275extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1276extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1277 1278/* nv17_tv.c */ 1279extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1280 1281/* nv04_display.c */ 1282extern int nv04_display_early_init(struct drm_device *); 1283extern void nv04_display_late_takedown(struct drm_device *); 1284extern int nv04_display_create(struct drm_device *); 1285extern int nv04_display_init(struct drm_device *); 1286extern void nv04_display_destroy(struct drm_device *); 1287 1288/* nv04_crtc.c */ 1289extern int nv04_crtc_create(struct drm_device *, int index); 1290 1291/* nouveau_bo.c */ 1292extern struct ttm_bo_driver nouveau_bo_driver; 1293extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1294 int size, int align, uint32_t flags, 1295 uint32_t tile_mode, uint32_t tile_flags, 1296 bool no_vm, bool mappable, struct nouveau_bo **); 1297extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1298extern int nouveau_bo_unpin(struct nouveau_bo *); 1299extern int nouveau_bo_map(struct nouveau_bo *); 1300extern void nouveau_bo_unmap(struct nouveau_bo *); 1301extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1302 uint32_t busy); 1303extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1304extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1305extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1306extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1307extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1308extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1309 bool no_wait_reserve, bool no_wait_gpu); 1310 1311/* nouveau_fence.c */ 1312struct nouveau_fence; 1313extern int nouveau_fence_init(struct drm_device *); 1314extern void nouveau_fence_fini(struct drm_device *); 1315extern int nouveau_fence_channel_init(struct nouveau_channel *); 1316extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1317extern void nouveau_fence_update(struct nouveau_channel *); 1318extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1319 bool emit); 1320extern int nouveau_fence_emit(struct nouveau_fence *); 1321extern void nouveau_fence_work(struct nouveau_fence *fence, 1322 void (*work)(void *priv, bool signalled), 1323 void *priv); 1324struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1325 1326extern bool __nouveau_fence_signalled(void *obj, void *arg); 1327extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1328extern int __nouveau_fence_flush(void *obj, void *arg); 1329extern void __nouveau_fence_unref(void **obj); 1330extern void *__nouveau_fence_ref(void *obj); 1331 1332static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1333{ 1334 return __nouveau_fence_signalled(obj, NULL); 1335} 1336static inline int 1337nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1338{ 1339 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1340} 1341extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1342static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1343{ 1344 return __nouveau_fence_flush(obj, NULL); 1345} 1346static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1347{ 1348 __nouveau_fence_unref((void **)obj); 1349} 1350static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1351{ 1352 return __nouveau_fence_ref(obj); 1353} 1354 1355/* nouveau_gem.c */ 1356extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1357 int size, int align, uint32_t flags, 1358 uint32_t tile_mode, uint32_t tile_flags, 1359 bool no_vm, bool mappable, struct nouveau_bo **); 1360extern int nouveau_gem_object_new(struct drm_gem_object *); 1361extern void nouveau_gem_object_del(struct drm_gem_object *); 1362extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1363 struct drm_file *); 1364extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1365 struct drm_file *); 1366extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1367 struct drm_file *); 1368extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1369 struct drm_file *); 1370extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1371 struct drm_file *); 1372 1373/* nouveau_display.c */ 1374int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1375void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1376int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1377 struct drm_pending_vblank_event *event); 1378int nouveau_finish_page_flip(struct nouveau_channel *, 1379 struct nouveau_page_flip_state *); 1380 1381/* nv10_gpio.c */ 1382int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1383int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1384 1385/* nv50_gpio.c */ 1386int nv50_gpio_init(struct drm_device *dev); 1387void nv50_gpio_fini(struct drm_device *dev); 1388int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1389int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1390int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1391 void (*)(void *, int), void *); 1392void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1393 void (*)(void *, int), void *); 1394bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1395 1396/* nv50_calc. */ 1397int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1398 int *N1, int *M1, int *N2, int *M2, int *P); 1399int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1400 int clk, int *N, int *fN, int *M, int *P); 1401 1402#ifndef ioread32_native 1403#ifdef __BIG_ENDIAN 1404#define ioread16_native ioread16be 1405#define iowrite16_native iowrite16be 1406#define ioread32_native ioread32be 1407#define iowrite32_native iowrite32be 1408#else /* def __BIG_ENDIAN */ 1409#define ioread16_native ioread16 1410#define iowrite16_native iowrite16 1411#define ioread32_native ioread32 1412#define iowrite32_native iowrite32 1413#endif /* def __BIG_ENDIAN else */ 1414#endif /* !ioread32_native */ 1415 1416/* channel control reg access */ 1417static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1418{ 1419 return ioread32_native(chan->user + reg); 1420} 1421 1422static inline void nvchan_wr32(struct nouveau_channel *chan, 1423 unsigned reg, u32 val) 1424{ 1425 iowrite32_native(val, chan->user + reg); 1426} 1427 1428/* register access */ 1429static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1430{ 1431 struct drm_nouveau_private *dev_priv = dev->dev_private; 1432 return ioread32_native(dev_priv->mmio + reg); 1433} 1434 1435static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1436{ 1437 struct drm_nouveau_private *dev_priv = dev->dev_private; 1438 iowrite32_native(val, dev_priv->mmio + reg); 1439} 1440 1441static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1442{ 1443 u32 tmp = nv_rd32(dev, reg); 1444 nv_wr32(dev, reg, (tmp & ~mask) | val); 1445 return tmp; 1446} 1447 1448static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1449{ 1450 struct drm_nouveau_private *dev_priv = dev->dev_private; 1451 return ioread8(dev_priv->mmio + reg); 1452} 1453 1454static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1455{ 1456 struct drm_nouveau_private *dev_priv = dev->dev_private; 1457 iowrite8(val, dev_priv->mmio + reg); 1458} 1459 1460#define nv_wait(dev, reg, mask, val) \ 1461 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1462#define nv_wait_ne(dev, reg, mask, val) \ 1463 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1464 1465/* PRAMIN access */ 1466static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1467{ 1468 struct drm_nouveau_private *dev_priv = dev->dev_private; 1469 return ioread32_native(dev_priv->ramin + offset); 1470} 1471 1472static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1473{ 1474 struct drm_nouveau_private *dev_priv = dev->dev_private; 1475 iowrite32_native(val, dev_priv->ramin + offset); 1476} 1477 1478/* object access */ 1479extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1480extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1481 1482/* 1483 * Logging 1484 * Argument d is (struct drm_device *). 1485 */ 1486#define NV_PRINTK(level, d, fmt, arg...) \ 1487 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1488 pci_name(d->pdev), ##arg) 1489#ifndef NV_DEBUG_NOTRACE 1490#define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) { \ 1492 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1493 __LINE__, ##arg); \ 1494 } \ 1495} while (0) 1496#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1497 if (drm_debug & DRM_UT_KMS) { \ 1498 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1499 __LINE__, ##arg); \ 1500 } \ 1501} while (0) 1502#else 1503#define NV_DEBUG(d, fmt, arg...) do { \ 1504 if (drm_debug & DRM_UT_DRIVER) \ 1505 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1506} while (0) 1507#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1508 if (drm_debug & DRM_UT_KMS) \ 1509 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1510} while (0) 1511#endif 1512#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1513#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1514#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1515#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1516#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1517 1518/* nouveau_reg_debug bitmask */ 1519enum { 1520 NOUVEAU_REG_DEBUG_MC = 0x1, 1521 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1522 NOUVEAU_REG_DEBUG_FB = 0x4, 1523 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1524 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1525 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1526 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1527 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1528 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1529 NOUVEAU_REG_DEBUG_EVO = 0x200, 1530}; 1531 1532#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1533 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1534 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1535} while (0) 1536 1537static inline bool 1538nv_two_heads(struct drm_device *dev) 1539{ 1540 struct drm_nouveau_private *dev_priv = dev->dev_private; 1541 const int impl = dev->pci_device & 0x0ff0; 1542 1543 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1544 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1545 return true; 1546 1547 return false; 1548} 1549 1550static inline bool 1551nv_gf4_disp_arch(struct drm_device *dev) 1552{ 1553 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1554} 1555 1556static inline bool 1557nv_two_reg_pll(struct drm_device *dev) 1558{ 1559 struct drm_nouveau_private *dev_priv = dev->dev_private; 1560 const int impl = dev->pci_device & 0x0ff0; 1561 1562 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1563 return true; 1564 return false; 1565} 1566 1567static inline bool 1568nv_match_device(struct drm_device *dev, unsigned device, 1569 unsigned sub_vendor, unsigned sub_device) 1570{ 1571 return dev->pdev->device == device && 1572 dev->pdev->subsystem_vendor == sub_vendor && 1573 dev->pdev->subsystem_device == sub_device; 1574} 1575 1576/* memory type/access flags, do not match hardware values */ 1577#define NV_MEM_ACCESS_RO 1 1578#define NV_MEM_ACCESS_WO 2 1579#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1580#define NV_MEM_ACCESS_SYS 4 1581#define NV_MEM_ACCESS_VM 8 1582 1583#define NV_MEM_TARGET_VRAM 0 1584#define NV_MEM_TARGET_PCI 1 1585#define NV_MEM_TARGET_PCI_NOSNOOP 2 1586#define NV_MEM_TARGET_VM 3 1587#define NV_MEM_TARGET_GART 4 1588 1589#define NV_MEM_TYPE_VM 0x7f 1590#define NV_MEM_COMP_VM 0x03 1591 1592/* NV_SW object class */ 1593#define NV_SW 0x0000506e 1594#define NV_SW_DMA_SEMAPHORE 0x00000060 1595#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1596#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1597#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1598#define NV_SW_YIELD 0x00000080 1599#define NV_SW_DMA_VBLSEM 0x0000018c 1600#define NV_SW_VBLSEM_OFFSET 0x00000400 1601#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1602#define NV_SW_VBLSEM_RELEASE 0x00000408 1603#define NV_SW_PAGE_FLIP 0x00000500 1604 1605#endif /* __NOUVEAU_DRV_H__ */ 1606