nouveau_drv.h revision f91bac5bf694e8060b7473fb0aefb8de09aa9595
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma tmp_vma; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_DISPLAY 15 167#define NVOBJ_ENGINE_NR 16 168 169#define NVOBJ_FLAG_DONT_MAP (1 << 0) 170#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172#define NVOBJ_FLAG_VM (1 << 3) 173#define NVOBJ_FLAG_VM_USER (1 << 4) 174 175#define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198}; 199 200struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205}; 206 207enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210}; 211 212struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 } fence; 243 244 /* DMA push buffer */ 245 struct nouveau_gpuobj *pushbuf; 246 struct nouveau_bo *pushbuf_bo; 247 uint32_t pushbuf_base; 248 249 /* Notifier memory */ 250 struct nouveau_bo *notifier_bo; 251 struct drm_mm notifier_heap; 252 253 /* PFIFO context */ 254 struct nouveau_gpuobj *ramfc; 255 struct nouveau_gpuobj *cache; 256 void *fifo_priv; 257 258 /* Execution engine contexts */ 259 void *engctx[NVOBJ_ENGINE_NR]; 260 261 /* NV50 VM */ 262 struct nouveau_vm *vm; 263 struct nouveau_gpuobj *vm_pd; 264 265 /* Objects */ 266 struct nouveau_gpuobj *ramin; /* Private instmem */ 267 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 268 struct nouveau_ramht *ramht; /* Hash table */ 269 270 /* GPU object info for stuff used in-kernel (mm_enabled) */ 271 uint32_t m2mf_ntfy; 272 uint32_t vram_handle; 273 uint32_t gart_handle; 274 bool accel_done; 275 276 /* Push buffer state (only for drm's channel on !mm_enabled) */ 277 struct { 278 int max; 279 int free; 280 int cur; 281 int put; 282 /* access via pushbuf_bo */ 283 284 int ib_base; 285 int ib_max; 286 int ib_free; 287 int ib_put; 288 } dma; 289 290 uint32_t sw_subchannel[8]; 291 292 struct { 293 struct nouveau_gpuobj *vblsem; 294 uint32_t vblsem_head; 295 uint32_t vblsem_offset; 296 uint32_t vblsem_rval; 297 struct list_head vbl_wait; 298 struct list_head flip; 299 } nvsw; 300 301 struct { 302 bool active; 303 char name[32]; 304 struct drm_info_list info; 305 } debugfs; 306}; 307 308struct nouveau_exec_engine { 309 void (*destroy)(struct drm_device *, int engine); 310 int (*init)(struct drm_device *, int engine); 311 int (*fini)(struct drm_device *, int engine); 312 int (*context_new)(struct nouveau_channel *, int engine); 313 void (*context_del)(struct nouveau_channel *, int engine); 314 int (*object_new)(struct nouveau_channel *, int engine, 315 u32 handle, u16 class); 316 void (*set_tile_region)(struct drm_device *dev, int i); 317 void (*tlb_flush)(struct drm_device *, int engine); 318}; 319 320struct nouveau_instmem_engine { 321 void *priv; 322 323 int (*init)(struct drm_device *dev); 324 void (*takedown)(struct drm_device *dev); 325 int (*suspend)(struct drm_device *dev); 326 void (*resume)(struct drm_device *dev); 327 328 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 329 u32 size, u32 align); 330 void (*put)(struct nouveau_gpuobj *); 331 int (*map)(struct nouveau_gpuobj *); 332 void (*unmap)(struct nouveau_gpuobj *); 333 334 void (*flush)(struct drm_device *); 335}; 336 337struct nouveau_mc_engine { 338 int (*init)(struct drm_device *dev); 339 void (*takedown)(struct drm_device *dev); 340}; 341 342struct nouveau_timer_engine { 343 int (*init)(struct drm_device *dev); 344 void (*takedown)(struct drm_device *dev); 345 uint64_t (*read)(struct drm_device *dev); 346}; 347 348struct nouveau_fb_engine { 349 int num_tiles; 350 struct drm_mm tag_heap; 351 void *priv; 352 353 int (*init)(struct drm_device *dev); 354 void (*takedown)(struct drm_device *dev); 355 356 void (*init_tile_region)(struct drm_device *dev, int i, 357 uint32_t addr, uint32_t size, 358 uint32_t pitch, uint32_t flags); 359 void (*set_tile_region)(struct drm_device *dev, int i); 360 void (*free_tile_region)(struct drm_device *dev, int i); 361}; 362 363struct nouveau_fifo_engine { 364 void *priv; 365 int channels; 366 367 struct nouveau_gpuobj *playlist[2]; 368 int cur_playlist; 369 370 int (*init)(struct drm_device *); 371 void (*takedown)(struct drm_device *); 372 373 void (*disable)(struct drm_device *); 374 void (*enable)(struct drm_device *); 375 bool (*reassign)(struct drm_device *, bool enable); 376 bool (*cache_pull)(struct drm_device *dev, bool enable); 377 378 int (*channel_id)(struct drm_device *); 379 380 int (*create_context)(struct nouveau_channel *); 381 void (*destroy_context)(struct nouveau_channel *); 382 int (*load_context)(struct nouveau_channel *); 383 int (*unload_context)(struct drm_device *); 384 void (*tlb_flush)(struct drm_device *dev); 385}; 386 387struct nouveau_display_engine { 388 void *priv; 389 int (*early_init)(struct drm_device *); 390 void (*late_takedown)(struct drm_device *); 391 int (*create)(struct drm_device *); 392 int (*init)(struct drm_device *); 393 void (*destroy)(struct drm_device *); 394}; 395 396struct nouveau_gpio_engine { 397 void *priv; 398 399 int (*init)(struct drm_device *); 400 void (*takedown)(struct drm_device *); 401 402 int (*get)(struct drm_device *, enum dcb_gpio_tag); 403 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 404 405 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 406 void (*)(void *, int), void *); 407 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 408 void (*)(void *, int), void *); 409 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 410}; 411 412struct nouveau_pm_voltage_level { 413 u8 voltage; 414 u8 vid; 415}; 416 417struct nouveau_pm_voltage { 418 bool supported; 419 u8 vid_mask; 420 421 struct nouveau_pm_voltage_level *level; 422 int nr_level; 423}; 424 425struct nouveau_pm_memtiming { 426 int id; 427 u32 reg_100220; 428 u32 reg_100224; 429 u32 reg_100228; 430 u32 reg_10022c; 431 u32 reg_100230; 432 u32 reg_100234; 433 u32 reg_100238; 434 u32 reg_10023c; 435 u32 reg_100240; 436}; 437 438#define NOUVEAU_PM_MAX_LEVEL 8 439struct nouveau_pm_level { 440 struct device_attribute dev_attr; 441 char name[32]; 442 int id; 443 444 u32 core; 445 u32 memory; 446 u32 shader; 447 u32 unk05; 448 u32 unk0a; 449 450 u8 voltage; 451 u8 fanspeed; 452 453 u16 memscript; 454 struct nouveau_pm_memtiming *timing; 455}; 456 457struct nouveau_pm_temp_sensor_constants { 458 u16 offset_constant; 459 s16 offset_mult; 460 u16 offset_div; 461 u16 slope_mult; 462 u16 slope_div; 463}; 464 465struct nouveau_pm_threshold_temp { 466 s16 critical; 467 s16 down_clock; 468 s16 fan_boost; 469}; 470 471struct nouveau_pm_memtimings { 472 bool supported; 473 struct nouveau_pm_memtiming *timing; 474 int nr_timing; 475}; 476 477struct nouveau_pm_engine { 478 struct nouveau_pm_voltage voltage; 479 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 480 int nr_perflvl; 481 struct nouveau_pm_memtimings memtimings; 482 struct nouveau_pm_temp_sensor_constants sensor_constants; 483 struct nouveau_pm_threshold_temp threshold_temp; 484 485 struct nouveau_pm_level boot; 486 struct nouveau_pm_level *cur; 487 488 struct device *hwmon; 489 struct notifier_block acpi_nb; 490 491 int (*clock_get)(struct drm_device *, u32 id); 492 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 493 u32 id, int khz); 494 void (*clock_set)(struct drm_device *, void *); 495 int (*voltage_get)(struct drm_device *); 496 int (*voltage_set)(struct drm_device *, int voltage); 497 int (*fanspeed_get)(struct drm_device *); 498 int (*fanspeed_set)(struct drm_device *, int fanspeed); 499 int (*temp_get)(struct drm_device *); 500}; 501 502struct nouveau_vram_engine { 503 int (*init)(struct drm_device *); 504 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 505 u32 type, struct nouveau_mem **); 506 void (*put)(struct drm_device *, struct nouveau_mem **); 507 508 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 509}; 510 511struct nouveau_engine { 512 struct nouveau_instmem_engine instmem; 513 struct nouveau_mc_engine mc; 514 struct nouveau_timer_engine timer; 515 struct nouveau_fb_engine fb; 516 struct nouveau_fifo_engine fifo; 517 struct nouveau_display_engine display; 518 struct nouveau_gpio_engine gpio; 519 struct nouveau_pm_engine pm; 520 struct nouveau_vram_engine vram; 521}; 522 523struct nouveau_pll_vals { 524 union { 525 struct { 526#ifdef __BIG_ENDIAN 527 uint8_t N1, M1, N2, M2; 528#else 529 uint8_t M1, N1, M2, N2; 530#endif 531 }; 532 struct { 533 uint16_t NM1, NM2; 534 } __attribute__((packed)); 535 }; 536 int log2P; 537 538 int refclk; 539}; 540 541enum nv04_fp_display_regs { 542 FP_DISPLAY_END, 543 FP_TOTAL, 544 FP_CRTC, 545 FP_SYNC_START, 546 FP_SYNC_END, 547 FP_VALID_START, 548 FP_VALID_END 549}; 550 551struct nv04_crtc_reg { 552 unsigned char MiscOutReg; 553 uint8_t CRTC[0xa0]; 554 uint8_t CR58[0x10]; 555 uint8_t Sequencer[5]; 556 uint8_t Graphics[9]; 557 uint8_t Attribute[21]; 558 unsigned char DAC[768]; 559 560 /* PCRTC regs */ 561 uint32_t fb_start; 562 uint32_t crtc_cfg; 563 uint32_t cursor_cfg; 564 uint32_t gpio_ext; 565 uint32_t crtc_830; 566 uint32_t crtc_834; 567 uint32_t crtc_850; 568 uint32_t crtc_eng_ctrl; 569 570 /* PRAMDAC regs */ 571 uint32_t nv10_cursync; 572 struct nouveau_pll_vals pllvals; 573 uint32_t ramdac_gen_ctrl; 574 uint32_t ramdac_630; 575 uint32_t ramdac_634; 576 uint32_t tv_setup; 577 uint32_t tv_vtotal; 578 uint32_t tv_vskew; 579 uint32_t tv_vsync_delay; 580 uint32_t tv_htotal; 581 uint32_t tv_hskew; 582 uint32_t tv_hsync_delay; 583 uint32_t tv_hsync_delay2; 584 uint32_t fp_horiz_regs[7]; 585 uint32_t fp_vert_regs[7]; 586 uint32_t dither; 587 uint32_t fp_control; 588 uint32_t dither_regs[6]; 589 uint32_t fp_debug_0; 590 uint32_t fp_debug_1; 591 uint32_t fp_debug_2; 592 uint32_t fp_margin_color; 593 uint32_t ramdac_8c0; 594 uint32_t ramdac_a20; 595 uint32_t ramdac_a24; 596 uint32_t ramdac_a34; 597 uint32_t ctv_regs[38]; 598}; 599 600struct nv04_output_reg { 601 uint32_t output; 602 int head; 603}; 604 605struct nv04_mode_state { 606 struct nv04_crtc_reg crtc_reg[2]; 607 uint32_t pllsel; 608 uint32_t sel_clk; 609}; 610 611enum nouveau_card_type { 612 NV_04 = 0x00, 613 NV_10 = 0x10, 614 NV_20 = 0x20, 615 NV_30 = 0x30, 616 NV_40 = 0x40, 617 NV_50 = 0x50, 618 NV_C0 = 0xc0, 619}; 620 621struct drm_nouveau_private { 622 struct drm_device *dev; 623 bool noaccel; 624 625 /* the card type, takes NV_* as values */ 626 enum nouveau_card_type card_type; 627 /* exact chipset, derived from NV_PMC_BOOT_0 */ 628 int chipset; 629 int stepping; 630 int flags; 631 632 void __iomem *mmio; 633 634 spinlock_t ramin_lock; 635 void __iomem *ramin; 636 u32 ramin_size; 637 u32 ramin_base; 638 bool ramin_available; 639 struct drm_mm ramin_heap; 640 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 641 struct list_head gpuobj_list; 642 struct list_head classes; 643 644 struct nouveau_bo *vga_ram; 645 646 /* interrupt handling */ 647 void (*irq_handler[32])(struct drm_device *); 648 bool msi_enabled; 649 650 struct list_head vbl_waiting; 651 652 struct { 653 struct drm_global_reference mem_global_ref; 654 struct ttm_bo_global_ref bo_global_ref; 655 struct ttm_bo_device bdev; 656 atomic_t validate_sequence; 657 } ttm; 658 659 struct { 660 spinlock_t lock; 661 struct drm_mm heap; 662 struct nouveau_bo *bo; 663 } fence; 664 665 struct { 666 spinlock_t lock; 667 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 668 } channels; 669 670 struct nouveau_engine engine; 671 struct nouveau_channel *channel; 672 673 /* For PFIFO and PGRAPH. */ 674 spinlock_t context_switch_lock; 675 676 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 677 spinlock_t vm_lock; 678 679 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 680 struct nouveau_ramht *ramht; 681 struct nouveau_gpuobj *ramfc; 682 struct nouveau_gpuobj *ramro; 683 684 uint32_t ramin_rsvd_vram; 685 686 struct { 687 enum { 688 NOUVEAU_GART_NONE = 0, 689 NOUVEAU_GART_AGP, /* AGP */ 690 NOUVEAU_GART_PDMA, /* paged dma object */ 691 NOUVEAU_GART_HW /* on-chip gart/vm */ 692 } type; 693 uint64_t aper_base; 694 uint64_t aper_size; 695 uint64_t aper_free; 696 697 struct ttm_backend_func *func; 698 699 struct { 700 struct page *page; 701 dma_addr_t addr; 702 } dummy; 703 704 struct nouveau_gpuobj *sg_ctxdma; 705 } gart_info; 706 707 /* nv10-nv40 tiling regions */ 708 struct { 709 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 710 spinlock_t lock; 711 } tile; 712 713 /* VRAM/fb configuration */ 714 uint64_t vram_size; 715 uint64_t vram_sys_base; 716 u32 vram_rblock_size; 717 718 uint64_t fb_phys; 719 uint64_t fb_available_size; 720 uint64_t fb_mappable_pages; 721 uint64_t fb_aper_free; 722 int fb_mtrr; 723 724 /* BAR control (NV50-) */ 725 struct nouveau_vm *bar1_vm; 726 struct nouveau_vm *bar3_vm; 727 728 /* G8x/G9x virtual address space */ 729 struct nouveau_vm *chan_vm; 730 731 struct nvbios vbios; 732 733 struct nv04_mode_state mode_reg; 734 struct nv04_mode_state saved_reg; 735 uint32_t saved_vga_font[4][16384]; 736 uint32_t crtc_owner; 737 uint32_t dac_users[4]; 738 739 struct backlight_device *backlight; 740 741 struct { 742 struct dentry *channel_root; 743 } debugfs; 744 745 struct nouveau_fbdev *nfbdev; 746 struct apertures_struct *apertures; 747}; 748 749static inline struct drm_nouveau_private * 750nouveau_private(struct drm_device *dev) 751{ 752 return dev->dev_private; 753} 754 755static inline struct drm_nouveau_private * 756nouveau_bdev(struct ttm_bo_device *bd) 757{ 758 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 759} 760 761static inline int 762nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 763{ 764 struct nouveau_bo *prev; 765 766 if (!pnvbo) 767 return -EINVAL; 768 prev = *pnvbo; 769 770 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 771 if (prev) { 772 struct ttm_buffer_object *bo = &prev->bo; 773 774 ttm_bo_unref(&bo); 775 } 776 777 return 0; 778} 779 780/* nouveau_drv.c */ 781extern int nouveau_agpmode; 782extern int nouveau_duallink; 783extern int nouveau_uscript_lvds; 784extern int nouveau_uscript_tmds; 785extern int nouveau_vram_pushbuf; 786extern int nouveau_vram_notify; 787extern int nouveau_fbpercrtc; 788extern int nouveau_tv_disable; 789extern char *nouveau_tv_norm; 790extern int nouveau_reg_debug; 791extern char *nouveau_vbios; 792extern int nouveau_ignorelid; 793extern int nouveau_nofbaccel; 794extern int nouveau_noaccel; 795extern int nouveau_force_post; 796extern int nouveau_override_conntype; 797extern char *nouveau_perflvl; 798extern int nouveau_perflvl_wr; 799extern int nouveau_msi; 800extern int nouveau_ctxfw; 801 802extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 803extern int nouveau_pci_resume(struct pci_dev *pdev); 804 805/* nouveau_state.c */ 806extern int nouveau_open(struct drm_device *, struct drm_file *); 807extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 808extern void nouveau_postclose(struct drm_device *, struct drm_file *); 809extern int nouveau_load(struct drm_device *, unsigned long flags); 810extern int nouveau_firstopen(struct drm_device *); 811extern void nouveau_lastclose(struct drm_device *); 812extern int nouveau_unload(struct drm_device *); 813extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 814 struct drm_file *); 815extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 816 struct drm_file *); 817extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 818 uint32_t reg, uint32_t mask, uint32_t val); 819extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 820 uint32_t reg, uint32_t mask, uint32_t val); 821extern bool nouveau_wait_for_idle(struct drm_device *); 822extern int nouveau_card_init(struct drm_device *); 823 824/* nouveau_mem.c */ 825extern int nouveau_mem_vram_init(struct drm_device *); 826extern void nouveau_mem_vram_fini(struct drm_device *); 827extern int nouveau_mem_gart_init(struct drm_device *); 828extern void nouveau_mem_gart_fini(struct drm_device *); 829extern int nouveau_mem_init_agp(struct drm_device *); 830extern int nouveau_mem_reset_agp(struct drm_device *); 831extern void nouveau_mem_close(struct drm_device *); 832extern int nouveau_mem_detect(struct drm_device *); 833extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 834extern struct nouveau_tile_reg *nv10_mem_set_tiling( 835 struct drm_device *dev, uint32_t addr, uint32_t size, 836 uint32_t pitch, uint32_t flags); 837extern void nv10_mem_put_tile_region(struct drm_device *dev, 838 struct nouveau_tile_reg *tile, 839 struct nouveau_fence *fence); 840extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 841extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 842 843/* nouveau_notifier.c */ 844extern int nouveau_notifier_init_channel(struct nouveau_channel *); 845extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 846extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 847 int cout, uint32_t start, uint32_t end, 848 uint32_t *offset); 849extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 850extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 851 struct drm_file *); 852extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 853 struct drm_file *); 854 855/* nouveau_channel.c */ 856extern struct drm_ioctl_desc nouveau_ioctls[]; 857extern int nouveau_max_ioctl; 858extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 859extern int nouveau_channel_alloc(struct drm_device *dev, 860 struct nouveau_channel **chan, 861 struct drm_file *file_priv, 862 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 863extern struct nouveau_channel * 864nouveau_channel_get_unlocked(struct nouveau_channel *); 865extern struct nouveau_channel * 866nouveau_channel_get(struct drm_file *, int id); 867extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 868extern void nouveau_channel_put(struct nouveau_channel **); 869extern void nouveau_channel_ref(struct nouveau_channel *chan, 870 struct nouveau_channel **pchan); 871extern void nouveau_channel_idle(struct nouveau_channel *chan); 872 873/* nouveau_object.c */ 874#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 875 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 876 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 877} while (0) 878 879#define NVOBJ_ENGINE_DEL(d, e) do { \ 880 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 881 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 882} while (0) 883 884#define NVOBJ_CLASS(d, c, e) do { \ 885 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 886 if (ret) \ 887 return ret; \ 888} while (0) 889 890#define NVOBJ_MTHD(d, c, m, e) do { \ 891 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 892 if (ret) \ 893 return ret; \ 894} while (0) 895 896extern int nouveau_gpuobj_early_init(struct drm_device *); 897extern int nouveau_gpuobj_init(struct drm_device *); 898extern void nouveau_gpuobj_takedown(struct drm_device *); 899extern int nouveau_gpuobj_suspend(struct drm_device *dev); 900extern void nouveau_gpuobj_resume(struct drm_device *dev); 901extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 902extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 903 int (*exec)(struct nouveau_channel *, 904 u32 class, u32 mthd, u32 data)); 905extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 906extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 907extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 908 uint32_t vram_h, uint32_t tt_h); 909extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 910extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 911 uint32_t size, int align, uint32_t flags, 912 struct nouveau_gpuobj **); 913extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 914 struct nouveau_gpuobj **); 915extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 916 u32 size, u32 flags, 917 struct nouveau_gpuobj **); 918extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 919 uint64_t offset, uint64_t size, int access, 920 int target, struct nouveau_gpuobj **); 921extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 922extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 923 u64 size, int target, int access, u32 type, 924 u32 comp, struct nouveau_gpuobj **pobj); 925extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 926 int class, u64 base, u64 size, int target, 927 int access, u32 type, u32 comp); 928extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 929 struct drm_file *); 930extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 931 struct drm_file *); 932 933/* nouveau_irq.c */ 934extern int nouveau_irq_init(struct drm_device *); 935extern void nouveau_irq_fini(struct drm_device *); 936extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 937extern void nouveau_irq_register(struct drm_device *, int status_bit, 938 void (*)(struct drm_device *)); 939extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 940extern void nouveau_irq_preinstall(struct drm_device *); 941extern int nouveau_irq_postinstall(struct drm_device *); 942extern void nouveau_irq_uninstall(struct drm_device *); 943 944/* nouveau_sgdma.c */ 945extern int nouveau_sgdma_init(struct drm_device *); 946extern void nouveau_sgdma_takedown(struct drm_device *); 947extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 948 uint32_t offset); 949extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 950 951/* nouveau_debugfs.c */ 952#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 953extern int nouveau_debugfs_init(struct drm_minor *); 954extern void nouveau_debugfs_takedown(struct drm_minor *); 955extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 956extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 957#else 958static inline int 959nouveau_debugfs_init(struct drm_minor *minor) 960{ 961 return 0; 962} 963 964static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 965{ 966} 967 968static inline int 969nouveau_debugfs_channel_init(struct nouveau_channel *chan) 970{ 971 return 0; 972} 973 974static inline void 975nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 976{ 977} 978#endif 979 980/* nouveau_dma.c */ 981extern void nouveau_dma_pre_init(struct nouveau_channel *); 982extern int nouveau_dma_init(struct nouveau_channel *); 983extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 984 985/* nouveau_acpi.c */ 986#define ROM_BIOS_PAGE 4096 987#if defined(CONFIG_ACPI) 988void nouveau_register_dsm_handler(void); 989void nouveau_unregister_dsm_handler(void); 990int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 991bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 992int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 993#else 994static inline void nouveau_register_dsm_handler(void) {} 995static inline void nouveau_unregister_dsm_handler(void) {} 996static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 997static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 998static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 999#endif 1000 1001/* nouveau_backlight.c */ 1002#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1003extern int nouveau_backlight_init(struct drm_connector *); 1004extern void nouveau_backlight_exit(struct drm_connector *); 1005#else 1006static inline int nouveau_backlight_init(struct drm_connector *dev) 1007{ 1008 return 0; 1009} 1010 1011static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1012#endif 1013 1014/* nouveau_bios.c */ 1015extern int nouveau_bios_init(struct drm_device *); 1016extern void nouveau_bios_takedown(struct drm_device *dev); 1017extern int nouveau_run_vbios_init(struct drm_device *); 1018extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1019 struct dcb_entry *); 1020extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1021 enum dcb_gpio_tag); 1022extern struct dcb_connector_table_entry * 1023nouveau_bios_connector_entry(struct drm_device *, int index); 1024extern u32 get_pll_register(struct drm_device *, enum pll_types); 1025extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1026 struct pll_lims *); 1027extern int nouveau_bios_run_display_table(struct drm_device *, 1028 struct dcb_entry *, 1029 uint32_t script, int pxclk); 1030extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1031 int *length); 1032extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1033extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1034extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1035 bool *dl, bool *if_is_24bit); 1036extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1037 int head, int pxclk); 1038extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1039 enum LVDS_script, int pxclk); 1040 1041/* nouveau_ttm.c */ 1042int nouveau_ttm_global_init(struct drm_nouveau_private *); 1043void nouveau_ttm_global_release(struct drm_nouveau_private *); 1044int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1045 1046/* nouveau_dp.c */ 1047int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1048 uint8_t *data, int data_nr); 1049bool nouveau_dp_detect(struct drm_encoder *); 1050bool nouveau_dp_link_train(struct drm_encoder *); 1051 1052/* nv04_fb.c */ 1053extern int nv04_fb_init(struct drm_device *); 1054extern void nv04_fb_takedown(struct drm_device *); 1055 1056/* nv10_fb.c */ 1057extern int nv10_fb_init(struct drm_device *); 1058extern void nv10_fb_takedown(struct drm_device *); 1059extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1060 uint32_t addr, uint32_t size, 1061 uint32_t pitch, uint32_t flags); 1062extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1063extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1064 1065/* nv30_fb.c */ 1066extern int nv30_fb_init(struct drm_device *); 1067extern void nv30_fb_takedown(struct drm_device *); 1068extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1069 uint32_t addr, uint32_t size, 1070 uint32_t pitch, uint32_t flags); 1071extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1072 1073/* nv40_fb.c */ 1074extern int nv40_fb_init(struct drm_device *); 1075extern void nv40_fb_takedown(struct drm_device *); 1076extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1077 1078/* nv50_fb.c */ 1079extern int nv50_fb_init(struct drm_device *); 1080extern void nv50_fb_takedown(struct drm_device *); 1081extern void nv50_fb_vm_trap(struct drm_device *, int display); 1082 1083/* nvc0_fb.c */ 1084extern int nvc0_fb_init(struct drm_device *); 1085extern void nvc0_fb_takedown(struct drm_device *); 1086 1087/* nv04_fifo.c */ 1088extern int nv04_fifo_init(struct drm_device *); 1089extern void nv04_fifo_fini(struct drm_device *); 1090extern void nv04_fifo_disable(struct drm_device *); 1091extern void nv04_fifo_enable(struct drm_device *); 1092extern bool nv04_fifo_reassign(struct drm_device *, bool); 1093extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1094extern int nv04_fifo_channel_id(struct drm_device *); 1095extern int nv04_fifo_create_context(struct nouveau_channel *); 1096extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1097extern int nv04_fifo_load_context(struct nouveau_channel *); 1098extern int nv04_fifo_unload_context(struct drm_device *); 1099extern void nv04_fifo_isr(struct drm_device *); 1100 1101/* nv10_fifo.c */ 1102extern int nv10_fifo_init(struct drm_device *); 1103extern int nv10_fifo_channel_id(struct drm_device *); 1104extern int nv10_fifo_create_context(struct nouveau_channel *); 1105extern int nv10_fifo_load_context(struct nouveau_channel *); 1106extern int nv10_fifo_unload_context(struct drm_device *); 1107 1108/* nv40_fifo.c */ 1109extern int nv40_fifo_init(struct drm_device *); 1110extern int nv40_fifo_create_context(struct nouveau_channel *); 1111extern int nv40_fifo_load_context(struct nouveau_channel *); 1112extern int nv40_fifo_unload_context(struct drm_device *); 1113 1114/* nv50_fifo.c */ 1115extern int nv50_fifo_init(struct drm_device *); 1116extern void nv50_fifo_takedown(struct drm_device *); 1117extern int nv50_fifo_channel_id(struct drm_device *); 1118extern int nv50_fifo_create_context(struct nouveau_channel *); 1119extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1120extern int nv50_fifo_load_context(struct nouveau_channel *); 1121extern int nv50_fifo_unload_context(struct drm_device *); 1122extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1123 1124/* nvc0_fifo.c */ 1125extern int nvc0_fifo_init(struct drm_device *); 1126extern void nvc0_fifo_takedown(struct drm_device *); 1127extern void nvc0_fifo_disable(struct drm_device *); 1128extern void nvc0_fifo_enable(struct drm_device *); 1129extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1130extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1131extern int nvc0_fifo_channel_id(struct drm_device *); 1132extern int nvc0_fifo_create_context(struct nouveau_channel *); 1133extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1134extern int nvc0_fifo_load_context(struct nouveau_channel *); 1135extern int nvc0_fifo_unload_context(struct drm_device *); 1136 1137/* nv04_graph.c */ 1138extern int nv04_graph_create(struct drm_device *); 1139extern void nv04_graph_fifo_access(struct drm_device *, bool); 1140extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1141extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1142 u32 class, u32 mthd, u32 data); 1143extern struct nouveau_bitfield nv04_graph_nsource[]; 1144 1145/* nv10_graph.c */ 1146extern int nv10_graph_create(struct drm_device *); 1147extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1148extern struct nouveau_bitfield nv10_graph_intr[]; 1149extern struct nouveau_bitfield nv10_graph_nstatus[]; 1150 1151/* nv20_graph.c */ 1152extern int nv20_graph_create(struct drm_device *); 1153 1154/* nv40_graph.c */ 1155extern int nv40_graph_create(struct drm_device *); 1156extern void nv40_grctx_init(struct nouveau_grctx *); 1157 1158/* nv50_graph.c */ 1159extern int nv50_graph_create(struct drm_device *); 1160extern int nv50_grctx_init(struct nouveau_grctx *); 1161extern struct nouveau_enum nv50_data_error_names[]; 1162extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1163 1164/* nvc0_graph.c */ 1165extern int nvc0_graph_create(struct drm_device *); 1166extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1167 1168/* nv84_crypt.c */ 1169extern int nv84_crypt_create(struct drm_device *); 1170 1171/* nva3_copy.c */ 1172extern int nva3_copy_create(struct drm_device *dev); 1173 1174/* nvc0_copy.c */ 1175extern int nvc0_copy_create(struct drm_device *dev, int engine); 1176 1177/* nv40_mpeg.c */ 1178extern int nv40_mpeg_create(struct drm_device *dev); 1179 1180/* nv50_mpeg.c */ 1181extern int nv50_mpeg_create(struct drm_device *dev); 1182 1183/* nv04_instmem.c */ 1184extern int nv04_instmem_init(struct drm_device *); 1185extern void nv04_instmem_takedown(struct drm_device *); 1186extern int nv04_instmem_suspend(struct drm_device *); 1187extern void nv04_instmem_resume(struct drm_device *); 1188extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1189 u32 size, u32 align); 1190extern void nv04_instmem_put(struct nouveau_gpuobj *); 1191extern int nv04_instmem_map(struct nouveau_gpuobj *); 1192extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1193extern void nv04_instmem_flush(struct drm_device *); 1194 1195/* nv50_instmem.c */ 1196extern int nv50_instmem_init(struct drm_device *); 1197extern void nv50_instmem_takedown(struct drm_device *); 1198extern int nv50_instmem_suspend(struct drm_device *); 1199extern void nv50_instmem_resume(struct drm_device *); 1200extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1201 u32 size, u32 align); 1202extern void nv50_instmem_put(struct nouveau_gpuobj *); 1203extern int nv50_instmem_map(struct nouveau_gpuobj *); 1204extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1205extern void nv50_instmem_flush(struct drm_device *); 1206extern void nv84_instmem_flush(struct drm_device *); 1207 1208/* nvc0_instmem.c */ 1209extern int nvc0_instmem_init(struct drm_device *); 1210extern void nvc0_instmem_takedown(struct drm_device *); 1211extern int nvc0_instmem_suspend(struct drm_device *); 1212extern void nvc0_instmem_resume(struct drm_device *); 1213 1214/* nv04_mc.c */ 1215extern int nv04_mc_init(struct drm_device *); 1216extern void nv04_mc_takedown(struct drm_device *); 1217 1218/* nv40_mc.c */ 1219extern int nv40_mc_init(struct drm_device *); 1220extern void nv40_mc_takedown(struct drm_device *); 1221 1222/* nv50_mc.c */ 1223extern int nv50_mc_init(struct drm_device *); 1224extern void nv50_mc_takedown(struct drm_device *); 1225 1226/* nv04_timer.c */ 1227extern int nv04_timer_init(struct drm_device *); 1228extern uint64_t nv04_timer_read(struct drm_device *); 1229extern void nv04_timer_takedown(struct drm_device *); 1230 1231extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1232 unsigned long arg); 1233 1234/* nv04_dac.c */ 1235extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1236extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1237extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1238extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1239extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1240 1241/* nv04_dfp.c */ 1242extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1243extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1244extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1245 int head, bool dl); 1246extern void nv04_dfp_disable(struct drm_device *dev, int head); 1247extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1248 1249/* nv04_tv.c */ 1250extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1251extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1252 1253/* nv17_tv.c */ 1254extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1255 1256/* nv04_display.c */ 1257extern int nv04_display_early_init(struct drm_device *); 1258extern void nv04_display_late_takedown(struct drm_device *); 1259extern int nv04_display_create(struct drm_device *); 1260extern int nv04_display_init(struct drm_device *); 1261extern void nv04_display_destroy(struct drm_device *); 1262 1263/* nv04_crtc.c */ 1264extern int nv04_crtc_create(struct drm_device *, int index); 1265 1266/* nouveau_bo.c */ 1267extern struct ttm_bo_driver nouveau_bo_driver; 1268extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1269 int size, int align, uint32_t flags, 1270 uint32_t tile_mode, uint32_t tile_flags, 1271 struct nouveau_bo **); 1272extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1273extern int nouveau_bo_unpin(struct nouveau_bo *); 1274extern int nouveau_bo_map(struct nouveau_bo *); 1275extern void nouveau_bo_unmap(struct nouveau_bo *); 1276extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1277 uint32_t busy); 1278extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1279extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1280extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1281extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1282extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1283extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1284 bool no_wait_reserve, bool no_wait_gpu); 1285 1286/* nouveau_fence.c */ 1287struct nouveau_fence; 1288extern int nouveau_fence_init(struct drm_device *); 1289extern void nouveau_fence_fini(struct drm_device *); 1290extern int nouveau_fence_channel_init(struct nouveau_channel *); 1291extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1292extern void nouveau_fence_update(struct nouveau_channel *); 1293extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1294 bool emit); 1295extern int nouveau_fence_emit(struct nouveau_fence *); 1296extern void nouveau_fence_work(struct nouveau_fence *fence, 1297 void (*work)(void *priv, bool signalled), 1298 void *priv); 1299struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1300 1301extern bool __nouveau_fence_signalled(void *obj, void *arg); 1302extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1303extern int __nouveau_fence_flush(void *obj, void *arg); 1304extern void __nouveau_fence_unref(void **obj); 1305extern void *__nouveau_fence_ref(void *obj); 1306 1307static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1308{ 1309 return __nouveau_fence_signalled(obj, NULL); 1310} 1311static inline int 1312nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1313{ 1314 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1315} 1316extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1317static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1318{ 1319 return __nouveau_fence_flush(obj, NULL); 1320} 1321static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1322{ 1323 __nouveau_fence_unref((void **)obj); 1324} 1325static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1326{ 1327 return __nouveau_fence_ref(obj); 1328} 1329 1330/* nouveau_gem.c */ 1331extern int nouveau_gem_new(struct drm_device *, int size, int align, 1332 uint32_t domain, uint32_t tile_mode, 1333 uint32_t tile_flags, struct nouveau_bo **); 1334extern int nouveau_gem_object_new(struct drm_gem_object *); 1335extern void nouveau_gem_object_del(struct drm_gem_object *); 1336extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1337extern void nouveau_gem_object_close(struct drm_gem_object *, 1338 struct drm_file *); 1339extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1340 struct drm_file *); 1341extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1342 struct drm_file *); 1343extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1344 struct drm_file *); 1345extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1346 struct drm_file *); 1347extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1348 struct drm_file *); 1349 1350/* nouveau_display.c */ 1351int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1352void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1353int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1354 struct drm_pending_vblank_event *event); 1355int nouveau_finish_page_flip(struct nouveau_channel *, 1356 struct nouveau_page_flip_state *); 1357 1358/* nv10_gpio.c */ 1359int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1360int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1361 1362/* nv50_gpio.c */ 1363int nv50_gpio_init(struct drm_device *dev); 1364void nv50_gpio_fini(struct drm_device *dev); 1365int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1366int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1367int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1368 void (*)(void *, int), void *); 1369void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1370 void (*)(void *, int), void *); 1371bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1372 1373/* nv50_calc. */ 1374int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1375 int *N1, int *M1, int *N2, int *M2, int *P); 1376int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1377 int clk, int *N, int *fN, int *M, int *P); 1378 1379#ifndef ioread32_native 1380#ifdef __BIG_ENDIAN 1381#define ioread16_native ioread16be 1382#define iowrite16_native iowrite16be 1383#define ioread32_native ioread32be 1384#define iowrite32_native iowrite32be 1385#else /* def __BIG_ENDIAN */ 1386#define ioread16_native ioread16 1387#define iowrite16_native iowrite16 1388#define ioread32_native ioread32 1389#define iowrite32_native iowrite32 1390#endif /* def __BIG_ENDIAN else */ 1391#endif /* !ioread32_native */ 1392 1393/* channel control reg access */ 1394static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1395{ 1396 return ioread32_native(chan->user + reg); 1397} 1398 1399static inline void nvchan_wr32(struct nouveau_channel *chan, 1400 unsigned reg, u32 val) 1401{ 1402 iowrite32_native(val, chan->user + reg); 1403} 1404 1405/* register access */ 1406static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1407{ 1408 struct drm_nouveau_private *dev_priv = dev->dev_private; 1409 return ioread32_native(dev_priv->mmio + reg); 1410} 1411 1412static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1413{ 1414 struct drm_nouveau_private *dev_priv = dev->dev_private; 1415 iowrite32_native(val, dev_priv->mmio + reg); 1416} 1417 1418static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1419{ 1420 u32 tmp = nv_rd32(dev, reg); 1421 nv_wr32(dev, reg, (tmp & ~mask) | val); 1422 return tmp; 1423} 1424 1425static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1426{ 1427 struct drm_nouveau_private *dev_priv = dev->dev_private; 1428 return ioread8(dev_priv->mmio + reg); 1429} 1430 1431static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1432{ 1433 struct drm_nouveau_private *dev_priv = dev->dev_private; 1434 iowrite8(val, dev_priv->mmio + reg); 1435} 1436 1437#define nv_wait(dev, reg, mask, val) \ 1438 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1439#define nv_wait_ne(dev, reg, mask, val) \ 1440 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1441 1442/* PRAMIN access */ 1443static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1444{ 1445 struct drm_nouveau_private *dev_priv = dev->dev_private; 1446 return ioread32_native(dev_priv->ramin + offset); 1447} 1448 1449static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1450{ 1451 struct drm_nouveau_private *dev_priv = dev->dev_private; 1452 iowrite32_native(val, dev_priv->ramin + offset); 1453} 1454 1455/* object access */ 1456extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1457extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1458 1459/* 1460 * Logging 1461 * Argument d is (struct drm_device *). 1462 */ 1463#define NV_PRINTK(level, d, fmt, arg...) \ 1464 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1465 pci_name(d->pdev), ##arg) 1466#ifndef NV_DEBUG_NOTRACE 1467#define NV_DEBUG(d, fmt, arg...) do { \ 1468 if (drm_debug & DRM_UT_DRIVER) { \ 1469 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1470 __LINE__, ##arg); \ 1471 } \ 1472} while (0) 1473#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1474 if (drm_debug & DRM_UT_KMS) { \ 1475 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1476 __LINE__, ##arg); \ 1477 } \ 1478} while (0) 1479#else 1480#define NV_DEBUG(d, fmt, arg...) do { \ 1481 if (drm_debug & DRM_UT_DRIVER) \ 1482 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1483} while (0) 1484#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1485 if (drm_debug & DRM_UT_KMS) \ 1486 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1487} while (0) 1488#endif 1489#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1490#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1491#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1492#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1493#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1494 1495/* nouveau_reg_debug bitmask */ 1496enum { 1497 NOUVEAU_REG_DEBUG_MC = 0x1, 1498 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1499 NOUVEAU_REG_DEBUG_FB = 0x4, 1500 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1501 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1502 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1503 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1504 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1505 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1506 NOUVEAU_REG_DEBUG_EVO = 0x200, 1507}; 1508 1509#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1510 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1511 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1512} while (0) 1513 1514static inline bool 1515nv_two_heads(struct drm_device *dev) 1516{ 1517 struct drm_nouveau_private *dev_priv = dev->dev_private; 1518 const int impl = dev->pci_device & 0x0ff0; 1519 1520 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1521 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1522 return true; 1523 1524 return false; 1525} 1526 1527static inline bool 1528nv_gf4_disp_arch(struct drm_device *dev) 1529{ 1530 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1531} 1532 1533static inline bool 1534nv_two_reg_pll(struct drm_device *dev) 1535{ 1536 struct drm_nouveau_private *dev_priv = dev->dev_private; 1537 const int impl = dev->pci_device & 0x0ff0; 1538 1539 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1540 return true; 1541 return false; 1542} 1543 1544static inline bool 1545nv_match_device(struct drm_device *dev, unsigned device, 1546 unsigned sub_vendor, unsigned sub_device) 1547{ 1548 return dev->pdev->device == device && 1549 dev->pdev->subsystem_vendor == sub_vendor && 1550 dev->pdev->subsystem_device == sub_device; 1551} 1552 1553static inline void * 1554nv_engine(struct drm_device *dev, int engine) 1555{ 1556 struct drm_nouveau_private *dev_priv = dev->dev_private; 1557 return (void *)dev_priv->eng[engine]; 1558} 1559 1560/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1561 * helpful to determine a number of other hardware features 1562 */ 1563static inline int 1564nv44_graph_class(struct drm_device *dev) 1565{ 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 1568 if ((dev_priv->chipset & 0xf0) == 0x60) 1569 return 1; 1570 1571 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1572} 1573 1574/* memory type/access flags, do not match hardware values */ 1575#define NV_MEM_ACCESS_RO 1 1576#define NV_MEM_ACCESS_WO 2 1577#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1578#define NV_MEM_ACCESS_SYS 4 1579#define NV_MEM_ACCESS_VM 8 1580 1581#define NV_MEM_TARGET_VRAM 0 1582#define NV_MEM_TARGET_PCI 1 1583#define NV_MEM_TARGET_PCI_NOSNOOP 2 1584#define NV_MEM_TARGET_VM 3 1585#define NV_MEM_TARGET_GART 4 1586 1587#define NV_MEM_TYPE_VM 0x7f 1588#define NV_MEM_COMP_VM 0x03 1589 1590/* NV_SW object class */ 1591#define NV_SW 0x0000506e 1592#define NV_SW_DMA_SEMAPHORE 0x00000060 1593#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1594#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1595#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1596#define NV_SW_YIELD 0x00000080 1597#define NV_SW_DMA_VBLSEM 0x0000018c 1598#define NV_SW_VBLSEM_OFFSET 0x00000400 1599#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1600#define NV_SW_VBLSEM_RELEASE 0x00000408 1601#define NV_SW_PAGE_FLIP 0x00000500 1602 1603#endif /* __NOUVEAU_DRV_H__ */ 1604