nouveau_drv.h revision fd2871af3d2dad4e07df84941128b0813b5dd34b
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct nouveau_vma vma; 119 struct list_head vma_list; 120 unsigned page_shift; 121 122 uint32_t tile_mode; 123 uint32_t tile_flags; 124 struct nouveau_tile_reg *tile; 125 126 struct drm_gem_object *gem; 127 int pin_refcnt; 128}; 129 130#define nouveau_bo_tile_layout(nvbo) \ 131 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 132 133static inline struct nouveau_bo * 134nouveau_bo(struct ttm_buffer_object *bo) 135{ 136 return container_of(bo, struct nouveau_bo, bo); 137} 138 139static inline struct nouveau_bo * 140nouveau_gem_object(struct drm_gem_object *gem) 141{ 142 return gem ? gem->driver_private : NULL; 143} 144 145/* TODO: submit equivalent to TTM generic API upstream? */ 146static inline void __iomem * 147nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 148{ 149 bool is_iomem; 150 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 151 &nvbo->kmap, &is_iomem); 152 WARN_ON_ONCE(ioptr && !is_iomem); 153 return ioptr; 154} 155 156enum nouveau_flags { 157 NV_NFORCE = 0x10000000, 158 NV_NFORCE2 = 0x20000000 159}; 160 161#define NVOBJ_ENGINE_SW 0 162#define NVOBJ_ENGINE_GR 1 163#define NVOBJ_ENGINE_CRYPT 2 164#define NVOBJ_ENGINE_COPY0 3 165#define NVOBJ_ENGINE_COPY1 4 166#define NVOBJ_ENGINE_MPEG 5 167#define NVOBJ_ENGINE_DISPLAY 15 168#define NVOBJ_ENGINE_NR 16 169 170#define NVOBJ_FLAG_DONT_MAP (1 << 0) 171#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 172#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 173#define NVOBJ_FLAG_VM (1 << 3) 174#define NVOBJ_FLAG_VM_USER (1 << 4) 175 176#define NVOBJ_CINST_GLOBAL 0xdeadbeef 177 178struct nouveau_gpuobj { 179 struct drm_device *dev; 180 struct kref refcount; 181 struct list_head list; 182 183 void *node; 184 u32 *suspend; 185 186 uint32_t flags; 187 188 u32 size; 189 u32 pinst; /* PRAMIN BAR offset */ 190 u32 cinst; /* Channel offset */ 191 u64 vinst; /* VRAM address */ 192 u64 linst; /* VM address */ 193 194 uint32_t engine; 195 uint32_t class; 196 197 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 198 void *priv; 199}; 200 201struct nouveau_page_flip_state { 202 struct list_head head; 203 struct drm_pending_vblank_event *event; 204 int crtc, bpp, pitch, x, y; 205 uint64_t offset; 206}; 207 208enum nouveau_channel_mutex_class { 209 NOUVEAU_UCHANNEL_MUTEX, 210 NOUVEAU_KCHANNEL_MUTEX 211}; 212 213struct nouveau_channel { 214 struct drm_device *dev; 215 struct list_head list; 216 int id; 217 218 /* references to the channel data structure */ 219 struct kref ref; 220 /* users of the hardware channel resources, the hardware 221 * context will be kicked off when it reaches zero. */ 222 atomic_t users; 223 struct mutex mutex; 224 225 /* owner of this fifo */ 226 struct drm_file *file_priv; 227 /* mapping of the fifo itself */ 228 struct drm_local_map *map; 229 230 /* mapping of the regs controlling the fifo */ 231 void __iomem *user; 232 uint32_t user_get; 233 uint32_t user_put; 234 235 /* Fencing */ 236 struct { 237 /* lock protects the pending list only */ 238 spinlock_t lock; 239 struct list_head pending; 240 uint32_t sequence; 241 uint32_t sequence_ack; 242 atomic_t last_sequence_irq; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 uint32_t pushbuf_base; 249 250 /* Notifier memory */ 251 struct nouveau_bo *notifier_bo; 252 struct drm_mm notifier_heap; 253 254 /* PFIFO context */ 255 struct nouveau_gpuobj *ramfc; 256 struct nouveau_gpuobj *cache; 257 void *fifo_priv; 258 259 /* Execution engine contexts */ 260 void *engctx[NVOBJ_ENGINE_NR]; 261 262 /* NV50 VM */ 263 struct nouveau_vm *vm; 264 struct nouveau_gpuobj *vm_pd; 265 266 /* Objects */ 267 struct nouveau_gpuobj *ramin; /* Private instmem */ 268 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 269 struct nouveau_ramht *ramht; /* Hash table */ 270 271 /* GPU object info for stuff used in-kernel (mm_enabled) */ 272 uint32_t m2mf_ntfy; 273 uint32_t vram_handle; 274 uint32_t gart_handle; 275 bool accel_done; 276 277 /* Push buffer state (only for drm's channel on !mm_enabled) */ 278 struct { 279 int max; 280 int free; 281 int cur; 282 int put; 283 /* access via pushbuf_bo */ 284 285 int ib_base; 286 int ib_max; 287 int ib_free; 288 int ib_put; 289 } dma; 290 291 uint32_t sw_subchannel[8]; 292 293 struct { 294 struct nouveau_gpuobj *vblsem; 295 uint32_t vblsem_head; 296 uint32_t vblsem_offset; 297 uint32_t vblsem_rval; 298 struct list_head vbl_wait; 299 struct list_head flip; 300 } nvsw; 301 302 struct { 303 bool active; 304 char name[32]; 305 struct drm_info_list info; 306 } debugfs; 307}; 308 309struct nouveau_exec_engine { 310 void (*destroy)(struct drm_device *, int engine); 311 int (*init)(struct drm_device *, int engine); 312 int (*fini)(struct drm_device *, int engine); 313 int (*context_new)(struct nouveau_channel *, int engine); 314 void (*context_del)(struct nouveau_channel *, int engine); 315 int (*object_new)(struct nouveau_channel *, int engine, 316 u32 handle, u16 class); 317 void (*set_tile_region)(struct drm_device *dev, int i); 318 void (*tlb_flush)(struct drm_device *, int engine); 319}; 320 321struct nouveau_instmem_engine { 322 void *priv; 323 324 int (*init)(struct drm_device *dev); 325 void (*takedown)(struct drm_device *dev); 326 int (*suspend)(struct drm_device *dev); 327 void (*resume)(struct drm_device *dev); 328 329 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 330 u32 size, u32 align); 331 void (*put)(struct nouveau_gpuobj *); 332 int (*map)(struct nouveau_gpuobj *); 333 void (*unmap)(struct nouveau_gpuobj *); 334 335 void (*flush)(struct drm_device *); 336}; 337 338struct nouveau_mc_engine { 339 int (*init)(struct drm_device *dev); 340 void (*takedown)(struct drm_device *dev); 341}; 342 343struct nouveau_timer_engine { 344 int (*init)(struct drm_device *dev); 345 void (*takedown)(struct drm_device *dev); 346 uint64_t (*read)(struct drm_device *dev); 347}; 348 349struct nouveau_fb_engine { 350 int num_tiles; 351 struct drm_mm tag_heap; 352 void *priv; 353 354 int (*init)(struct drm_device *dev); 355 void (*takedown)(struct drm_device *dev); 356 357 void (*init_tile_region)(struct drm_device *dev, int i, 358 uint32_t addr, uint32_t size, 359 uint32_t pitch, uint32_t flags); 360 void (*set_tile_region)(struct drm_device *dev, int i); 361 void (*free_tile_region)(struct drm_device *dev, int i); 362}; 363 364struct nouveau_fifo_engine { 365 void *priv; 366 int channels; 367 368 struct nouveau_gpuobj *playlist[2]; 369 int cur_playlist; 370 371 int (*init)(struct drm_device *); 372 void (*takedown)(struct drm_device *); 373 374 void (*disable)(struct drm_device *); 375 void (*enable)(struct drm_device *); 376 bool (*reassign)(struct drm_device *, bool enable); 377 bool (*cache_pull)(struct drm_device *dev, bool enable); 378 379 int (*channel_id)(struct drm_device *); 380 381 int (*create_context)(struct nouveau_channel *); 382 void (*destroy_context)(struct nouveau_channel *); 383 int (*load_context)(struct nouveau_channel *); 384 int (*unload_context)(struct drm_device *); 385 void (*tlb_flush)(struct drm_device *dev); 386}; 387 388struct nouveau_display_engine { 389 void *priv; 390 int (*early_init)(struct drm_device *); 391 void (*late_takedown)(struct drm_device *); 392 int (*create)(struct drm_device *); 393 int (*init)(struct drm_device *); 394 void (*destroy)(struct drm_device *); 395}; 396 397struct nouveau_gpio_engine { 398 void *priv; 399 400 int (*init)(struct drm_device *); 401 void (*takedown)(struct drm_device *); 402 403 int (*get)(struct drm_device *, enum dcb_gpio_tag); 404 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 405 406 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 407 void (*)(void *, int), void *); 408 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 409 void (*)(void *, int), void *); 410 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 411}; 412 413struct nouveau_pm_voltage_level { 414 u8 voltage; 415 u8 vid; 416}; 417 418struct nouveau_pm_voltage { 419 bool supported; 420 u8 vid_mask; 421 422 struct nouveau_pm_voltage_level *level; 423 int nr_level; 424}; 425 426struct nouveau_pm_memtiming { 427 int id; 428 u32 reg_100220; 429 u32 reg_100224; 430 u32 reg_100228; 431 u32 reg_10022c; 432 u32 reg_100230; 433 u32 reg_100234; 434 u32 reg_100238; 435 u32 reg_10023c; 436 u32 reg_100240; 437}; 438 439#define NOUVEAU_PM_MAX_LEVEL 8 440struct nouveau_pm_level { 441 struct device_attribute dev_attr; 442 char name[32]; 443 int id; 444 445 u32 core; 446 u32 memory; 447 u32 shader; 448 u32 unk05; 449 u32 unk0a; 450 451 u8 voltage; 452 u8 fanspeed; 453 454 u16 memscript; 455 struct nouveau_pm_memtiming *timing; 456}; 457 458struct nouveau_pm_temp_sensor_constants { 459 u16 offset_constant; 460 s16 offset_mult; 461 u16 offset_div; 462 u16 slope_mult; 463 u16 slope_div; 464}; 465 466struct nouveau_pm_threshold_temp { 467 s16 critical; 468 s16 down_clock; 469 s16 fan_boost; 470}; 471 472struct nouveau_pm_memtimings { 473 bool supported; 474 struct nouveau_pm_memtiming *timing; 475 int nr_timing; 476}; 477 478struct nouveau_pm_engine { 479 struct nouveau_pm_voltage voltage; 480 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 481 int nr_perflvl; 482 struct nouveau_pm_memtimings memtimings; 483 struct nouveau_pm_temp_sensor_constants sensor_constants; 484 struct nouveau_pm_threshold_temp threshold_temp; 485 486 struct nouveau_pm_level boot; 487 struct nouveau_pm_level *cur; 488 489 struct device *hwmon; 490 struct notifier_block acpi_nb; 491 492 int (*clock_get)(struct drm_device *, u32 id); 493 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 494 u32 id, int khz); 495 void (*clock_set)(struct drm_device *, void *); 496 int (*voltage_get)(struct drm_device *); 497 int (*voltage_set)(struct drm_device *, int voltage); 498 int (*fanspeed_get)(struct drm_device *); 499 int (*fanspeed_set)(struct drm_device *, int fanspeed); 500 int (*temp_get)(struct drm_device *); 501}; 502 503struct nouveau_vram_engine { 504 int (*init)(struct drm_device *); 505 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 506 u32 type, struct nouveau_mem **); 507 void (*put)(struct drm_device *, struct nouveau_mem **); 508 509 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 510}; 511 512struct nouveau_engine { 513 struct nouveau_instmem_engine instmem; 514 struct nouveau_mc_engine mc; 515 struct nouveau_timer_engine timer; 516 struct nouveau_fb_engine fb; 517 struct nouveau_fifo_engine fifo; 518 struct nouveau_display_engine display; 519 struct nouveau_gpio_engine gpio; 520 struct nouveau_pm_engine pm; 521 struct nouveau_vram_engine vram; 522}; 523 524struct nouveau_pll_vals { 525 union { 526 struct { 527#ifdef __BIG_ENDIAN 528 uint8_t N1, M1, N2, M2; 529#else 530 uint8_t M1, N1, M2, N2; 531#endif 532 }; 533 struct { 534 uint16_t NM1, NM2; 535 } __attribute__((packed)); 536 }; 537 int log2P; 538 539 int refclk; 540}; 541 542enum nv04_fp_display_regs { 543 FP_DISPLAY_END, 544 FP_TOTAL, 545 FP_CRTC, 546 FP_SYNC_START, 547 FP_SYNC_END, 548 FP_VALID_START, 549 FP_VALID_END 550}; 551 552struct nv04_crtc_reg { 553 unsigned char MiscOutReg; 554 uint8_t CRTC[0xa0]; 555 uint8_t CR58[0x10]; 556 uint8_t Sequencer[5]; 557 uint8_t Graphics[9]; 558 uint8_t Attribute[21]; 559 unsigned char DAC[768]; 560 561 /* PCRTC regs */ 562 uint32_t fb_start; 563 uint32_t crtc_cfg; 564 uint32_t cursor_cfg; 565 uint32_t gpio_ext; 566 uint32_t crtc_830; 567 uint32_t crtc_834; 568 uint32_t crtc_850; 569 uint32_t crtc_eng_ctrl; 570 571 /* PRAMDAC regs */ 572 uint32_t nv10_cursync; 573 struct nouveau_pll_vals pllvals; 574 uint32_t ramdac_gen_ctrl; 575 uint32_t ramdac_630; 576 uint32_t ramdac_634; 577 uint32_t tv_setup; 578 uint32_t tv_vtotal; 579 uint32_t tv_vskew; 580 uint32_t tv_vsync_delay; 581 uint32_t tv_htotal; 582 uint32_t tv_hskew; 583 uint32_t tv_hsync_delay; 584 uint32_t tv_hsync_delay2; 585 uint32_t fp_horiz_regs[7]; 586 uint32_t fp_vert_regs[7]; 587 uint32_t dither; 588 uint32_t fp_control; 589 uint32_t dither_regs[6]; 590 uint32_t fp_debug_0; 591 uint32_t fp_debug_1; 592 uint32_t fp_debug_2; 593 uint32_t fp_margin_color; 594 uint32_t ramdac_8c0; 595 uint32_t ramdac_a20; 596 uint32_t ramdac_a24; 597 uint32_t ramdac_a34; 598 uint32_t ctv_regs[38]; 599}; 600 601struct nv04_output_reg { 602 uint32_t output; 603 int head; 604}; 605 606struct nv04_mode_state { 607 struct nv04_crtc_reg crtc_reg[2]; 608 uint32_t pllsel; 609 uint32_t sel_clk; 610}; 611 612enum nouveau_card_type { 613 NV_04 = 0x00, 614 NV_10 = 0x10, 615 NV_20 = 0x20, 616 NV_30 = 0x30, 617 NV_40 = 0x40, 618 NV_50 = 0x50, 619 NV_C0 = 0xc0, 620}; 621 622struct drm_nouveau_private { 623 struct drm_device *dev; 624 bool noaccel; 625 626 /* the card type, takes NV_* as values */ 627 enum nouveau_card_type card_type; 628 /* exact chipset, derived from NV_PMC_BOOT_0 */ 629 int chipset; 630 int stepping; 631 int flags; 632 633 void __iomem *mmio; 634 635 spinlock_t ramin_lock; 636 void __iomem *ramin; 637 u32 ramin_size; 638 u32 ramin_base; 639 bool ramin_available; 640 struct drm_mm ramin_heap; 641 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 642 struct list_head gpuobj_list; 643 struct list_head classes; 644 645 struct nouveau_bo *vga_ram; 646 647 /* interrupt handling */ 648 void (*irq_handler[32])(struct drm_device *); 649 bool msi_enabled; 650 651 struct list_head vbl_waiting; 652 653 struct { 654 struct drm_global_reference mem_global_ref; 655 struct ttm_bo_global_ref bo_global_ref; 656 struct ttm_bo_device bdev; 657 atomic_t validate_sequence; 658 } ttm; 659 660 struct { 661 spinlock_t lock; 662 struct drm_mm heap; 663 struct nouveau_bo *bo; 664 } fence; 665 666 struct { 667 spinlock_t lock; 668 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 669 } channels; 670 671 struct nouveau_engine engine; 672 struct nouveau_channel *channel; 673 674 /* For PFIFO and PGRAPH. */ 675 spinlock_t context_switch_lock; 676 677 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 678 spinlock_t vm_lock; 679 680 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 681 struct nouveau_ramht *ramht; 682 struct nouveau_gpuobj *ramfc; 683 struct nouveau_gpuobj *ramro; 684 685 uint32_t ramin_rsvd_vram; 686 687 struct { 688 enum { 689 NOUVEAU_GART_NONE = 0, 690 NOUVEAU_GART_AGP, /* AGP */ 691 NOUVEAU_GART_PDMA, /* paged dma object */ 692 NOUVEAU_GART_HW /* on-chip gart/vm */ 693 } type; 694 uint64_t aper_base; 695 uint64_t aper_size; 696 uint64_t aper_free; 697 698 struct ttm_backend_func *func; 699 700 struct { 701 struct page *page; 702 dma_addr_t addr; 703 } dummy; 704 705 struct nouveau_gpuobj *sg_ctxdma; 706 } gart_info; 707 708 /* nv10-nv40 tiling regions */ 709 struct { 710 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 711 spinlock_t lock; 712 } tile; 713 714 /* VRAM/fb configuration */ 715 uint64_t vram_size; 716 uint64_t vram_sys_base; 717 u32 vram_rblock_size; 718 719 uint64_t fb_phys; 720 uint64_t fb_available_size; 721 uint64_t fb_mappable_pages; 722 uint64_t fb_aper_free; 723 int fb_mtrr; 724 725 /* BAR control (NV50-) */ 726 struct nouveau_vm *bar1_vm; 727 struct nouveau_vm *bar3_vm; 728 729 /* G8x/G9x virtual address space */ 730 struct nouveau_vm *chan_vm; 731 732 struct nvbios vbios; 733 734 struct nv04_mode_state mode_reg; 735 struct nv04_mode_state saved_reg; 736 uint32_t saved_vga_font[4][16384]; 737 uint32_t crtc_owner; 738 uint32_t dac_users[4]; 739 740 struct backlight_device *backlight; 741 742 struct { 743 struct dentry *channel_root; 744 } debugfs; 745 746 struct nouveau_fbdev *nfbdev; 747 struct apertures_struct *apertures; 748}; 749 750static inline struct drm_nouveau_private * 751nouveau_private(struct drm_device *dev) 752{ 753 return dev->dev_private; 754} 755 756static inline struct drm_nouveau_private * 757nouveau_bdev(struct ttm_bo_device *bd) 758{ 759 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 760} 761 762static inline int 763nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 764{ 765 struct nouveau_bo *prev; 766 767 if (!pnvbo) 768 return -EINVAL; 769 prev = *pnvbo; 770 771 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 772 if (prev) { 773 struct ttm_buffer_object *bo = &prev->bo; 774 775 ttm_bo_unref(&bo); 776 } 777 778 return 0; 779} 780 781/* nouveau_drv.c */ 782extern int nouveau_agpmode; 783extern int nouveau_duallink; 784extern int nouveau_uscript_lvds; 785extern int nouveau_uscript_tmds; 786extern int nouveau_vram_pushbuf; 787extern int nouveau_vram_notify; 788extern int nouveau_fbpercrtc; 789extern int nouveau_tv_disable; 790extern char *nouveau_tv_norm; 791extern int nouveau_reg_debug; 792extern char *nouveau_vbios; 793extern int nouveau_ignorelid; 794extern int nouveau_nofbaccel; 795extern int nouveau_noaccel; 796extern int nouveau_force_post; 797extern int nouveau_override_conntype; 798extern char *nouveau_perflvl; 799extern int nouveau_perflvl_wr; 800extern int nouveau_msi; 801extern int nouveau_ctxfw; 802 803extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 804extern int nouveau_pci_resume(struct pci_dev *pdev); 805 806/* nouveau_state.c */ 807extern int nouveau_open(struct drm_device *, struct drm_file *); 808extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 809extern void nouveau_postclose(struct drm_device *, struct drm_file *); 810extern int nouveau_load(struct drm_device *, unsigned long flags); 811extern int nouveau_firstopen(struct drm_device *); 812extern void nouveau_lastclose(struct drm_device *); 813extern int nouveau_unload(struct drm_device *); 814extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 815 struct drm_file *); 816extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 817 struct drm_file *); 818extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 819 uint32_t reg, uint32_t mask, uint32_t val); 820extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 821 uint32_t reg, uint32_t mask, uint32_t val); 822extern bool nouveau_wait_for_idle(struct drm_device *); 823extern int nouveau_card_init(struct drm_device *); 824 825/* nouveau_mem.c */ 826extern int nouveau_mem_vram_init(struct drm_device *); 827extern void nouveau_mem_vram_fini(struct drm_device *); 828extern int nouveau_mem_gart_init(struct drm_device *); 829extern void nouveau_mem_gart_fini(struct drm_device *); 830extern int nouveau_mem_init_agp(struct drm_device *); 831extern int nouveau_mem_reset_agp(struct drm_device *); 832extern void nouveau_mem_close(struct drm_device *); 833extern int nouveau_mem_detect(struct drm_device *); 834extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 835extern struct nouveau_tile_reg *nv10_mem_set_tiling( 836 struct drm_device *dev, uint32_t addr, uint32_t size, 837 uint32_t pitch, uint32_t flags); 838extern void nv10_mem_put_tile_region(struct drm_device *dev, 839 struct nouveau_tile_reg *tile, 840 struct nouveau_fence *fence); 841extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 842extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 843 844/* nouveau_notifier.c */ 845extern int nouveau_notifier_init_channel(struct nouveau_channel *); 846extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 847extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 848 int cout, uint32_t start, uint32_t end, 849 uint32_t *offset); 850extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 851extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 852 struct drm_file *); 853extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 854 struct drm_file *); 855 856/* nouveau_channel.c */ 857extern struct drm_ioctl_desc nouveau_ioctls[]; 858extern int nouveau_max_ioctl; 859extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 860extern int nouveau_channel_alloc(struct drm_device *dev, 861 struct nouveau_channel **chan, 862 struct drm_file *file_priv, 863 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 864extern struct nouveau_channel * 865nouveau_channel_get_unlocked(struct nouveau_channel *); 866extern struct nouveau_channel * 867nouveau_channel_get(struct drm_file *, int id); 868extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 869extern void nouveau_channel_put(struct nouveau_channel **); 870extern void nouveau_channel_ref(struct nouveau_channel *chan, 871 struct nouveau_channel **pchan); 872extern void nouveau_channel_idle(struct nouveau_channel *chan); 873 874/* nouveau_object.c */ 875#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 876 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 877 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 878} while (0) 879 880#define NVOBJ_ENGINE_DEL(d, e) do { \ 881 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 882 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 883} while (0) 884 885#define NVOBJ_CLASS(d, c, e) do { \ 886 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 887 if (ret) \ 888 return ret; \ 889} while (0) 890 891#define NVOBJ_MTHD(d, c, m, e) do { \ 892 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 893 if (ret) \ 894 return ret; \ 895} while (0) 896 897extern int nouveau_gpuobj_early_init(struct drm_device *); 898extern int nouveau_gpuobj_init(struct drm_device *); 899extern void nouveau_gpuobj_takedown(struct drm_device *); 900extern int nouveau_gpuobj_suspend(struct drm_device *dev); 901extern void nouveau_gpuobj_resume(struct drm_device *dev); 902extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 903extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 904 int (*exec)(struct nouveau_channel *, 905 u32 class, u32 mthd, u32 data)); 906extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 907extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 908extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 909 uint32_t vram_h, uint32_t tt_h); 910extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 911extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 912 uint32_t size, int align, uint32_t flags, 913 struct nouveau_gpuobj **); 914extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 915 struct nouveau_gpuobj **); 916extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 917 u32 size, u32 flags, 918 struct nouveau_gpuobj **); 919extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 920 uint64_t offset, uint64_t size, int access, 921 int target, struct nouveau_gpuobj **); 922extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 923extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 924 u64 size, int target, int access, u32 type, 925 u32 comp, struct nouveau_gpuobj **pobj); 926extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 927 int class, u64 base, u64 size, int target, 928 int access, u32 type, u32 comp); 929extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 930 struct drm_file *); 931extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 932 struct drm_file *); 933 934/* nouveau_irq.c */ 935extern int nouveau_irq_init(struct drm_device *); 936extern void nouveau_irq_fini(struct drm_device *); 937extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 938extern void nouveau_irq_register(struct drm_device *, int status_bit, 939 void (*)(struct drm_device *)); 940extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 941extern void nouveau_irq_preinstall(struct drm_device *); 942extern int nouveau_irq_postinstall(struct drm_device *); 943extern void nouveau_irq_uninstall(struct drm_device *); 944 945/* nouveau_sgdma.c */ 946extern int nouveau_sgdma_init(struct drm_device *); 947extern void nouveau_sgdma_takedown(struct drm_device *); 948extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 949 uint32_t offset); 950extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 951 952/* nouveau_debugfs.c */ 953#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 954extern int nouveau_debugfs_init(struct drm_minor *); 955extern void nouveau_debugfs_takedown(struct drm_minor *); 956extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 957extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 958#else 959static inline int 960nouveau_debugfs_init(struct drm_minor *minor) 961{ 962 return 0; 963} 964 965static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 966{ 967} 968 969static inline int 970nouveau_debugfs_channel_init(struct nouveau_channel *chan) 971{ 972 return 0; 973} 974 975static inline void 976nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 977{ 978} 979#endif 980 981/* nouveau_dma.c */ 982extern void nouveau_dma_pre_init(struct nouveau_channel *); 983extern int nouveau_dma_init(struct nouveau_channel *); 984extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 985 986/* nouveau_acpi.c */ 987#define ROM_BIOS_PAGE 4096 988#if defined(CONFIG_ACPI) 989void nouveau_register_dsm_handler(void); 990void nouveau_unregister_dsm_handler(void); 991int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 992bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 993int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 994#else 995static inline void nouveau_register_dsm_handler(void) {} 996static inline void nouveau_unregister_dsm_handler(void) {} 997static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 998static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 999static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1000#endif 1001 1002/* nouveau_backlight.c */ 1003#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1004extern int nouveau_backlight_init(struct drm_connector *); 1005extern void nouveau_backlight_exit(struct drm_connector *); 1006#else 1007static inline int nouveau_backlight_init(struct drm_connector *dev) 1008{ 1009 return 0; 1010} 1011 1012static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1013#endif 1014 1015/* nouveau_bios.c */ 1016extern int nouveau_bios_init(struct drm_device *); 1017extern void nouveau_bios_takedown(struct drm_device *dev); 1018extern int nouveau_run_vbios_init(struct drm_device *); 1019extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1020 struct dcb_entry *); 1021extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1022 enum dcb_gpio_tag); 1023extern struct dcb_connector_table_entry * 1024nouveau_bios_connector_entry(struct drm_device *, int index); 1025extern u32 get_pll_register(struct drm_device *, enum pll_types); 1026extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1027 struct pll_lims *); 1028extern int nouveau_bios_run_display_table(struct drm_device *, 1029 struct dcb_entry *, 1030 uint32_t script, int pxclk); 1031extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1032 int *length); 1033extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1034extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1035extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1036 bool *dl, bool *if_is_24bit); 1037extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1038 int head, int pxclk); 1039extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1040 enum LVDS_script, int pxclk); 1041 1042/* nouveau_ttm.c */ 1043int nouveau_ttm_global_init(struct drm_nouveau_private *); 1044void nouveau_ttm_global_release(struct drm_nouveau_private *); 1045int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1046 1047/* nouveau_dp.c */ 1048int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1049 uint8_t *data, int data_nr); 1050bool nouveau_dp_detect(struct drm_encoder *); 1051bool nouveau_dp_link_train(struct drm_encoder *); 1052 1053/* nv04_fb.c */ 1054extern int nv04_fb_init(struct drm_device *); 1055extern void nv04_fb_takedown(struct drm_device *); 1056 1057/* nv10_fb.c */ 1058extern int nv10_fb_init(struct drm_device *); 1059extern void nv10_fb_takedown(struct drm_device *); 1060extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1061 uint32_t addr, uint32_t size, 1062 uint32_t pitch, uint32_t flags); 1063extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1064extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1065 1066/* nv30_fb.c */ 1067extern int nv30_fb_init(struct drm_device *); 1068extern void nv30_fb_takedown(struct drm_device *); 1069extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1070 uint32_t addr, uint32_t size, 1071 uint32_t pitch, uint32_t flags); 1072extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1073 1074/* nv40_fb.c */ 1075extern int nv40_fb_init(struct drm_device *); 1076extern void nv40_fb_takedown(struct drm_device *); 1077extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1078 1079/* nv50_fb.c */ 1080extern int nv50_fb_init(struct drm_device *); 1081extern void nv50_fb_takedown(struct drm_device *); 1082extern void nv50_fb_vm_trap(struct drm_device *, int display); 1083 1084/* nvc0_fb.c */ 1085extern int nvc0_fb_init(struct drm_device *); 1086extern void nvc0_fb_takedown(struct drm_device *); 1087 1088/* nv04_fifo.c */ 1089extern int nv04_fifo_init(struct drm_device *); 1090extern void nv04_fifo_fini(struct drm_device *); 1091extern void nv04_fifo_disable(struct drm_device *); 1092extern void nv04_fifo_enable(struct drm_device *); 1093extern bool nv04_fifo_reassign(struct drm_device *, bool); 1094extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1095extern int nv04_fifo_channel_id(struct drm_device *); 1096extern int nv04_fifo_create_context(struct nouveau_channel *); 1097extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1098extern int nv04_fifo_load_context(struct nouveau_channel *); 1099extern int nv04_fifo_unload_context(struct drm_device *); 1100extern void nv04_fifo_isr(struct drm_device *); 1101 1102/* nv10_fifo.c */ 1103extern int nv10_fifo_init(struct drm_device *); 1104extern int nv10_fifo_channel_id(struct drm_device *); 1105extern int nv10_fifo_create_context(struct nouveau_channel *); 1106extern int nv10_fifo_load_context(struct nouveau_channel *); 1107extern int nv10_fifo_unload_context(struct drm_device *); 1108 1109/* nv40_fifo.c */ 1110extern int nv40_fifo_init(struct drm_device *); 1111extern int nv40_fifo_create_context(struct nouveau_channel *); 1112extern int nv40_fifo_load_context(struct nouveau_channel *); 1113extern int nv40_fifo_unload_context(struct drm_device *); 1114 1115/* nv50_fifo.c */ 1116extern int nv50_fifo_init(struct drm_device *); 1117extern void nv50_fifo_takedown(struct drm_device *); 1118extern int nv50_fifo_channel_id(struct drm_device *); 1119extern int nv50_fifo_create_context(struct nouveau_channel *); 1120extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1121extern int nv50_fifo_load_context(struct nouveau_channel *); 1122extern int nv50_fifo_unload_context(struct drm_device *); 1123extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1124 1125/* nvc0_fifo.c */ 1126extern int nvc0_fifo_init(struct drm_device *); 1127extern void nvc0_fifo_takedown(struct drm_device *); 1128extern void nvc0_fifo_disable(struct drm_device *); 1129extern void nvc0_fifo_enable(struct drm_device *); 1130extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1131extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1132extern int nvc0_fifo_channel_id(struct drm_device *); 1133extern int nvc0_fifo_create_context(struct nouveau_channel *); 1134extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1135extern int nvc0_fifo_load_context(struct nouveau_channel *); 1136extern int nvc0_fifo_unload_context(struct drm_device *); 1137 1138/* nv04_graph.c */ 1139extern int nv04_graph_create(struct drm_device *); 1140extern void nv04_graph_fifo_access(struct drm_device *, bool); 1141extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1142extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1143 u32 class, u32 mthd, u32 data); 1144extern struct nouveau_bitfield nv04_graph_nsource[]; 1145 1146/* nv10_graph.c */ 1147extern int nv10_graph_create(struct drm_device *); 1148extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1149extern struct nouveau_bitfield nv10_graph_intr[]; 1150extern struct nouveau_bitfield nv10_graph_nstatus[]; 1151 1152/* nv20_graph.c */ 1153extern int nv20_graph_create(struct drm_device *); 1154 1155/* nv40_graph.c */ 1156extern int nv40_graph_create(struct drm_device *); 1157extern void nv40_grctx_init(struct nouveau_grctx *); 1158 1159/* nv50_graph.c */ 1160extern int nv50_graph_create(struct drm_device *); 1161extern int nv50_grctx_init(struct nouveau_grctx *); 1162extern struct nouveau_enum nv50_data_error_names[]; 1163extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1164 1165/* nvc0_graph.c */ 1166extern int nvc0_graph_create(struct drm_device *); 1167extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1168 1169/* nv84_crypt.c */ 1170extern int nv84_crypt_create(struct drm_device *); 1171 1172/* nva3_copy.c */ 1173extern int nva3_copy_create(struct drm_device *dev); 1174 1175/* nvc0_copy.c */ 1176extern int nvc0_copy_create(struct drm_device *dev, int engine); 1177 1178/* nv40_mpeg.c */ 1179extern int nv40_mpeg_create(struct drm_device *dev); 1180 1181/* nv50_mpeg.c */ 1182extern int nv50_mpeg_create(struct drm_device *dev); 1183 1184/* nv04_instmem.c */ 1185extern int nv04_instmem_init(struct drm_device *); 1186extern void nv04_instmem_takedown(struct drm_device *); 1187extern int nv04_instmem_suspend(struct drm_device *); 1188extern void nv04_instmem_resume(struct drm_device *); 1189extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1190 u32 size, u32 align); 1191extern void nv04_instmem_put(struct nouveau_gpuobj *); 1192extern int nv04_instmem_map(struct nouveau_gpuobj *); 1193extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1194extern void nv04_instmem_flush(struct drm_device *); 1195 1196/* nv50_instmem.c */ 1197extern int nv50_instmem_init(struct drm_device *); 1198extern void nv50_instmem_takedown(struct drm_device *); 1199extern int nv50_instmem_suspend(struct drm_device *); 1200extern void nv50_instmem_resume(struct drm_device *); 1201extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1202 u32 size, u32 align); 1203extern void nv50_instmem_put(struct nouveau_gpuobj *); 1204extern int nv50_instmem_map(struct nouveau_gpuobj *); 1205extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1206extern void nv50_instmem_flush(struct drm_device *); 1207extern void nv84_instmem_flush(struct drm_device *); 1208 1209/* nvc0_instmem.c */ 1210extern int nvc0_instmem_init(struct drm_device *); 1211extern void nvc0_instmem_takedown(struct drm_device *); 1212extern int nvc0_instmem_suspend(struct drm_device *); 1213extern void nvc0_instmem_resume(struct drm_device *); 1214 1215/* nv04_mc.c */ 1216extern int nv04_mc_init(struct drm_device *); 1217extern void nv04_mc_takedown(struct drm_device *); 1218 1219/* nv40_mc.c */ 1220extern int nv40_mc_init(struct drm_device *); 1221extern void nv40_mc_takedown(struct drm_device *); 1222 1223/* nv50_mc.c */ 1224extern int nv50_mc_init(struct drm_device *); 1225extern void nv50_mc_takedown(struct drm_device *); 1226 1227/* nv04_timer.c */ 1228extern int nv04_timer_init(struct drm_device *); 1229extern uint64_t nv04_timer_read(struct drm_device *); 1230extern void nv04_timer_takedown(struct drm_device *); 1231 1232extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1233 unsigned long arg); 1234 1235/* nv04_dac.c */ 1236extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1237extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1238extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1239extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1240extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1241 1242/* nv04_dfp.c */ 1243extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1244extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1245extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1246 int head, bool dl); 1247extern void nv04_dfp_disable(struct drm_device *dev, int head); 1248extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1249 1250/* nv04_tv.c */ 1251extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1252extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1253 1254/* nv17_tv.c */ 1255extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1256 1257/* nv04_display.c */ 1258extern int nv04_display_early_init(struct drm_device *); 1259extern void nv04_display_late_takedown(struct drm_device *); 1260extern int nv04_display_create(struct drm_device *); 1261extern int nv04_display_init(struct drm_device *); 1262extern void nv04_display_destroy(struct drm_device *); 1263 1264/* nv04_crtc.c */ 1265extern int nv04_crtc_create(struct drm_device *, int index); 1266 1267/* nouveau_bo.c */ 1268extern struct ttm_bo_driver nouveau_bo_driver; 1269extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1270 int size, int align, uint32_t flags, 1271 uint32_t tile_mode, uint32_t tile_flags, 1272 struct nouveau_bo **); 1273extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1274extern int nouveau_bo_unpin(struct nouveau_bo *); 1275extern int nouveau_bo_map(struct nouveau_bo *); 1276extern void nouveau_bo_unmap(struct nouveau_bo *); 1277extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1278 uint32_t busy); 1279extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1280extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1281extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1282extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1283extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1284extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1285 bool no_wait_reserve, bool no_wait_gpu); 1286 1287extern struct nouveau_vma * 1288nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1289extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1290 struct nouveau_vma *); 1291extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1292 1293/* nouveau_fence.c */ 1294struct nouveau_fence; 1295extern int nouveau_fence_init(struct drm_device *); 1296extern void nouveau_fence_fini(struct drm_device *); 1297extern int nouveau_fence_channel_init(struct nouveau_channel *); 1298extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1299extern void nouveau_fence_update(struct nouveau_channel *); 1300extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1301 bool emit); 1302extern int nouveau_fence_emit(struct nouveau_fence *); 1303extern void nouveau_fence_work(struct nouveau_fence *fence, 1304 void (*work)(void *priv, bool signalled), 1305 void *priv); 1306struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1307 1308extern bool __nouveau_fence_signalled(void *obj, void *arg); 1309extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1310extern int __nouveau_fence_flush(void *obj, void *arg); 1311extern void __nouveau_fence_unref(void **obj); 1312extern void *__nouveau_fence_ref(void *obj); 1313 1314static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1315{ 1316 return __nouveau_fence_signalled(obj, NULL); 1317} 1318static inline int 1319nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1320{ 1321 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1322} 1323extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1324static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1325{ 1326 return __nouveau_fence_flush(obj, NULL); 1327} 1328static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1329{ 1330 __nouveau_fence_unref((void **)obj); 1331} 1332static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1333{ 1334 return __nouveau_fence_ref(obj); 1335} 1336 1337/* nouveau_gem.c */ 1338extern int nouveau_gem_new(struct drm_device *, int size, int align, 1339 uint32_t domain, uint32_t tile_mode, 1340 uint32_t tile_flags, struct nouveau_bo **); 1341extern int nouveau_gem_object_new(struct drm_gem_object *); 1342extern void nouveau_gem_object_del(struct drm_gem_object *); 1343extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1344extern void nouveau_gem_object_close(struct drm_gem_object *, 1345 struct drm_file *); 1346extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1347 struct drm_file *); 1348extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1349 struct drm_file *); 1350extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1351 struct drm_file *); 1352extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1353 struct drm_file *); 1354extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1355 struct drm_file *); 1356 1357/* nouveau_display.c */ 1358int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1359void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1360int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1361 struct drm_pending_vblank_event *event); 1362int nouveau_finish_page_flip(struct nouveau_channel *, 1363 struct nouveau_page_flip_state *); 1364 1365/* nv10_gpio.c */ 1366int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1367int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1368 1369/* nv50_gpio.c */ 1370int nv50_gpio_init(struct drm_device *dev); 1371void nv50_gpio_fini(struct drm_device *dev); 1372int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1373int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1374int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1375 void (*)(void *, int), void *); 1376void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1377 void (*)(void *, int), void *); 1378bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1379 1380/* nv50_calc. */ 1381int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1382 int *N1, int *M1, int *N2, int *M2, int *P); 1383int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1384 int clk, int *N, int *fN, int *M, int *P); 1385 1386#ifndef ioread32_native 1387#ifdef __BIG_ENDIAN 1388#define ioread16_native ioread16be 1389#define iowrite16_native iowrite16be 1390#define ioread32_native ioread32be 1391#define iowrite32_native iowrite32be 1392#else /* def __BIG_ENDIAN */ 1393#define ioread16_native ioread16 1394#define iowrite16_native iowrite16 1395#define ioread32_native ioread32 1396#define iowrite32_native iowrite32 1397#endif /* def __BIG_ENDIAN else */ 1398#endif /* !ioread32_native */ 1399 1400/* channel control reg access */ 1401static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1402{ 1403 return ioread32_native(chan->user + reg); 1404} 1405 1406static inline void nvchan_wr32(struct nouveau_channel *chan, 1407 unsigned reg, u32 val) 1408{ 1409 iowrite32_native(val, chan->user + reg); 1410} 1411 1412/* register access */ 1413static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1414{ 1415 struct drm_nouveau_private *dev_priv = dev->dev_private; 1416 return ioread32_native(dev_priv->mmio + reg); 1417} 1418 1419static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1420{ 1421 struct drm_nouveau_private *dev_priv = dev->dev_private; 1422 iowrite32_native(val, dev_priv->mmio + reg); 1423} 1424 1425static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1426{ 1427 u32 tmp = nv_rd32(dev, reg); 1428 nv_wr32(dev, reg, (tmp & ~mask) | val); 1429 return tmp; 1430} 1431 1432static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1433{ 1434 struct drm_nouveau_private *dev_priv = dev->dev_private; 1435 return ioread8(dev_priv->mmio + reg); 1436} 1437 1438static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1439{ 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 iowrite8(val, dev_priv->mmio + reg); 1442} 1443 1444#define nv_wait(dev, reg, mask, val) \ 1445 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1446#define nv_wait_ne(dev, reg, mask, val) \ 1447 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1448 1449/* PRAMIN access */ 1450static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1451{ 1452 struct drm_nouveau_private *dev_priv = dev->dev_private; 1453 return ioread32_native(dev_priv->ramin + offset); 1454} 1455 1456static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1457{ 1458 struct drm_nouveau_private *dev_priv = dev->dev_private; 1459 iowrite32_native(val, dev_priv->ramin + offset); 1460} 1461 1462/* object access */ 1463extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1464extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1465 1466/* 1467 * Logging 1468 * Argument d is (struct drm_device *). 1469 */ 1470#define NV_PRINTK(level, d, fmt, arg...) \ 1471 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1472 pci_name(d->pdev), ##arg) 1473#ifndef NV_DEBUG_NOTRACE 1474#define NV_DEBUG(d, fmt, arg...) do { \ 1475 if (drm_debug & DRM_UT_DRIVER) { \ 1476 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1477 __LINE__, ##arg); \ 1478 } \ 1479} while (0) 1480#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1481 if (drm_debug & DRM_UT_KMS) { \ 1482 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1483 __LINE__, ##arg); \ 1484 } \ 1485} while (0) 1486#else 1487#define NV_DEBUG(d, fmt, arg...) do { \ 1488 if (drm_debug & DRM_UT_DRIVER) \ 1489 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1490} while (0) 1491#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1492 if (drm_debug & DRM_UT_KMS) \ 1493 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1494} while (0) 1495#endif 1496#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1497#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1498#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1499#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1500#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1501 1502/* nouveau_reg_debug bitmask */ 1503enum { 1504 NOUVEAU_REG_DEBUG_MC = 0x1, 1505 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1506 NOUVEAU_REG_DEBUG_FB = 0x4, 1507 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1508 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1509 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1510 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1511 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1512 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1513 NOUVEAU_REG_DEBUG_EVO = 0x200, 1514}; 1515 1516#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1517 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1518 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1519} while (0) 1520 1521static inline bool 1522nv_two_heads(struct drm_device *dev) 1523{ 1524 struct drm_nouveau_private *dev_priv = dev->dev_private; 1525 const int impl = dev->pci_device & 0x0ff0; 1526 1527 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1528 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1529 return true; 1530 1531 return false; 1532} 1533 1534static inline bool 1535nv_gf4_disp_arch(struct drm_device *dev) 1536{ 1537 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1538} 1539 1540static inline bool 1541nv_two_reg_pll(struct drm_device *dev) 1542{ 1543 struct drm_nouveau_private *dev_priv = dev->dev_private; 1544 const int impl = dev->pci_device & 0x0ff0; 1545 1546 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1547 return true; 1548 return false; 1549} 1550 1551static inline bool 1552nv_match_device(struct drm_device *dev, unsigned device, 1553 unsigned sub_vendor, unsigned sub_device) 1554{ 1555 return dev->pdev->device == device && 1556 dev->pdev->subsystem_vendor == sub_vendor && 1557 dev->pdev->subsystem_device == sub_device; 1558} 1559 1560static inline void * 1561nv_engine(struct drm_device *dev, int engine) 1562{ 1563 struct drm_nouveau_private *dev_priv = dev->dev_private; 1564 return (void *)dev_priv->eng[engine]; 1565} 1566 1567/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1568 * helpful to determine a number of other hardware features 1569 */ 1570static inline int 1571nv44_graph_class(struct drm_device *dev) 1572{ 1573 struct drm_nouveau_private *dev_priv = dev->dev_private; 1574 1575 if ((dev_priv->chipset & 0xf0) == 0x60) 1576 return 1; 1577 1578 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1579} 1580 1581/* memory type/access flags, do not match hardware values */ 1582#define NV_MEM_ACCESS_RO 1 1583#define NV_MEM_ACCESS_WO 2 1584#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1585#define NV_MEM_ACCESS_SYS 4 1586#define NV_MEM_ACCESS_VM 8 1587 1588#define NV_MEM_TARGET_VRAM 0 1589#define NV_MEM_TARGET_PCI 1 1590#define NV_MEM_TARGET_PCI_NOSNOOP 2 1591#define NV_MEM_TARGET_VM 3 1592#define NV_MEM_TARGET_GART 4 1593 1594#define NV_MEM_TYPE_VM 0x7f 1595#define NV_MEM_COMP_VM 0x03 1596 1597/* NV_SW object class */ 1598#define NV_SW 0x0000506e 1599#define NV_SW_DMA_SEMAPHORE 0x00000060 1600#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1601#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1602#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1603#define NV_SW_YIELD 0x00000080 1604#define NV_SW_DMA_VBLSEM 0x0000018c 1605#define NV_SW_VBLSEM_OFFSET 0x00000400 1606#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1607#define NV_SW_VBLSEM_RELEASE 0x00000408 1608#define NV_SW_PAGE_FLIP 0x00000500 1609 1610#endif /* __NOUVEAU_DRV_H__ */ 1611