nouveau_drv.h revision ff2b6c6e587cf2add3071b3a9a5c61abbbaf4677
1/* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef __NOUVEAU_DRV_H__ 26#define __NOUVEAU_DRV_H__ 27 28#define DRIVER_AUTHOR "Stephane Marchesin" 29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31#define DRIVER_NAME "nouveau" 32#define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33#define DRIVER_DATE "20090420" 34 35#define DRIVER_MAJOR 0 36#define DRIVER_MINOR 0 37#define DRIVER_PATCHLEVEL 16 38 39#define NOUVEAU_FAMILY 0x0000FFFF 40#define NOUVEAU_FLAGS 0xFFFF0000 41 42#include "ttm/ttm_bo_api.h" 43#include "ttm/ttm_bo_driver.h" 44#include "ttm/ttm_placement.h" 45#include "ttm/ttm_memory.h" 46#include "ttm/ttm_module.h" 47 48struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52}; 53 54static inline struct nouveau_fpriv * 55nouveau_fpriv(struct drm_file *file_priv) 56{ 57 return file_priv ? file_priv->driver_priv : NULL; 58} 59 60#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62#include "nouveau_drm.h" 63#include "nouveau_reg.h" 64#include "nouveau_bios.h" 65#include "nouveau_util.h" 66 67struct nouveau_grctx; 68struct nouveau_mem; 69#include "nouveau_vm.h" 70 71#define MAX_NUM_DCB_ENTRIES 16 72 73#define NOUVEAU_MAX_CHANNEL_NR 128 74#define NOUVEAU_MAX_TILE_NR 15 75 76struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89}; 90 91struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99}; 100 101struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127}; 128 129#define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132static inline struct nouveau_bo * 133nouveau_bo(struct ttm_buffer_object *bo) 134{ 135 return container_of(bo, struct nouveau_bo, bo); 136} 137 138static inline struct nouveau_bo * 139nouveau_gem_object(struct drm_gem_object *gem) 140{ 141 return gem ? gem->driver_private : NULL; 142} 143 144/* TODO: submit equivalent to TTM generic API upstream? */ 145static inline void __iomem * 146nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147{ 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153} 154 155enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158}; 159 160#define NVOBJ_ENGINE_SW 0 161#define NVOBJ_ENGINE_GR 1 162#define NVOBJ_ENGINE_CRYPT 2 163#define NVOBJ_ENGINE_COPY0 3 164#define NVOBJ_ENGINE_COPY1 4 165#define NVOBJ_ENGINE_MPEG 5 166#define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 167#define NVOBJ_ENGINE_BSP 6 168#define NVOBJ_ENGINE_VP 7 169#define NVOBJ_ENGINE_DISPLAY 15 170#define NVOBJ_ENGINE_NR 16 171 172#define NVOBJ_FLAG_DONT_MAP (1 << 0) 173#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 174#define NVOBJ_FLAG_ZERO_FREE (1 << 2) 175#define NVOBJ_FLAG_VM (1 << 3) 176#define NVOBJ_FLAG_VM_USER (1 << 4) 177 178#define NVOBJ_CINST_GLOBAL 0xdeadbeef 179 180struct nouveau_gpuobj { 181 struct drm_device *dev; 182 struct kref refcount; 183 struct list_head list; 184 185 void *node; 186 u32 *suspend; 187 188 uint32_t flags; 189 190 u32 size; 191 u32 pinst; /* PRAMIN BAR offset */ 192 u32 cinst; /* Channel offset */ 193 u64 vinst; /* VRAM address */ 194 u64 linst; /* VM address */ 195 196 uint32_t engine; 197 uint32_t class; 198 199 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 200 void *priv; 201}; 202 203struct nouveau_page_flip_state { 204 struct list_head head; 205 struct drm_pending_vblank_event *event; 206 int crtc, bpp, pitch, x, y; 207 uint64_t offset; 208}; 209 210enum nouveau_channel_mutex_class { 211 NOUVEAU_UCHANNEL_MUTEX, 212 NOUVEAU_KCHANNEL_MUTEX 213}; 214 215struct nouveau_channel { 216 struct drm_device *dev; 217 struct list_head list; 218 int id; 219 220 /* references to the channel data structure */ 221 struct kref ref; 222 /* users of the hardware channel resources, the hardware 223 * context will be kicked off when it reaches zero. */ 224 atomic_t users; 225 struct mutex mutex; 226 227 /* owner of this fifo */ 228 struct drm_file *file_priv; 229 /* mapping of the fifo itself */ 230 struct drm_local_map *map; 231 232 /* mapping of the regs controlling the fifo */ 233 void __iomem *user; 234 uint32_t user_get; 235 uint32_t user_put; 236 237 /* Fencing */ 238 struct { 239 /* lock protects the pending list only */ 240 spinlock_t lock; 241 struct list_head pending; 242 uint32_t sequence; 243 uint32_t sequence_ack; 244 atomic_t last_sequence_irq; 245 struct nouveau_vma vma; 246 } fence; 247 248 /* DMA push buffer */ 249 struct nouveau_gpuobj *pushbuf; 250 struct nouveau_bo *pushbuf_bo; 251 struct nouveau_vma pushbuf_vma; 252 uint32_t pushbuf_base; 253 254 /* Notifier memory */ 255 struct nouveau_bo *notifier_bo; 256 struct nouveau_vma notifier_vma; 257 struct drm_mm notifier_heap; 258 259 /* PFIFO context */ 260 struct nouveau_gpuobj *ramfc; 261 struct nouveau_gpuobj *cache; 262 void *fifo_priv; 263 264 /* Execution engine contexts */ 265 void *engctx[NVOBJ_ENGINE_NR]; 266 267 /* NV50 VM */ 268 struct nouveau_vm *vm; 269 struct nouveau_gpuobj *vm_pd; 270 271 /* Objects */ 272 struct nouveau_gpuobj *ramin; /* Private instmem */ 273 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 274 struct nouveau_ramht *ramht; /* Hash table */ 275 276 /* GPU object info for stuff used in-kernel (mm_enabled) */ 277 uint32_t m2mf_ntfy; 278 uint32_t vram_handle; 279 uint32_t gart_handle; 280 bool accel_done; 281 282 /* Push buffer state (only for drm's channel on !mm_enabled) */ 283 struct { 284 int max; 285 int free; 286 int cur; 287 int put; 288 /* access via pushbuf_bo */ 289 290 int ib_base; 291 int ib_max; 292 int ib_free; 293 int ib_put; 294 } dma; 295 296 uint32_t sw_subchannel[8]; 297 298 struct nouveau_vma dispc_vma[2]; 299 struct { 300 struct nouveau_gpuobj *vblsem; 301 uint32_t vblsem_head; 302 uint32_t vblsem_offset; 303 uint32_t vblsem_rval; 304 struct list_head vbl_wait; 305 struct list_head flip; 306 } nvsw; 307 308 struct { 309 bool active; 310 char name[32]; 311 struct drm_info_list info; 312 } debugfs; 313}; 314 315struct nouveau_exec_engine { 316 void (*destroy)(struct drm_device *, int engine); 317 int (*init)(struct drm_device *, int engine); 318 int (*fini)(struct drm_device *, int engine, bool suspend); 319 int (*context_new)(struct nouveau_channel *, int engine); 320 void (*context_del)(struct nouveau_channel *, int engine); 321 int (*object_new)(struct nouveau_channel *, int engine, 322 u32 handle, u16 class); 323 void (*set_tile_region)(struct drm_device *dev, int i); 324 void (*tlb_flush)(struct drm_device *, int engine); 325}; 326 327struct nouveau_instmem_engine { 328 void *priv; 329 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 int (*suspend)(struct drm_device *dev); 333 void (*resume)(struct drm_device *dev); 334 335 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 336 u32 size, u32 align); 337 void (*put)(struct nouveau_gpuobj *); 338 int (*map)(struct nouveau_gpuobj *); 339 void (*unmap)(struct nouveau_gpuobj *); 340 341 void (*flush)(struct drm_device *); 342}; 343 344struct nouveau_mc_engine { 345 int (*init)(struct drm_device *dev); 346 void (*takedown)(struct drm_device *dev); 347}; 348 349struct nouveau_timer_engine { 350 int (*init)(struct drm_device *dev); 351 void (*takedown)(struct drm_device *dev); 352 uint64_t (*read)(struct drm_device *dev); 353}; 354 355struct nouveau_fb_engine { 356 int num_tiles; 357 struct drm_mm tag_heap; 358 void *priv; 359 360 int (*init)(struct drm_device *dev); 361 void (*takedown)(struct drm_device *dev); 362 363 void (*init_tile_region)(struct drm_device *dev, int i, 364 uint32_t addr, uint32_t size, 365 uint32_t pitch, uint32_t flags); 366 void (*set_tile_region)(struct drm_device *dev, int i); 367 void (*free_tile_region)(struct drm_device *dev, int i); 368}; 369 370struct nouveau_fifo_engine { 371 void *priv; 372 int channels; 373 374 struct nouveau_gpuobj *playlist[2]; 375 int cur_playlist; 376 377 int (*init)(struct drm_device *); 378 void (*takedown)(struct drm_device *); 379 380 void (*disable)(struct drm_device *); 381 void (*enable)(struct drm_device *); 382 bool (*reassign)(struct drm_device *, bool enable); 383 bool (*cache_pull)(struct drm_device *dev, bool enable); 384 385 int (*channel_id)(struct drm_device *); 386 387 int (*create_context)(struct nouveau_channel *); 388 void (*destroy_context)(struct nouveau_channel *); 389 int (*load_context)(struct nouveau_channel *); 390 int (*unload_context)(struct drm_device *); 391 void (*tlb_flush)(struct drm_device *dev); 392}; 393 394struct nouveau_display_engine { 395 void *priv; 396 int (*early_init)(struct drm_device *); 397 void (*late_takedown)(struct drm_device *); 398 int (*create)(struct drm_device *); 399 int (*init)(struct drm_device *); 400 void (*destroy)(struct drm_device *); 401 402 struct drm_property *dithering_mode; 403 struct drm_property *dithering_depth; 404 struct drm_property *underscan_property; 405 struct drm_property *underscan_hborder_property; 406 struct drm_property *underscan_vborder_property; 407}; 408 409struct nouveau_gpio_engine { 410 void *priv; 411 412 int (*init)(struct drm_device *); 413 void (*takedown)(struct drm_device *); 414 415 int (*get)(struct drm_device *, enum dcb_gpio_tag); 416 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 417 418 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 419 void (*)(void *, int), void *); 420 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 421 void (*)(void *, int), void *); 422 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 423}; 424 425struct nouveau_pm_voltage_level { 426 u32 voltage; /* microvolts */ 427 u8 vid; 428}; 429 430struct nouveau_pm_voltage { 431 bool supported; 432 u8 version; 433 u8 vid_mask; 434 435 struct nouveau_pm_voltage_level *level; 436 int nr_level; 437}; 438 439struct nouveau_pm_memtiming { 440 int id; 441 u32 reg_0; /* 0x10f290 on Fermi, 0x100220 for older */ 442 u32 reg_1; 443 u32 reg_2; 444 u32 reg_3; 445 u32 reg_4; 446 u32 reg_5; 447 u32 reg_6; 448 u32 reg_7; 449 u32 reg_8; 450 /* To be written to 0x1002c0 */ 451 u8 CL; 452 u8 WR; 453}; 454 455struct nouveau_pm_tbl_header{ 456 u8 version; 457 u8 header_len; 458 u8 entry_cnt; 459 u8 entry_len; 460}; 461 462struct nouveau_pm_tbl_entry{ 463 u8 tWR; 464 u8 tUNK_1; 465 u8 tCL; 466 u8 tRP; /* Byte 3 */ 467 u8 empty_4; 468 u8 tRAS; /* Byte 5 */ 469 u8 empty_6; 470 u8 tRFC; /* Byte 7 */ 471 u8 empty_8; 472 u8 tRC; /* Byte 9 */ 473 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14; 474 u8 empty_15,empty_16,empty_17; 475 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21; 476}; 477 478/* nouveau_mem.c */ 479void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, 480 struct nouveau_pm_tbl_entry *e, uint8_t magic_number, 481 struct nouveau_pm_memtiming *timing); 482 483#define NOUVEAU_PM_MAX_LEVEL 8 484struct nouveau_pm_level { 485 struct device_attribute dev_attr; 486 char name[32]; 487 int id; 488 489 u32 core; 490 u32 memory; 491 u32 shader; 492 u32 rop; 493 u32 copy; 494 u32 daemon; 495 u32 vdec; 496 u32 dom6; 497 u32 unka0; /* nva3:nvc0 */ 498 u32 hub01; /* nvc0- */ 499 u32 hub06; /* nvc0- */ 500 u32 hub07; /* nvc0- */ 501 502 u32 volt_min; /* microvolts */ 503 u32 volt_max; 504 u8 fanspeed; 505 506 u16 memscript; 507 struct nouveau_pm_memtiming *timing; 508}; 509 510struct nouveau_pm_temp_sensor_constants { 511 u16 offset_constant; 512 s16 offset_mult; 513 s16 offset_div; 514 s16 slope_mult; 515 s16 slope_div; 516}; 517 518struct nouveau_pm_threshold_temp { 519 s16 critical; 520 s16 down_clock; 521 s16 fan_boost; 522}; 523 524struct nouveau_pm_memtimings { 525 bool supported; 526 struct nouveau_pm_memtiming *timing; 527 int nr_timing; 528}; 529 530struct nouveau_pm_fan { 531 u32 min_duty; 532 u32 max_duty; 533 u32 pwm_freq; 534}; 535 536struct nouveau_pm_engine { 537 struct nouveau_pm_voltage voltage; 538 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 539 int nr_perflvl; 540 struct nouveau_pm_memtimings memtimings; 541 struct nouveau_pm_temp_sensor_constants sensor_constants; 542 struct nouveau_pm_threshold_temp threshold_temp; 543 struct nouveau_pm_fan fan; 544 u32 pwm_divisor; 545 546 struct nouveau_pm_level boot; 547 struct nouveau_pm_level *cur; 548 549 struct device *hwmon; 550 struct notifier_block acpi_nb; 551 552 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 553 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 554 int (*clocks_set)(struct drm_device *, void *); 555 556 int (*voltage_get)(struct drm_device *); 557 int (*voltage_set)(struct drm_device *, int voltage); 558 int (*pwm_get)(struct drm_device *, struct dcb_gpio_entry*, u32*, u32*); 559 int (*pwm_set)(struct drm_device *, struct dcb_gpio_entry*, u32, u32); 560 int (*temp_get)(struct drm_device *); 561}; 562 563struct nouveau_vram_engine { 564 struct nouveau_mm mm; 565 566 int (*init)(struct drm_device *); 567 void (*takedown)(struct drm_device *dev); 568 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 569 u32 type, struct nouveau_mem **); 570 void (*put)(struct drm_device *, struct nouveau_mem **); 571 572 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 573}; 574 575struct nouveau_engine { 576 struct nouveau_instmem_engine instmem; 577 struct nouveau_mc_engine mc; 578 struct nouveau_timer_engine timer; 579 struct nouveau_fb_engine fb; 580 struct nouveau_fifo_engine fifo; 581 struct nouveau_display_engine display; 582 struct nouveau_gpio_engine gpio; 583 struct nouveau_pm_engine pm; 584 struct nouveau_vram_engine vram; 585}; 586 587struct nouveau_pll_vals { 588 union { 589 struct { 590#ifdef __BIG_ENDIAN 591 uint8_t N1, M1, N2, M2; 592#else 593 uint8_t M1, N1, M2, N2; 594#endif 595 }; 596 struct { 597 uint16_t NM1, NM2; 598 } __attribute__((packed)); 599 }; 600 int log2P; 601 602 int refclk; 603}; 604 605enum nv04_fp_display_regs { 606 FP_DISPLAY_END, 607 FP_TOTAL, 608 FP_CRTC, 609 FP_SYNC_START, 610 FP_SYNC_END, 611 FP_VALID_START, 612 FP_VALID_END 613}; 614 615struct nv04_crtc_reg { 616 unsigned char MiscOutReg; 617 uint8_t CRTC[0xa0]; 618 uint8_t CR58[0x10]; 619 uint8_t Sequencer[5]; 620 uint8_t Graphics[9]; 621 uint8_t Attribute[21]; 622 unsigned char DAC[768]; 623 624 /* PCRTC regs */ 625 uint32_t fb_start; 626 uint32_t crtc_cfg; 627 uint32_t cursor_cfg; 628 uint32_t gpio_ext; 629 uint32_t crtc_830; 630 uint32_t crtc_834; 631 uint32_t crtc_850; 632 uint32_t crtc_eng_ctrl; 633 634 /* PRAMDAC regs */ 635 uint32_t nv10_cursync; 636 struct nouveau_pll_vals pllvals; 637 uint32_t ramdac_gen_ctrl; 638 uint32_t ramdac_630; 639 uint32_t ramdac_634; 640 uint32_t tv_setup; 641 uint32_t tv_vtotal; 642 uint32_t tv_vskew; 643 uint32_t tv_vsync_delay; 644 uint32_t tv_htotal; 645 uint32_t tv_hskew; 646 uint32_t tv_hsync_delay; 647 uint32_t tv_hsync_delay2; 648 uint32_t fp_horiz_regs[7]; 649 uint32_t fp_vert_regs[7]; 650 uint32_t dither; 651 uint32_t fp_control; 652 uint32_t dither_regs[6]; 653 uint32_t fp_debug_0; 654 uint32_t fp_debug_1; 655 uint32_t fp_debug_2; 656 uint32_t fp_margin_color; 657 uint32_t ramdac_8c0; 658 uint32_t ramdac_a20; 659 uint32_t ramdac_a24; 660 uint32_t ramdac_a34; 661 uint32_t ctv_regs[38]; 662}; 663 664struct nv04_output_reg { 665 uint32_t output; 666 int head; 667}; 668 669struct nv04_mode_state { 670 struct nv04_crtc_reg crtc_reg[2]; 671 uint32_t pllsel; 672 uint32_t sel_clk; 673}; 674 675enum nouveau_card_type { 676 NV_04 = 0x00, 677 NV_10 = 0x10, 678 NV_20 = 0x20, 679 NV_30 = 0x30, 680 NV_40 = 0x40, 681 NV_50 = 0x50, 682 NV_C0 = 0xc0, 683 NV_D0 = 0xd0 684}; 685 686struct drm_nouveau_private { 687 struct drm_device *dev; 688 bool noaccel; 689 690 /* the card type, takes NV_* as values */ 691 enum nouveau_card_type card_type; 692 /* exact chipset, derived from NV_PMC_BOOT_0 */ 693 int chipset; 694 int flags; 695 u32 crystal; 696 697 void __iomem *mmio; 698 699 spinlock_t ramin_lock; 700 void __iomem *ramin; 701 u32 ramin_size; 702 u32 ramin_base; 703 bool ramin_available; 704 struct drm_mm ramin_heap; 705 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 706 struct list_head gpuobj_list; 707 struct list_head classes; 708 709 struct nouveau_bo *vga_ram; 710 711 /* interrupt handling */ 712 void (*irq_handler[32])(struct drm_device *); 713 bool msi_enabled; 714 715 struct list_head vbl_waiting; 716 717 struct { 718 struct drm_global_reference mem_global_ref; 719 struct ttm_bo_global_ref bo_global_ref; 720 struct ttm_bo_device bdev; 721 atomic_t validate_sequence; 722 } ttm; 723 724 struct { 725 spinlock_t lock; 726 struct drm_mm heap; 727 struct nouveau_bo *bo; 728 } fence; 729 730 struct { 731 spinlock_t lock; 732 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 733 } channels; 734 735 struct nouveau_engine engine; 736 struct nouveau_channel *channel; 737 738 /* For PFIFO and PGRAPH. */ 739 spinlock_t context_switch_lock; 740 741 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 742 spinlock_t vm_lock; 743 744 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 745 struct nouveau_ramht *ramht; 746 struct nouveau_gpuobj *ramfc; 747 struct nouveau_gpuobj *ramro; 748 749 uint32_t ramin_rsvd_vram; 750 751 struct { 752 enum { 753 NOUVEAU_GART_NONE = 0, 754 NOUVEAU_GART_AGP, /* AGP */ 755 NOUVEAU_GART_PDMA, /* paged dma object */ 756 NOUVEAU_GART_HW /* on-chip gart/vm */ 757 } type; 758 uint64_t aper_base; 759 uint64_t aper_size; 760 uint64_t aper_free; 761 762 struct ttm_backend_func *func; 763 764 struct { 765 struct page *page; 766 dma_addr_t addr; 767 } dummy; 768 769 struct nouveau_gpuobj *sg_ctxdma; 770 } gart_info; 771 772 /* nv10-nv40 tiling regions */ 773 struct { 774 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 775 spinlock_t lock; 776 } tile; 777 778 /* VRAM/fb configuration */ 779 uint64_t vram_size; 780 uint64_t vram_sys_base; 781 782 uint64_t fb_available_size; 783 uint64_t fb_mappable_pages; 784 uint64_t fb_aper_free; 785 int fb_mtrr; 786 787 /* BAR control (NV50-) */ 788 struct nouveau_vm *bar1_vm; 789 struct nouveau_vm *bar3_vm; 790 791 /* G8x/G9x virtual address space */ 792 struct nouveau_vm *chan_vm; 793 794 struct nvbios vbios; 795 796 struct nv04_mode_state mode_reg; 797 struct nv04_mode_state saved_reg; 798 uint32_t saved_vga_font[4][16384]; 799 uint32_t crtc_owner; 800 uint32_t dac_users[4]; 801 802 struct backlight_device *backlight; 803 804 struct { 805 struct dentry *channel_root; 806 } debugfs; 807 808 struct nouveau_fbdev *nfbdev; 809 struct apertures_struct *apertures; 810}; 811 812static inline struct drm_nouveau_private * 813nouveau_private(struct drm_device *dev) 814{ 815 return dev->dev_private; 816} 817 818static inline struct drm_nouveau_private * 819nouveau_bdev(struct ttm_bo_device *bd) 820{ 821 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 822} 823 824static inline int 825nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 826{ 827 struct nouveau_bo *prev; 828 829 if (!pnvbo) 830 return -EINVAL; 831 prev = *pnvbo; 832 833 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 834 if (prev) { 835 struct ttm_buffer_object *bo = &prev->bo; 836 837 ttm_bo_unref(&bo); 838 } 839 840 return 0; 841} 842 843/* nouveau_drv.c */ 844extern int nouveau_modeset; 845extern int nouveau_agpmode; 846extern int nouveau_duallink; 847extern int nouveau_uscript_lvds; 848extern int nouveau_uscript_tmds; 849extern int nouveau_vram_pushbuf; 850extern int nouveau_vram_notify; 851extern int nouveau_fbpercrtc; 852extern int nouveau_tv_disable; 853extern char *nouveau_tv_norm; 854extern int nouveau_reg_debug; 855extern char *nouveau_vbios; 856extern int nouveau_ignorelid; 857extern int nouveau_nofbaccel; 858extern int nouveau_noaccel; 859extern int nouveau_force_post; 860extern int nouveau_override_conntype; 861extern char *nouveau_perflvl; 862extern int nouveau_perflvl_wr; 863extern int nouveau_msi; 864extern int nouveau_ctxfw; 865 866extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 867extern int nouveau_pci_resume(struct pci_dev *pdev); 868 869/* nouveau_state.c */ 870extern int nouveau_open(struct drm_device *, struct drm_file *); 871extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 872extern void nouveau_postclose(struct drm_device *, struct drm_file *); 873extern int nouveau_load(struct drm_device *, unsigned long flags); 874extern int nouveau_firstopen(struct drm_device *); 875extern void nouveau_lastclose(struct drm_device *); 876extern int nouveau_unload(struct drm_device *); 877extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 878 struct drm_file *); 879extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 880 struct drm_file *); 881extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 882 uint32_t reg, uint32_t mask, uint32_t val); 883extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 884 uint32_t reg, uint32_t mask, uint32_t val); 885extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 886 bool (*cond)(void *), void *); 887extern bool nouveau_wait_for_idle(struct drm_device *); 888extern int nouveau_card_init(struct drm_device *); 889 890/* nouveau_mem.c */ 891extern int nouveau_mem_vram_init(struct drm_device *); 892extern void nouveau_mem_vram_fini(struct drm_device *); 893extern int nouveau_mem_gart_init(struct drm_device *); 894extern void nouveau_mem_gart_fini(struct drm_device *); 895extern int nouveau_mem_init_agp(struct drm_device *); 896extern int nouveau_mem_reset_agp(struct drm_device *); 897extern void nouveau_mem_close(struct drm_device *); 898extern int nouveau_mem_detect(struct drm_device *); 899extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 900extern struct nouveau_tile_reg *nv10_mem_set_tiling( 901 struct drm_device *dev, uint32_t addr, uint32_t size, 902 uint32_t pitch, uint32_t flags); 903extern void nv10_mem_put_tile_region(struct drm_device *dev, 904 struct nouveau_tile_reg *tile, 905 struct nouveau_fence *fence); 906extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 907extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 908 909/* nouveau_notifier.c */ 910extern int nouveau_notifier_init_channel(struct nouveau_channel *); 911extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 912extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 913 int cout, uint32_t start, uint32_t end, 914 uint32_t *offset); 915extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 916extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 917 struct drm_file *); 918extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 919 struct drm_file *); 920 921/* nouveau_channel.c */ 922extern struct drm_ioctl_desc nouveau_ioctls[]; 923extern int nouveau_max_ioctl; 924extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 925extern int nouveau_channel_alloc(struct drm_device *dev, 926 struct nouveau_channel **chan, 927 struct drm_file *file_priv, 928 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 929extern struct nouveau_channel * 930nouveau_channel_get_unlocked(struct nouveau_channel *); 931extern struct nouveau_channel * 932nouveau_channel_get(struct drm_file *, int id); 933extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 934extern void nouveau_channel_put(struct nouveau_channel **); 935extern void nouveau_channel_ref(struct nouveau_channel *chan, 936 struct nouveau_channel **pchan); 937extern void nouveau_channel_idle(struct nouveau_channel *chan); 938 939/* nouveau_object.c */ 940#define NVOBJ_ENGINE_ADD(d, e, p) do { \ 941 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 942 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 943} while (0) 944 945#define NVOBJ_ENGINE_DEL(d, e) do { \ 946 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 947 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 948} while (0) 949 950#define NVOBJ_CLASS(d, c, e) do { \ 951 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 952 if (ret) \ 953 return ret; \ 954} while (0) 955 956#define NVOBJ_MTHD(d, c, m, e) do { \ 957 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 958 if (ret) \ 959 return ret; \ 960} while (0) 961 962extern int nouveau_gpuobj_early_init(struct drm_device *); 963extern int nouveau_gpuobj_init(struct drm_device *); 964extern void nouveau_gpuobj_takedown(struct drm_device *); 965extern int nouveau_gpuobj_suspend(struct drm_device *dev); 966extern void nouveau_gpuobj_resume(struct drm_device *dev); 967extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 968extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 969 int (*exec)(struct nouveau_channel *, 970 u32 class, u32 mthd, u32 data)); 971extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 972extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 973extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 974 uint32_t vram_h, uint32_t tt_h); 975extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 976extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 977 uint32_t size, int align, uint32_t flags, 978 struct nouveau_gpuobj **); 979extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 980 struct nouveau_gpuobj **); 981extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 982 u32 size, u32 flags, 983 struct nouveau_gpuobj **); 984extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 985 uint64_t offset, uint64_t size, int access, 986 int target, struct nouveau_gpuobj **); 987extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 988extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 989 u64 size, int target, int access, u32 type, 990 u32 comp, struct nouveau_gpuobj **pobj); 991extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 992 int class, u64 base, u64 size, int target, 993 int access, u32 type, u32 comp); 994extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 995 struct drm_file *); 996extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 997 struct drm_file *); 998 999/* nouveau_irq.c */ 1000extern int nouveau_irq_init(struct drm_device *); 1001extern void nouveau_irq_fini(struct drm_device *); 1002extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 1003extern void nouveau_irq_register(struct drm_device *, int status_bit, 1004 void (*)(struct drm_device *)); 1005extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 1006extern void nouveau_irq_preinstall(struct drm_device *); 1007extern int nouveau_irq_postinstall(struct drm_device *); 1008extern void nouveau_irq_uninstall(struct drm_device *); 1009 1010/* nouveau_sgdma.c */ 1011extern int nouveau_sgdma_init(struct drm_device *); 1012extern void nouveau_sgdma_takedown(struct drm_device *); 1013extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 1014 uint32_t offset); 1015extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1016 unsigned long size, 1017 uint32_t page_flags, 1018 struct page *dummy_read_page); 1019 1020/* nouveau_debugfs.c */ 1021#if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1022extern int nouveau_debugfs_init(struct drm_minor *); 1023extern void nouveau_debugfs_takedown(struct drm_minor *); 1024extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1025extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1026#else 1027static inline int 1028nouveau_debugfs_init(struct drm_minor *minor) 1029{ 1030 return 0; 1031} 1032 1033static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1034{ 1035} 1036 1037static inline int 1038nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1039{ 1040 return 0; 1041} 1042 1043static inline void 1044nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1045{ 1046} 1047#endif 1048 1049/* nouveau_dma.c */ 1050extern void nouveau_dma_pre_init(struct nouveau_channel *); 1051extern int nouveau_dma_init(struct nouveau_channel *); 1052extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1053 1054/* nouveau_acpi.c */ 1055#define ROM_BIOS_PAGE 4096 1056#if defined(CONFIG_ACPI) 1057void nouveau_register_dsm_handler(void); 1058void nouveau_unregister_dsm_handler(void); 1059int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1060bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1061int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1062#else 1063static inline void nouveau_register_dsm_handler(void) {} 1064static inline void nouveau_unregister_dsm_handler(void) {} 1065static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1066static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1067static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1068#endif 1069 1070/* nouveau_backlight.c */ 1071#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1072extern int nouveau_backlight_init(struct drm_device *); 1073extern void nouveau_backlight_exit(struct drm_device *); 1074#else 1075static inline int nouveau_backlight_init(struct drm_device *dev) 1076{ 1077 return 0; 1078} 1079 1080static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1081#endif 1082 1083/* nouveau_bios.c */ 1084extern int nouveau_bios_init(struct drm_device *); 1085extern void nouveau_bios_takedown(struct drm_device *dev); 1086extern int nouveau_run_vbios_init(struct drm_device *); 1087extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1088 struct dcb_entry *, int crtc); 1089extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1090extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1091 enum dcb_gpio_tag); 1092extern struct dcb_connector_table_entry * 1093nouveau_bios_connector_entry(struct drm_device *, int index); 1094extern u32 get_pll_register(struct drm_device *, enum pll_types); 1095extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1096 struct pll_lims *); 1097extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1098 struct dcb_entry *, int crtc); 1099extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1100extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1101extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1102 bool *dl, bool *if_is_24bit); 1103extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1104 int head, int pxclk); 1105extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1106 enum LVDS_script, int pxclk); 1107bool bios_encoder_match(struct dcb_entry *, u32 hash); 1108 1109/* nouveau_ttm.c */ 1110int nouveau_ttm_global_init(struct drm_nouveau_private *); 1111void nouveau_ttm_global_release(struct drm_nouveau_private *); 1112int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1113 1114/* nouveau_hdmi.c */ 1115void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1116 1117/* nouveau_dp.c */ 1118int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1119 uint8_t *data, int data_nr); 1120bool nouveau_dp_detect(struct drm_encoder *); 1121bool nouveau_dp_link_train(struct drm_encoder *, u32 datarate); 1122void nouveau_dp_tu_update(struct drm_device *, int, int, u32, u32); 1123u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_entry *, u8 **); 1124 1125/* nv04_fb.c */ 1126extern int nv04_fb_init(struct drm_device *); 1127extern void nv04_fb_takedown(struct drm_device *); 1128 1129/* nv10_fb.c */ 1130extern int nv10_fb_init(struct drm_device *); 1131extern void nv10_fb_takedown(struct drm_device *); 1132extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1133 uint32_t addr, uint32_t size, 1134 uint32_t pitch, uint32_t flags); 1135extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1136extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1137 1138/* nv30_fb.c */ 1139extern int nv30_fb_init(struct drm_device *); 1140extern void nv30_fb_takedown(struct drm_device *); 1141extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1142 uint32_t addr, uint32_t size, 1143 uint32_t pitch, uint32_t flags); 1144extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1145 1146/* nv40_fb.c */ 1147extern int nv40_fb_init(struct drm_device *); 1148extern void nv40_fb_takedown(struct drm_device *); 1149extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1150 1151/* nv50_fb.c */ 1152extern int nv50_fb_init(struct drm_device *); 1153extern void nv50_fb_takedown(struct drm_device *); 1154extern void nv50_fb_vm_trap(struct drm_device *, int display); 1155 1156/* nvc0_fb.c */ 1157extern int nvc0_fb_init(struct drm_device *); 1158extern void nvc0_fb_takedown(struct drm_device *); 1159 1160/* nv04_fifo.c */ 1161extern int nv04_fifo_init(struct drm_device *); 1162extern void nv04_fifo_fini(struct drm_device *); 1163extern void nv04_fifo_disable(struct drm_device *); 1164extern void nv04_fifo_enable(struct drm_device *); 1165extern bool nv04_fifo_reassign(struct drm_device *, bool); 1166extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1167extern int nv04_fifo_channel_id(struct drm_device *); 1168extern int nv04_fifo_create_context(struct nouveau_channel *); 1169extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1170extern int nv04_fifo_load_context(struct nouveau_channel *); 1171extern int nv04_fifo_unload_context(struct drm_device *); 1172extern void nv04_fifo_isr(struct drm_device *); 1173 1174/* nv10_fifo.c */ 1175extern int nv10_fifo_init(struct drm_device *); 1176extern int nv10_fifo_channel_id(struct drm_device *); 1177extern int nv10_fifo_create_context(struct nouveau_channel *); 1178extern int nv10_fifo_load_context(struct nouveau_channel *); 1179extern int nv10_fifo_unload_context(struct drm_device *); 1180 1181/* nv40_fifo.c */ 1182extern int nv40_fifo_init(struct drm_device *); 1183extern int nv40_fifo_create_context(struct nouveau_channel *); 1184extern int nv40_fifo_load_context(struct nouveau_channel *); 1185extern int nv40_fifo_unload_context(struct drm_device *); 1186 1187/* nv50_fifo.c */ 1188extern int nv50_fifo_init(struct drm_device *); 1189extern void nv50_fifo_takedown(struct drm_device *); 1190extern int nv50_fifo_channel_id(struct drm_device *); 1191extern int nv50_fifo_create_context(struct nouveau_channel *); 1192extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1193extern int nv50_fifo_load_context(struct nouveau_channel *); 1194extern int nv50_fifo_unload_context(struct drm_device *); 1195extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1196 1197/* nvc0_fifo.c */ 1198extern int nvc0_fifo_init(struct drm_device *); 1199extern void nvc0_fifo_takedown(struct drm_device *); 1200extern void nvc0_fifo_disable(struct drm_device *); 1201extern void nvc0_fifo_enable(struct drm_device *); 1202extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1203extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1204extern int nvc0_fifo_channel_id(struct drm_device *); 1205extern int nvc0_fifo_create_context(struct nouveau_channel *); 1206extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1207extern int nvc0_fifo_load_context(struct nouveau_channel *); 1208extern int nvc0_fifo_unload_context(struct drm_device *); 1209 1210/* nv04_graph.c */ 1211extern int nv04_graph_create(struct drm_device *); 1212extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1213extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1214 u32 class, u32 mthd, u32 data); 1215extern struct nouveau_bitfield nv04_graph_nsource[]; 1216 1217/* nv10_graph.c */ 1218extern int nv10_graph_create(struct drm_device *); 1219extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1220extern struct nouveau_bitfield nv10_graph_intr[]; 1221extern struct nouveau_bitfield nv10_graph_nstatus[]; 1222 1223/* nv20_graph.c */ 1224extern int nv20_graph_create(struct drm_device *); 1225 1226/* nv40_graph.c */ 1227extern int nv40_graph_create(struct drm_device *); 1228extern void nv40_grctx_init(struct nouveau_grctx *); 1229 1230/* nv50_graph.c */ 1231extern int nv50_graph_create(struct drm_device *); 1232extern int nv50_grctx_init(struct nouveau_grctx *); 1233extern struct nouveau_enum nv50_data_error_names[]; 1234extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1235 1236/* nvc0_graph.c */ 1237extern int nvc0_graph_create(struct drm_device *); 1238extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1239 1240/* nv84_crypt.c */ 1241extern int nv84_crypt_create(struct drm_device *); 1242 1243/* nv98_crypt.c */ 1244extern int nv98_crypt_create(struct drm_device *dev); 1245 1246/* nva3_copy.c */ 1247extern int nva3_copy_create(struct drm_device *dev); 1248 1249/* nvc0_copy.c */ 1250extern int nvc0_copy_create(struct drm_device *dev, int engine); 1251 1252/* nv31_mpeg.c */ 1253extern int nv31_mpeg_create(struct drm_device *dev); 1254 1255/* nv50_mpeg.c */ 1256extern int nv50_mpeg_create(struct drm_device *dev); 1257 1258/* nv84_bsp.c */ 1259/* nv98_bsp.c */ 1260extern int nv84_bsp_create(struct drm_device *dev); 1261 1262/* nv84_vp.c */ 1263/* nv98_vp.c */ 1264extern int nv84_vp_create(struct drm_device *dev); 1265 1266/* nv98_ppp.c */ 1267extern int nv98_ppp_create(struct drm_device *dev); 1268 1269/* nv04_instmem.c */ 1270extern int nv04_instmem_init(struct drm_device *); 1271extern void nv04_instmem_takedown(struct drm_device *); 1272extern int nv04_instmem_suspend(struct drm_device *); 1273extern void nv04_instmem_resume(struct drm_device *); 1274extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1275 u32 size, u32 align); 1276extern void nv04_instmem_put(struct nouveau_gpuobj *); 1277extern int nv04_instmem_map(struct nouveau_gpuobj *); 1278extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1279extern void nv04_instmem_flush(struct drm_device *); 1280 1281/* nv50_instmem.c */ 1282extern int nv50_instmem_init(struct drm_device *); 1283extern void nv50_instmem_takedown(struct drm_device *); 1284extern int nv50_instmem_suspend(struct drm_device *); 1285extern void nv50_instmem_resume(struct drm_device *); 1286extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1287 u32 size, u32 align); 1288extern void nv50_instmem_put(struct nouveau_gpuobj *); 1289extern int nv50_instmem_map(struct nouveau_gpuobj *); 1290extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1291extern void nv50_instmem_flush(struct drm_device *); 1292extern void nv84_instmem_flush(struct drm_device *); 1293 1294/* nvc0_instmem.c */ 1295extern int nvc0_instmem_init(struct drm_device *); 1296extern void nvc0_instmem_takedown(struct drm_device *); 1297extern int nvc0_instmem_suspend(struct drm_device *); 1298extern void nvc0_instmem_resume(struct drm_device *); 1299 1300/* nv04_mc.c */ 1301extern int nv04_mc_init(struct drm_device *); 1302extern void nv04_mc_takedown(struct drm_device *); 1303 1304/* nv40_mc.c */ 1305extern int nv40_mc_init(struct drm_device *); 1306extern void nv40_mc_takedown(struct drm_device *); 1307 1308/* nv50_mc.c */ 1309extern int nv50_mc_init(struct drm_device *); 1310extern void nv50_mc_takedown(struct drm_device *); 1311 1312/* nv04_timer.c */ 1313extern int nv04_timer_init(struct drm_device *); 1314extern uint64_t nv04_timer_read(struct drm_device *); 1315extern void nv04_timer_takedown(struct drm_device *); 1316 1317extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1318 unsigned long arg); 1319 1320/* nv04_dac.c */ 1321extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1322extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1323extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1324extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1325extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1326 1327/* nv04_dfp.c */ 1328extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1329extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1330extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1331 int head, bool dl); 1332extern void nv04_dfp_disable(struct drm_device *dev, int head); 1333extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1334 1335/* nv04_tv.c */ 1336extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1337extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1338 1339/* nv17_tv.c */ 1340extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1341 1342/* nv04_display.c */ 1343extern int nv04_display_early_init(struct drm_device *); 1344extern void nv04_display_late_takedown(struct drm_device *); 1345extern int nv04_display_create(struct drm_device *); 1346extern int nv04_display_init(struct drm_device *); 1347extern void nv04_display_destroy(struct drm_device *); 1348 1349/* nvd0_display.c */ 1350extern int nvd0_display_create(struct drm_device *); 1351extern int nvd0_display_init(struct drm_device *); 1352extern void nvd0_display_destroy(struct drm_device *); 1353 1354/* nv04_crtc.c */ 1355extern int nv04_crtc_create(struct drm_device *, int index); 1356 1357/* nouveau_bo.c */ 1358extern struct ttm_bo_driver nouveau_bo_driver; 1359extern int nouveau_bo_new(struct drm_device *, int size, int align, 1360 uint32_t flags, uint32_t tile_mode, 1361 uint32_t tile_flags, struct nouveau_bo **); 1362extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1363extern int nouveau_bo_unpin(struct nouveau_bo *); 1364extern int nouveau_bo_map(struct nouveau_bo *); 1365extern void nouveau_bo_unmap(struct nouveau_bo *); 1366extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1367 uint32_t busy); 1368extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1369extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1370extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1371extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1372extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1373extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1374 bool no_wait_reserve, bool no_wait_gpu); 1375 1376extern struct nouveau_vma * 1377nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1378extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1379 struct nouveau_vma *); 1380extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1381 1382/* nouveau_fence.c */ 1383struct nouveau_fence; 1384extern int nouveau_fence_init(struct drm_device *); 1385extern void nouveau_fence_fini(struct drm_device *); 1386extern int nouveau_fence_channel_init(struct nouveau_channel *); 1387extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1388extern void nouveau_fence_update(struct nouveau_channel *); 1389extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1390 bool emit); 1391extern int nouveau_fence_emit(struct nouveau_fence *); 1392extern void nouveau_fence_work(struct nouveau_fence *fence, 1393 void (*work)(void *priv, bool signalled), 1394 void *priv); 1395struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1396 1397extern bool __nouveau_fence_signalled(void *obj, void *arg); 1398extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1399extern int __nouveau_fence_flush(void *obj, void *arg); 1400extern void __nouveau_fence_unref(void **obj); 1401extern void *__nouveau_fence_ref(void *obj); 1402 1403static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1404{ 1405 return __nouveau_fence_signalled(obj, NULL); 1406} 1407static inline int 1408nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1409{ 1410 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1411} 1412extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1413static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1414{ 1415 return __nouveau_fence_flush(obj, NULL); 1416} 1417static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1418{ 1419 __nouveau_fence_unref((void **)obj); 1420} 1421static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1422{ 1423 return __nouveau_fence_ref(obj); 1424} 1425 1426/* nouveau_gem.c */ 1427extern int nouveau_gem_new(struct drm_device *, int size, int align, 1428 uint32_t domain, uint32_t tile_mode, 1429 uint32_t tile_flags, struct nouveau_bo **); 1430extern int nouveau_gem_object_new(struct drm_gem_object *); 1431extern void nouveau_gem_object_del(struct drm_gem_object *); 1432extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1433extern void nouveau_gem_object_close(struct drm_gem_object *, 1434 struct drm_file *); 1435extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1436 struct drm_file *); 1437extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1438 struct drm_file *); 1439extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1440 struct drm_file *); 1441extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1442 struct drm_file *); 1443extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1444 struct drm_file *); 1445 1446/* nouveau_display.c */ 1447int nouveau_display_create(struct drm_device *dev); 1448void nouveau_display_destroy(struct drm_device *dev); 1449int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1450void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1451int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1452 struct drm_pending_vblank_event *event); 1453int nouveau_finish_page_flip(struct nouveau_channel *, 1454 struct nouveau_page_flip_state *); 1455int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1456 struct drm_mode_create_dumb *args); 1457int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1458 uint32_t handle, uint64_t *offset); 1459int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1460 uint32_t handle); 1461 1462/* nv10_gpio.c */ 1463int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1464int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1465 1466/* nv50_gpio.c */ 1467int nv50_gpio_init(struct drm_device *dev); 1468void nv50_gpio_fini(struct drm_device *dev); 1469int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1470int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1471int nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1472int nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1473int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1474 void (*)(void *, int), void *); 1475void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1476 void (*)(void *, int), void *); 1477bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1478 1479/* nv50_calc. */ 1480int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1481 int *N1, int *M1, int *N2, int *M2, int *P); 1482int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1483 int clk, int *N, int *fN, int *M, int *P); 1484 1485#ifndef ioread32_native 1486#ifdef __BIG_ENDIAN 1487#define ioread16_native ioread16be 1488#define iowrite16_native iowrite16be 1489#define ioread32_native ioread32be 1490#define iowrite32_native iowrite32be 1491#else /* def __BIG_ENDIAN */ 1492#define ioread16_native ioread16 1493#define iowrite16_native iowrite16 1494#define ioread32_native ioread32 1495#define iowrite32_native iowrite32 1496#endif /* def __BIG_ENDIAN else */ 1497#endif /* !ioread32_native */ 1498 1499/* channel control reg access */ 1500static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1501{ 1502 return ioread32_native(chan->user + reg); 1503} 1504 1505static inline void nvchan_wr32(struct nouveau_channel *chan, 1506 unsigned reg, u32 val) 1507{ 1508 iowrite32_native(val, chan->user + reg); 1509} 1510 1511/* register access */ 1512static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1513{ 1514 struct drm_nouveau_private *dev_priv = dev->dev_private; 1515 return ioread32_native(dev_priv->mmio + reg); 1516} 1517 1518static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1519{ 1520 struct drm_nouveau_private *dev_priv = dev->dev_private; 1521 iowrite32_native(val, dev_priv->mmio + reg); 1522} 1523 1524static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1525{ 1526 u32 tmp = nv_rd32(dev, reg); 1527 nv_wr32(dev, reg, (tmp & ~mask) | val); 1528 return tmp; 1529} 1530 1531static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1532{ 1533 struct drm_nouveau_private *dev_priv = dev->dev_private; 1534 return ioread8(dev_priv->mmio + reg); 1535} 1536 1537static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1538{ 1539 struct drm_nouveau_private *dev_priv = dev->dev_private; 1540 iowrite8(val, dev_priv->mmio + reg); 1541} 1542 1543#define nv_wait(dev, reg, mask, val) \ 1544 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1545#define nv_wait_ne(dev, reg, mask, val) \ 1546 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1547#define nv_wait_cb(dev, func, data) \ 1548 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1549 1550/* PRAMIN access */ 1551static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1552{ 1553 struct drm_nouveau_private *dev_priv = dev->dev_private; 1554 return ioread32_native(dev_priv->ramin + offset); 1555} 1556 1557static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1558{ 1559 struct drm_nouveau_private *dev_priv = dev->dev_private; 1560 iowrite32_native(val, dev_priv->ramin + offset); 1561} 1562 1563/* object access */ 1564extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1565extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1566 1567/* 1568 * Logging 1569 * Argument d is (struct drm_device *). 1570 */ 1571#define NV_PRINTK(level, d, fmt, arg...) \ 1572 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1573 pci_name(d->pdev), ##arg) 1574#ifndef NV_DEBUG_NOTRACE 1575#define NV_DEBUG(d, fmt, arg...) do { \ 1576 if (drm_debug & DRM_UT_DRIVER) { \ 1577 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1578 __LINE__, ##arg); \ 1579 } \ 1580} while (0) 1581#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1582 if (drm_debug & DRM_UT_KMS) { \ 1583 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1584 __LINE__, ##arg); \ 1585 } \ 1586} while (0) 1587#else 1588#define NV_DEBUG(d, fmt, arg...) do { \ 1589 if (drm_debug & DRM_UT_DRIVER) \ 1590 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1591} while (0) 1592#define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1593 if (drm_debug & DRM_UT_KMS) \ 1594 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1595} while (0) 1596#endif 1597#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1598#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1599#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1600#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1601#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1602 1603/* nouveau_reg_debug bitmask */ 1604enum { 1605 NOUVEAU_REG_DEBUG_MC = 0x1, 1606 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1607 NOUVEAU_REG_DEBUG_FB = 0x4, 1608 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1609 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1610 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1611 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1612 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1613 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1614 NOUVEAU_REG_DEBUG_EVO = 0x200, 1615 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1616}; 1617 1618#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1619 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1620 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1621} while (0) 1622 1623static inline bool 1624nv_two_heads(struct drm_device *dev) 1625{ 1626 struct drm_nouveau_private *dev_priv = dev->dev_private; 1627 const int impl = dev->pci_device & 0x0ff0; 1628 1629 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1630 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1631 return true; 1632 1633 return false; 1634} 1635 1636static inline bool 1637nv_gf4_disp_arch(struct drm_device *dev) 1638{ 1639 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1640} 1641 1642static inline bool 1643nv_two_reg_pll(struct drm_device *dev) 1644{ 1645 struct drm_nouveau_private *dev_priv = dev->dev_private; 1646 const int impl = dev->pci_device & 0x0ff0; 1647 1648 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1649 return true; 1650 return false; 1651} 1652 1653static inline bool 1654nv_match_device(struct drm_device *dev, unsigned device, 1655 unsigned sub_vendor, unsigned sub_device) 1656{ 1657 return dev->pdev->device == device && 1658 dev->pdev->subsystem_vendor == sub_vendor && 1659 dev->pdev->subsystem_device == sub_device; 1660} 1661 1662static inline void * 1663nv_engine(struct drm_device *dev, int engine) 1664{ 1665 struct drm_nouveau_private *dev_priv = dev->dev_private; 1666 return (void *)dev_priv->eng[engine]; 1667} 1668 1669/* returns 1 if device is one of the nv4x using the 0x4497 object class, 1670 * helpful to determine a number of other hardware features 1671 */ 1672static inline int 1673nv44_graph_class(struct drm_device *dev) 1674{ 1675 struct drm_nouveau_private *dev_priv = dev->dev_private; 1676 1677 if ((dev_priv->chipset & 0xf0) == 0x60) 1678 return 1; 1679 1680 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1681} 1682 1683/* memory type/access flags, do not match hardware values */ 1684#define NV_MEM_ACCESS_RO 1 1685#define NV_MEM_ACCESS_WO 2 1686#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1687#define NV_MEM_ACCESS_SYS 4 1688#define NV_MEM_ACCESS_VM 8 1689 1690#define NV_MEM_TARGET_VRAM 0 1691#define NV_MEM_TARGET_PCI 1 1692#define NV_MEM_TARGET_PCI_NOSNOOP 2 1693#define NV_MEM_TARGET_VM 3 1694#define NV_MEM_TARGET_GART 4 1695 1696#define NV_MEM_TYPE_VM 0x7f 1697#define NV_MEM_COMP_VM 0x03 1698 1699/* NV_SW object class */ 1700#define NV_SW 0x0000506e 1701#define NV_SW_DMA_SEMAPHORE 0x00000060 1702#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1703#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1704#define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1705#define NV_SW_YIELD 0x00000080 1706#define NV_SW_DMA_VBLSEM 0x0000018c 1707#define NV_SW_VBLSEM_OFFSET 0x00000400 1708#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1709#define NV_SW_VBLSEM_RELEASE 0x00000408 1710#define NV_SW_PAGE_FLIP 0x00000500 1711 1712#endif /* __NOUVEAU_DRV_H__ */ 1713