16ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs/* 26ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Copyright 1993-2003 NVIDIA, Corporation 36ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Copyright 2006 Dave Airlie 46ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Copyright 2007 Maarten Maathuis 56ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 66ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Permission is hereby granted, free of charge, to any person obtaining a 76ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * copy of this software and associated documentation files (the "Software"), 86ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * to deal in the Software without restriction, including without limitation 96ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense, 106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * and/or sell copies of the Software, and to permit persons to whom the 116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Software is furnished to do so, subject to the following conditions: 126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * The above copyright notice and this permission notice (including the next 146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * paragraph) shall be included in all copies or substantial portions of the 156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Software. 166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * DEALINGS IN THE SOFTWARE. 246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "drmP.h" 276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "drm_crtc_helper.h" 286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_drv.h" 306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_encoder.h" 316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_connector.h" 326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_crtc.h" 336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_fb.h" 346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nouveau_hw.h" 356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#include "nvreg.h" 36a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball#include "nouveau_fbcon.h" 376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic int 396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_framebuffer *old_fb); 416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggscrtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtcstate->CRTC[index]); 476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->sharpness = level; 716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs level += 0x40; 736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_634 = level; 746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#define PLLSEL_VPLL1_MASK \ 786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#define PLLSEL_VPLL2_MASK \ 816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#define PLLSEL_TV_MASK \ 846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs/* NV4x 0x40.. pll notes: 906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * gpu pll: 0x4000 + 0x4004 916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * ?gpu? pll: 0x4008 + 0x400c 926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * vpll1: 0x4010 + 0x4014 936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * vpll2: 0x4018 + 0x401c 946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * mpll: 0x4020 + 0x4024 956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * mpll: 0x4038 + 0x403c 966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * the first register of each pair has some unknown details: 986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bits 20-23: (mpll) something to do with post divider? 1006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bits 28-31: related to single stage mode? (bit 8/12) 1016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 1026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 1046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 1056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 1066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 1076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_mode_state *state = &dev_priv->mode_reg; 1096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 1106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_pll_vals *pv = ®p->pllvals; 1116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct pll_lims pll_lim; 1126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 113855a95e4fc2ac6b758145ca7d6a0c95b66a57ef8Ben Skeggs if (get_pll_limits(dev, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, &pll_lim)) 1146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return; 1156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* NM2 == 0 is used to determine single stage mode on two stage plls */ 1176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pv->NM2 = 0; 1186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* for newer nv4x the blob uses only the first stage of the vpll below a 1206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * certain clock. for a certain nv4b this is 150MHz. since the max 1216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * output frequency of the first stage for this card is 300MHz, it is 1226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * assumed the threshold is given by vco1 maxfreq/2 1236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 1246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 1256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * not 8, others unknown), the blob always uses both plls. no problem 1266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * has yet been observed in allowing the use a single stage pll on all 1276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * nv43 however. the behaviour of single stage use is untested on nv40 1286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 1296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2)) 1306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 1316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv)) 1336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return; 1346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 1366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* The blob uses this always, so let's do the same */ 1386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) 1396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 1406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* again nv40 and some nv43 act more like nv3x as described above */ 1416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset < 0x41) 1426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 1436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 1446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 1456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (pv->NM2) 147ef2bb506687a5f1cc8ef2fef370bb168b2808106Maarten Maathuis NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 1486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 1496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else 150ef2bb506687a5f1cc8ef2fef370bb168b2808106Maarten Maathuis NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n", 1516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pv->N1, pv->M1, pv->log2P); 1526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 1556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 1576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_dpms(struct drm_crtc *crtc, int mode) 1586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 1596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 1616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs unsigned char seq1 = 0, crtc17 = 0; 1626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs unsigned char crtc1A; 1636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 164ef2bb506687a5f1cc8ef2fef370bb168b2808106Maarten Maathuis NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 1656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->index); 1666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 16725985edcedea6396277003854657b5f3cb31a628Lucas De Marchi if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 1686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return; 1696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->last_dpms = mode; 1716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_two_heads(dev)) 1736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVSetOwner(dev, nv_crtc->index); 1746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 1766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 1776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 1786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs switch (mode) { 1796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs case DRM_MODE_DPMS_STANDBY: 1806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 1816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs seq1 = 0x20; 1826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc17 = 0x80; 1836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc1A |= 0x80; 1846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs break; 1856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs case DRM_MODE_DPMS_SUSPEND: 1866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 1876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs seq1 = 0x20; 1886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc17 = 0x80; 1896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc1A |= 0x40; 1906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs break; 1916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs case DRM_MODE_DPMS_OFF: 1926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Screen: Off; HSync: Off, VSync: Off */ 1936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs seq1 = 0x20; 1946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc17 = 0x00; 1956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc1A |= 0xC0; 1966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs break; 1976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs case DRM_MODE_DPMS_ON: 1986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs default: 1996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Screen: On; HSync: On, VSync: On */ 2006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs seq1 = 0x00; 2016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc17 = 0x80; 2026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs break; 2036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 2046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVVgaSeqReset(dev, nv_crtc->index, true); 2066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Each head has it's own sequencer, so we can turn it off when we want */ 2076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 2086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 2096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 2106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs mdelay(10); 2116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 2126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVVgaSeqReset(dev, nv_crtc->index, false); 2136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 2156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 2166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic bool 2186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode, 2196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_display_mode *adjusted_mode) 2206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 2216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return true; 2226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 2236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 2256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 2266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 2276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 2286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 2296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 2306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 2316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_framebuffer *fb = crtc->fb; 2326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Calculate our timings */ 234e5ec882cfc18007c6076236ac33a713bcc1d35aaFrancisco Jerez int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 235e5ec882cfc18007c6076236ac33a713bcc1d35aaFrancisco Jerez int horizStart = (mode->crtc_hsync_start >> 3) + 1; 236e5ec882cfc18007c6076236ac33a713bcc1d35aaFrancisco Jerez int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 2376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int horizTotal = (mode->crtc_htotal >> 3) - 5; 2386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 2396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 2406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertDisplay = mode->crtc_vdisplay - 1; 2416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertStart = mode->crtc_vsync_start - 1; 2426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertEnd = mode->crtc_vsync_end - 1; 2436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertTotal = mode->crtc_vtotal - 2; 2446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertBlankStart = mode->crtc_vdisplay - 1; 2456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vertBlankEnd = mode->crtc_vtotal - 1; 2466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_encoder *encoder; 2486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs bool fp_output = false; 2496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 2526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (encoder->crtc == crtc && 2546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs (nv_encoder->dcb->type == OUTPUT_LVDS || 2556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_encoder->dcb->type == OUTPUT_TMDS)) 2566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs fp_output = true; 2576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 2586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (fp_output) { 2606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vertStart = vertTotal - 3; 2616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vertEnd = vertTotal - 2; 2626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vertBlankStart = vertStart; 2636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs horizStart = horizTotal - 5; 2646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs horizEnd = horizTotal - 2; 2656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs horizBlankEnd = horizTotal + 4; 2666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#if 0 2676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev->overlayAdaptor && dev_priv->card_type >= NV_10) 2686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* This reportedly works around some video overlay bandwidth problems */ 2696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs horizTotal += 2; 2706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#endif 2716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 2726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vertTotal |= 1; 2756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#if 0 2776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizDisplay: 0x%X \n", horizDisplay); 2786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizStart: 0x%X \n", horizStart); 2796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizEnd: 0x%X \n", horizEnd); 2806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizTotal: 0x%X \n", horizTotal); 2816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 2826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 2836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertDisplay: 0x%X \n", vertDisplay); 2846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertStart: 0x%X \n", vertStart); 2856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertEnd: 0x%X \n", vertEnd); 2866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertTotal: 0x%X \n", vertTotal); 2876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 2886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 2896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#endif 2906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 2926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * compute correct Hsync & Vsync polarity 2936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 2946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 2956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 2966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 2976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg = 0x23; 2986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_NHSYNC) 2996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg |= 0x40; 3006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg |= 0x80; 3026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } else { 3036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int vdisplay = mode->vdisplay; 3046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 3056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vdisplay *= 2; 3066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->vscan > 1) 3076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs vdisplay *= mode->vscan; 3086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (vdisplay < 400) 3096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 3106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else if (vdisplay < 480) 3116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg = 0x63; /* -hsync +vsync */ 3126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else if (vdisplay < 768) 3136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 3146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else 3156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg = 0x23; /* +hsync +vsync */ 3166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 3176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->MiscOutReg |= (mode->clock_index & 0x03) << 2; 3196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 3216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Time Sequencer 3226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 3236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 3246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 0x20 disables the sequencer */ 3256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 3266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 3276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else 3286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 3296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 3306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 3316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 3326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 3346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * CRTC 3356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 3366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 3376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 3386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 3396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 3406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 3416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 3426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 3436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 3446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 3456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 3466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 3476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 3486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs (1 << 4) | 3496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 3506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 3516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 3526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 3536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 3546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 3556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1 << 6 | 3566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 3576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 3586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 3596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 3606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 3616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 3626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 3636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 3646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 3656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 3666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* framebuffer can be larger than crtc scanout area. */ 36701f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 3686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 3696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 3706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 3716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 3726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 3736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 3756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Some extended CRTC registers (they are not saved with the rest of the vga regs). 3766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 3776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* framebuffer can be larger than crtc scanout area. */ 379c1003d9c90f410777ab57f675b2a575c9c7ab5d7Francisco Jerez regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 38001f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 381c1003d9c90f410777ab57f675b2a575c9c7ab5d7Francisco Jerez regp->CRTC[NV_CIO_CRE_42] = 38201f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 3836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 3846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 3856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 3866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 3876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 3886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 3896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 3906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 3916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 3926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 3936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 3946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 3956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 3966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 3976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 3986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 3996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 4006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs horizTotal = (horizTotal >> 1) & ~1; 4016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 4026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 4036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } else 4046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 4056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 4076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Graphics Display Controller 4086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 4096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 4106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 4116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 4126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 4136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 4146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 4156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 4166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 4176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 4186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[0] = 0x00; /* standard colormap translation */ 4206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[1] = 0x01; 4216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[2] = 0x02; 4226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[3] = 0x03; 4236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[4] = 0x04; 4246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[5] = 0x05; 4256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[6] = 0x06; 4266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[7] = 0x07; 4276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[8] = 0x08; 4286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[9] = 0x09; 4296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[10] = 0x0A; 4306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[11] = 0x0B; 4316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[12] = 0x0C; 4326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[13] = 0x0D; 4336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[14] = 0x0E; 4346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[15] = 0x0F; 4356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 4366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Non-vga */ 4376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 4386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 4396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 4406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 4416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 4426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs/** 4446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Sets up registers for the given mode/adjusted_mode pair. 4456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 4466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * The clocks, CRTCs and outputs attached to this CRTC must be off. 4476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 4486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * This shouldn't enable any clocks, CRTCs, or outputs, but they should 4496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * be easily turned on/off after this. 4506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 4516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 4526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 4536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 4546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 4556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 4566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 4576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 4586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index]; 4596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_encoder *encoder; 4606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs bool lvds_output = false, tmds_output = false, tv_output = false, 4616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs off_chip_digital = false; 4626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 4646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 4656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs bool digital = false; 4666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (encoder->crtc != crtc) 4686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs continue; 4696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_encoder->dcb->type == OUTPUT_LVDS) 4716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs digital = lvds_output = true; 4726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_encoder->dcb->type == OUTPUT_TV) 4736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs tv_output = true; 4746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_encoder->dcb->type == OUTPUT_TMDS) 4756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs digital = tmds_output = true; 4766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 4776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs off_chip_digital = true; 4786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 4796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Registers not directly related to the (s)vga mode */ 4816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* What is the meaning of this register? */ 4836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 4846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 4856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_eng_ctrl = 0; 4876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Except for rare conditions I2C is enabled on the primary crtc */ 4886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_crtc->index == 0) 4896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 4906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#if 0 4916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Set overlay to desired crtc. */ 4926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev->overlayAdaptor) { 4936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 4946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (pPriv->overlayCRTC == nv_crtc->index) 4956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 4966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 4976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#endif 4986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 4996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 5006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 5016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 5026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 5036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset >= 0x11) 5046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 5056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 5066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 5076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Unblock some timings */ 5096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_53] = 0; 5106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_54] = 0; 5116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 5136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (lvds_output) 5146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 5156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else if (tmds_output) 5166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 5176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else 5186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 5196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* These values seem to vary */ 5216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 5226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 5236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 5256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* probably a scratch reg, but kept for cargo-cult purposes: 5276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bit0: crtc0?, head A 5286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bit6: lvds, head A 5296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * bit7: (only in X), head A 5306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 5316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_crtc->index == 0) 5326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 5336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* The blob seems to take the current value from crtc 0, add 4 to that 5356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * and reuse the old value for crtc 1 */ 5366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 5376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!nv_crtc->index) 5386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 5396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* the blob sometimes sets |= 0x10 (which is the same as setting |= 5416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 1 << 30 on 0x60.830), for no apparent reason */ 5426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 5436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5444a9f822fe1a6ca5de7d8cdd5efbead3b9ab4283bFrancisco Jerez if (dev_priv->card_type >= NV_30) 5454a9f822fe1a6ca5de7d8cdd5efbead3b9ab4283bFrancisco Jerez regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 5464a9f822fe1a6ca5de7d8cdd5efbead3b9ab4283bFrancisco Jerez 5476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_830 = mode->crtc_vdisplay - 3; 5486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_834 = mode->crtc_vdisplay - 1; 5496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) 5516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* This is what the blob does */ 5526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 5536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type >= NV_30) 5556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 5566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 55763f7fcfebd2ff1995b649101d6120b60fa0e5b06Francisco Jerez if (dev_priv->card_type >= NV_10) 55863f7fcfebd2ff1995b649101d6120b60fa0e5b06Francisco Jerez regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 55963f7fcfebd2ff1995b649101d6120b60fa0e5b06Francisco Jerez else 56063f7fcfebd2ff1995b649101d6120b60fa0e5b06Francisco Jerez regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 5616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Some misc regs */ 5636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) { 5646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_85] = 0xFF; 5656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_86] = 0x1; 5666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 5676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8; 5696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 5706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (lvds_output || tmds_output || tv_output) 5716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 5726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Generic PRAMDAC regs */ 5746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type >= NV_10) 5766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Only bit that bios and blob set. */ 5776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->nv10_cursync = (1 << 25); 5786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 5806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 5816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 5826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (crtc->fb->depth == 16) 5836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 5846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset >= 0x11) 5856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 5866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 5886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->tv_setup = 0; 5896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 5916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Some values the blob sets */ 5936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_8c0 = 0x100; 5946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_a20 = 0x0; 5956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_a24 = 0xfffff; 5966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_a34 = 0x1; 5976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 5986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 5996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs/** 6006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * Sets up registers for the given mode/adjusted_mode pair. 6016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 6026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * The clocks, CRTCs and outputs attached to this CRTC must be off. 6036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * 6046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * This shouldn't enable any clocks, CRTCs, or outputs, but they should 6056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * be easily turned on/off after this. 6066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 6076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic int 6086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 6096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_display_mode *adjusted_mode, 6106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int x, int y, struct drm_framebuffer *old_fb) 6116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 6126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 6136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 6146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 6156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 616ef2bb506687a5f1cc8ef2fef370bb168b2808106Maarten Maathuis NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 6176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs drm_mode_debug_printmodeline(adjusted_mode); 6186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 6206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 6216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_mode_set_vga(crtc, adjusted_mode); 6236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 6246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) 6256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); 6266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_mode_set_regs(crtc, adjusted_mode); 6276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 6286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 6296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 6306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_save(struct drm_crtc *crtc) 6326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 6336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 6346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 6356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_mode_state *state = &dev_priv->mode_reg; 6366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 6376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_mode_state *saved = &dev_priv->saved_reg; 6386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 6396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_two_heads(crtc->dev)) 6416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVSetOwner(crtc->dev, nv_crtc->index); 6426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 6446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* init some state to saved value */ 6466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->sel_clk = saved->sel_clk & ~(0x5 << 16); 6476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 6486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 6496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_state->gpio_ext = crtc_saved->gpio_ext; 6506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 6516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_restore(struct drm_crtc *crtc) 6536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 6546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 6556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 6566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int head = nv_crtc->index; 6576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 6586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_two_heads(crtc->dev)) 6606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVSetOwner(crtc->dev, head); 6616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg); 6636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 6646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->last_dpms = NV_DPMS_CLEARED; 6666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 6676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_prepare(struct drm_crtc *crtc) 6696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 6706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 6716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 6726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 6736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 6746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_two_heads(dev)) 6766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVSetOwner(dev, nv_crtc->index); 6776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6781c180fa5bd5f264e4863bb88861e8cd7d135b917Francisco Jerez drm_vblank_pre_modeset(dev, nv_crtc->index); 6796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 6806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVBlankScreen(dev, nv_crtc->index, true); 6826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 68325985edcedea6396277003854657b5f3cb31a628Lucas De Marchi /* Some more preparation. */ 6846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 6856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->card_type == NV_40) { 6866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 6876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 6886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 6896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 6906ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_commit(struct drm_crtc *crtc) 6926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 6936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 6946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 6956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 6966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 6976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 6986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg); 6996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 7006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#ifdef __BIG_ENDIAN 7026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* turn on LFB swapping */ 7036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs { 7046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 7056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 7066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 7076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 7086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#endif 7096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs funcs->dpms(crtc, DRM_MODE_DPMS_ON); 7111c180fa5bd5f264e4863bb88861e8cd7d135b917Francisco Jerez drm_vblank_post_modeset(dev, nv_crtc->index); 7126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 7136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv_crtc_destroy(struct drm_crtc *crtc) 7156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 7166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 7176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 718ef2bb506687a5f1cc8ef2fef370bb168b2808106Maarten Maathuis NV_DEBUG_KMS(crtc->dev, "\n"); 7196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!nv_crtc) 7216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return; 7226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs drm_crtc_cleanup(crtc); 7246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7259d59e8a1fc8fc35bf22dc92d7722a7502769ab7eBen Skeggs nouveau_bo_unmap(nv_crtc->cursor.nvbo); 7266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 7276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs kfree(nv_crtc); 7286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 7296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 7316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv_crtc_gamma_load(struct drm_crtc *crtc) 7326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 7336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 7346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = nv_crtc->base.dev; 7356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 7366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 7376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int i; 7386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC; 7406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs for (i = 0; i < 256; i++) { 7416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs rgbs[i].r = nv_crtc->lut.r[i] >> 8; 7426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs rgbs[i].g = nv_crtc->lut.g[i] >> 8; 7436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs rgbs[i].b = nv_crtc->lut.b[i] >> 8; 7446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 7456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg); 7476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 7486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void 7507203425a943eb3e189ba6b512827e0deb5f23872James Simmonsnv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, 7517203425a943eb3e189ba6b512827e0deb5f23872James Simmons uint32_t size) 7526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 7537203425a943eb3e189ba6b512827e0deb5f23872James Simmons int end = (start + size > 256) ? 256 : start + size, i; 7546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 7556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7567203425a943eb3e189ba6b512827e0deb5f23872James Simmons for (i = start; i < end; i++) { 7576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.r[i] = r[i]; 7586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.g[i] = g[i]; 7596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.b[i] = b[i]; 7606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 7616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* We need to know the depth before we upload, but it's possible to 7636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * get called before a framebuffer is bound. If this is the case, 7646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * mark the lut values as dirty by setting depth==0, and it'll be 7656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * uploaded on the first mode_set_base() 7666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 7676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!nv_crtc->base.fb) { 7686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.depth = 0; 7696ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return; 7706ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 7716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_gamma_load(crtc); 7736ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 7746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic int 776be64c2bb4731b0e6223a496eed615b816ac879ecChris Ballnv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 777be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball struct drm_framebuffer *passed_fb, 778be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball int x, int y, bool atomic) 7796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 7806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 7816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = crtc->dev; 7826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 7836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; 7840e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov struct drm_framebuffer *drm_fb; 7850e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov struct nouveau_framebuffer *fb; 7866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int arb_burst, arb_lwm; 7876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int ret; 7886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 7890e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 7900e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov 7910e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov /* no fb bound */ 7920e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov if (!atomic && !crtc->fb) { 7930e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov NV_DEBUG_KMS(dev, "No FB bound\n"); 7940e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov return 0; 7950e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov } 7960e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov 7970e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov 798be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball /* If atomic, we want to switch to the fb we were passed, so 799be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball * now we update pointers to do that. (We don't pin; just 800be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball * assume we're already pinned and update the base address.) 801be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball */ 802be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball if (atomic) { 803be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball drm_fb = passed_fb; 804be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball fb = nouveau_framebuffer(passed_fb); 805f9ec8f6c8dea942bc4be5cc1f34c99df7a4d78eeEmil Velikov } else { 8060e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov drm_fb = crtc->fb; 8070e83bb4eee1c504ab98367b4f7d1bc337ab213d2Emil Velikov fb = nouveau_framebuffer(crtc->fb); 808be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball /* If not atomic, we can go ahead and pin, and unpin the 809be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball * old fb we were passed. 810be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball */ 811be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); 812be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball if (ret) 813be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball return ret; 8146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 815be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball if (passed_fb) { 816be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); 817be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball nouveau_bo_unpin(ofb->nvbo); 818be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball } 8196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 8206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->fb.offset = fb->nvbo->bo.offset; 8226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (nv_crtc->lut.depth != drm_fb->depth) { 8246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.depth = drm_fb->depth; 8256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc_gamma_load(crtc); 8266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 8276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Update the framebuffer format. */ 8296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 8306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; 8316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 8326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (crtc->fb->depth == 16) 8336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 8346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 8356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 8366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->ramdac_gen_ctrl); 8376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 83801f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 8396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 84001f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 841c1003d9c90f410777ab57f675b2a575c9c7ab5d7Francisco Jerez regp->CRTC[NV_CIO_CRE_42] = 84201f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 8436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 8446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 845c1003d9c90f410777ab57f675b2a575c9c7ab5d7Francisco Jerez crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 8466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Update the framebuffer location. */ 8486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->fb_start = nv_crtc->fb.offset & ~3; 84901f2c7730e188077026c5f766f85f329c7000c54Ville Syrjälä regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); 8505794b5fdb579abf7be2c27c6e0d6106f391a26e4Francisco Jerez nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 8516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* Update the arbitration parameters. */ 8536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, 8546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs &arb_burst, &arb_lwm); 8556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 8576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 8586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 8596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 8606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8614295f188e8297660b498e021caee430a40558d8bFrancisco Jerez if (dev_priv->card_type >= NV_20) { 8626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 8636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 8646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 8656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 8676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 8686ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 869be64c2bb4731b0e6223a496eed615b816ac879ecChris Ballstatic int 870be64c2bb4731b0e6223a496eed615b816ac879ecChris Ballnv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 871be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball struct drm_framebuffer *old_fb) 872be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball{ 873be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 874be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball} 875be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball 876be64c2bb4731b0e6223a496eed615b816ac879ecChris Ballstatic int 877be64c2bb4731b0e6223a496eed615b816ac879ecChris Ballnv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 878be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball struct drm_framebuffer *fb, 87921c74a8ea8b47eb6c3c621e36578f6e27f65c5c7Jason Wessel int x, int y, enum mode_set_atomic state) 880be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball{ 881a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 882a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball struct drm_device *dev = dev_priv->dev; 883a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball 88421c74a8ea8b47eb6c3c621e36578f6e27f65c5c7Jason Wessel if (state == ENTER_ATOMIC_MODE_SET) 885a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball nouveau_fbcon_save_disable_accel(dev); 886a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball else 887a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball nouveau_fbcon_restore_accel(dev); 888a424d761a00c0233cb7734a8cd572ecd6d0362aaChris Ball 889be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 890be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball} 891be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball 8926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 8936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_bo *dst) 8946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 8956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int width = nv_cursor_width(dev); 8966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint32_t pixel; 8976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int i, j; 8986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 8996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs for (i = 0; i < width; i++) { 9006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs for (j = 0; j < width; j++) { 9016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pixel = nouveau_bo_rd32(src, i*64 + j); 9026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 9046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | (pixel & 0xf80000) >> 9 9056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | (pixel & 0xf800) >> 6 9066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs | (pixel & 0xf8) >> 3); 9076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 9106ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 9126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_bo *dst) 9136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 9146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint32_t pixel; 9156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int alpha, i; 9166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 9186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * cursors (though NPM in combination with fp dithering may not work on 9196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * nv11, from "nv" driver history) 9206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 9216ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * blob uses, however we get given PM cursors so we use PM mode 9226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 9236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs for (i = 0; i < 64 * 64; i++) { 9246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pixel = nouveau_bo_rd32(src, i); 9256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs /* hw gets unhappy if alpha <= rgb values. for a PM image "less 9276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * than" shouldn't happen; fix "equal to" case by adding one to 9286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * alpha channel (slightly inaccurate, but so is attempting to 9296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs * get back to NPM images, due to limits of integer precision) 9306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs */ 9316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs alpha = pixel >> 24; 9326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (alpha > 0 && alpha < 255) 9336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 9346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#ifdef __BIG_ENDIAN 9366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs { 9376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = dev->dev_private; 9386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset == 0x11) { 9406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs pixel = ((pixel & 0x000000ff) << 24) | 9416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ((pixel & 0x0000ff00) << 8) | 9426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ((pixel & 0x00ff0000) >> 8) | 9436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ((pixel & 0xff000000) >> 24); 9446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs#endif 9476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_bo_wr32(dst, i, pixel); 9496ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9506ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 9516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic int 9536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 9546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs uint32_t buffer_handle, uint32_t width, uint32_t height) 9556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 9566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 9576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_device *dev = dev_priv->dev; 9586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 9596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_bo *cursor = NULL; 9606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct drm_gem_object *gem; 9616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int ret = 0; 9626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!buffer_handle) { 9646ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.hide(nv_crtc, true); 9656ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 9666ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 9676ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 968b4fa9d0f6563756036f61c74fb38e3e97a1defd4Marcin Slusarz if (width != 64 || height != 64) 969b4fa9d0f6563756036f61c74fb38e3e97a1defd4Marcin Slusarz return -EINVAL; 970b4fa9d0f6563756036f61c74fb38e3e97a1defd4Marcin Slusarz 9716ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); 9726ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!gem) 973bf79cb914dbfe848add8bb76cbb8ff89110d29ffChris Wilson return -ENOENT; 9746ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs cursor = nouveau_gem_object(gem); 9756ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9766ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ret = nouveau_bo_map(cursor); 9776ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (ret) 9786ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs goto out; 9796ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9806ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (dev_priv->chipset >= 0x11) 9816ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 9826ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs else 9836ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 9846ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9856ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_bo_unmap(cursor); 9866ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 9876ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 9886ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.show(nv_crtc, true); 9896ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsout: 990bc9025bdc4e2b591734cca17697093845007b63dLuca Barbieri drm_gem_object_unreference_unlocked(gem); 9916ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return ret; 9926ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 9936ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9946ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic int 9956ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 9966ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 9976ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 9986ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 9996ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->cursor.set_pos(nv_crtc, x, y); 10006ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 10016ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 10026ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10036ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic const struct drm_crtc_funcs nv04_crtc_funcs = { 10046ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .save = nv_crtc_save, 10056ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .restore = nv_crtc_restore, 10066ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .cursor_set = nv04_crtc_cursor_set, 10076ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .cursor_move = nv04_crtc_cursor_move, 10086ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .gamma_set = nv_crtc_gamma_set, 10096ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .set_config = drm_crtc_helper_set_config, 1010332b242f47786d1a43bd7a19a0513dd5d493db8eFrancisco Jerez .page_flip = nouveau_crtc_page_flip, 10116ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .destroy = nv_crtc_destroy, 10126ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs}; 10136ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10146ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsstatic const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 10156ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .dpms = nv_crtc_dpms, 10166ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .prepare = nv_crtc_prepare, 10176ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .commit = nv_crtc_commit, 10186ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .mode_fixup = nv_crtc_mode_fixup, 10196ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .mode_set = nv_crtc_mode_set, 10206ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .mode_set_base = nv04_crtc_mode_set_base, 1021be64c2bb4731b0e6223a496eed615b816ac879ecChris Ball .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 10226ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs .load_lut = nv_crtc_gamma_load, 10236ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs}; 10246ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10256ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsint 10266ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggsnv04_crtc_create(struct drm_device *dev, int crtc_num) 10276ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs{ 10286ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs struct nouveau_crtc *nv_crtc; 10296ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs int ret, i; 10306ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10316ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 10326ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!nv_crtc) 10336ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return -ENOMEM; 10346ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10356ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs for (i = 0; i < 256; i++) { 10366ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.r[i] = i << 8; 10376ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.g[i] = i << 8; 10386ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.b[i] = i << 8; 10396ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 10406ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->lut.depth = 0; 10416ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10426ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->index = crtc_num; 10436ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv_crtc->last_dpms = NV_DPMS_CLEARED; 10446ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10456ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); 10466ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 10476ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 10486ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10497375c95b343aa575940704a38482a334ea87ac6cBen Skeggs ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 1050d550c41e4ff11fe69b5f92868157253d27937d1fBen Skeggs 0, 0x0000, &nv_crtc->cursor.nvbo); 10516ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!ret) { 10526ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); 10536ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (!ret) 10546ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 10556ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs if (ret) 10566ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 10576ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs } 10586ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10596ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs nv04_cursor_init(nv_crtc); 10606ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 10616ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs return 0; 10626ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs} 10636ee738610f41b59733f63718f0bdbcba7d3a3f12Ben Skeggs 1064