1#include "drmP.h"
2#include "drm.h"
3#include "nouveau_drv.h"
4#include "nouveau_drm.h"
5
6int
7nv04_fb_vram_init(struct drm_device *dev)
8{
9	struct drm_nouveau_private *dev_priv = dev->dev_private;
10	u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
11
12	if (boot0 & 0x00000100) {
13		dev_priv->vram_size  = ((boot0 >> 12) & 0xf) * 2 + 2;
14		dev_priv->vram_size *= 1024 * 1024;
15	} else {
16		switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
17		case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
18			dev_priv->vram_size = 32 * 1024 * 1024;
19			break;
20		case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
21			dev_priv->vram_size = 16 * 1024 * 1024;
22			break;
23		case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
24			dev_priv->vram_size = 8 * 1024 * 1024;
25			break;
26		case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
27			dev_priv->vram_size = 4 * 1024 * 1024;
28			break;
29		}
30	}
31
32	if ((boot0 & 0x00000038) <= 0x10)
33		dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
34	else
35		dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
36
37	return 0;
38}
39
40int
41nv04_fb_init(struct drm_device *dev)
42{
43	/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
44	 * nvidia reading PFB_CFG_0, then writing back its original value.
45	 * (which was 0x701114 in this case)
46	 */
47
48	nv_wr32(dev, NV04_PFB_CFG0, 0x1114);
49	return 0;
50}
51
52void
53nv04_fb_takedown(struct drm_device *dev)
54{
55}
56