nv20_graph.c revision f56cb86f9abd229418f894a8ffedfb9ff465c181
1#include "drmP.h" 2#include "drm.h" 3#include "nouveau_drv.h" 4#include "nouveau_drm.h" 5 6/* 7 * NV20 8 * ----- 9 * There are 3 families : 10 * NV20 is 0x10de:0x020* 11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028* 12 * NV2A is 0x10de:0x02A0 13 * 14 * NV30 15 * ----- 16 * There are 3 families : 17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031* 18 * NV34 is 0x10de:0x032* 19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034* 20 * 21 * Not seen in the wild, no dumps (probably NV35) : 22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd 23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe 24 * 25 */ 26 27#define NV20_GRCTX_SIZE (3580*4) 28#define NV25_GRCTX_SIZE (3529*4) 29#define NV2A_GRCTX_SIZE (3500*4) 30 31#define NV30_31_GRCTX_SIZE (24392) 32#define NV34_GRCTX_SIZE (18140) 33#define NV35_36_GRCTX_SIZE (22396) 34 35static void 36nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 37{ 38 int i; 39 40 nv_wo32(dev, ctx, 0x033c/4, 0xffff0000); 41 nv_wo32(dev, ctx, 0x03a0/4, 0x0fff0000); 42 nv_wo32(dev, ctx, 0x03a4/4, 0x0fff0000); 43 nv_wo32(dev, ctx, 0x047c/4, 0x00000101); 44 nv_wo32(dev, ctx, 0x0490/4, 0x00000111); 45 nv_wo32(dev, ctx, 0x04a8/4, 0x44400000); 46 for (i = 0x04d4; i <= 0x04e0; i += 4) 47 nv_wo32(dev, ctx, i/4, 0x00030303); 48 for (i = 0x04f4; i <= 0x0500; i += 4) 49 nv_wo32(dev, ctx, i/4, 0x00080000); 50 for (i = 0x050c; i <= 0x0518; i += 4) 51 nv_wo32(dev, ctx, i/4, 0x01012000); 52 for (i = 0x051c; i <= 0x0528; i += 4) 53 nv_wo32(dev, ctx, i/4, 0x000105b8); 54 for (i = 0x052c; i <= 0x0538; i += 4) 55 nv_wo32(dev, ctx, i/4, 0x00080008); 56 for (i = 0x055c; i <= 0x0598; i += 4) 57 nv_wo32(dev, ctx, i/4, 0x07ff0000); 58 nv_wo32(dev, ctx, 0x05a4/4, 0x4b7fffff); 59 nv_wo32(dev, ctx, 0x05fc/4, 0x00000001); 60 nv_wo32(dev, ctx, 0x0604/4, 0x00004000); 61 nv_wo32(dev, ctx, 0x0610/4, 0x00000001); 62 nv_wo32(dev, ctx, 0x0618/4, 0x00040000); 63 nv_wo32(dev, ctx, 0x061c/4, 0x00010000); 64 for (i = 0x1c1c; i <= 0x248c; i += 16) { 65 nv_wo32(dev, ctx, (i + 0)/4, 0x10700ff9); 66 nv_wo32(dev, ctx, (i + 4)/4, 0x0436086c); 67 nv_wo32(dev, ctx, (i + 8)/4, 0x000c001b); 68 } 69 nv_wo32(dev, ctx, 0x281c/4, 0x3f800000); 70 nv_wo32(dev, ctx, 0x2830/4, 0x3f800000); 71 nv_wo32(dev, ctx, 0x285c/4, 0x40000000); 72 nv_wo32(dev, ctx, 0x2860/4, 0x3f800000); 73 nv_wo32(dev, ctx, 0x2864/4, 0x3f000000); 74 nv_wo32(dev, ctx, 0x286c/4, 0x40000000); 75 nv_wo32(dev, ctx, 0x2870/4, 0x3f800000); 76 nv_wo32(dev, ctx, 0x2878/4, 0xbf800000); 77 nv_wo32(dev, ctx, 0x2880/4, 0xbf800000); 78 nv_wo32(dev, ctx, 0x34a4/4, 0x000fe000); 79 nv_wo32(dev, ctx, 0x3530/4, 0x000003f8); 80 nv_wo32(dev, ctx, 0x3540/4, 0x002fe000); 81 for (i = 0x355c; i <= 0x3578; i += 4) 82 nv_wo32(dev, ctx, i/4, 0x001c527c); 83} 84 85static void 86nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 87{ 88 int i; 89 90 nv_wo32(dev, ctx, 0x035c/4, 0xffff0000); 91 nv_wo32(dev, ctx, 0x03c0/4, 0x0fff0000); 92 nv_wo32(dev, ctx, 0x03c4/4, 0x0fff0000); 93 nv_wo32(dev, ctx, 0x049c/4, 0x00000101); 94 nv_wo32(dev, ctx, 0x04b0/4, 0x00000111); 95 nv_wo32(dev, ctx, 0x04c8/4, 0x00000080); 96 nv_wo32(dev, ctx, 0x04cc/4, 0xffff0000); 97 nv_wo32(dev, ctx, 0x04d0/4, 0x00000001); 98 nv_wo32(dev, ctx, 0x04e4/4, 0x44400000); 99 nv_wo32(dev, ctx, 0x04fc/4, 0x4b800000); 100 for (i = 0x0510; i <= 0x051c; i += 4) 101 nv_wo32(dev, ctx, i/4, 0x00030303); 102 for (i = 0x0530; i <= 0x053c; i += 4) 103 nv_wo32(dev, ctx, i/4, 0x00080000); 104 for (i = 0x0548; i <= 0x0554; i += 4) 105 nv_wo32(dev, ctx, i/4, 0x01012000); 106 for (i = 0x0558; i <= 0x0564; i += 4) 107 nv_wo32(dev, ctx, i/4, 0x000105b8); 108 for (i = 0x0568; i <= 0x0574; i += 4) 109 nv_wo32(dev, ctx, i/4, 0x00080008); 110 for (i = 0x0598; i <= 0x05d4; i += 4) 111 nv_wo32(dev, ctx, i/4, 0x07ff0000); 112 nv_wo32(dev, ctx, 0x05e0/4, 0x4b7fffff); 113 nv_wo32(dev, ctx, 0x0620/4, 0x00000080); 114 nv_wo32(dev, ctx, 0x0624/4, 0x30201000); 115 nv_wo32(dev, ctx, 0x0628/4, 0x70605040); 116 nv_wo32(dev, ctx, 0x062c/4, 0xb0a09080); 117 nv_wo32(dev, ctx, 0x0630/4, 0xf0e0d0c0); 118 nv_wo32(dev, ctx, 0x0664/4, 0x00000001); 119 nv_wo32(dev, ctx, 0x066c/4, 0x00004000); 120 nv_wo32(dev, ctx, 0x0678/4, 0x00000001); 121 nv_wo32(dev, ctx, 0x0680/4, 0x00040000); 122 nv_wo32(dev, ctx, 0x0684/4, 0x00010000); 123 for (i = 0x1b04; i <= 0x2374; i += 16) { 124 nv_wo32(dev, ctx, (i + 0)/4, 0x10700ff9); 125 nv_wo32(dev, ctx, (i + 4)/4, 0x0436086c); 126 nv_wo32(dev, ctx, (i + 8)/4, 0x000c001b); 127 } 128 nv_wo32(dev, ctx, 0x2704/4, 0x3f800000); 129 nv_wo32(dev, ctx, 0x2718/4, 0x3f800000); 130 nv_wo32(dev, ctx, 0x2744/4, 0x40000000); 131 nv_wo32(dev, ctx, 0x2748/4, 0x3f800000); 132 nv_wo32(dev, ctx, 0x274c/4, 0x3f000000); 133 nv_wo32(dev, ctx, 0x2754/4, 0x40000000); 134 nv_wo32(dev, ctx, 0x2758/4, 0x3f800000); 135 nv_wo32(dev, ctx, 0x2760/4, 0xbf800000); 136 nv_wo32(dev, ctx, 0x2768/4, 0xbf800000); 137 nv_wo32(dev, ctx, 0x308c/4, 0x000fe000); 138 nv_wo32(dev, ctx, 0x3108/4, 0x000003f8); 139 nv_wo32(dev, ctx, 0x3468/4, 0x002fe000); 140 for (i = 0x3484; i <= 0x34a0; i += 4) 141 nv_wo32(dev, ctx, i/4, 0x001c527c); 142} 143 144static void 145nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 146{ 147 int i; 148 149 nv_wo32(dev, ctx, 0x033c/4, 0xffff0000); 150 nv_wo32(dev, ctx, 0x03a0/4, 0x0fff0000); 151 nv_wo32(dev, ctx, 0x03a4/4, 0x0fff0000); 152 nv_wo32(dev, ctx, 0x047c/4, 0x00000101); 153 nv_wo32(dev, ctx, 0x0490/4, 0x00000111); 154 nv_wo32(dev, ctx, 0x04a8/4, 0x44400000); 155 for (i = 0x04d4; i <= 0x04e0; i += 4) 156 nv_wo32(dev, ctx, i/4, 0x00030303); 157 for (i = 0x04f4; i <= 0x0500; i += 4) 158 nv_wo32(dev, ctx, i/4, 0x00080000); 159 for (i = 0x050c; i <= 0x0518; i += 4) 160 nv_wo32(dev, ctx, i/4, 0x01012000); 161 for (i = 0x051c; i <= 0x0528; i += 4) 162 nv_wo32(dev, ctx, i/4, 0x000105b8); 163 for (i = 0x052c; i <= 0x0538; i += 4) 164 nv_wo32(dev, ctx, i/4, 0x00080008); 165 for (i = 0x055c; i <= 0x0598; i += 4) 166 nv_wo32(dev, ctx, i/4, 0x07ff0000); 167 nv_wo32(dev, ctx, 0x05a4/4, 0x4b7fffff); 168 nv_wo32(dev, ctx, 0x05fc/4, 0x00000001); 169 nv_wo32(dev, ctx, 0x0604/4, 0x00004000); 170 nv_wo32(dev, ctx, 0x0610/4, 0x00000001); 171 nv_wo32(dev, ctx, 0x0618/4, 0x00040000); 172 nv_wo32(dev, ctx, 0x061c/4, 0x00010000); 173 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ 174 nv_wo32(dev, ctx, (i + 0)/4, 0x10700ff9); 175 nv_wo32(dev, ctx, (i + 4)/4, 0x0436086c); 176 nv_wo32(dev, ctx, (i + 8)/4, 0x000c001b); 177 } 178 nv_wo32(dev, ctx, 0x269c/4, 0x3f800000); 179 nv_wo32(dev, ctx, 0x26b0/4, 0x3f800000); 180 nv_wo32(dev, ctx, 0x26dc/4, 0x40000000); 181 nv_wo32(dev, ctx, 0x26e0/4, 0x3f800000); 182 nv_wo32(dev, ctx, 0x26e4/4, 0x3f000000); 183 nv_wo32(dev, ctx, 0x26ec/4, 0x40000000); 184 nv_wo32(dev, ctx, 0x26f0/4, 0x3f800000); 185 nv_wo32(dev, ctx, 0x26f8/4, 0xbf800000); 186 nv_wo32(dev, ctx, 0x2700/4, 0xbf800000); 187 nv_wo32(dev, ctx, 0x3024/4, 0x000fe000); 188 nv_wo32(dev, ctx, 0x30a0/4, 0x000003f8); 189 nv_wo32(dev, ctx, 0x33fc/4, 0x002fe000); 190 for (i = 0x341c; i <= 0x3438; i += 4) 191 nv_wo32(dev, ctx, i/4, 0x001c527c); 192} 193 194static void 195nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 196{ 197 int i; 198 199 nv_wo32(dev, ctx, 0x0410/4, 0x00000101); 200 nv_wo32(dev, ctx, 0x0424/4, 0x00000111); 201 nv_wo32(dev, ctx, 0x0428/4, 0x00000060); 202 nv_wo32(dev, ctx, 0x0444/4, 0x00000080); 203 nv_wo32(dev, ctx, 0x0448/4, 0xffff0000); 204 nv_wo32(dev, ctx, 0x044c/4, 0x00000001); 205 nv_wo32(dev, ctx, 0x0460/4, 0x44400000); 206 nv_wo32(dev, ctx, 0x048c/4, 0xffff0000); 207 for (i = 0x04e0; i < 0x04e8; i += 4) 208 nv_wo32(dev, ctx, i/4, 0x0fff0000); 209 nv_wo32(dev, ctx, 0x04ec/4, 0x00011100); 210 for (i = 0x0508; i < 0x0548; i += 4) 211 nv_wo32(dev, ctx, i/4, 0x07ff0000); 212 nv_wo32(dev, ctx, 0x0550/4, 0x4b7fffff); 213 nv_wo32(dev, ctx, 0x058c/4, 0x00000080); 214 nv_wo32(dev, ctx, 0x0590/4, 0x30201000); 215 nv_wo32(dev, ctx, 0x0594/4, 0x70605040); 216 nv_wo32(dev, ctx, 0x0598/4, 0xb8a89888); 217 nv_wo32(dev, ctx, 0x059c/4, 0xf8e8d8c8); 218 nv_wo32(dev, ctx, 0x05b0/4, 0xb0000000); 219 for (i = 0x0600; i < 0x0640; i += 4) 220 nv_wo32(dev, ctx, i/4, 0x00010588); 221 for (i = 0x0640; i < 0x0680; i += 4) 222 nv_wo32(dev, ctx, i/4, 0x00030303); 223 for (i = 0x06c0; i < 0x0700; i += 4) 224 nv_wo32(dev, ctx, i/4, 0x0008aae4); 225 for (i = 0x0700; i < 0x0740; i += 4) 226 nv_wo32(dev, ctx, i/4, 0x01012000); 227 for (i = 0x0740; i < 0x0780; i += 4) 228 nv_wo32(dev, ctx, i/4, 0x00080008); 229 nv_wo32(dev, ctx, 0x085c/4, 0x00040000); 230 nv_wo32(dev, ctx, 0x0860/4, 0x00010000); 231 for (i = 0x0864; i < 0x0874; i += 4) 232 nv_wo32(dev, ctx, i/4, 0x00040004); 233 for (i = 0x1f18; i <= 0x3088 ; i += 16) { 234 nv_wo32(dev, ctx, i/4 + 0, 0x10700ff9); 235 nv_wo32(dev, ctx, i/4 + 1, 0x0436086c); 236 nv_wo32(dev, ctx, i/4 + 2, 0x000c001b); 237 } 238 for (i = 0x30b8; i < 0x30c8; i += 4) 239 nv_wo32(dev, ctx, i/4, 0x0000ffff); 240 nv_wo32(dev, ctx, 0x344c/4, 0x3f800000); 241 nv_wo32(dev, ctx, 0x3808/4, 0x3f800000); 242 nv_wo32(dev, ctx, 0x381c/4, 0x3f800000); 243 nv_wo32(dev, ctx, 0x3848/4, 0x40000000); 244 nv_wo32(dev, ctx, 0x384c/4, 0x3f800000); 245 nv_wo32(dev, ctx, 0x3850/4, 0x3f000000); 246 nv_wo32(dev, ctx, 0x3858/4, 0x40000000); 247 nv_wo32(dev, ctx, 0x385c/4, 0x3f800000); 248 nv_wo32(dev, ctx, 0x3864/4, 0xbf800000); 249 nv_wo32(dev, ctx, 0x386c/4, 0xbf800000); 250} 251 252static void 253nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 254{ 255 int i; 256 257 nv_wo32(dev, ctx, 0x040c/4, 0x01000101); 258 nv_wo32(dev, ctx, 0x0420/4, 0x00000111); 259 nv_wo32(dev, ctx, 0x0424/4, 0x00000060); 260 nv_wo32(dev, ctx, 0x0440/4, 0x00000080); 261 nv_wo32(dev, ctx, 0x0444/4, 0xffff0000); 262 nv_wo32(dev, ctx, 0x0448/4, 0x00000001); 263 nv_wo32(dev, ctx, 0x045c/4, 0x44400000); 264 nv_wo32(dev, ctx, 0x0480/4, 0xffff0000); 265 for (i = 0x04d4; i < 0x04dc; i += 4) 266 nv_wo32(dev, ctx, i/4, 0x0fff0000); 267 nv_wo32(dev, ctx, 0x04e0/4, 0x00011100); 268 for (i = 0x04fc; i < 0x053c; i += 4) 269 nv_wo32(dev, ctx, i/4, 0x07ff0000); 270 nv_wo32(dev, ctx, 0x0544/4, 0x4b7fffff); 271 nv_wo32(dev, ctx, 0x057c/4, 0x00000080); 272 nv_wo32(dev, ctx, 0x0580/4, 0x30201000); 273 nv_wo32(dev, ctx, 0x0584/4, 0x70605040); 274 nv_wo32(dev, ctx, 0x0588/4, 0xb8a89888); 275 nv_wo32(dev, ctx, 0x058c/4, 0xf8e8d8c8); 276 nv_wo32(dev, ctx, 0x05a0/4, 0xb0000000); 277 for (i = 0x05f0; i < 0x0630; i += 4) 278 nv_wo32(dev, ctx, i/4, 0x00010588); 279 for (i = 0x0630; i < 0x0670; i += 4) 280 nv_wo32(dev, ctx, i/4, 0x00030303); 281 for (i = 0x06b0; i < 0x06f0; i += 4) 282 nv_wo32(dev, ctx, i/4, 0x0008aae4); 283 for (i = 0x06f0; i < 0x0730; i += 4) 284 nv_wo32(dev, ctx, i/4, 0x01012000); 285 for (i = 0x0730; i < 0x0770; i += 4) 286 nv_wo32(dev, ctx, i/4, 0x00080008); 287 nv_wo32(dev, ctx, 0x0850/4, 0x00040000); 288 nv_wo32(dev, ctx, 0x0854/4, 0x00010000); 289 for (i = 0x0858; i < 0x0868; i += 4) 290 nv_wo32(dev, ctx, i/4, 0x00040004); 291 for (i = 0x15ac; i <= 0x271c ; i += 16) { 292 nv_wo32(dev, ctx, i/4 + 0, 0x10700ff9); 293 nv_wo32(dev, ctx, i/4 + 1, 0x0436086c); 294 nv_wo32(dev, ctx, i/4 + 2, 0x000c001b); 295 } 296 for (i = 0x274c; i < 0x275c; i += 4) 297 nv_wo32(dev, ctx, i/4, 0x0000ffff); 298 nv_wo32(dev, ctx, 0x2ae0/4, 0x3f800000); 299 nv_wo32(dev, ctx, 0x2e9c/4, 0x3f800000); 300 nv_wo32(dev, ctx, 0x2eb0/4, 0x3f800000); 301 nv_wo32(dev, ctx, 0x2edc/4, 0x40000000); 302 nv_wo32(dev, ctx, 0x2ee0/4, 0x3f800000); 303 nv_wo32(dev, ctx, 0x2ee4/4, 0x3f000000); 304 nv_wo32(dev, ctx, 0x2eec/4, 0x40000000); 305 nv_wo32(dev, ctx, 0x2ef0/4, 0x3f800000); 306 nv_wo32(dev, ctx, 0x2ef8/4, 0xbf800000); 307 nv_wo32(dev, ctx, 0x2f00/4, 0xbf800000); 308} 309 310static void 311nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 312{ 313 int i; 314 315 nv_wo32(dev, ctx, 0x040c/4, 0x00000101); 316 nv_wo32(dev, ctx, 0x0420/4, 0x00000111); 317 nv_wo32(dev, ctx, 0x0424/4, 0x00000060); 318 nv_wo32(dev, ctx, 0x0440/4, 0x00000080); 319 nv_wo32(dev, ctx, 0x0444/4, 0xffff0000); 320 nv_wo32(dev, ctx, 0x0448/4, 0x00000001); 321 nv_wo32(dev, ctx, 0x045c/4, 0x44400000); 322 nv_wo32(dev, ctx, 0x0488/4, 0xffff0000); 323 for (i = 0x04dc; i < 0x04e4; i += 4) 324 nv_wo32(dev, ctx, i/4, 0x0fff0000); 325 nv_wo32(dev, ctx, 0x04e8/4, 0x00011100); 326 for (i = 0x0504; i < 0x0544; i += 4) 327 nv_wo32(dev, ctx, i/4, 0x07ff0000); 328 nv_wo32(dev, ctx, 0x054c/4, 0x4b7fffff); 329 nv_wo32(dev, ctx, 0x0588/4, 0x00000080); 330 nv_wo32(dev, ctx, 0x058c/4, 0x30201000); 331 nv_wo32(dev, ctx, 0x0590/4, 0x70605040); 332 nv_wo32(dev, ctx, 0x0594/4, 0xb8a89888); 333 nv_wo32(dev, ctx, 0x0598/4, 0xf8e8d8c8); 334 nv_wo32(dev, ctx, 0x05ac/4, 0xb0000000); 335 for (i = 0x0604; i < 0x0644; i += 4) 336 nv_wo32(dev, ctx, i/4, 0x00010588); 337 for (i = 0x0644; i < 0x0684; i += 4) 338 nv_wo32(dev, ctx, i/4, 0x00030303); 339 for (i = 0x06c4; i < 0x0704; i += 4) 340 nv_wo32(dev, ctx, i/4, 0x0008aae4); 341 for (i = 0x0704; i < 0x0744; i += 4) 342 nv_wo32(dev, ctx, i/4, 0x01012000); 343 for (i = 0x0744; i < 0x0784; i += 4) 344 nv_wo32(dev, ctx, i/4, 0x00080008); 345 nv_wo32(dev, ctx, 0x0860/4, 0x00040000); 346 nv_wo32(dev, ctx, 0x0864/4, 0x00010000); 347 for (i = 0x0868; i < 0x0878; i += 4) 348 nv_wo32(dev, ctx, i/4, 0x00040004); 349 for (i = 0x1f1c; i <= 0x308c ; i += 16) { 350 nv_wo32(dev, ctx, i/4 + 0, 0x10700ff9); 351 nv_wo32(dev, ctx, i/4 + 1, 0x0436086c); 352 nv_wo32(dev, ctx, i/4 + 2, 0x000c001b); 353 } 354 for (i = 0x30bc; i < 0x30cc; i += 4) 355 nv_wo32(dev, ctx, i/4, 0x0000ffff); 356 nv_wo32(dev, ctx, 0x3450/4, 0x3f800000); 357 nv_wo32(dev, ctx, 0x380c/4, 0x3f800000); 358 nv_wo32(dev, ctx, 0x3820/4, 0x3f800000); 359 nv_wo32(dev, ctx, 0x384c/4, 0x40000000); 360 nv_wo32(dev, ctx, 0x3850/4, 0x3f800000); 361 nv_wo32(dev, ctx, 0x3854/4, 0x3f000000); 362 nv_wo32(dev, ctx, 0x385c/4, 0x40000000); 363 nv_wo32(dev, ctx, 0x3860/4, 0x3f800000); 364 nv_wo32(dev, ctx, 0x3868/4, 0xbf800000); 365 nv_wo32(dev, ctx, 0x3870/4, 0xbf800000); 366} 367 368int 369nv20_graph_create_context(struct nouveau_channel *chan) 370{ 371 struct drm_device *dev = chan->dev; 372 struct drm_nouveau_private *dev_priv = dev->dev_private; 373 void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); 374 unsigned int ctx_size; 375 unsigned int idoffs = 0x28/4; 376 int ret; 377 378 switch (dev_priv->chipset) { 379 case 0x20: 380 ctx_size = NV20_GRCTX_SIZE; 381 ctx_init = nv20_graph_context_init; 382 idoffs = 0; 383 break; 384 case 0x25: 385 case 0x28: 386 ctx_size = NV25_GRCTX_SIZE; 387 ctx_init = nv25_graph_context_init; 388 break; 389 case 0x2a: 390 ctx_size = NV2A_GRCTX_SIZE; 391 ctx_init = nv2a_graph_context_init; 392 idoffs = 0; 393 break; 394 case 0x30: 395 case 0x31: 396 ctx_size = NV30_31_GRCTX_SIZE; 397 ctx_init = nv30_31_graph_context_init; 398 break; 399 case 0x34: 400 ctx_size = NV34_GRCTX_SIZE; 401 ctx_init = nv34_graph_context_init; 402 break; 403 case 0x35: 404 case 0x36: 405 ctx_size = NV35_36_GRCTX_SIZE; 406 ctx_init = nv35_36_graph_context_init; 407 break; 408 default: 409 ctx_size = 0; 410 ctx_init = nv35_36_graph_context_init; 411 NV_ERROR(dev, "Please contact the devs if you want your NV%x" 412 " card to work\n", dev_priv->chipset); 413 return -ENOSYS; 414 break; 415 } 416 417 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, 418 NVOBJ_FLAG_ZERO_ALLOC, 419 &chan->ramin_grctx); 420 if (ret) 421 return ret; 422 423 /* Initialise default context values */ 424 ctx_init(dev, chan->ramin_grctx->gpuobj); 425 426 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ 427 nv_wo32(dev, chan->ramin_grctx->gpuobj, idoffs, 428 (chan->id << 24) | 0x1); /* CTX_USER */ 429 430 nv_wo32(dev, dev_priv->ctx_table->gpuobj, chan->id, 431 chan->ramin_grctx->instance >> 4); 432 return 0; 433} 434 435void 436nv20_graph_destroy_context(struct nouveau_channel *chan) 437{ 438 struct drm_device *dev = chan->dev; 439 struct drm_nouveau_private *dev_priv = dev->dev_private; 440 441 if (chan->ramin_grctx) 442 nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); 443 444 nv_wo32(dev, dev_priv->ctx_table->gpuobj, chan->id, 0); 445} 446 447int 448nv20_graph_load_context(struct nouveau_channel *chan) 449{ 450 struct drm_device *dev = chan->dev; 451 uint32_t inst; 452 453 if (!chan->ramin_grctx) 454 return -EINVAL; 455 inst = chan->ramin_grctx->instance >> 4; 456 457 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 458 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, 459 NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); 460 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100); 461 462 nouveau_wait_for_idle(dev); 463 return 0; 464} 465 466int 467nv20_graph_unload_context(struct drm_device *dev) 468{ 469 struct drm_nouveau_private *dev_priv = dev->dev_private; 470 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 471 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 472 struct nouveau_channel *chan; 473 uint32_t inst, tmp; 474 475 chan = pgraph->channel(dev); 476 if (!chan) 477 return 0; 478 inst = chan->ramin_grctx->instance >> 4; 479 480 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 481 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, 482 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); 483 484 nouveau_wait_for_idle(dev); 485 486 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); 487 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; 488 tmp |= (pfifo->channels - 1) << 24; 489 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); 490 return 0; 491} 492 493static void 494nv20_graph_rdi(struct drm_device *dev) 495{ 496 struct drm_nouveau_private *dev_priv = dev->dev_private; 497 int i, writecount = 32; 498 uint32_t rdi_index = 0x2c80000; 499 500 if (dev_priv->chipset == 0x20) { 501 rdi_index = 0x3d0000; 502 writecount = 15; 503 } 504 505 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index); 506 for (i = 0; i < writecount; i++) 507 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0); 508 509 nouveau_wait_for_idle(dev); 510} 511 512void 513nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 514 uint32_t size, uint32_t pitch) 515{ 516 uint32_t limit = max(1u, addr + size) - 1; 517 518 if (pitch) 519 addr |= 1; 520 521 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); 522 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); 523 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); 524 525 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); 526 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit); 527 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); 528 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch); 529 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); 530 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr); 531} 532 533int 534nv20_graph_init(struct drm_device *dev) 535{ 536 struct drm_nouveau_private *dev_priv = 537 (struct drm_nouveau_private *)dev->dev_private; 538 uint32_t tmp, vramsz; 539 int ret, i; 540 541 nv_wr32(dev, NV03_PMC_ENABLE, 542 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); 543 nv_wr32(dev, NV03_PMC_ENABLE, 544 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); 545 546 if (!dev_priv->ctx_table) { 547 /* Create Context Pointer Table */ 548 dev_priv->ctx_table_size = 32 * 4; 549 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 550 dev_priv->ctx_table_size, 16, 551 NVOBJ_FLAG_ZERO_ALLOC, 552 &dev_priv->ctx_table); 553 if (ret) 554 return ret; 555 } 556 557 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, 558 dev_priv->ctx_table->instance >> 4); 559 560 nv20_graph_rdi(dev); 561 562 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 563 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 564 565 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 566 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); 567 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700); 568 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ 569 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); 570 nv_wr32(dev, 0x40009C , 0x00000040); 571 572 if (dev_priv->chipset >= 0x25) { 573 nv_wr32(dev, 0x400890, 0x00080000); 574 nv_wr32(dev, 0x400610, 0x304B1FB6); 575 nv_wr32(dev, 0x400B80, 0x18B82880); 576 nv_wr32(dev, 0x400B84, 0x44000000); 577 nv_wr32(dev, 0x400098, 0x40000080); 578 nv_wr32(dev, 0x400B88, 0x000000ff); 579 } else { 580 nv_wr32(dev, 0x400880, 0x00080000); /* 0x0008c7df */ 581 nv_wr32(dev, 0x400094, 0x00000005); 582 nv_wr32(dev, 0x400B80, 0x45CAA208); /* 0x45eae20e */ 583 nv_wr32(dev, 0x400B84, 0x24000000); 584 nv_wr32(dev, 0x400098, 0x00000040); 585 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038); 586 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); 587 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038); 588 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); 589 } 590 591 /* Turn all the tiling regions off. */ 592 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 593 nv20_graph_set_region_tiling(dev, i, 0, 0, 0); 594 595 for (i = 0; i < 8; i++) { 596 nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4)); 597 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4); 598 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 599 nv_rd32(dev, 0x100300 + i * 4)); 600 } 601 nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324)); 602 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); 603 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324)); 604 605 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 606 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 607 608 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00; 609 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp); 610 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100; 611 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp); 612 613 /* begin RAM config */ 614 vramsz = pci_resource_len(dev->pdev, 0) - 1; 615 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); 616 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); 617 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 618 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG0)); 619 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 620 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG1)); 621 nv_wr32(dev, 0x400820, 0); 622 nv_wr32(dev, 0x400824, 0); 623 nv_wr32(dev, 0x400864, vramsz - 1); 624 nv_wr32(dev, 0x400868, vramsz - 1); 625 626 /* interesting.. the below overwrites some of the tile setup above.. */ 627 nv_wr32(dev, 0x400B20, 0x00000000); 628 nv_wr32(dev, 0x400B04, 0xFFFFFFFF); 629 630 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); 631 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); 632 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); 633 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); 634 635 return 0; 636} 637 638void 639nv20_graph_takedown(struct drm_device *dev) 640{ 641 struct drm_nouveau_private *dev_priv = dev->dev_private; 642 643 nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table); 644} 645 646int 647nv30_graph_init(struct drm_device *dev) 648{ 649 struct drm_nouveau_private *dev_priv = dev->dev_private; 650 int ret, i; 651 652 nv_wr32(dev, NV03_PMC_ENABLE, 653 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); 654 nv_wr32(dev, NV03_PMC_ENABLE, 655 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); 656 657 if (!dev_priv->ctx_table) { 658 /* Create Context Pointer Table */ 659 dev_priv->ctx_table_size = 32 * 4; 660 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 661 dev_priv->ctx_table_size, 16, 662 NVOBJ_FLAG_ZERO_ALLOC, 663 &dev_priv->ctx_table); 664 if (ret) 665 return ret; 666 } 667 668 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, 669 dev_priv->ctx_table->instance >> 4); 670 671 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 672 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 673 674 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); 675 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); 676 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0); 677 nv_wr32(dev, 0x400890, 0x01b463ff); 678 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475); 679 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000); 680 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); 681 nv_wr32(dev, 0x400B80, 0x1003d888); 682 nv_wr32(dev, 0x400B84, 0x0c000000); 683 nv_wr32(dev, 0x400098, 0x00000000); 684 nv_wr32(dev, 0x40009C, 0x0005ad00); 685 nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ 686 nv_wr32(dev, 0x4000a0, 0x00000000); 687 nv_wr32(dev, 0x4000a4, 0x00000008); 688 nv_wr32(dev, 0x4008a8, 0xb784a400); 689 nv_wr32(dev, 0x400ba0, 0x002f8685); 690 nv_wr32(dev, 0x400ba4, 0x00231f3f); 691 nv_wr32(dev, 0x4008a4, 0x40000020); 692 693 if (dev_priv->chipset == 0x34) { 694 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); 695 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201); 696 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); 697 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008); 698 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); 699 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032); 700 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004); 701 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002); 702 } 703 704 nv_wr32(dev, 0x4000c0, 0x00000016); 705 706 /* Turn all the tiling regions off. */ 707 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) 708 nv20_graph_set_region_tiling(dev, i, 0, 0, 0); 709 710 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); 711 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); 712 nv_wr32(dev, 0x0040075c , 0x00000001); 713 714 /* begin RAM config */ 715 /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */ 716 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); 717 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); 718 if (dev_priv->chipset != 0x34) { 719 nv_wr32(dev, 0x400750, 0x00EA0000); 720 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0)); 721 nv_wr32(dev, 0x400750, 0x00EA0004); 722 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1)); 723 } 724 725 return 0; 726} 727 728struct nouveau_pgraph_object_class nv20_graph_grclass[] = { 729 { 0x0030, false, NULL }, /* null */ 730 { 0x0039, false, NULL }, /* m2mf */ 731 { 0x004a, false, NULL }, /* gdirect */ 732 { 0x009f, false, NULL }, /* imageblit (nv12) */ 733 { 0x008a, false, NULL }, /* ifc */ 734 { 0x0089, false, NULL }, /* sifm */ 735 { 0x0062, false, NULL }, /* surf2d */ 736 { 0x0043, false, NULL }, /* rop */ 737 { 0x0012, false, NULL }, /* beta1 */ 738 { 0x0072, false, NULL }, /* beta4 */ 739 { 0x0019, false, NULL }, /* cliprect */ 740 { 0x0044, false, NULL }, /* pattern */ 741 { 0x009e, false, NULL }, /* swzsurf */ 742 { 0x0096, false, NULL }, /* celcius */ 743 { 0x0097, false, NULL }, /* kelvin (nv20) */ 744 { 0x0597, false, NULL }, /* kelvin (nv25) */ 745 {} 746}; 747 748struct nouveau_pgraph_object_class nv30_graph_grclass[] = { 749 { 0x0030, false, NULL }, /* null */ 750 { 0x0039, false, NULL }, /* m2mf */ 751 { 0x004a, false, NULL }, /* gdirect */ 752 { 0x009f, false, NULL }, /* imageblit (nv12) */ 753 { 0x008a, false, NULL }, /* ifc */ 754 { 0x038a, false, NULL }, /* ifc (nv30) */ 755 { 0x0089, false, NULL }, /* sifm */ 756 { 0x0389, false, NULL }, /* sifm (nv30) */ 757 { 0x0062, false, NULL }, /* surf2d */ 758 { 0x0362, false, NULL }, /* surf2d (nv30) */ 759 { 0x0043, false, NULL }, /* rop */ 760 { 0x0012, false, NULL }, /* beta1 */ 761 { 0x0072, false, NULL }, /* beta4 */ 762 { 0x0019, false, NULL }, /* cliprect */ 763 { 0x0044, false, NULL }, /* pattern */ 764 { 0x039e, false, NULL }, /* swzsurf */ 765 { 0x0397, false, NULL }, /* rankine (nv30) */ 766 { 0x0497, false, NULL }, /* rankine (nv35) */ 767 { 0x0697, false, NULL }, /* rankine (nv34) */ 768 {} 769}; 770 771