1/*
2 * Copyright 2005 Nicolai Haehnle et al.
3 * Copyright 2008 Advanced Micro Devices, Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Nicolai Haehnle
25 *          Jerome Glisse
26 */
27#ifndef _R300_REG_H_
28#define _R300_REG_H_
29
30#define R300_SURF_TILE_MACRO (1<<16)
31#define R300_SURF_TILE_MICRO (2<<16)
32#define R300_SURF_TILE_BOTH (3<<16)
33
34
35#define R300_MC_INIT_MISC_LAT_TIMER	0x180
36#	define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT	0
37#	define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT	4
38#	define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT	8
39#	define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT	12
40#	define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT	16
41#	define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT	20
42#	define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT	24
43#	define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT	28
44
45#define R300_MC_INIT_GFX_LAT_TIMER	0x154
46#	define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT	0
47#	define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT	4
48#	define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT	8
49#	define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT	12
50#	define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT	16
51#	define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT	20
52#	define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT	24
53#	define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT	28
54
55/*
56 * This file contains registers and constants for the R300. They have been
57 * found mostly by examining command buffers captured using glxtest, as well
58 * as by extrapolating some known registers and constants from the R200.
59 * I am fairly certain that they are correct unless stated otherwise
60 * in comments.
61 */
62
63#define R300_SE_VPORT_XSCALE                0x1D98
64#define R300_SE_VPORT_XOFFSET               0x1D9C
65#define R300_SE_VPORT_YSCALE                0x1DA0
66#define R300_SE_VPORT_YOFFSET               0x1DA4
67#define R300_SE_VPORT_ZSCALE                0x1DA8
68#define R300_SE_VPORT_ZOFFSET               0x1DAC
69
70
71/*
72 * Vertex Array Processing (VAP) Control
73 * Stolen from r200 code from Christoph Brill (It's a guess!)
74 */
75#define R300_VAP_CNTL	0x2080
76
77/* This register is written directly and also starts data section
78 * in many 3d CP_PACKET3's
79 */
80#define R300_VAP_VF_CNTL	0x2084
81#	define	R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT              0
82#	define  R300_VAP_VF_CNTL__PRIM_NONE                     (0<<0)
83#	define  R300_VAP_VF_CNTL__PRIM_POINTS                   (1<<0)
84#	define  R300_VAP_VF_CNTL__PRIM_LINES                    (2<<0)
85#	define  R300_VAP_VF_CNTL__PRIM_LINE_STRIP               (3<<0)
86#	define  R300_VAP_VF_CNTL__PRIM_TRIANGLES                (4<<0)
87#	define  R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN             (5<<0)
88#	define  R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP           (6<<0)
89#	define  R300_VAP_VF_CNTL__PRIM_LINE_LOOP                (12<<0)
90#	define  R300_VAP_VF_CNTL__PRIM_QUADS                    (13<<0)
91#	define  R300_VAP_VF_CNTL__PRIM_QUAD_STRIP               (14<<0)
92#	define  R300_VAP_VF_CNTL__PRIM_POLYGON                  (15<<0)
93
94#	define	R300_VAP_VF_CNTL__PRIM_WALK__SHIFT              4
95	/* State based - direct writes to registers trigger vertex
96           generation */
97#	define	R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED         (0<<4)
98#	define	R300_VAP_VF_CNTL__PRIM_WALK_INDICES             (1<<4)
99#	define	R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST         (2<<4)
100#	define	R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED     (3<<4)
101
102	/* I don't think I saw these three used.. */
103#	define	R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT            6
104#	define	R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT     9
105#	define	R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT        10
106
107	/* index size - when not set the indices are assumed to be 16 bit */
108#	define	R300_VAP_VF_CNTL__INDEX_SIZE_32bit              (1<<11)
109	/* number of vertices */
110#	define	R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT           16
111
112/* BEGIN: Wild guesses */
113#define R300_VAP_OUTPUT_VTX_FMT_0           0x2090
114#       define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT     (1<<0)
115#       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT   (1<<1)
116#       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)  /* GUESS */
117#       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)  /* GUESS */
118#       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)  /* GUESS */
119#       define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
120
121#define R300_VAP_OUTPUT_VTX_FMT_1           0x2094
122	/* each of the following is 3 bits wide, specifies number
123	   of components */
124#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
125#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
126#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
127#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
128#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
129#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
130#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
131#       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
132/* END: Wild guesses */
133
134#define R300_SE_VTE_CNTL                  0x20b0
135#	define     R300_VPORT_X_SCALE_ENA                0x00000001
136#	define     R300_VPORT_X_OFFSET_ENA               0x00000002
137#	define     R300_VPORT_Y_SCALE_ENA                0x00000004
138#	define     R300_VPORT_Y_OFFSET_ENA               0x00000008
139#	define     R300_VPORT_Z_SCALE_ENA                0x00000010
140#	define     R300_VPORT_Z_OFFSET_ENA               0x00000020
141#	define     R300_VTX_XY_FMT                       0x00000100
142#	define     R300_VTX_Z_FMT                        0x00000200
143#	define     R300_VTX_W0_FMT                       0x00000400
144#	define     R300_VTX_W0_NORMALIZE                 0x00000800
145#	define     R300_VTX_ST_DENORMALIZED              0x00001000
146
147/* BEGIN: Vertex data assembly - lots of uncertainties */
148
149/* gap */
150
151#define R300_VAP_CNTL_STATUS              0x2140
152#	define R300_VC_NO_SWAP                  (0 << 0)
153#	define R300_VC_16BIT_SWAP               (1 << 0)
154#	define R300_VC_32BIT_SWAP               (2 << 0)
155#	define R300_VAP_TCL_BYPASS		(1 << 8)
156
157/* gap */
158
159/* Where do we get our vertex data?
160 *
161 * Vertex data either comes either from immediate mode registers or from
162 * vertex arrays.
163 * There appears to be no mixed mode (though we can force the pitch of
164 * vertex arrays to 0, effectively reusing the same element over and over
165 * again).
166 *
167 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
168 * if these registers influence vertex array processing.
169 *
170 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
171 *
172 * In both cases, vertex attributes are then passed through INPUT_ROUTE.
173 *
174 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
175 * into the vertex processor's input registers.
176 * The first word routes the first input, the second word the second, etc.
177 * The corresponding input is routed into the register with the given index.
178 * The list is ended by a word with INPUT_ROUTE_END set.
179 *
180 * Always set COMPONENTS_4 in immediate mode.
181 */
182
183#define R300_VAP_INPUT_ROUTE_0_0            0x2150
184#       define R300_INPUT_ROUTE_COMPONENTS_1     (0 << 0)
185#       define R300_INPUT_ROUTE_COMPONENTS_2     (1 << 0)
186#       define R300_INPUT_ROUTE_COMPONENTS_3     (2 << 0)
187#       define R300_INPUT_ROUTE_COMPONENTS_4     (3 << 0)
188#       define R300_INPUT_ROUTE_COMPONENTS_RGBA  (4 << 0) /* GUESS */
189#       define R300_VAP_INPUT_ROUTE_IDX_SHIFT    8
190#       define R300_VAP_INPUT_ROUTE_IDX_MASK     (31 << 8) /* GUESS */
191#       define R300_VAP_INPUT_ROUTE_END          (1 << 13)
192#       define R300_INPUT_ROUTE_IMMEDIATE_MODE   (0 << 14) /* GUESS */
193#       define R300_INPUT_ROUTE_FLOAT            (1 << 14) /* GUESS */
194#       define R300_INPUT_ROUTE_UNSIGNED_BYTE    (2 << 14) /* GUESS */
195#       define R300_INPUT_ROUTE_FLOAT_COLOR      (3 << 14) /* GUESS */
196#define R300_VAP_INPUT_ROUTE_0_1            0x2154
197#define R300_VAP_INPUT_ROUTE_0_2            0x2158
198#define R300_VAP_INPUT_ROUTE_0_3            0x215C
199#define R300_VAP_INPUT_ROUTE_0_4            0x2160
200#define R300_VAP_INPUT_ROUTE_0_5            0x2164
201#define R300_VAP_INPUT_ROUTE_0_6            0x2168
202#define R300_VAP_INPUT_ROUTE_0_7            0x216C
203
204/* gap */
205
206/* Notes:
207 *  - always set up to produce at least two attributes:
208 *    if vertex program uses only position, fglrx will set normal, too
209 *  - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
210 */
211#define R300_VAP_INPUT_CNTL_0               0x2180
212#       define R300_INPUT_CNTL_0_COLOR           0x00000001
213#define R300_VAP_INPUT_CNTL_1               0x2184
214#       define R300_INPUT_CNTL_POS               0x00000001
215#       define R300_INPUT_CNTL_NORMAL            0x00000002
216#       define R300_INPUT_CNTL_COLOR             0x00000004
217#       define R300_INPUT_CNTL_TC0               0x00000400
218#       define R300_INPUT_CNTL_TC1               0x00000800
219#       define R300_INPUT_CNTL_TC2               0x00001000 /* GUESS */
220#       define R300_INPUT_CNTL_TC3               0x00002000 /* GUESS */
221#       define R300_INPUT_CNTL_TC4               0x00004000 /* GUESS */
222#       define R300_INPUT_CNTL_TC5               0x00008000 /* GUESS */
223#       define R300_INPUT_CNTL_TC6               0x00010000 /* GUESS */
224#       define R300_INPUT_CNTL_TC7               0x00020000 /* GUESS */
225
226/* gap */
227
228/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
229 * are set to a swizzling bit pattern, other words are 0.
230 *
231 * In immediate mode, the pattern is always set to xyzw. In vertex array
232 * mode, the swizzling pattern is e.g. used to set zw components in texture
233 * coordinates with only tweo components.
234 */
235#define R300_VAP_INPUT_ROUTE_1_0            0x21E0
236#       define R300_INPUT_ROUTE_SELECT_X    0
237#       define R300_INPUT_ROUTE_SELECT_Y    1
238#       define R300_INPUT_ROUTE_SELECT_Z    2
239#       define R300_INPUT_ROUTE_SELECT_W    3
240#       define R300_INPUT_ROUTE_SELECT_ZERO 4
241#       define R300_INPUT_ROUTE_SELECT_ONE  5
242#       define R300_INPUT_ROUTE_SELECT_MASK 7
243#       define R300_INPUT_ROUTE_X_SHIFT     0
244#       define R300_INPUT_ROUTE_Y_SHIFT     3
245#       define R300_INPUT_ROUTE_Z_SHIFT     6
246#       define R300_INPUT_ROUTE_W_SHIFT     9
247#       define R300_INPUT_ROUTE_ENABLE      (15 << 12)
248#define R300_VAP_INPUT_ROUTE_1_1            0x21E4
249#define R300_VAP_INPUT_ROUTE_1_2            0x21E8
250#define R300_VAP_INPUT_ROUTE_1_3            0x21EC
251#define R300_VAP_INPUT_ROUTE_1_4            0x21F0
252#define R300_VAP_INPUT_ROUTE_1_5            0x21F4
253#define R300_VAP_INPUT_ROUTE_1_6            0x21F8
254#define R300_VAP_INPUT_ROUTE_1_7            0x21FC
255
256/* END: Vertex data assembly */
257
258/* gap */
259
260/* BEGIN: Upload vertex program and data */
261
262/*
263 * The programmable vertex shader unit has a memory bank of unknown size
264 * that can be written to in 16 byte units by writing the address into
265 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
266 *
267 * Pointers into the memory bank are always in multiples of 16 bytes.
268 *
269 * The memory bank is divided into areas with fixed meaning.
270 *
271 * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
272 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
273 * whereas the difference between known addresses suggests size 512.
274 *
275 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
276 * Native reported limits and the VPI layout suggest size 256, whereas
277 * difference between known addresses suggests size 512.
278 *
279 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
280 * floating point pointsize. The exact purpose of this state is uncertain,
281 * as there is also the R300_RE_POINTSIZE register.
282 *
283 * Multiple vertex programs and parameter sets can be loaded at once,
284 * which could explain the size discrepancy.
285 */
286#define R300_VAP_PVS_UPLOAD_ADDRESS         0x2200
287#       define R300_PVS_UPLOAD_PROGRAM           0x00000000
288#       define R300_PVS_UPLOAD_PARAMETERS        0x00000200
289#       define R300_PVS_UPLOAD_POINTSIZE         0x00000406
290
291/* gap */
292
293#define R300_VAP_PVS_UPLOAD_DATA            0x2208
294
295/* END: Upload vertex program and data */
296
297/* gap */
298
299/* I do not know the purpose of this register. However, I do know that
300 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
301 * for normal rendering.
302 */
303#define R300_VAP_UNKNOWN_221C               0x221C
304#       define R300_221C_NORMAL                  0x00000000
305#       define R300_221C_CLEAR                   0x0001C000
306
307/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
309 *
310 * This was determined by experimentation alone but I believe it is correct.
311 *
312 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
313 */
314#define R300_VAP_CLIP_X_0                   0x2220
315#define R300_VAP_CLIP_X_1                   0x2224
316#define R300_VAP_CLIP_Y_0                   0x2228
317#define R300_VAP_CLIP_Y_1                   0x2230
318
319/* gap */
320
321/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
322 * rendering commands and overwriting vertex program parameters.
323 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
324 * avoids bugs caused by still running shaders reading bad data from memory.
325 */
326#define R300_VAP_PVS_STATE_FLUSH_REG        0x2284
327
328/* Absolutely no clue what this register is about. */
329#define R300_VAP_UNKNOWN_2288               0x2288
330#       define R300_2288_R300                    0x00750000 /* -- nh */
331#       define R300_2288_RV350                   0x0000FFFF /* -- Vladimir */
332
333/* gap */
334
335/* Addresses are relative to the vertex program instruction area of the
336 * memory bank. PROGRAM_END points to the last instruction of the active
337 * program
338 *
339 * The meaning of the two UNKNOWN fields is obviously not known. However,
340 * experiments so far have shown that both *must* point to an instruction
341 * inside the vertex program, otherwise the GPU locks up.
342 *
343 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
344 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
345 * position takes place.
346 *
347 * Most likely this is used to ignore rest of the program in cases
348 * where group of verts arent visible. For some reason this "section"
349 * is sometimes accepted other instruction that have no relationship with
350 * position calculations.
351 */
352#define R300_VAP_PVS_CNTL_1                 0x22D0
353#       define R300_PVS_CNTL_1_PROGRAM_START_SHIFT   0
354#       define R300_PVS_CNTL_1_POS_END_SHIFT         10
355#       define R300_PVS_CNTL_1_PROGRAM_END_SHIFT     20
356/* Addresses are relative the the vertex program parameters area. */
357#define R300_VAP_PVS_CNTL_2                 0x22D4
358#       define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
359#       define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT  16
360#define R300_VAP_PVS_CNTL_3	           0x22D8
361#       define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
362#       define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
363
364/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
365 * immediate vertices
366 */
367#define R300_VAP_VTX_COLOR_R                0x2464
368#define R300_VAP_VTX_COLOR_G                0x2468
369#define R300_VAP_VTX_COLOR_B                0x246C
370#define R300_VAP_VTX_POS_0_X_1              0x2490 /* used for glVertex2*() */
371#define R300_VAP_VTX_POS_0_Y_1              0x2494
372#define R300_VAP_VTX_COLOR_PKD              0x249C /* RGBA */
373#define R300_VAP_VTX_POS_0_X_2              0x24A0 /* used for glVertex3*() */
374#define R300_VAP_VTX_POS_0_Y_2              0x24A4
375#define R300_VAP_VTX_POS_0_Z_2              0x24A8
376/* write 0 to indicate end of packet? */
377#define R300_VAP_VTX_END_OF_PKT             0x24AC
378
379/* gap */
380
381/* These are values from r300_reg/r300_reg.h - they are known to be correct
382 * and are here so we can use one register file instead of several
383 * - Vladimir
384 */
385#define R300_GB_VAP_RASTER_VTX_FMT_0	0x4000
386#	define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT	(1<<0)
387#	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT	(1<<1)
388#	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT	(1<<2)
389#	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT	(1<<3)
390#	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT	(1<<4)
391#	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE	(0xf<<5)
392#	define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT	(0x1<<16)
393
394#define R300_GB_VAP_RASTER_VTX_FMT_1	0x4004
395	/* each of the following is 3 bits wide, specifies number
396	   of components */
397#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT	0
398#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT	3
399#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT	6
400#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT	9
401#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT	12
402#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT	15
403#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT	18
404#	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT	21
405
406/* UNK30 seems to enables point to quad transformation on textures
407 * (or something closely related to that).
408 * This bit is rather fatal at the time being due to lackings at pixel
409 * shader side
410 */
411#define R300_GB_ENABLE	0x4008
412#	define R300_GB_POINT_STUFF_ENABLE	(1<<0)
413#	define R300_GB_LINE_STUFF_ENABLE	(1<<1)
414#	define R300_GB_TRIANGLE_STUFF_ENABLE	(1<<2)
415#	define R300_GB_STENCIL_AUTO_ENABLE	(1<<4)
416#	define R300_GB_UNK31			(1<<31)
417	/* each of the following is 2 bits wide */
418#define R300_GB_TEX_REPLICATE	0
419#define R300_GB_TEX_ST		1
420#define R300_GB_TEX_STR		2
421#	define R300_GB_TEX0_SOURCE_SHIFT	16
422#	define R300_GB_TEX1_SOURCE_SHIFT	18
423#	define R300_GB_TEX2_SOURCE_SHIFT	20
424#	define R300_GB_TEX3_SOURCE_SHIFT	22
425#	define R300_GB_TEX4_SOURCE_SHIFT	24
426#	define R300_GB_TEX5_SOURCE_SHIFT	26
427#	define R300_GB_TEX6_SOURCE_SHIFT	28
428#	define R300_GB_TEX7_SOURCE_SHIFT	30
429
430/* MSPOS - positions for multisample antialiasing (?) */
431#define R300_GB_MSPOS0	0x4010
432	/* shifts - each of the fields is 4 bits */
433#	define R300_GB_MSPOS0__MS_X0_SHIFT	0
434#	define R300_GB_MSPOS0__MS_Y0_SHIFT	4
435#	define R300_GB_MSPOS0__MS_X1_SHIFT	8
436#	define R300_GB_MSPOS0__MS_Y1_SHIFT	12
437#	define R300_GB_MSPOS0__MS_X2_SHIFT	16
438#	define R300_GB_MSPOS0__MS_Y2_SHIFT	20
439#	define R300_GB_MSPOS0__MSBD0_Y		24
440#	define R300_GB_MSPOS0__MSBD0_X		28
441
442#define R300_GB_MSPOS1	0x4014
443#	define R300_GB_MSPOS1__MS_X3_SHIFT	0
444#	define R300_GB_MSPOS1__MS_Y3_SHIFT	4
445#	define R300_GB_MSPOS1__MS_X4_SHIFT	8
446#	define R300_GB_MSPOS1__MS_Y4_SHIFT	12
447#	define R300_GB_MSPOS1__MS_X5_SHIFT	16
448#	define R300_GB_MSPOS1__MS_Y5_SHIFT	20
449#	define R300_GB_MSPOS1__MSBD1		24
450
451
452#define R300_GB_TILE_CONFIG	0x4018
453#	define R300_GB_TILE_ENABLE	(1<<0)
454#	define R300_GB_TILE_PIPE_COUNT_RV300	0
455#	define R300_GB_TILE_PIPE_COUNT_R300	(3<<1)
456#	define R300_GB_TILE_PIPE_COUNT_R420	(7<<1)
457#	define R300_GB_TILE_PIPE_COUNT_RV410	(3<<1)
458#	define R300_GB_TILE_SIZE_8		0
459#	define R300_GB_TILE_SIZE_16		(1<<4)
460#	define R300_GB_TILE_SIZE_32		(2<<4)
461#	define R300_GB_SUPER_SIZE_1		(0<<6)
462#	define R300_GB_SUPER_SIZE_2		(1<<6)
463#	define R300_GB_SUPER_SIZE_4		(2<<6)
464#	define R300_GB_SUPER_SIZE_8		(3<<6)
465#	define R300_GB_SUPER_SIZE_16		(4<<6)
466#	define R300_GB_SUPER_SIZE_32		(5<<6)
467#	define R300_GB_SUPER_SIZE_64		(6<<6)
468#	define R300_GB_SUPER_SIZE_128		(7<<6)
469#	define R300_GB_SUPER_X_SHIFT		9	/* 3 bits wide */
470#	define R300_GB_SUPER_Y_SHIFT		12	/* 3 bits wide */
471#	define R300_GB_SUPER_TILE_A		0
472#	define R300_GB_SUPER_TILE_B		(1<<15)
473#	define R300_GB_SUBPIXEL_1_12		0
474#	define R300_GB_SUBPIXEL_1_16		(1<<16)
475
476#define R300_GB_FIFO_SIZE	0x4024
477	/* each of the following is 2 bits wide */
478#define R300_GB_FIFO_SIZE_32	0
479#define R300_GB_FIFO_SIZE_64	1
480#define R300_GB_FIFO_SIZE_128	2
481#define R300_GB_FIFO_SIZE_256	3
482#	define R300_SC_IFIFO_SIZE_SHIFT	0
483#	define R300_SC_TZFIFO_SIZE_SHIFT	2
484#	define R300_SC_BFIFO_SIZE_SHIFT	4
485
486#	define R300_US_OFIFO_SIZE_SHIFT	12
487#	define R300_US_WFIFO_SIZE_SHIFT	14
488	/* the following use the same constants as above, but meaning is
489	   is times 2 (i.e. instead of 32 words it means 64 */
490#	define R300_RS_TFIFO_SIZE_SHIFT	6
491#	define R300_RS_CFIFO_SIZE_SHIFT	8
492#	define R300_US_RAM_SIZE_SHIFT		10
493	/* watermarks, 3 bits wide */
494#	define R300_RS_HIGHWATER_COL_SHIFT	16
495#	define R300_RS_HIGHWATER_TEX_SHIFT	19
496#	define R300_OFIFO_HIGHWATER_SHIFT	22	/* two bits only */
497#	define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT	24
498
499#define R300_GB_SELECT	0x401C
500#	define R300_GB_FOG_SELECT_C0A		0
501#	define R300_GB_FOG_SELECT_C1A		1
502#	define R300_GB_FOG_SELECT_C2A		2
503#	define R300_GB_FOG_SELECT_C3A		3
504#	define R300_GB_FOG_SELECT_1_1_W	4
505#	define R300_GB_FOG_SELECT_Z		5
506#	define R300_GB_DEPTH_SELECT_Z		0
507#	define R300_GB_DEPTH_SELECT_1_1_W	(1<<3)
508#	define R300_GB_W_SELECT_1_W		0
509#	define R300_GB_W_SELECT_1		(1<<4)
510
511#define R300_GB_AA_CONFIG		0x4020
512#	define R300_AA_DISABLE			0x00
513#	define R300_AA_ENABLE			0x01
514#	define R300_AA_SUBSAMPLES_2		0
515#	define R300_AA_SUBSAMPLES_3		(1<<1)
516#	define R300_AA_SUBSAMPLES_4		(2<<1)
517#	define R300_AA_SUBSAMPLES_6		(3<<1)
518
519/* gap */
520
521/* Zero to flush caches. */
522#define R300_TX_INVALTAGS                   0x4100
523#define R300_TX_FLUSH                       0x0
524
525/* The upper enable bits are guessed, based on fglrx reported limits. */
526#define R300_TX_ENABLE                      0x4104
527#       define R300_TX_ENABLE_0                  (1 << 0)
528#       define R300_TX_ENABLE_1                  (1 << 1)
529#       define R300_TX_ENABLE_2                  (1 << 2)
530#       define R300_TX_ENABLE_3                  (1 << 3)
531#       define R300_TX_ENABLE_4                  (1 << 4)
532#       define R300_TX_ENABLE_5                  (1 << 5)
533#       define R300_TX_ENABLE_6                  (1 << 6)
534#       define R300_TX_ENABLE_7                  (1 << 7)
535#       define R300_TX_ENABLE_8                  (1 << 8)
536#       define R300_TX_ENABLE_9                  (1 << 9)
537#       define R300_TX_ENABLE_10                 (1 << 10)
538#       define R300_TX_ENABLE_11                 (1 << 11)
539#       define R300_TX_ENABLE_12                 (1 << 12)
540#       define R300_TX_ENABLE_13                 (1 << 13)
541#       define R300_TX_ENABLE_14                 (1 << 14)
542#       define R300_TX_ENABLE_15                 (1 << 15)
543
544/* The pointsize is given in multiples of 6. The pointsize can be
545 * enormous: Clear() renders a single point that fills the entire
546 * framebuffer.
547 */
548#define R300_RE_POINTSIZE                   0x421C
549#       define R300_POINTSIZE_Y_SHIFT            0
550#       define R300_POINTSIZE_Y_MASK             (0xFFFF << 0) /* GUESS */
551#       define R300_POINTSIZE_X_SHIFT            16
552#       define R300_POINTSIZE_X_MASK             (0xFFFF << 16) /* GUESS */
553#       define R300_POINTSIZE_MAX             (R300_POINTSIZE_Y_MASK / 6)
554
555/* The line width is given in multiples of 6.
556 * In default mode lines are classified as vertical lines.
557 * HO: horizontal
558 * VE: vertical or horizontal
559 * HO & VE: no classification
560 */
561#define R300_RE_LINE_CNT                      0x4234
562#       define R300_LINESIZE_SHIFT            0
563#       define R300_LINESIZE_MASK             (0xFFFF << 0) /* GUESS */
564#       define R300_LINESIZE_MAX             (R300_LINESIZE_MASK / 6)
565#       define R300_LINE_CNT_HO               (1 << 16)
566#       define R300_LINE_CNT_VE               (1 << 17)
567
568/* Some sort of scale or clamp value for texcoordless textures. */
569#define R300_RE_UNK4238                       0x4238
570
571/* Something shade related */
572#define R300_RE_SHADE                         0x4274
573
574#define R300_RE_SHADE_MODEL                   0x4278
575#	define R300_RE_SHADE_MODEL_SMOOTH     0x3aaaa
576#	define R300_RE_SHADE_MODEL_FLAT       0x39595
577
578/* Dangerous */
579#define R300_RE_POLYGON_MODE                  0x4288
580#	define R300_PM_ENABLED                (1 << 0)
581#	define R300_PM_FRONT_POINT            (0 << 0)
582#	define R300_PM_BACK_POINT             (0 << 0)
583#	define R300_PM_FRONT_LINE             (1 << 4)
584#	define R300_PM_FRONT_FILL             (1 << 5)
585#	define R300_PM_BACK_LINE              (1 << 7)
586#	define R300_PM_BACK_FILL              (1 << 8)
587
588/* Fog parameters */
589#define R300_RE_FOG_SCALE                     0x4294
590#define R300_RE_FOG_START                     0x4298
591
592/* Not sure why there are duplicate of factor and constant values.
593 * My best guess so far is that there are separate zbiases for test and write.
594 * Ordering might be wrong.
595 * Some of the tests indicate that fgl has a fallback implementation of zbias
596 * via pixel shaders.
597 */
598#define R300_RE_ZBIAS_CNTL                    0x42A0 /* GUESS */
599#define R300_RE_ZBIAS_T_FACTOR                0x42A4
600#define R300_RE_ZBIAS_T_CONSTANT              0x42A8
601#define R300_RE_ZBIAS_W_FACTOR                0x42AC
602#define R300_RE_ZBIAS_W_CONSTANT              0x42B0
603
604/* This register needs to be set to (1<<1) for RV350 to correctly
605 * perform depth test (see --vb-triangles in r300_demo)
606 * Don't know about other chips. - Vladimir
607 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
608 * My guess is that there are two bits for each zbias primitive
609 * (FILL, LINE, POINT).
610 *  One to enable depth test and one for depth write.
611 * Yet this doesn't explain why depth writes work ...
612 */
613#define R300_RE_OCCLUSION_CNTL		    0x42B4
614#	define R300_OCCLUSION_ON		(1<<1)
615
616#define R300_RE_CULL_CNTL                   0x42B8
617#       define R300_CULL_FRONT                   (1 << 0)
618#       define R300_CULL_BACK                    (1 << 1)
619#       define R300_FRONT_FACE_CCW               (0 << 2)
620#       define R300_FRONT_FACE_CW                (1 << 2)
621
622
623/* BEGIN: Rasterization / Interpolators - many guesses */
624
625/* 0_UNKNOWN_18 has always been set except for clear operations.
626 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
627 * on the vertex program, *not* the fragment program)
628 */
629#define R300_RS_CNTL_0                      0x4300
630#       define R300_RS_CNTL_TC_CNT_SHIFT         2
631#       define R300_RS_CNTL_TC_CNT_MASK          (7 << 2)
632	/* number of color interpolators used */
633#	define R300_RS_CNTL_CI_CNT_SHIFT         7
634#       define R300_RS_CNTL_0_UNKNOWN_18         (1 << 18)
635	/* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n
636	   register. */
637#define R300_RS_CNTL_1                      0x4304
638
639/* gap */
640
641/* Only used for texture coordinates.
642 * Use the source field to route texture coordinate input from the
643 * vertex program to the desired interpolator. Note that the source
644 * field is relative to the outputs the vertex program *actually*
645 * writes. If a vertex program only writes texcoord[1], this will
646 * be source index 0.
647 * Set INTERP_USED on all interpolators that produce data used by
648 * the fragment program. INTERP_USED looks like a swizzling mask,
649 * but I haven't seen it used that way.
650 *
651 * Note: The _UNKNOWN constants are always set in their respective
652 * register. I don't know if this is necessary.
653 */
654#define R300_RS_INTERP_0                    0x4310
655#define R300_RS_INTERP_1                    0x4314
656#       define R300_RS_INTERP_1_UNKNOWN          0x40
657#define R300_RS_INTERP_2                    0x4318
658#       define R300_RS_INTERP_2_UNKNOWN          0x80
659#define R300_RS_INTERP_3                    0x431C
660#       define R300_RS_INTERP_3_UNKNOWN          0xC0
661#define R300_RS_INTERP_4                    0x4320
662#define R300_RS_INTERP_5                    0x4324
663#define R300_RS_INTERP_6                    0x4328
664#define R300_RS_INTERP_7                    0x432C
665#       define R300_RS_INTERP_SRC_SHIFT          2
666#       define R300_RS_INTERP_SRC_MASK           (7 << 2)
667#       define R300_RS_INTERP_USED               0x00D10000
668
669/* These DWORDs control how vertex data is routed into fragment program
670 * registers, after interpolators.
671 */
672#define R300_RS_ROUTE_0                     0x4330
673#define R300_RS_ROUTE_1                     0x4334
674#define R300_RS_ROUTE_2                     0x4338
675#define R300_RS_ROUTE_3                     0x433C /* GUESS */
676#define R300_RS_ROUTE_4                     0x4340 /* GUESS */
677#define R300_RS_ROUTE_5                     0x4344 /* GUESS */
678#define R300_RS_ROUTE_6                     0x4348 /* GUESS */
679#define R300_RS_ROUTE_7                     0x434C /* GUESS */
680#       define R300_RS_ROUTE_SOURCE_INTERP_0     0
681#       define R300_RS_ROUTE_SOURCE_INTERP_1     1
682#       define R300_RS_ROUTE_SOURCE_INTERP_2     2
683#       define R300_RS_ROUTE_SOURCE_INTERP_3     3
684#       define R300_RS_ROUTE_SOURCE_INTERP_4     4
685#       define R300_RS_ROUTE_SOURCE_INTERP_5     5 /* GUESS */
686#       define R300_RS_ROUTE_SOURCE_INTERP_6     6 /* GUESS */
687#       define R300_RS_ROUTE_SOURCE_INTERP_7     7 /* GUESS */
688#       define R300_RS_ROUTE_ENABLE              (1 << 3) /* GUESS */
689#       define R300_RS_ROUTE_DEST_SHIFT          6
690#       define R300_RS_ROUTE_DEST_MASK           (31 << 6) /* GUESS */
691
692/* Special handling for color: When the fragment program uses color,
693 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
694 * color register index.
695 *
696 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any
697 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.
698 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly
699 * correct or not. - Oliver.
700 */
701#       define R300_RS_ROUTE_0_COLOR             (1 << 14)
702#       define R300_RS_ROUTE_0_COLOR_DEST_SHIFT  17
703#       define R300_RS_ROUTE_0_COLOR_DEST_MASK   (31 << 17) /* GUESS */
704/* As above, but for secondary color */
705#		define R300_RS_ROUTE_1_COLOR1            (1 << 14)
706#		define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17
707#		define R300_RS_ROUTE_1_COLOR1_DEST_MASK  (31 << 17)
708#		define R300_RS_ROUTE_1_UNKNOWN11         (1 << 11)
709/* END: Rasterization / Interpolators - many guesses */
710
711/* Hierarchical Z Enable */
712#define R300_SC_HYPERZ                   0x43a4
713#	define R300_SC_HYPERZ_DISABLE     (0 << 0)
714#	define R300_SC_HYPERZ_ENABLE      (1 << 0)
715#	define R300_SC_HYPERZ_MIN         (0 << 1)
716#	define R300_SC_HYPERZ_MAX         (1 << 1)
717#	define R300_SC_HYPERZ_ADJ_256     (0 << 2)
718#	define R300_SC_HYPERZ_ADJ_128     (1 << 2)
719#	define R300_SC_HYPERZ_ADJ_64      (2 << 2)
720#	define R300_SC_HYPERZ_ADJ_32      (3 << 2)
721#	define R300_SC_HYPERZ_ADJ_16      (4 << 2)
722#	define R300_SC_HYPERZ_ADJ_8       (5 << 2)
723#	define R300_SC_HYPERZ_ADJ_4       (6 << 2)
724#	define R300_SC_HYPERZ_ADJ_2       (7 << 2)
725#	define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
726#	define R300_SC_HYPERZ_HZ_Z0MIN    (1 << 5)
727#	define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
728#	define R300_SC_HYPERZ_HZ_Z0MAX    (1 << 6)
729
730#define R300_SC_EDGERULE                 0x43a8
731
732/* BEGIN: Scissors and cliprects */
733
734/* There are four clipping rectangles. Their corner coordinates are inclusive.
735 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
736 * on whether the pixel is inside cliprects 0-3, respectively. For example,
737 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
738 * the number 3 (binary 0011).
739 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
740 * the pixel is rasterized.
741 *
742 * In addition to this, there is a scissors rectangle. Only pixels inside the
743 * scissors rectangle are drawn. (coordinates are inclusive)
744 *
745 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
746 * for the purpose of clipping and scissors.
747 */
748#define R300_RE_CLIPRECT_TL_0               0x43B0
749#define R300_RE_CLIPRECT_BR_0               0x43B4
750#define R300_RE_CLIPRECT_TL_1               0x43B8
751#define R300_RE_CLIPRECT_BR_1               0x43BC
752#define R300_RE_CLIPRECT_TL_2               0x43C0
753#define R300_RE_CLIPRECT_BR_2               0x43C4
754#define R300_RE_CLIPRECT_TL_3               0x43C8
755#define R300_RE_CLIPRECT_BR_3               0x43CC
756#       define R300_CLIPRECT_OFFSET              1440
757#       define R300_CLIPRECT_MASK                0x1FFF
758#       define R300_CLIPRECT_X_SHIFT             0
759#       define R300_CLIPRECT_X_MASK              (0x1FFF << 0)
760#       define R300_CLIPRECT_Y_SHIFT             13
761#       define R300_CLIPRECT_Y_MASK              (0x1FFF << 13)
762#define R300_RE_CLIPRECT_CNTL               0x43D0
763#       define R300_CLIP_OUT                     (1 << 0)
764#       define R300_CLIP_0                       (1 << 1)
765#       define R300_CLIP_1                       (1 << 2)
766#       define R300_CLIP_10                      (1 << 3)
767#       define R300_CLIP_2                       (1 << 4)
768#       define R300_CLIP_20                      (1 << 5)
769#       define R300_CLIP_21                      (1 << 6)
770#       define R300_CLIP_210                     (1 << 7)
771#       define R300_CLIP_3                       (1 << 8)
772#       define R300_CLIP_30                      (1 << 9)
773#       define R300_CLIP_31                      (1 << 10)
774#       define R300_CLIP_310                     (1 << 11)
775#       define R300_CLIP_32                      (1 << 12)
776#       define R300_CLIP_320                     (1 << 13)
777#       define R300_CLIP_321                     (1 << 14)
778#       define R300_CLIP_3210                    (1 << 15)
779
780/* gap */
781
782#define R300_RE_SCISSORS_TL                 0x43E0
783#define R300_RE_SCISSORS_BR                 0x43E4
784#       define R300_SCISSORS_OFFSET              1440
785#       define R300_SCISSORS_X_SHIFT             0
786#       define R300_SCISSORS_X_MASK              (0x1FFF << 0)
787#       define R300_SCISSORS_Y_SHIFT             13
788#       define R300_SCISSORS_Y_MASK              (0x1FFF << 13)
789/* END: Scissors and cliprects */
790
791/* BEGIN: Texture specification */
792
793/*
794 * The texture specification dwords are grouped by meaning and not by texture
795 * unit. This means that e.g. the offset for texture image unit N is found in
796 * register TX_OFFSET_0 + (4*N)
797 */
798#define R300_TX_FILTER_0                    0x4400
799#       define R300_TX_REPEAT                    0
800#       define R300_TX_MIRRORED                  1
801#       define R300_TX_CLAMP                     4
802#       define R300_TX_CLAMP_TO_EDGE             2
803#       define R300_TX_CLAMP_TO_BORDER           6
804#       define R300_TX_WRAP_S_SHIFT              0
805#       define R300_TX_WRAP_S_MASK               (7 << 0)
806#       define R300_TX_WRAP_T_SHIFT              3
807#       define R300_TX_WRAP_T_MASK               (7 << 3)
808#       define R300_TX_WRAP_Q_SHIFT              6
809#       define R300_TX_WRAP_Q_MASK               (7 << 6)
810#       define R300_TX_MAG_FILTER_NEAREST        (1 << 9)
811#       define R300_TX_MAG_FILTER_LINEAR         (2 << 9)
812#       define R300_TX_MAG_FILTER_MASK           (3 << 9)
813#       define R300_TX_MIN_FILTER_NEAREST        (1 << 11)
814#       define R300_TX_MIN_FILTER_LINEAR         (2 << 11)
815#	define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST       (5  <<  11)
816#	define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR        (9  <<  11)
817#	define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST        (6  <<  11)
818#	define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR         (10 <<  11)
819
820/* NOTE: NEAREST doesn't seem to exist.
821 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all
822 * anisotropy modes because that would void selected mag filter
823 */
824#	define R300_TX_MIN_FILTER_ANISO_NEAREST             (0 << 13)
825#	define R300_TX_MIN_FILTER_ANISO_LINEAR              (0 << 13)
826#	define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)
827#	define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR  (2 << 13)
828#       define R300_TX_MIN_FILTER_MASK   ( (15 << 11) | (3 << 13) )
829#	define R300_TX_MAX_ANISO_1_TO_1  (0 << 21)
830#	define R300_TX_MAX_ANISO_2_TO_1  (2 << 21)
831#	define R300_TX_MAX_ANISO_4_TO_1  (4 << 21)
832#	define R300_TX_MAX_ANISO_8_TO_1  (6 << 21)
833#	define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)
834#	define R300_TX_MAX_ANISO_MASK    (14 << 21)
835
836#define R300_TX_FILTER1_0                      0x4440
837#	define R300_CHROMA_KEY_MODE_DISABLE    0
838#	define R300_CHROMA_KEY_FORCE	       1
839#	define R300_CHROMA_KEY_BLEND           2
840#	define R300_MC_ROUND_NORMAL            (0<<2)
841#	define R300_MC_ROUND_MPEG4             (1<<2)
842#	define R300_LOD_BIAS_MASK	    0x1fff
843#	define R300_EDGE_ANISO_EDGE_DIAG       (0<<13)
844#	define R300_EDGE_ANISO_EDGE_ONLY       (1<<13)
845#	define R300_MC_COORD_TRUNCATE_DISABLE  (0<<14)
846#	define R300_MC_COORD_TRUNCATE_MPEG     (1<<14)
847#	define R300_TX_TRI_PERF_0_8            (0<<15)
848#	define R300_TX_TRI_PERF_1_8            (1<<15)
849#	define R300_TX_TRI_PERF_1_4            (2<<15)
850#	define R300_TX_TRI_PERF_3_8            (3<<15)
851#	define R300_ANISO_THRESHOLD_MASK       (7<<17)
852
853#define R300_TX_SIZE_0                      0x4480
854#       define R300_TX_WIDTHMASK_SHIFT           0
855#       define R300_TX_WIDTHMASK_MASK            (2047 << 0)
856#       define R300_TX_HEIGHTMASK_SHIFT          11
857#       define R300_TX_HEIGHTMASK_MASK           (2047 << 11)
858#       define R300_TX_UNK23                     (1 << 23)
859#       define R300_TX_MAX_MIP_LEVEL_SHIFT       26
860#       define R300_TX_MAX_MIP_LEVEL_MASK        (0xf << 26)
861#       define R300_TX_SIZE_PROJECTED            (1<<30)
862#       define R300_TX_SIZE_TXPITCH_EN           (1<<31)
863#define R300_TX_FORMAT_0                    0x44C0
864	/* The interpretation of the format word by Wladimir van der Laan */
865	/* The X, Y, Z and W refer to the layout of the components.
866	   They are given meanings as R, G, B and Alpha by the swizzle
867	   specification */
868#	define R300_TX_FORMAT_X8		    0x0
869#	define R300_TX_FORMAT_X16		    0x1
870#	define R300_TX_FORMAT_Y4X4		    0x2
871#	define R300_TX_FORMAT_Y8X8		    0x3
872#	define R300_TX_FORMAT_Y16X16		    0x4
873#	define R300_TX_FORMAT_Z3Y3X2		    0x5
874#	define R300_TX_FORMAT_Z5Y6X5		    0x6
875#	define R300_TX_FORMAT_Z6Y5X5		    0x7
876#	define R300_TX_FORMAT_Z11Y11X10		    0x8
877#	define R300_TX_FORMAT_Z10Y11X11		    0x9
878#	define R300_TX_FORMAT_W4Z4Y4X4		    0xA
879#	define R300_TX_FORMAT_W1Z5Y5X5		    0xB
880#	define R300_TX_FORMAT_W8Z8Y8X8		    0xC
881#	define R300_TX_FORMAT_W2Z10Y10X10	    0xD
882#	define R300_TX_FORMAT_W16Z16Y16X16	    0xE
883#	define R300_TX_FORMAT_DXT1		    0xF
884#	define R300_TX_FORMAT_DXT3		    0x10
885#	define R300_TX_FORMAT_DXT5		    0x11
886#	define R300_TX_FORMAT_D3DMFT_CxV8U8	    0x12     /* no swizzle */
887#	define R300_TX_FORMAT_A8R8G8B8		    0x13     /* no swizzle */
888#	define R300_TX_FORMAT_B8G8_B8G8		    0x14     /* no swizzle */
889#	define R300_TX_FORMAT_G8R8_G8B8		    0x15     /* no swizzle */
890	/* 0x16 - some 16 bit green format.. ?? */
891#	define R300_TX_FORMAT_UNK25		   (1 << 25) /* no swizzle */
892#	define R300_TX_FORMAT_CUBIC_MAP		   (1 << 26)
893
894	/* gap */
895	/* Floating point formats */
896	/* Note - hardware supports both 16 and 32 bit floating point */
897#	define R300_TX_FORMAT_FL_I16		    0x18
898#	define R300_TX_FORMAT_FL_I16A16		    0x19
899#	define R300_TX_FORMAT_FL_R16G16B16A16	    0x1A
900#	define R300_TX_FORMAT_FL_I32		    0x1B
901#	define R300_TX_FORMAT_FL_I32A32		    0x1C
902#	define R300_TX_FORMAT_FL_R32G32B32A32	    0x1D
903#	define R300_TX_FORMAT_ATI2N		    0x1F
904	/* alpha modes, convenience mostly */
905	/* if you have alpha, pick constant appropriate to the
906	   number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
907#	define R300_TX_FORMAT_ALPHA_1CH		    0x000
908#	define R300_TX_FORMAT_ALPHA_2CH		    0x200
909#	define R300_TX_FORMAT_ALPHA_4CH		    0x600
910#	define R300_TX_FORMAT_ALPHA_NONE	    0xA00
911	/* Swizzling */
912	/* constants */
913#	define R300_TX_FORMAT_X		0
914#	define R300_TX_FORMAT_Y		1
915#	define R300_TX_FORMAT_Z		2
916#	define R300_TX_FORMAT_W		3
917#	define R300_TX_FORMAT_ZERO	4
918#	define R300_TX_FORMAT_ONE	5
919	/* 2.0*Z, everything above 1.0 is set to 0.0 */
920#	define R300_TX_FORMAT_CUT_Z	6
921	/* 2.0*W, everything above 1.0 is set to 0.0 */
922#	define R300_TX_FORMAT_CUT_W	7
923
924#	define R300_TX_FORMAT_B_SHIFT	18
925#	define R300_TX_FORMAT_G_SHIFT	15
926#	define R300_TX_FORMAT_R_SHIFT	12
927#	define R300_TX_FORMAT_A_SHIFT	9
928	/* Convenience macro to take care of layout and swizzling */
929#	define R300_EASY_TX_FORMAT(B, G, R, A, FMT)	(		\
930		((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT)		\
931		| ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT)	\
932		| ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT)	\
933		| ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT)	\
934		| (R300_TX_FORMAT_##FMT)				\
935		)
936	/* These can be ORed with result of R300_EASY_TX_FORMAT()
937	   We don't really know what they do. Take values from a
938           constant color ? */
939#	define R300_TX_FORMAT_CONST_X		(1<<5)
940#	define R300_TX_FORMAT_CONST_Y		(2<<5)
941#	define R300_TX_FORMAT_CONST_Z		(4<<5)
942#	define R300_TX_FORMAT_CONST_W		(8<<5)
943
944#	define R300_TX_FORMAT_YUV_MODE		0x00800000
945
946#define R300_TX_PITCH_0			    0x4500 /* obvious missing in gap */
947#define R300_TX_OFFSET_0                    0x4540
948	/* BEGIN: Guess from R200 */
949#       define R300_TXO_ENDIAN_NO_SWAP           (0 << 0)
950#       define R300_TXO_ENDIAN_BYTE_SWAP         (1 << 0)
951#       define R300_TXO_ENDIAN_WORD_SWAP         (2 << 0)
952#       define R300_TXO_ENDIAN_HALFDW_SWAP       (3 << 0)
953#       define R300_TXO_MACRO_TILE               (1 << 2)
954#       define R300_TXO_MICRO_TILE               (1 << 3)
955#       define R300_TXO_MICRO_TILE_SQUARE        (2 << 3)
956#       define R300_TXO_OFFSET_MASK              0xffffffe0
957#       define R300_TXO_OFFSET_SHIFT             5
958	/* END: Guess from R200 */
959
960/* 32 bit chroma key */
961#define R300_TX_CHROMA_KEY_0                      0x4580
962/* ff00ff00 == { 0, 1.0, 0, 1.0 } */
963#define R300_TX_BORDER_COLOR_0              0x45C0
964
965/* END: Texture specification */
966
967/* BEGIN: Fragment program instruction set */
968
969/* Fragment programs are written directly into register space.
970 * There are separate instruction streams for texture instructions and ALU
971 * instructions.
972 * In order to synchronize these streams, the program is divided into up
973 * to 4 nodes. Each node begins with a number of TEX operations, followed
974 * by a number of ALU operations.
975 * The first node can have zero TEX ops, all subsequent nodes must have at
976 * least
977 * one TEX ops.
978 * All nodes must have at least one ALU op.
979 *
980 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
981 * 1 node, a value of 3 means 4 nodes.
982 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
983 * offsets into the respective instruction streams, while *_END points to the
984 * last instruction relative to this offset.
985 */
986#define R300_PFS_CNTL_0                     0x4600
987#       define R300_PFS_CNTL_LAST_NODES_SHIFT    0
988#       define R300_PFS_CNTL_LAST_NODES_MASK     (3 << 0)
989#       define R300_PFS_CNTL_FIRST_NODE_HAS_TEX  (1 << 3)
990#define R300_PFS_CNTL_1                     0x4604
991/* There is an unshifted value here which has so far always been equal to the
992 * index of the highest used temporary register.
993 */
994#define R300_PFS_CNTL_2                     0x4608
995#       define R300_PFS_CNTL_ALU_OFFSET_SHIFT    0
996#       define R300_PFS_CNTL_ALU_OFFSET_MASK     (63 << 0)
997#       define R300_PFS_CNTL_ALU_END_SHIFT       6
998#       define R300_PFS_CNTL_ALU_END_MASK        (63 << 6)
999#       define R300_PFS_CNTL_TEX_OFFSET_SHIFT    12
1000#       define R300_PFS_CNTL_TEX_OFFSET_MASK     (31 << 12) /* GUESS */
1001#       define R300_PFS_CNTL_TEX_END_SHIFT       18
1002#       define R300_PFS_CNTL_TEX_END_MASK        (31 << 18) /* GUESS */
1003
1004/* gap */
1005
1006/* Nodes are stored backwards. The last active node is always stored in
1007 * PFS_NODE_3.
1008 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
1009 * first node is stored in NODE_2, the second node is stored in NODE_3.
1010 *
1011 * Offsets are relative to the master offset from PFS_CNTL_2.
1012 */
1013#define R300_PFS_NODE_0                     0x4610
1014#define R300_PFS_NODE_1                     0x4614
1015#define R300_PFS_NODE_2                     0x4618
1016#define R300_PFS_NODE_3                     0x461C
1017#       define R300_PFS_NODE_ALU_OFFSET_SHIFT    0
1018#       define R300_PFS_NODE_ALU_OFFSET_MASK     (63 << 0)
1019#       define R300_PFS_NODE_ALU_END_SHIFT       6
1020#       define R300_PFS_NODE_ALU_END_MASK        (63 << 6)
1021#       define R300_PFS_NODE_TEX_OFFSET_SHIFT    12
1022#       define R300_PFS_NODE_TEX_OFFSET_MASK     (31 << 12)
1023#       define R300_PFS_NODE_TEX_END_SHIFT       17
1024#       define R300_PFS_NODE_TEX_END_MASK        (31 << 17)
1025#		define R300_PFS_NODE_OUTPUT_COLOR        (1 << 22)
1026#		define R300_PFS_NODE_OUTPUT_DEPTH        (1 << 23)
1027
1028/* TEX
1029 * As far as I can tell, texture instructions cannot write into output
1030 * registers directly. A subsequent ALU instruction is always necessary,
1031 * even if it's just MAD o0, r0, 1, 0
1032 */
1033#define R300_PFS_TEXI_0                     0x4620
1034#	define R300_FPITX_SRC_SHIFT              0
1035#	define R300_FPITX_SRC_MASK               (31 << 0)
1036	/* GUESS */
1037#	define R300_FPITX_SRC_CONST              (1 << 5)
1038#	define R300_FPITX_DST_SHIFT              6
1039#	define R300_FPITX_DST_MASK               (31 << 6)
1040#	define R300_FPITX_IMAGE_SHIFT            11
1041	/* GUESS based on layout and native limits */
1042#       define R300_FPITX_IMAGE_MASK             (15 << 11)
1043/* Unsure if these are opcodes, or some kind of bitfield, but this is how
1044 * they were set when I checked
1045 */
1046#	define R300_FPITX_OPCODE_SHIFT		15
1047#		define R300_FPITX_OP_TEX	1
1048#		define R300_FPITX_OP_KIL	2
1049#		define R300_FPITX_OP_TXP	3
1050#		define R300_FPITX_OP_TXB	4
1051#	define R300_FPITX_OPCODE_MASK           (7 << 15)
1052
1053/* ALU
1054 * The ALU instructions register blocks are enumerated according to the order
1055 * in which fglrx. I assume there is space for 64 instructions, since
1056 * each block has space for a maximum of 64 DWORDs, and this matches reported
1057 * native limits.
1058 *
1059 * The basic functional block seems to be one MAD for each color and alpha,
1060 * and an adder that adds all components after the MUL.
1061 *  - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
1062 *  - DP4: Use OUTC_DP4, OUTA_DP4
1063 *  - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
1064 *  - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
1065 *  - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
1066 *  - CMP: If ARG2 < 0, return ARG1, else return ARG0
1067 *  - FLR: use FRC+MAD
1068 *  - XPD: use MAD+MAD
1069 *  - SGE, SLT: use MAD+CMP
1070 *  - RSQ: use ABS modifier for argument
1071 *  - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
1072 *    (e.g. RCP) into color register
1073 *  - apparently, there's no quick DST operation
1074 *  - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
1075 *  - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
1076 *  - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
1077 *
1078 * Operand selection
1079 * First stage selects three sources from the available registers and
1080 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
1081 * fglrx sorts the three source fields: Registers before constants,
1082 * lower indices before higher indices; I do not know whether this is
1083 * necessary.
1084 *
1085 * fglrx fills unused sources with "read constant 0"
1086 * According to specs, you cannot select more than two different constants.
1087 *
1088 * Second stage selects the operands from the sources. This is defined in
1089 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
1090 * zero and one.
1091 * Swizzling and negation happens in this stage, as well.
1092 *
1093 * Important: Color and alpha seem to be mostly separate, i.e. their sources
1094 * selection appears to be fully independent (the register storage is probably
1095 * physically split into a color and an alpha section).
1096 * However (because of the apparent physical split), there is some interaction
1097 * WRT swizzling. If, for example, you want to load an R component into an
1098 * Alpha operand, this R component is taken from a *color* source, not from
1099 * an alpha source. The corresponding register doesn't even have to appear in
1100 * the alpha sources list. (I hope this all makes sense to you)
1101 *
1102 * Destination selection
1103 * The destination register index is in FPI1 (color) and FPI3 (alpha)
1104 * together with enable bits.
1105 * There are separate enable bits for writing into temporary registers
1106 * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_*
1107 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
1108 * same index must be used for both).
1109 *
1110 * Note: There is a special form for LRP
1111 *  - Argument order is the same as in ARB_fragment_program.
1112 *  - Operation is MAD
1113 *  - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1114 *  - Set FPI0/FPI2_SPECIAL_LRP
1115 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
1116 */
1117#define R300_PFS_INSTR1_0                   0x46C0
1118#       define R300_FPI1_SRC0C_SHIFT             0
1119#       define R300_FPI1_SRC0C_MASK              (31 << 0)
1120#       define R300_FPI1_SRC0C_CONST             (1 << 5)
1121#       define R300_FPI1_SRC1C_SHIFT             6
1122#       define R300_FPI1_SRC1C_MASK              (31 << 6)
1123#       define R300_FPI1_SRC1C_CONST             (1 << 11)
1124#       define R300_FPI1_SRC2C_SHIFT             12
1125#       define R300_FPI1_SRC2C_MASK              (31 << 12)
1126#       define R300_FPI1_SRC2C_CONST             (1 << 17)
1127#       define R300_FPI1_SRC_MASK                0x0003ffff
1128#       define R300_FPI1_DSTC_SHIFT              18
1129#       define R300_FPI1_DSTC_MASK               (31 << 18)
1130#		define R300_FPI1_DSTC_REG_MASK_SHIFT     23
1131#       define R300_FPI1_DSTC_REG_X              (1 << 23)
1132#       define R300_FPI1_DSTC_REG_Y              (1 << 24)
1133#       define R300_FPI1_DSTC_REG_Z              (1 << 25)
1134#		define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT  26
1135#       define R300_FPI1_DSTC_OUTPUT_X           (1 << 26)
1136#       define R300_FPI1_DSTC_OUTPUT_Y           (1 << 27)
1137#       define R300_FPI1_DSTC_OUTPUT_Z           (1 << 28)
1138
1139#define R300_PFS_INSTR3_0                   0x47C0
1140#       define R300_FPI3_SRC0A_SHIFT             0
1141#       define R300_FPI3_SRC0A_MASK              (31 << 0)
1142#       define R300_FPI3_SRC0A_CONST             (1 << 5)
1143#       define R300_FPI3_SRC1A_SHIFT             6
1144#       define R300_FPI3_SRC1A_MASK              (31 << 6)
1145#       define R300_FPI3_SRC1A_CONST             (1 << 11)
1146#       define R300_FPI3_SRC2A_SHIFT             12
1147#       define R300_FPI3_SRC2A_MASK              (31 << 12)
1148#       define R300_FPI3_SRC2A_CONST             (1 << 17)
1149#       define R300_FPI3_SRC_MASK                0x0003ffff
1150#       define R300_FPI3_DSTA_SHIFT              18
1151#       define R300_FPI3_DSTA_MASK               (31 << 18)
1152#       define R300_FPI3_DSTA_REG                (1 << 23)
1153#       define R300_FPI3_DSTA_OUTPUT             (1 << 24)
1154#		define R300_FPI3_DSTA_DEPTH              (1 << 27)
1155
1156#define R300_PFS_INSTR0_0                   0x48C0
1157#       define R300_FPI0_ARGC_SRC0C_XYZ          0
1158#       define R300_FPI0_ARGC_SRC0C_XXX          1
1159#       define R300_FPI0_ARGC_SRC0C_YYY          2
1160#       define R300_FPI0_ARGC_SRC0C_ZZZ          3
1161#       define R300_FPI0_ARGC_SRC1C_XYZ          4
1162#       define R300_FPI0_ARGC_SRC1C_XXX          5
1163#       define R300_FPI0_ARGC_SRC1C_YYY          6
1164#       define R300_FPI0_ARGC_SRC1C_ZZZ          7
1165#       define R300_FPI0_ARGC_SRC2C_XYZ          8
1166#       define R300_FPI0_ARGC_SRC2C_XXX          9
1167#       define R300_FPI0_ARGC_SRC2C_YYY          10
1168#       define R300_FPI0_ARGC_SRC2C_ZZZ          11
1169#       define R300_FPI0_ARGC_SRC0A              12
1170#       define R300_FPI0_ARGC_SRC1A              13
1171#       define R300_FPI0_ARGC_SRC2A              14
1172#       define R300_FPI0_ARGC_SRC1C_LRP          15
1173#       define R300_FPI0_ARGC_ZERO               20
1174#       define R300_FPI0_ARGC_ONE                21
1175	/* GUESS */
1176#       define R300_FPI0_ARGC_HALF               22
1177#       define R300_FPI0_ARGC_SRC0C_YZX          23
1178#       define R300_FPI0_ARGC_SRC1C_YZX          24
1179#       define R300_FPI0_ARGC_SRC2C_YZX          25
1180#       define R300_FPI0_ARGC_SRC0C_ZXY          26
1181#       define R300_FPI0_ARGC_SRC1C_ZXY          27
1182#       define R300_FPI0_ARGC_SRC2C_ZXY          28
1183#       define R300_FPI0_ARGC_SRC0CA_WZY         29
1184#       define R300_FPI0_ARGC_SRC1CA_WZY         30
1185#       define R300_FPI0_ARGC_SRC2CA_WZY         31
1186
1187#       define R300_FPI0_ARG0C_SHIFT             0
1188#       define R300_FPI0_ARG0C_MASK              (31 << 0)
1189#       define R300_FPI0_ARG0C_NEG               (1 << 5)
1190#       define R300_FPI0_ARG0C_ABS               (1 << 6)
1191#       define R300_FPI0_ARG1C_SHIFT             7
1192#       define R300_FPI0_ARG1C_MASK              (31 << 7)
1193#       define R300_FPI0_ARG1C_NEG               (1 << 12)
1194#       define R300_FPI0_ARG1C_ABS               (1 << 13)
1195#       define R300_FPI0_ARG2C_SHIFT             14
1196#       define R300_FPI0_ARG2C_MASK              (31 << 14)
1197#       define R300_FPI0_ARG2C_NEG               (1 << 19)
1198#       define R300_FPI0_ARG2C_ABS               (1 << 20)
1199#       define R300_FPI0_SPECIAL_LRP             (1 << 21)
1200#       define R300_FPI0_OUTC_MAD                (0 << 23)
1201#       define R300_FPI0_OUTC_DP3                (1 << 23)
1202#       define R300_FPI0_OUTC_DP4                (2 << 23)
1203#       define R300_FPI0_OUTC_MIN                (4 << 23)
1204#       define R300_FPI0_OUTC_MAX                (5 << 23)
1205#       define R300_FPI0_OUTC_CMPH               (7 << 23)
1206#       define R300_FPI0_OUTC_CMP                (8 << 23)
1207#       define R300_FPI0_OUTC_FRC                (9 << 23)
1208#       define R300_FPI0_OUTC_REPL_ALPHA         (10 << 23)
1209#       define R300_FPI0_OUTC_SAT                (1 << 30)
1210#       define R300_FPI0_INSERT_NOP              (1 << 31)
1211
1212#define R300_PFS_INSTR2_0                   0x49C0
1213#       define R300_FPI2_ARGA_SRC0C_X            0
1214#       define R300_FPI2_ARGA_SRC0C_Y            1
1215#       define R300_FPI2_ARGA_SRC0C_Z            2
1216#       define R300_FPI2_ARGA_SRC1C_X            3
1217#       define R300_FPI2_ARGA_SRC1C_Y            4
1218#       define R300_FPI2_ARGA_SRC1C_Z            5
1219#       define R300_FPI2_ARGA_SRC2C_X            6
1220#       define R300_FPI2_ARGA_SRC2C_Y            7
1221#       define R300_FPI2_ARGA_SRC2C_Z            8
1222#       define R300_FPI2_ARGA_SRC0A              9
1223#       define R300_FPI2_ARGA_SRC1A              10
1224#       define R300_FPI2_ARGA_SRC2A              11
1225#       define R300_FPI2_ARGA_SRC1A_LRP          15
1226#       define R300_FPI2_ARGA_ZERO               16
1227#       define R300_FPI2_ARGA_ONE                17
1228	/* GUESS */
1229#       define R300_FPI2_ARGA_HALF               18
1230#       define R300_FPI2_ARG0A_SHIFT             0
1231#       define R300_FPI2_ARG0A_MASK              (31 << 0)
1232#       define R300_FPI2_ARG0A_NEG               (1 << 5)
1233	/* GUESS */
1234#	define R300_FPI2_ARG0A_ABS		 (1 << 6)
1235#       define R300_FPI2_ARG1A_SHIFT             7
1236#       define R300_FPI2_ARG1A_MASK              (31 << 7)
1237#       define R300_FPI2_ARG1A_NEG               (1 << 12)
1238	/* GUESS */
1239#	define R300_FPI2_ARG1A_ABS		 (1 << 13)
1240#       define R300_FPI2_ARG2A_SHIFT             14
1241#       define R300_FPI2_ARG2A_MASK              (31 << 14)
1242#       define R300_FPI2_ARG2A_NEG               (1 << 19)
1243	/* GUESS */
1244#	define R300_FPI2_ARG2A_ABS		 (1 << 20)
1245#       define R300_FPI2_SPECIAL_LRP             (1 << 21)
1246#       define R300_FPI2_OUTA_MAD                (0 << 23)
1247#       define R300_FPI2_OUTA_DP4                (1 << 23)
1248#       define R300_FPI2_OUTA_MIN                (2 << 23)
1249#       define R300_FPI2_OUTA_MAX                (3 << 23)
1250#       define R300_FPI2_OUTA_CMP                (6 << 23)
1251#       define R300_FPI2_OUTA_FRC                (7 << 23)
1252#       define R300_FPI2_OUTA_EX2                (8 << 23)
1253#       define R300_FPI2_OUTA_LG2                (9 << 23)
1254#       define R300_FPI2_OUTA_RCP                (10 << 23)
1255#       define R300_FPI2_OUTA_RSQ                (11 << 23)
1256#       define R300_FPI2_OUTA_SAT                (1 << 30)
1257#       define R300_FPI2_UNKNOWN_31              (1 << 31)
1258/* END: Fragment program instruction set */
1259
1260/* Fog state and color */
1261#define R300_RE_FOG_STATE                   0x4BC0
1262#       define R300_FOG_ENABLE                   (1 << 0)
1263#	define R300_FOG_MODE_LINEAR              (0 << 1)
1264#	define R300_FOG_MODE_EXP                 (1 << 1)
1265#	define R300_FOG_MODE_EXP2                (2 << 1)
1266#	define R300_FOG_MODE_MASK                (3 << 1)
1267#define R300_FOG_COLOR_R                    0x4BC8
1268#define R300_FOG_COLOR_G                    0x4BCC
1269#define R300_FOG_COLOR_B                    0x4BD0
1270
1271#define R300_PP_ALPHA_TEST                  0x4BD4
1272#       define R300_REF_ALPHA_MASK               0x000000ff
1273#       define R300_ALPHA_TEST_FAIL              (0 << 8)
1274#       define R300_ALPHA_TEST_LESS              (1 << 8)
1275#       define R300_ALPHA_TEST_LEQUAL            (3 << 8)
1276#       define R300_ALPHA_TEST_EQUAL             (2 << 8)
1277#       define R300_ALPHA_TEST_GEQUAL            (6 << 8)
1278#       define R300_ALPHA_TEST_GREATER           (4 << 8)
1279#       define R300_ALPHA_TEST_NEQUAL            (5 << 8)
1280#       define R300_ALPHA_TEST_PASS              (7 << 8)
1281#       define R300_ALPHA_TEST_OP_MASK           (7 << 8)
1282#       define R300_ALPHA_TEST_ENABLE            (1 << 11)
1283
1284/* gap */
1285
1286/* Fragment program parameters in 7.16 floating point */
1287#define R300_PFS_PARAM_0_X                  0x4C00
1288#define R300_PFS_PARAM_0_Y                  0x4C04
1289#define R300_PFS_PARAM_0_Z                  0x4C08
1290#define R300_PFS_PARAM_0_W                  0x4C0C
1291/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
1292#define R300_PFS_PARAM_31_X                 0x4DF0
1293#define R300_PFS_PARAM_31_Y                 0x4DF4
1294#define R300_PFS_PARAM_31_Z                 0x4DF8
1295#define R300_PFS_PARAM_31_W                 0x4DFC
1296
1297/* Notes:
1298 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
1299 *   the application
1300 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
1301 *    are set to the same
1302 *   function (both registers are always set up completely in any case)
1303 * - Most blend flags are simply copied from R200 and not tested yet
1304 */
1305#define R300_RB3D_CBLEND                    0x4E04
1306#define R300_RB3D_ABLEND                    0x4E08
1307/* the following only appear in CBLEND */
1308#       define R300_BLEND_ENABLE                     (1 << 0)
1309#       define R300_BLEND_UNKNOWN                    (3 << 1)
1310#       define R300_BLEND_NO_SEPARATE                (1 << 3)
1311/* the following are shared between CBLEND and ABLEND */
1312#       define R300_FCN_MASK                         (3  << 12)
1313#       define R300_COMB_FCN_ADD_CLAMP               (0  << 12)
1314#       define R300_COMB_FCN_ADD_NOCLAMP             (1  << 12)
1315#       define R300_COMB_FCN_SUB_CLAMP               (2  << 12)
1316#       define R300_COMB_FCN_SUB_NOCLAMP             (3  << 12)
1317#       define R300_COMB_FCN_MIN                     (4  << 12)
1318#       define R300_COMB_FCN_MAX                     (5  << 12)
1319#       define R300_COMB_FCN_RSUB_CLAMP              (6  << 12)
1320#       define R300_COMB_FCN_RSUB_NOCLAMP            (7  << 12)
1321#       define R300_BLEND_GL_ZERO                    (32)
1322#       define R300_BLEND_GL_ONE                     (33)
1323#       define R300_BLEND_GL_SRC_COLOR               (34)
1324#       define R300_BLEND_GL_ONE_MINUS_SRC_COLOR     (35)
1325#       define R300_BLEND_GL_DST_COLOR               (36)
1326#       define R300_BLEND_GL_ONE_MINUS_DST_COLOR     (37)
1327#       define R300_BLEND_GL_SRC_ALPHA               (38)
1328#       define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA     (39)
1329#       define R300_BLEND_GL_DST_ALPHA               (40)
1330#       define R300_BLEND_GL_ONE_MINUS_DST_ALPHA     (41)
1331#       define R300_BLEND_GL_SRC_ALPHA_SATURATE      (42)
1332#       define R300_BLEND_GL_CONST_COLOR             (43)
1333#       define R300_BLEND_GL_ONE_MINUS_CONST_COLOR   (44)
1334#       define R300_BLEND_GL_CONST_ALPHA             (45)
1335#       define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA   (46)
1336#       define R300_BLEND_MASK                       (63)
1337#       define R300_SRC_BLEND_SHIFT                  (16)
1338#       define R300_DST_BLEND_SHIFT                  (24)
1339#define R300_RB3D_BLEND_COLOR               0x4E10
1340#define R300_RB3D_COLORMASK                 0x4E0C
1341#       define R300_COLORMASK0_B                 (1<<0)
1342#       define R300_COLORMASK0_G                 (1<<1)
1343#       define R300_COLORMASK0_R                 (1<<2)
1344#       define R300_COLORMASK0_A                 (1<<3)
1345
1346/* gap */
1347
1348#define R300_RB3D_COLOROFFSET0              0x4E28
1349#       define R300_COLOROFFSET_MASK             0xFFFFFFF0 /* GUESS */
1350#define R300_RB3D_COLOROFFSET1              0x4E2C /* GUESS */
1351#define R300_RB3D_COLOROFFSET2              0x4E30 /* GUESS */
1352#define R300_RB3D_COLOROFFSET3              0x4E34 /* GUESS */
1353
1354/* gap */
1355
1356/* Bit 16: Larger tiles
1357 * Bit 17: 4x2 tiles
1358 * Bit 18: Extremely weird tile like, but some pixels duplicated?
1359 */
1360#define R300_RB3D_COLORPITCH0               0x4E38
1361#       define R300_COLORPITCH_MASK              0x00001FF8 /* GUESS */
1362#       define R300_COLOR_TILE_ENABLE            (1 << 16) /* GUESS */
1363#       define R300_COLOR_MICROTILE_ENABLE       (1 << 17) /* GUESS */
1364#       define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17)
1365#       define R300_COLOR_ENDIAN_NO_SWAP         (0 << 18) /* GUESS */
1366#       define R300_COLOR_ENDIAN_WORD_SWAP       (1 << 18) /* GUESS */
1367#       define R300_COLOR_ENDIAN_DWORD_SWAP      (2 << 18) /* GUESS */
1368#       define R300_COLOR_FORMAT_RGB565          (2 << 22)
1369#       define R300_COLOR_FORMAT_ARGB8888        (3 << 22)
1370#define R300_RB3D_COLORPITCH1               0x4E3C /* GUESS */
1371#define R300_RB3D_COLORPITCH2               0x4E40 /* GUESS */
1372#define R300_RB3D_COLORPITCH3               0x4E44 /* GUESS */
1373
1374#define R300_RB3D_AARESOLVE_OFFSET          0x4E80
1375#define R300_RB3D_AARESOLVE_PITCH           0x4E84
1376#define R300_RB3D_AARESOLVE_CTL             0x4E88
1377/* gap */
1378
1379/* Guess by Vladimir.
1380 * Set to 0A before 3D operations, set to 02 afterwards.
1381 */
1382/*#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C*/
1383#       define R300_RB3D_DSTCACHE_UNKNOWN_02             0x00000002
1384#       define R300_RB3D_DSTCACHE_UNKNOWN_0A             0x0000000A
1385
1386/* gap */
1387/* There seems to be no "write only" setting, so use Z-test = ALWAYS
1388 * for this.
1389 * Bit (1<<8) is the "test" bit. so plain write is 6  - vd
1390 */
1391#define R300_ZB_CNTL                             0x4F00
1392#	define R300_STENCIL_ENABLE		 (1 << 0)
1393#	define R300_Z_ENABLE		         (1 << 1)
1394#	define R300_Z_WRITE_ENABLE		 (1 << 2)
1395#	define R300_Z_SIGNED_COMPARE		 (1 << 3)
1396#	define R300_STENCIL_FRONT_BACK		 (1 << 4)
1397
1398#define R300_ZB_ZSTENCILCNTL                   0x4f04
1399	/* functions */
1400#	define R300_ZS_NEVER			0
1401#	define R300_ZS_LESS			1
1402#	define R300_ZS_LEQUAL			2
1403#	define R300_ZS_EQUAL			3
1404#	define R300_ZS_GEQUAL			4
1405#	define R300_ZS_GREATER			5
1406#	define R300_ZS_NOTEQUAL			6
1407#	define R300_ZS_ALWAYS			7
1408#       define R300_ZS_MASK                     7
1409	/* operations */
1410#	define R300_ZS_KEEP			0
1411#	define R300_ZS_ZERO			1
1412#	define R300_ZS_REPLACE			2
1413#	define R300_ZS_INCR			3
1414#	define R300_ZS_DECR			4
1415#	define R300_ZS_INVERT			5
1416#	define R300_ZS_INCR_WRAP		6
1417#	define R300_ZS_DECR_WRAP		7
1418#	define R300_Z_FUNC_SHIFT		0
1419	/* front and back refer to operations done for front
1420	   and back faces, i.e. separate stencil function support */
1421#	define R300_S_FRONT_FUNC_SHIFT	        3
1422#	define R300_S_FRONT_SFAIL_OP_SHIFT	6
1423#	define R300_S_FRONT_ZPASS_OP_SHIFT	9
1424#	define R300_S_FRONT_ZFAIL_OP_SHIFT      12
1425#	define R300_S_BACK_FUNC_SHIFT           15
1426#	define R300_S_BACK_SFAIL_OP_SHIFT       18
1427#	define R300_S_BACK_ZPASS_OP_SHIFT       21
1428#	define R300_S_BACK_ZFAIL_OP_SHIFT       24
1429
1430#define R300_ZB_STENCILREFMASK                        0x4f08
1431#	define R300_STENCILREF_SHIFT       0
1432#	define R300_STENCILREF_MASK        0x000000ff
1433#	define R300_STENCILMASK_SHIFT      8
1434#	define R300_STENCILMASK_MASK       0x0000ff00
1435#	define R300_STENCILWRITEMASK_SHIFT 16
1436#	define R300_STENCILWRITEMASK_MASK  0x00ff0000
1437
1438/* gap */
1439
1440#define R300_ZB_FORMAT                             0x4f10
1441#	define R300_DEPTHFORMAT_16BIT_INT_Z   (0 << 0)
1442#	define R300_DEPTHFORMAT_16BIT_13E3    (1 << 0)
1443#	define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL   (2 << 0)
1444/* reserved up to (15 << 0) */
1445#	define R300_INVERT_13E3_LEADING_ONES  (0 << 4)
1446#	define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1447
1448#define R300_ZB_ZTOP                             0x4F14
1449#	define R300_ZTOP_DISABLE                 (0 << 0)
1450#	define R300_ZTOP_ENABLE                  (1 << 0)
1451
1452/* gap */
1453
1454#define R300_ZB_ZCACHE_CTLSTAT            0x4f18
1455#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT      (0 << 0)
1456#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1457#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT       (0 << 1)
1458#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE            (1 << 1)
1459#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE            (0 << 31)
1460#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY            (1 << 31)
1461
1462#define R300_ZB_BW_CNTL                     0x4f1c
1463#	define R300_HIZ_DISABLE                              (0 << 0)
1464#	define R300_HIZ_ENABLE                               (1 << 0)
1465#	define R300_HIZ_MIN                                  (0 << 1)
1466#	define R300_HIZ_MAX                                  (1 << 1)
1467#	define R300_FAST_FILL_DISABLE                        (0 << 2)
1468#	define R300_FAST_FILL_ENABLE                         (1 << 2)
1469#	define R300_RD_COMP_DISABLE                          (0 << 3)
1470#	define R300_RD_COMP_ENABLE                           (1 << 3)
1471#	define R300_WR_COMP_DISABLE                          (0 << 4)
1472#	define R300_WR_COMP_ENABLE                           (1 << 4)
1473#	define R300_ZB_CB_CLEAR_RMW                          (0 << 5)
1474#	define R300_ZB_CB_CLEAR_CACHE_LINEAR                 (1 << 5)
1475#	define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE   (0 << 6)
1476#	define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE    (1 << 6)
1477
1478#	define R500_ZEQUAL_OPTIMIZE_ENABLE                   (0 << 7)
1479#	define R500_ZEQUAL_OPTIMIZE_DISABLE                  (1 << 7)
1480#	define R500_SEQUAL_OPTIMIZE_ENABLE                   (0 << 8)
1481#	define R500_SEQUAL_OPTIMIZE_DISABLE                  (1 << 8)
1482
1483#	define R500_BMASK_ENABLE                             (0 << 10)
1484#	define R500_BMASK_DISABLE                            (1 << 10)
1485#	define R500_HIZ_EQUAL_REJECT_DISABLE                 (0 << 11)
1486#	define R500_HIZ_EQUAL_REJECT_ENABLE                  (1 << 11)
1487#	define R500_HIZ_FP_EXP_BITS_DISABLE                  (0 << 12)
1488#	define R500_HIZ_FP_EXP_BITS_1                        (1 << 12)
1489#	define R500_HIZ_FP_EXP_BITS_2                        (2 << 12)
1490#	define R500_HIZ_FP_EXP_BITS_3                        (3 << 12)
1491#	define R500_HIZ_FP_EXP_BITS_4                        (4 << 12)
1492#	define R500_HIZ_FP_EXP_BITS_5                        (5 << 12)
1493#	define R500_HIZ_FP_INVERT_LEADING_ONES               (0 << 15)
1494#	define R500_HIZ_FP_INVERT_LEADING_ZEROS              (1 << 15)
1495#	define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE      (0 << 16)
1496#	define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE     (1 << 16)
1497#	define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE           (0 << 17)
1498#	define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE          (1 << 17)
1499#	define R500_PEQ_PACKING_DISABLE                      (0 << 18)
1500#	define R500_PEQ_PACKING_ENABLE                       (1 << 18)
1501#	define R500_COVERED_PTR_MASKING_DISABLE              (0 << 18)
1502#	define R500_COVERED_PTR_MASKING_ENABLE               (1 << 18)
1503
1504
1505/* gap */
1506
1507/* Z Buffer Address Offset.
1508 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1509 */
1510#define R300_ZB_DEPTHOFFSET               0x4f20
1511
1512/* Z Buffer Pitch and Endian Control */
1513#define R300_ZB_DEPTHPITCH                0x4f24
1514#       define R300_DEPTHPITCH_MASK              0x00003FFC
1515#       define R300_DEPTHMACROTILE_DISABLE      (0 << 16)
1516#       define R300_DEPTHMACROTILE_ENABLE       (1 << 16)
1517#       define R300_DEPTHMICROTILE_LINEAR       (0 << 17)
1518#       define R300_DEPTHMICROTILE_TILED        (1 << 17)
1519#       define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1520#       define R300_DEPTHENDIAN_NO_SWAP         (0 << 18)
1521#       define R300_DEPTHENDIAN_WORD_SWAP       (1 << 18)
1522#       define R300_DEPTHENDIAN_DWORD_SWAP      (2 << 18)
1523#       define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1524
1525/* Z Buffer Clear Value */
1526#define R300_ZB_DEPTHCLEARVALUE                  0x4f28
1527
1528#define R300_ZB_ZMASK_OFFSET			 0x4f30
1529#define R300_ZB_ZMASK_PITCH			 0x4f34
1530#define R300_ZB_ZMASK_WRINDEX			 0x4f38
1531#define R300_ZB_ZMASK_DWORD			 0x4f3c
1532#define R300_ZB_ZMASK_RDINDEX			 0x4f40
1533
1534/* Hierarchical Z Memory Offset */
1535#define R300_ZB_HIZ_OFFSET                       0x4f44
1536
1537/* Hierarchical Z Write Index */
1538#define R300_ZB_HIZ_WRINDEX                      0x4f48
1539
1540/* Hierarchical Z Data */
1541#define R300_ZB_HIZ_DWORD                        0x4f4c
1542
1543/* Hierarchical Z Read Index */
1544#define R300_ZB_HIZ_RDINDEX                      0x4f50
1545
1546/* Hierarchical Z Pitch */
1547#define R300_ZB_HIZ_PITCH                        0x4f54
1548
1549/* Z Buffer Z Pass Counter Data */
1550#define R300_ZB_ZPASS_DATA                       0x4f58
1551
1552/* Z Buffer Z Pass Counter Address */
1553#define R300_ZB_ZPASS_ADDR                       0x4f5c
1554
1555/* Depth buffer X and Y coordinate offset */
1556#define R300_ZB_DEPTHXY_OFFSET                   0x4f60
1557#	define R300_DEPTHX_OFFSET_SHIFT  1
1558#	define R300_DEPTHX_OFFSET_MASK   0x000007FE
1559#	define R300_DEPTHY_OFFSET_SHIFT  17
1560#	define R300_DEPTHY_OFFSET_MASK   0x07FE0000
1561
1562/* Sets the fifo sizes */
1563#define R500_ZB_FIFO_SIZE                        0x4fd0
1564#	define R500_OP_FIFO_SIZE_FULL   (0 << 0)
1565#	define R500_OP_FIFO_SIZE_HALF   (1 << 0)
1566#	define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1567#	define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1568
1569/* Stencil Reference Value and Mask for backfacing quads */
1570/* R300_ZB_STENCILREFMASK handles front face */
1571#define R500_ZB_STENCILREFMASK_BF                0x4fd4
1572#	define R500_STENCILREF_SHIFT       0
1573#	define R500_STENCILREF_MASK        0x000000ff
1574#	define R500_STENCILMASK_SHIFT      8
1575#	define R500_STENCILMASK_MASK       0x0000ff00
1576#	define R500_STENCILWRITEMASK_SHIFT 16
1577#	define R500_STENCILWRITEMASK_MASK  0x00ff0000
1578
1579/* BEGIN: Vertex program instruction set */
1580
1581/* Every instruction is four dwords long:
1582 *  DWORD 0: output and opcode
1583 *  DWORD 1: first argument
1584 *  DWORD 2: second argument
1585 *  DWORD 3: third argument
1586 *
1587 * Notes:
1588 *  - ABS r, a is implemented as MAX r, a, -a
1589 *  - MOV is implemented as ADD to zero
1590 *  - XPD is implemented as MUL + MAD
1591 *  - FLR is implemented as FRC + ADD
1592 *  - apparently, fglrx tries to schedule instructions so that there is at
1593 *    least one instruction between the write to a temporary and the first
1594 *    read from said temporary; however, violations of this scheduling are
1595 *    allowed
1596 *  - register indices seem to be unrelated with OpenGL aliasing to
1597 *    conventional state
1598 *  - only one attribute and one parameter can be loaded at a time; however,
1599 *    the same attribute/parameter can be used for more than one argument
1600 *  - the second software argument for POW is the third hardware argument
1601 *    (no idea why)
1602 *  - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1603 *
1604 * There is some magic surrounding LIT:
1605 *   The single argument is replicated across all three inputs, but swizzled:
1606 *     First argument: xyzy
1607 *     Second argument: xyzx
1608 *     Third argument: xyzw
1609 *   Whenever the result is used later in the fragment program, fglrx forces
1610 *   x and w to be 1.0 in the input selection; I don't know whether this is
1611 *   strictly necessary
1612 */
1613#define R300_VPI_OUT_OP_DOT                     (1 << 0)
1614#define R300_VPI_OUT_OP_MUL                     (2 << 0)
1615#define R300_VPI_OUT_OP_ADD                     (3 << 0)
1616#define R300_VPI_OUT_OP_MAD                     (4 << 0)
1617#define R300_VPI_OUT_OP_DST                     (5 << 0)
1618#define R300_VPI_OUT_OP_FRC                     (6 << 0)
1619#define R300_VPI_OUT_OP_MAX                     (7 << 0)
1620#define R300_VPI_OUT_OP_MIN                     (8 << 0)
1621#define R300_VPI_OUT_OP_SGE                     (9 << 0)
1622#define R300_VPI_OUT_OP_SLT                     (10 << 0)
1623	/* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */
1624#define R300_VPI_OUT_OP_UNK12                   (12 << 0)
1625#define R300_VPI_OUT_OP_ARL                     (13 << 0)
1626#define R300_VPI_OUT_OP_EXP                     (65 << 0)
1627#define R300_VPI_OUT_OP_LOG                     (66 << 0)
1628	/* Used in fog computations, scalar(scalar) */
1629#define R300_VPI_OUT_OP_UNK67                   (67 << 0)
1630#define R300_VPI_OUT_OP_LIT                     (68 << 0)
1631#define R300_VPI_OUT_OP_POW                     (69 << 0)
1632#define R300_VPI_OUT_OP_RCP                     (70 << 0)
1633#define R300_VPI_OUT_OP_RSQ                     (72 << 0)
1634	/* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */
1635#define R300_VPI_OUT_OP_UNK73                   (73 << 0)
1636#define R300_VPI_OUT_OP_EX2                     (75 << 0)
1637#define R300_VPI_OUT_OP_LG2                     (76 << 0)
1638#define R300_VPI_OUT_OP_MAD_2                   (128 << 0)
1639	/* all temps, vector(scalar, vector, vector) */
1640#define R300_VPI_OUT_OP_UNK129                  (129 << 0)
1641
1642#define R300_VPI_OUT_REG_CLASS_TEMPORARY        (0 << 8)
1643#define R300_VPI_OUT_REG_CLASS_ADDR             (1 << 8)
1644#define R300_VPI_OUT_REG_CLASS_RESULT           (2 << 8)
1645#define R300_VPI_OUT_REG_CLASS_MASK             (31 << 8)
1646
1647#define R300_VPI_OUT_REG_INDEX_SHIFT            13
1648	/* GUESS based on fglrx native limits */
1649#define R300_VPI_OUT_REG_INDEX_MASK             (31 << 13)
1650
1651#define R300_VPI_OUT_WRITE_X                    (1 << 20)
1652#define R300_VPI_OUT_WRITE_Y                    (1 << 21)
1653#define R300_VPI_OUT_WRITE_Z                    (1 << 22)
1654#define R300_VPI_OUT_WRITE_W                    (1 << 23)
1655
1656#define R300_VPI_IN_REG_CLASS_TEMPORARY         (0 << 0)
1657#define R300_VPI_IN_REG_CLASS_ATTRIBUTE         (1 << 0)
1658#define R300_VPI_IN_REG_CLASS_PARAMETER         (2 << 0)
1659#define R300_VPI_IN_REG_CLASS_NONE              (9 << 0)
1660#define R300_VPI_IN_REG_CLASS_MASK              (31 << 0)
1661
1662#define R300_VPI_IN_REG_INDEX_SHIFT             5
1663	/* GUESS based on fglrx native limits */
1664#define R300_VPI_IN_REG_INDEX_MASK              (255 << 5)
1665
1666/* The R300 can select components from the input register arbitrarily.
1667 * Use the following constants, shifted by the component shift you
1668 * want to select
1669 */
1670#define R300_VPI_IN_SELECT_X    0
1671#define R300_VPI_IN_SELECT_Y    1
1672#define R300_VPI_IN_SELECT_Z    2
1673#define R300_VPI_IN_SELECT_W    3
1674#define R300_VPI_IN_SELECT_ZERO 4
1675#define R300_VPI_IN_SELECT_ONE  5
1676#define R300_VPI_IN_SELECT_MASK 7
1677
1678#define R300_VPI_IN_X_SHIFT                     13
1679#define R300_VPI_IN_Y_SHIFT                     16
1680#define R300_VPI_IN_Z_SHIFT                     19
1681#define R300_VPI_IN_W_SHIFT                     22
1682
1683#define R300_VPI_IN_NEG_X                       (1 << 25)
1684#define R300_VPI_IN_NEG_Y                       (1 << 26)
1685#define R300_VPI_IN_NEG_Z                       (1 << 27)
1686#define R300_VPI_IN_NEG_W                       (1 << 28)
1687/* END: Vertex program instruction set */
1688
1689/* BEGIN: Packet 3 commands */
1690
1691/* A primitive emission dword. */
1692#define R300_PRIM_TYPE_NONE                     (0 << 0)
1693#define R300_PRIM_TYPE_POINT                    (1 << 0)
1694#define R300_PRIM_TYPE_LINE                     (2 << 0)
1695#define R300_PRIM_TYPE_LINE_STRIP               (3 << 0)
1696#define R300_PRIM_TYPE_TRI_LIST                 (4 << 0)
1697#define R300_PRIM_TYPE_TRI_FAN                  (5 << 0)
1698#define R300_PRIM_TYPE_TRI_STRIP                (6 << 0)
1699#define R300_PRIM_TYPE_TRI_TYPE2                (7 << 0)
1700#define R300_PRIM_TYPE_RECT_LIST                (8 << 0)
1701#define R300_PRIM_TYPE_3VRT_POINT_LIST          (9 << 0)
1702#define R300_PRIM_TYPE_3VRT_LINE_LIST           (10 << 0)
1703	/* GUESS (based on r200) */
1704#define R300_PRIM_TYPE_POINT_SPRITES            (11 << 0)
1705#define R300_PRIM_TYPE_LINE_LOOP                (12 << 0)
1706#define R300_PRIM_TYPE_QUADS                    (13 << 0)
1707#define R300_PRIM_TYPE_QUAD_STRIP               (14 << 0)
1708#define R300_PRIM_TYPE_POLYGON                  (15 << 0)
1709#define R300_PRIM_TYPE_MASK                     0xF
1710#define R300_PRIM_WALK_IND                      (1 << 4)
1711#define R300_PRIM_WALK_LIST                     (2 << 4)
1712#define R300_PRIM_WALK_RING                     (3 << 4)
1713#define R300_PRIM_WALK_MASK                     (3 << 4)
1714	/* GUESS (based on r200) */
1715#define R300_PRIM_COLOR_ORDER_BGRA              (0 << 6)
1716#define R300_PRIM_COLOR_ORDER_RGBA              (1 << 6)
1717#define R300_PRIM_NUM_VERTICES_SHIFT            16
1718#define R300_PRIM_NUM_VERTICES_MASK             0xffff
1719
1720/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
1721 * Two parameter dwords:
1722 * 0. The first parameter appears to be always 0
1723 * 1. The second parameter is a standard primitive emission dword.
1724 */
1725#define R300_PACKET3_3D_DRAW_VBUF           0x00002800
1726
1727/* Specify the full set of vertex arrays as (address, stride).
1728 * The first parameter is the number of vertex arrays specified.
1729 * The rest of the command is a variable length list of blocks, where
1730 * each block is three dwords long and specifies two arrays.
1731 * The first dword of a block is split into two words, the lower significant
1732 * word refers to the first array, the more significant word to the second
1733 * array in the block.
1734 * The low byte of each word contains the size of an array entry in dwords,
1735 * the high byte contains the stride of the array.
1736 * The second dword of a block contains the pointer to the first array,
1737 * the third dword of a block contains the pointer to the second array.
1738 * Note that if the total number of arrays is odd, the third dword of
1739 * the last block is omitted.
1740 */
1741#define R300_PACKET3_3D_LOAD_VBPNTR         0x00002F00
1742
1743#define R300_PACKET3_INDX_BUFFER            0x00003300
1744#    define R300_EB_UNK1_SHIFT                      24
1745#    define R300_EB_UNK1                    (0x80<<24)
1746#    define R300_EB_UNK2                        0x0810
1747#define R300_PACKET3_3D_DRAW_VBUF_2         0x00003400
1748#define R300_PACKET3_3D_DRAW_INDX_2         0x00003600
1749
1750/* END: Packet 3 commands */
1751
1752
1753/* Color formats for 2d packets
1754 */
1755#define R300_CP_COLOR_FORMAT_CI8	2
1756#define R300_CP_COLOR_FORMAT_ARGB1555	3
1757#define R300_CP_COLOR_FORMAT_RGB565	4
1758#define R300_CP_COLOR_FORMAT_ARGB8888	6
1759#define R300_CP_COLOR_FORMAT_RGB332	7
1760#define R300_CP_COLOR_FORMAT_RGB8	9
1761#define R300_CP_COLOR_FORMAT_ARGB4444	15
1762
1763/*
1764 * CP type-3 packets
1765 */
1766#define R300_CP_CMD_BITBLT_MULTI	0xC0009B00
1767
1768#define R500_VAP_INDEX_OFFSET		0x208c
1769
1770#define R500_GA_US_VECTOR_INDEX         0x4250
1771#define R500_GA_US_VECTOR_DATA          0x4254
1772
1773#define R500_RS_IP_0                    0x4074
1774#define R500_RS_INST_0                  0x4320
1775
1776#define R500_US_CONFIG                  0x4600
1777
1778#define R500_US_FC_CTRL			0x4624
1779#define R500_US_CODE_ADDR		0x4630
1780
1781#define R500_RB3D_COLOR_CLEAR_VALUE_AR  0x46c0
1782#define R500_RB3D_CONSTANT_COLOR_AR     0x4ef8
1783
1784#define R300_SU_REG_DEST                0x42c8
1785#define RV530_FG_ZBREG_DEST             0x4be8
1786#define R300_ZB_ZPASS_DATA              0x4f58
1787#define R300_ZB_ZPASS_ADDR              0x4f5c
1788
1789#endif /* _R300_REG_H */
1790