radeon_ring.c revision 6cdf65855cf884712532fc72770baaef7bdf1b9a
1771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 2771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 6771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 13771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * all copies or substantial portions of the Software. 15771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 16771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 24771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Authors: Dave Airlie 25771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Alex Deucher 26771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Jerome Glisse 27771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 28771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include <linux/seq_file.h> 29771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "drmP.h" 30771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon_drm.h" 31771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon_reg.h" 32771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon.h" 33771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "atom.h" 34771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 35771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_debugfs_ib_init(struct radeon_device *rdev); 36771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 37771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 38771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * IB. 39771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 40771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) 41771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 42771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_fence *fence; 43771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *nib; 44771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned long i; 45771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r = 0; 46771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 47771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = NULL; 48771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_create(rdev, &fence); 49771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 50771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("failed to create fence for new IB\n"); 51771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 52771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 53771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 54771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 55771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (i < RADEON_IB_POOL_SIZE) { 56771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse set_bit(i, rdev->ib_pool.alloc_bm); 57771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].length_dw = 0; 58771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = &rdev->ib_pool.ibs[i]; 59771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse goto out; 60771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 61771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (list_empty(&rdev->ib_pool.scheduled_ibs)) { 62771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* we go do nothings here */ 63771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("all IB allocated none scheduled.\n"); 64771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = -EINVAL; 65771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse goto out; 66771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 67771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* get the first ib on the scheduled list */ 68771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse nib = list_entry(rdev->ib_pool.scheduled_ibs.next, 69771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib, list); 70771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (nib->fence == NULL) { 71771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* we go do nothings here */ 72771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); 73771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = -EINVAL; 74771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse goto out; 75771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 76771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_wait(nib->fence, false); 77771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 78771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, 79771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (unsigned long)nib->gpu_addr, nib->length_dw); 80771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); 81771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse goto out; 82771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 83771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_unref(&nib->fence); 84771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse nib->length_dw = 0; 85771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse list_del(&nib->list); 86771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse INIT_LIST_HEAD(&nib->list); 87771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = nib; 88771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseout: 89771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 90771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 91771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_unref(&fence); 92771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } else { 93771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (*ib)->fence = fence; 94771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 95771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 96771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 97771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 98771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) 99771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 100771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *tmp = *ib; 101771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 102771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = NULL; 103771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (tmp == NULL) { 104771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return; 105771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 106771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 107771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { 108771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* IB is scheduled & not signaled don't do anythings */ 109771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 110771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return; 111771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 112771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse list_del(&tmp->list); 113771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse INIT_LIST_HEAD(&tmp->list); 114771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (tmp->fence) { 115771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_unref(&tmp->fence); 116771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 117771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse tmp->length_dw = 0; 118771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); 119771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 120771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 121771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 122771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) 123771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 124771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse while ((ib->length_dw & rdev->cp.align_mask)) { 125771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[ib->length_dw++] = PACKET2(0); 126771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 127771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 128771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 129771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 130771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 131771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r = 0; 132771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 133771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 134771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ib_align(rdev, ib); 135771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!ib->length_dw || !rdev->cp.ready) { 136771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* TODO: Nothings in the ib we should report. */ 137771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 138771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); 139771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return -EINVAL; 140771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 1416cdf65855cf884712532fc72770baaef7bdf1b9aDave Airlie /* 64 dwords should be enough for fence too */ 142771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_ring_lock(rdev, 64); 143771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 144771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); 145771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 146771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 147771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 148771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 149771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, ib->gpu_addr); 150771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, ib->length_dw); 151771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_emit(rdev, ib->fence); 152771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_unlock_commit(rdev); 153771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); 154771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 155771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 156771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 157771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 158771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_pool_init(struct radeon_device *rdev) 159771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 160771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse void *ptr; 161771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint64_t gpu_addr; 162771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int i; 163771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r = 0; 164771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 165771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Allocate 1M object buffer */ 166771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); 167771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, 168771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse true, RADEON_GEM_DOMAIN_GTT, 169771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse false, &rdev->ib_pool.robj); 170771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 171771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to ib pool (%d).\n", r); 172771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 173771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 174771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); 175771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 176771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); 177771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 178771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 179771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_kmap(rdev->ib_pool.robj, &ptr); 180771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 181771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); 182771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 183771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 184771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 185771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned offset; 186771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 187771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse offset = i * 64 * 1024; 188771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; 189771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].ptr = ptr + offset; 190771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].idx = i; 191771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].length_dw = 0; 192771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); 193771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 194771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 195771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ready = true; 196771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_INFO("radeon: ib pool ready.\n"); 197771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (radeon_debugfs_ib_init(rdev)) { 198771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("Failed to register debugfs file for IB !\n"); 199771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 200771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 201771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 202771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 203771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ib_pool_fini(struct radeon_device *rdev) 204771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 205771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!rdev->ib_pool.ready) { 206771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return; 207771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 208771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 209771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); 210771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (rdev->ib_pool.robj) { 211771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_object_kunmap(rdev->ib_pool.robj); 212771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_object_unref(&rdev->ib_pool.robj); 213771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.robj = NULL; 214771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 215771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 216771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 217771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 218771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_test(struct radeon_device *rdev) 219771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 220771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *ib; 221771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint32_t scratch; 222771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint32_t tmp = 0; 223771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 224771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 225771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 226771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_scratch_get(rdev, &scratch); 227771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 228771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 229771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 230771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 231771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse WREG32(scratch, 0xCAFEDEAD); 232771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_ib_get(rdev, &ib); 233771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 234771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 235771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 236771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[0] = PACKET0(scratch, 0); 237771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[1] = 0xDEADBEEF; 238771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[2] = PACKET2(0); 239771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[3] = PACKET2(0); 240771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[4] = PACKET2(0); 241771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[5] = PACKET2(0); 242771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[6] = PACKET2(0); 243771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->ptr[7] = PACKET2(0); 244771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ib->length_dw = 8; 245771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_ib_schedule(rdev, ib); 246771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 247771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_scratch_free(rdev, scratch); 248771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ib_free(rdev, &ib); 249771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 250771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 251771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_wait(ib->fence, false); 252771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 253771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 254771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 255771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 256771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse tmp = RREG32(scratch); 257771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (tmp == 0xDEADBEEF) { 258771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse break; 259771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 260771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_UDELAY(1); 261771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 262771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (i < rdev->usec_timeout) { 263771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_INFO("ib test succeeded in %u usecs\n", i); 264771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } else { 265771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", 266771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse scratch, tmp); 267771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = -EINVAL; 268771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 269771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_scratch_free(rdev, scratch); 270771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ib_free(rdev, &ib); 271771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 272771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 273771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 274771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 275771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 276771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Ring. 277771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 278771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_free_size(struct radeon_device *rdev) 279771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 280771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 281771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* This works because ring_size is a power of 2 */ 282771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); 283771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw -= rdev->cp.wptr; 284771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; 285771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!rdev->cp.ring_free_dw) { 286771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 287771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 288771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 289771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 290771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) 291771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 292771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 293771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 294771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Align requested size with padding so unlock_commit can 295771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * pad safely */ 296771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; 297771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->cp.mutex); 298771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse while (ndw > (rdev->cp.ring_free_dw - 1)) { 299771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_free_size(rdev); 300771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (ndw < rdev->cp.ring_free_dw) { 301771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse break; 302771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 303771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_wait_next(rdev); 304771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 305771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 306771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 307771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 308771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 309771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.count_dw = ndw; 310771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.wptr_old = rdev->cp.wptr; 311771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 312771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 313771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 314771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_unlock_commit(struct radeon_device *rdev) 315771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 316771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned count_dw_pad; 317771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 318771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 319771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* We pad to match fetch size */ 320771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse count_dw_pad = (rdev->cp.align_mask + 1) - 321771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (rdev->cp.wptr & rdev->cp.align_mask); 322771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < count_dw_pad; i++) { 323771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, PACKET2(0)); 324771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 325771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_MEMORYBARRIER(); 326771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 327771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (void)RREG32(RADEON_CP_RB_WPTR); 328771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 329771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 330771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 331771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_unlock_undo(struct radeon_device *rdev) 332771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 333771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.wptr = rdev->cp.wptr_old; 334771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 335771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 336771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 337771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ring_test(struct radeon_device *rdev) 338771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 339771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint32_t scratch; 340771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint32_t tmp = 0; 341771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 342771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 343771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 344771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_scratch_get(rdev, &scratch); 345771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 346771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 347771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 348771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 349771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse WREG32(scratch, 0xCAFEDEAD); 350771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_ring_lock(rdev, 2); 351771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 352771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 353771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_scratch_free(rdev, scratch); 354771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 355771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 356771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, PACKET0(scratch, 0)); 357771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_write(rdev, 0xDEADBEEF); 358771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_unlock_commit(rdev); 359771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < rdev->usec_timeout; i++) { 360771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse tmp = RREG32(scratch); 361771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (tmp == 0xDEADBEEF) { 362771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse break; 363771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 364771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_UDELAY(1); 365771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 366771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (i < rdev->usec_timeout) { 367771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_INFO("ring test succeeded in %d usecs\n", i); 368771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } else { 369771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", 370771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse scratch, tmp); 371771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = -EINVAL; 372771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 373771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_scratch_free(rdev, scratch); 374771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 375771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 376771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 377771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) 378771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 379771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 380771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 381771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_size = ring_size; 382771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Allocate ring buffer */ 383771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (rdev->cp.ring_obj == NULL) { 384771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_create(rdev, NULL, rdev->cp.ring_size, 385771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse true, 386771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse RADEON_GEM_DOMAIN_GTT, 387771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse false, 388771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse &rdev->cp.ring_obj); 389771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 390771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r); 391771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 392771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 393771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 394771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_pin(rdev->cp.ring_obj, 395771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse RADEON_GEM_DOMAIN_GTT, 396771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse &rdev->cp.gpu_addr); 397771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 398771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r); 399771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 400771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 401771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 402771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_object_kmap(rdev->cp.ring_obj, 403771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (void **)&rdev->cp.ring); 404771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 405771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r); 406771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 407771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 408771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 409771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 410771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; 411771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 412771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 413771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 414771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 415771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_fini(struct radeon_device *rdev) 416771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 417771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->cp.mutex); 418771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (rdev->cp.ring_obj) { 419771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_object_kunmap(rdev->cp.ring_obj); 420771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_object_unpin(rdev->cp.ring_obj); 421771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_object_unref(&rdev->cp.ring_obj); 422771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring = NULL; 423771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_obj = NULL; 424771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 425771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 426771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 427771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 428771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 429771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 430771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Debugfs info 431771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 432771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#if defined(CONFIG_DEBUG_FS) 433771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic int radeon_debugfs_ib_info(struct seq_file *m, void *data) 434771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 435771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 436771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *ib = node->info_ent->data; 437771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 438771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 439771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (ib == NULL) { 440771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 441771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 442771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "IB %04lu\n", ib->idx); 443771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "IB fence %p\n", ib->fence); 444771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "IB size %05u dwords\n", ib->length_dw); 445771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < ib->length_dw; i++) { 446771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); 447771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 448771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 449771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 450771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 451771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; 452771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; 453771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#endif 454771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 455771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_debugfs_ib_init(struct radeon_device *rdev) 456771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 457771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#if defined(CONFIG_DEBUG_FS) 458771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 459771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 460771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 461771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); 462771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; 463771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; 464771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].driver_features = 0; 465771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; 466771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 467771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, 468771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse RADEON_IB_POOL_SIZE); 469771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#else 470771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 471771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#endif 472771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 473