radeon_ring.c revision ec4f2ac471e25d3e0cea05abb8da34c05a0868f9
1771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 2771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2008 Advanced Micro Devices, Inc. 3771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2008 Red Hat Inc. 4771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Copyright 2009 Jerome Glisse. 5771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 6771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Permission is hereby granted, free of charge, to any person obtaining a 7771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * copy of this software and associated documentation files (the "Software"), 8771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * to deal in the Software without restriction, including without limitation 9771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * and/or sell copies of the Software, and to permit persons to whom the 11771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Software is furnished to do so, subject to the following conditions: 12771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 13771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * The above copyright notice and this permission notice shall be included in 14771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * all copies or substantial portions of the Software. 15771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 16771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * OTHER DEALINGS IN THE SOFTWARE. 23771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * 24771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Authors: Dave Airlie 25771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Alex Deucher 26771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Jerome Glisse 27771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 28771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include <linux/seq_file.h> 295a0e3ad6af8660be21ca98a971cd00f331318c05Tejun Heo#include <linux/slab.h> 30771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "drmP.h" 31771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon_drm.h" 32771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon_reg.h" 33771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "radeon.h" 34771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#include "atom.h" 35771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 36771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_debugfs_ib_init(struct radeon_device *rdev); 37771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 389f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glissevoid radeon_ib_bogus_cleanup(struct radeon_device *rdev) 399f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse{ 409f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse struct radeon_ib *ib, *n; 419f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 429f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) { 439f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse list_del(&ib->list); 449f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse vfree(ib->ptr); 459f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse kfree(ib); 469f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse } 479f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse} 489f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 499f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glissevoid radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib) 509f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse{ 519f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse struct radeon_ib *bib; 529f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 539f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse bib = kmalloc(sizeof(*bib), GFP_KERNEL); 549f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse if (bib == NULL) 559f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse return; 569f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse bib->ptr = vmalloc(ib->length_dw * 4); 579f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse if (bib->ptr == NULL) { 589f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse kfree(bib); 599f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse return; 609f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse } 619f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse memcpy(bib->ptr, ib->ptr, ib->length_dw * 4); 629f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse bib->length_dw = ib->length_dw; 639f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 649f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib); 659f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 669f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse} 679f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 68771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 69771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * IB. 70771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 71771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) 72771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 73771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_fence *fence; 74771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *nib; 7591cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse int r = 0, i, c; 76771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 77771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = NULL; 78771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_create(rdev, &fence); 79771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 8091cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse dev_err(rdev->dev, "failed to create fence for new IB\n"); 81771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 82771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 83771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 8491cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) { 8591cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse i &= (RADEON_IB_POOL_SIZE - 1); 8691cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse if (rdev->ib_pool.ibs[i].free) { 8791cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse nib = &rdev->ib_pool.ibs[i]; 8891cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse break; 8991cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse } 90771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 9191cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse if (nib == NULL) { 9291cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse /* This should never happen, it means we allocated all 9391cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse * IB and haven't scheduled one yet, return EBUSY to 9491cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse * userspace hoping that on ioctl recall we get better 9591cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse * luck 9691cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse */ 9791cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse dev_err(rdev->dev, "no free indirect buffer !\n"); 98ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie mutex_unlock(&rdev->ib_pool.mutex); 9991cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse radeon_fence_unref(&fence); 10091cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse return -EBUSY; 101771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 10291cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); 10391cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse nib->free = false; 10491cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse if (nib->fence) { 105ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie mutex_unlock(&rdev->ib_pool.mutex); 10691cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse r = radeon_fence_wait(nib->fence, false); 10791cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse if (r) { 10891cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", 10991cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); 11091cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse mutex_lock(&rdev->ib_pool.mutex); 11191cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse nib->free = true; 11291cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 11391cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse radeon_fence_unref(&fence); 11491cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse return r; 11591cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse } 11691cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse mutex_lock(&rdev->ib_pool.mutex); 117771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 118771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_unref(&nib->fence); 11991cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse nib->fence = fence; 120771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse nib->length_dw = 0; 121ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie mutex_unlock(&rdev->ib_pool.mutex); 122771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = nib; 12391cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse return 0; 124771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 125771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 126771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) 127771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 128771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *tmp = *ib; 129771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 130771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse *ib = NULL; 131771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (tmp == NULL) { 132771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return; 133771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 1347d404c7b5f4c004712bc15ed6e6edd6779842126Jerome Glisse if (!tmp->fence->emited) 1357d404c7b5f4c004712bc15ed6e6edd6779842126Jerome Glisse radeon_fence_unref(&tmp->fence); 136771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 13791cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse tmp->free = true; 138771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 139771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 140771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 141771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 142771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 143771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r = 0; 144771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 145771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!ib->length_dw || !rdev->cp.ready) { 146771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* TODO: Nothings in the ib we should report. */ 14791cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); 148771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return -EINVAL; 149771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 150ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie 1516cdf65855cf884712532fc72770baaef7bdf1b9aDave Airlie /* 64 dwords should be enough for fence too */ 152771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_ring_lock(rdev, 64); 153771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 154ec4f2ac471e25d3e0cea05abb8da34c05a0868f9Paul Bolle DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); 155771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 156771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 1573ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_ring_ib_execute(rdev, ib); 158771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_fence_emit(rdev, ib->fence); 159ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie mutex_lock(&rdev->ib_pool.mutex); 16091cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse /* once scheduled IB is considered free and protected by the fence */ 16191cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse ib->free = true; 162771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 163ecb114a128d150422d22eda238cb812f6b20bf39Dave Airlie radeon_ring_unlock_commit(rdev); 164771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 165771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 166771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 167771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ib_pool_init(struct radeon_device *rdev) 168771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 169771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse void *ptr; 170771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse uint64_t gpu_addr; 171771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int i; 172771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r = 0; 173771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 1749f022ddfb23793b475ff7e57ac08a766dd5d31bdJerome Glisse if (rdev->ib_pool.robj) 1759f022ddfb23793b475ff7e57ac08a766dd5d31bdJerome Glisse return 0; 1769f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib); 177771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Allocate 1M object buffer */ 1784c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, 179268b2510de14f62134d87ba9b4981816192db386Alex Deucher PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT, 180268b2510de14f62134d87ba9b4981816192db386Alex Deucher &rdev->ib_pool.robj); 181771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 182771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to ib pool (%d).\n", r); 183771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 184771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 1854c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_reserve(rdev->ib_pool.robj, false); 1864c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse if (unlikely(r != 0)) 1874c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse return r; 1884c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); 189771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 1904c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse radeon_bo_unreserve(rdev->ib_pool.robj); 191771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); 192771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 193771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 1944c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr); 1954c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse radeon_bo_unreserve(rdev->ib_pool.robj); 196771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 197771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); 198771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 199771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 200771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 201771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned offset; 202771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 203771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse offset = i * 64 * 1024; 204771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; 205771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].ptr = ptr + offset; 206771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].idx = i; 207771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ibs[i].length_dw = 0; 20891cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse rdev->ib_pool.ibs[i].free = true; 209771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 21091cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse rdev->ib_pool.head_id = 0; 211771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->ib_pool.ready = true; 212771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_INFO("radeon: ib pool ready.\n"); 213771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (radeon_debugfs_ib_init(rdev)) { 214771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_ERROR("Failed to register debugfs file for IB !\n"); 215771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 216771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 217771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 218771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 219771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ib_pool_fini(struct radeon_device *rdev) 220771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 2214c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse int r; 222ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher struct radeon_bo *robj; 2234c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse 224771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!rdev->ib_pool.ready) { 225771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return; 226771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 227771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 2289f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse radeon_ib_bogus_cleanup(rdev); 229ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher robj = rdev->ib_pool.robj; 230ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher rdev->ib_pool.robj = NULL; 231ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher mutex_unlock(&rdev->ib_pool.mutex); 232eb6b6d7cdd5548fa03a919d14615195600013be2Dave Airlie 233ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher if (robj) { 234ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher r = radeon_bo_reserve(robj, false); 2354c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse if (likely(r == 0)) { 236ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_kunmap(robj); 237ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unpin(robj); 238ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unreserve(robj); 2394c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse } 240ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unref(&robj); 241771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 242771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 243771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 244771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 245771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 246771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Ring. 247771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 248771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_free_size(struct radeon_device *rdev) 249771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 250724c80e1d630296d1324859e964d80d35007d83cAlex Deucher if (rdev->wb.enabled) 251724c80e1d630296d1324859e964d80d35007d83cAlex Deucher rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]; 252724c80e1d630296d1324859e964d80d35007d83cAlex Deucher else { 253724c80e1d630296d1324859e964d80d35007d83cAlex Deucher if (rdev->family >= CHIP_R600) 254724c80e1d630296d1324859e964d80d35007d83cAlex Deucher rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 255724c80e1d630296d1324859e964d80d35007d83cAlex Deucher else 256724c80e1d630296d1324859e964d80d35007d83cAlex Deucher rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 257724c80e1d630296d1324859e964d80d35007d83cAlex Deucher } 258771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* This works because ring_size is a power of 2 */ 259771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); 260771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw -= rdev->cp.wptr; 261771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; 262771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (!rdev->cp.ring_free_dw) { 263771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 264771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 265771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 266771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 26791700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrettint radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw) 268771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 269771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 270771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 271771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Align requested size with padding so unlock_commit can 272771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * pad safely */ 273771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; 274771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse while (ndw > (rdev->cp.ring_free_dw - 1)) { 275771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_ring_free_size(rdev); 276771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (ndw < rdev->cp.ring_free_dw) { 277771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse break; 278771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 279771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse r = radeon_fence_wait_next(rdev); 28091700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett if (r) 281771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 282771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 283771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.count_dw = ndw; 284771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.wptr_old = rdev->cp.wptr; 285771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 286771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 287771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 28891700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrettint radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) 28991700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett{ 29091700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett int r; 29191700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett 29291700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett mutex_lock(&rdev->cp.mutex); 29391700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett r = radeon_ring_alloc(rdev, ndw); 29491700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett if (r) { 29591700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett mutex_unlock(&rdev->cp.mutex); 29691700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett return r; 29791700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett } 29891700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett return 0; 29991700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett} 30091700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett 30191700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrettvoid radeon_ring_commit(struct radeon_device *rdev) 302771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 303771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned count_dw_pad; 304771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 305771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 306771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* We pad to match fetch size */ 307771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse count_dw_pad = (rdev->cp.align_mask + 1) - 308771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (rdev->cp.wptr & rdev->cp.align_mask); 309771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < count_dw_pad; i++) { 3103ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_ring_write(rdev, 2 << 30); 311771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 312771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse DRM_MEMORYBARRIER(); 3133ce0a23d2d253185df24e22e3d5f89800bb3dd1cJerome Glisse radeon_cp_commit(rdev); 31491700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett} 31591700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett 31691700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrettvoid radeon_ring_unlock_commit(struct radeon_device *rdev) 31791700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett{ 31891700f3cac56a1998a56d41e4459a5cebdb4f752Matthew Garrett radeon_ring_commit(rdev); 319771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 320771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 321771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 322771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_unlock_undo(struct radeon_device *rdev) 323771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 324771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.wptr = rdev->cp.wptr_old; 325771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_unlock(&rdev->cp.mutex); 326771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 327771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 328771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) 329771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 330771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse int r; 331771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 332771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_size = ring_size; 333771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse /* Allocate ring buffer */ 334771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (rdev->cp.ring_obj == NULL) { 335268b2510de14f62134d87ba9b4981816192db386Alex Deucher r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, PAGE_SIZE, true, 3364c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse RADEON_GEM_DOMAIN_GTT, 3374c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse &rdev->cp.ring_obj); 338771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 3394c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse dev_err(rdev->dev, "(%d) ring create failed\n", r); 340771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 341771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 3424c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_reserve(rdev->cp.ring_obj, false); 3434c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse if (unlikely(r != 0)) 3444c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse return r; 3454c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT, 3464c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse &rdev->cp.gpu_addr); 347771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 3484c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse radeon_bo_unreserve(rdev->cp.ring_obj); 3494c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse dev_err(rdev->dev, "(%d) ring pin failed\n", r); 350771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 351771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 3524c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse r = radeon_bo_kmap(rdev->cp.ring_obj, 353771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse (void **)&rdev->cp.ring); 3544c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse radeon_bo_unreserve(rdev->cp.ring_obj); 355771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (r) { 3564c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse dev_err(rdev->dev, "(%d) ring map failed\n", r); 357771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return r; 358771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 359771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 360771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; 361771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 362771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 363771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 364771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 365771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissevoid radeon_ring_fini(struct radeon_device *rdev) 366771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 3674c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse int r; 368ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher struct radeon_bo *ring_obj; 3694c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse 370771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse mutex_lock(&rdev->cp.mutex); 371ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher ring_obj = rdev->cp.ring_obj; 372ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher rdev->cp.ring = NULL; 373ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher rdev->cp.ring_obj = NULL; 374ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher mutex_unlock(&rdev->cp.mutex); 375ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher 376ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher if (ring_obj) { 377ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher r = radeon_bo_reserve(ring_obj, false); 3784c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse if (likely(r == 0)) { 379ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_kunmap(ring_obj); 380ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unpin(ring_obj); 381ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unreserve(ring_obj); 3824c7886791264f03428d5424befb1b96f08fc90f4Jerome Glisse } 383ca2af92311eee95820f3b48c35045e5f56bc1477Alex Deucher radeon_bo_unref(&ring_obj); 384771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 385771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 386771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 387771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 388771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse/* 389771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse * Debugfs info 390771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse */ 391771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#if defined(CONFIG_DEBUG_FS) 392771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic int radeon_debugfs_ib_info(struct seq_file *m, void *data) 393771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 394771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 395771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse struct radeon_ib *ib = node->info_ent->data; 396771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 397771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 398771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse if (ib == NULL) { 399771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 400771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 40191cb91becf372b5308cdd7d2e15b2e3ef66bae7eJerome Glisse seq_printf(m, "IB %04u\n", ib->idx); 402771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "IB fence %p\n", ib->fence); 403771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "IB size %05u dwords\n", ib->length_dw); 404771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < ib->length_dw; i++) { 405771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); 406771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 407771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 408771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 409771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 4109f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glissestatic int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data) 4119f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse{ 4129f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse struct drm_info_node *node = (struct drm_info_node *) m->private; 4139f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse struct radeon_device *rdev = node->info_ent->data; 4149f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse struct radeon_ib *ib; 4159f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse unsigned i; 4169f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 4179f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse mutex_lock(&rdev->ib_pool.mutex); 4189f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse if (list_empty(&rdev->ib_pool.bogus_ib)) { 4199f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 4209f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse seq_printf(m, "no bogus IB recorded\n"); 4219f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse return 0; 4229f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse } 4239f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list); 4249f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse list_del_init(&ib->list); 4259f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse mutex_unlock(&rdev->ib_pool.mutex); 4269f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse seq_printf(m, "IB size %05u dwords\n", ib->length_dw); 4279f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse for (i = 0; i < ib->length_dw; i++) { 4289f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); 4299f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse } 4309f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse vfree(ib->ptr); 4319f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse kfree(ib); 4329f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse return 0; 4339f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse} 4349f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 435771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; 436771fe6b912fca54f03e8a72eb63058b582775362Jerome Glissestatic char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; 4379f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse 4389f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glissestatic struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = { 4399f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL}, 4409f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse}; 441771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#endif 442771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 443771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisseint radeon_debugfs_ib_init(struct radeon_device *rdev) 444771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse{ 445771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#if defined(CONFIG_DEBUG_FS) 446771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse unsigned i; 4479f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse int r; 448771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse 4499f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse radeon_debugfs_ib_bogus_info_list[0].data = rdev; 4509f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1); 4519f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse if (r) 4529f93ed39804a9cfe10577cfae66059fe6bc6e3a5Jerome Glisse return r; 453771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { 454771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); 455771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; 456771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; 457771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].driver_features = 0; 458771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; 459771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse } 460771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, 461771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse RADEON_IB_POOL_SIZE); 462771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#else 463771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse return 0; 464771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse#endif 465771fe6b912fca54f03e8a72eb63058b582775362Jerome Glisse} 466