1/* savage_bci.c -- BCI support for Savage 2 * 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25#include "drmP.h" 26#include "savage_drm.h" 27#include "savage_drv.h" 28 29/* Need a long timeout for shadow status updates can take a while 30 * and so can waiting for events when the queue is full. */ 31#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 32#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 33#define SAVAGE_FREELIST_DEBUG 0 34 35static int savage_do_cleanup_bci(struct drm_device *dev); 36 37static int 38savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) 39{ 40 uint32_t mask = dev_priv->status_used_mask; 41 uint32_t threshold = dev_priv->bci_threshold_hi; 42 uint32_t status; 43 int i; 44 45#if SAVAGE_BCI_DEBUG 46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) 47 DRM_ERROR("Trying to emit %d words " 48 "(more than guaranteed space in COB)\n", n); 49#endif 50 51 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 52 DRM_MEMORYBARRIER(); 53 status = dev_priv->status_ptr[0]; 54 if ((status & mask) < threshold) 55 return 0; 56 DRM_UDELAY(1); 57 } 58 59#if SAVAGE_BCI_DEBUG 60 DRM_ERROR("failed!\n"); 61 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); 62#endif 63 return -EBUSY; 64} 65 66static int 67savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) 68{ 69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 70 uint32_t status; 71 int i; 72 73 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 74 status = SAVAGE_READ(SAVAGE_STATUS_WORD0); 75 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) 76 return 0; 77 DRM_UDELAY(1); 78 } 79 80#if SAVAGE_BCI_DEBUG 81 DRM_ERROR("failed!\n"); 82 DRM_INFO(" status=0x%08x\n", status); 83#endif 84 return -EBUSY; 85} 86 87static int 88savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) 89{ 90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 91 uint32_t status; 92 int i; 93 94 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 95 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); 96 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) 97 return 0; 98 DRM_UDELAY(1); 99 } 100 101#if SAVAGE_BCI_DEBUG 102 DRM_ERROR("failed!\n"); 103 DRM_INFO(" status=0x%08x\n", status); 104#endif 105 return -EBUSY; 106} 107 108/* 109 * Waiting for events. 110 * 111 * The BIOSresets the event tag to 0 on mode changes. Therefore we 112 * never emit 0 to the event tag. If we find a 0 event tag we know the 113 * BIOS stomped on it and return success assuming that the BIOS waited 114 * for engine idle. 115 * 116 * Note: if the Xserver uses the event tag it has to follow the same 117 * rule. Otherwise there may be glitches every 2^16 events. 118 */ 119static int 120savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) 121{ 122 uint32_t status; 123 int i; 124 125 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 126 DRM_MEMORYBARRIER(); 127 status = dev_priv->status_ptr[1]; 128 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 129 (status & 0xffff) == 0) 130 return 0; 131 DRM_UDELAY(1); 132 } 133 134#if SAVAGE_BCI_DEBUG 135 DRM_ERROR("failed!\n"); 136 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 137#endif 138 139 return -EBUSY; 140} 141 142static int 143savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e) 144{ 145 uint32_t status; 146 int i; 147 148 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 149 status = SAVAGE_READ(SAVAGE_STATUS_WORD1); 150 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 151 (status & 0xffff) == 0) 152 return 0; 153 DRM_UDELAY(1); 154 } 155 156#if SAVAGE_BCI_DEBUG 157 DRM_ERROR("failed!\n"); 158 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 159#endif 160 161 return -EBUSY; 162} 163 164uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 165 unsigned int flags) 166{ 167 uint16_t count; 168 BCI_LOCALS; 169 170 if (dev_priv->status_ptr) { 171 /* coordinate with Xserver */ 172 count = dev_priv->status_ptr[1023]; 173 if (count < dev_priv->event_counter) 174 dev_priv->event_wrap++; 175 } else { 176 count = dev_priv->event_counter; 177 } 178 count = (count + 1) & 0xffff; 179 if (count == 0) { 180 count++; /* See the comment above savage_wait_event_*. */ 181 dev_priv->event_wrap++; 182 } 183 dev_priv->event_counter = count; 184 if (dev_priv->status_ptr) 185 dev_priv->status_ptr[1023] = (uint32_t) count; 186 187 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 188 unsigned int wait_cmd = BCI_CMD_WAIT; 189 if ((flags & SAVAGE_WAIT_2D)) 190 wait_cmd |= BCI_CMD_WAIT_2D; 191 if ((flags & SAVAGE_WAIT_3D)) 192 wait_cmd |= BCI_CMD_WAIT_3D; 193 BEGIN_BCI(2); 194 BCI_WRITE(wait_cmd); 195 } else { 196 BEGIN_BCI(1); 197 } 198 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count); 199 200 return count; 201} 202 203/* 204 * Freelist management 205 */ 206static int savage_freelist_init(struct drm_device * dev) 207{ 208 drm_savage_private_t *dev_priv = dev->dev_private; 209 struct drm_device_dma *dma = dev->dma; 210 struct drm_buf *buf; 211 drm_savage_buf_priv_t *entry; 212 int i; 213 DRM_DEBUG("count=%d\n", dma->buf_count); 214 215 dev_priv->head.next = &dev_priv->tail; 216 dev_priv->head.prev = NULL; 217 dev_priv->head.buf = NULL; 218 219 dev_priv->tail.next = NULL; 220 dev_priv->tail.prev = &dev_priv->head; 221 dev_priv->tail.buf = NULL; 222 223 for (i = 0; i < dma->buf_count; i++) { 224 buf = dma->buflist[i]; 225 entry = buf->dev_private; 226 227 SET_AGE(&entry->age, 0, 0); 228 entry->buf = buf; 229 230 entry->next = dev_priv->head.next; 231 entry->prev = &dev_priv->head; 232 dev_priv->head.next->prev = entry; 233 dev_priv->head.next = entry; 234 } 235 236 return 0; 237} 238 239static struct drm_buf *savage_freelist_get(struct drm_device * dev) 240{ 241 drm_savage_private_t *dev_priv = dev->dev_private; 242 drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 243 uint16_t event; 244 unsigned int wrap; 245 DRM_DEBUG("\n"); 246 247 UPDATE_EVENT_COUNTER(); 248 if (dev_priv->status_ptr) 249 event = dev_priv->status_ptr[1] & 0xffff; 250 else 251 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 252 wrap = dev_priv->event_wrap; 253 if (event > dev_priv->event_counter) 254 wrap--; /* hardware hasn't passed the last wrap yet */ 255 256 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 257 DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 258 259 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { 260 drm_savage_buf_priv_t *next = tail->next; 261 drm_savage_buf_priv_t *prev = tail->prev; 262 prev->next = next; 263 next->prev = prev; 264 tail->next = tail->prev = NULL; 265 return tail->buf; 266 } 267 268 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); 269 return NULL; 270} 271 272void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf) 273{ 274 drm_savage_private_t *dev_priv = dev->dev_private; 275 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 276 277 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); 278 279 if (entry->next != NULL || entry->prev != NULL) { 280 DRM_ERROR("entry already on freelist.\n"); 281 return; 282 } 283 284 prev = &dev_priv->head; 285 next = prev->next; 286 prev->next = entry; 287 next->prev = entry; 288 entry->prev = prev; 289 entry->next = next; 290} 291 292/* 293 * Command DMA 294 */ 295static int savage_dma_init(drm_savage_private_t * dev_priv) 296{ 297 unsigned int i; 298 299 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 300 (SAVAGE_DMA_PAGE_SIZE * 4); 301 dev_priv->dma_pages = kmalloc(sizeof(drm_savage_dma_page_t) * 302 dev_priv->nr_dma_pages, GFP_KERNEL); 303 if (dev_priv->dma_pages == NULL) 304 return -ENOMEM; 305 306 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 307 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); 308 dev_priv->dma_pages[i].used = 0; 309 dev_priv->dma_pages[i].flushed = 0; 310 } 311 SET_AGE(&dev_priv->last_dma_age, 0, 0); 312 313 dev_priv->first_dma_page = 0; 314 dev_priv->current_dma_page = 0; 315 316 return 0; 317} 318 319void savage_dma_reset(drm_savage_private_t * dev_priv) 320{ 321 uint16_t event; 322 unsigned int wrap, i; 323 event = savage_bci_emit_event(dev_priv, 0); 324 wrap = dev_priv->event_wrap; 325 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 326 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 327 dev_priv->dma_pages[i].used = 0; 328 dev_priv->dma_pages[i].flushed = 0; 329 } 330 SET_AGE(&dev_priv->last_dma_age, event, wrap); 331 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 332} 333 334void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page) 335{ 336 uint16_t event; 337 unsigned int wrap; 338 339 /* Faked DMA buffer pages don't age. */ 340 if (dev_priv->cmd_dma == &dev_priv->fake_dma) 341 return; 342 343 UPDATE_EVENT_COUNTER(); 344 if (dev_priv->status_ptr) 345 event = dev_priv->status_ptr[1] & 0xffff; 346 else 347 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 348 wrap = dev_priv->event_wrap; 349 if (event > dev_priv->event_counter) 350 wrap--; /* hardware hasn't passed the last wrap yet */ 351 352 if (dev_priv->dma_pages[page].age.wrap > wrap || 353 (dev_priv->dma_pages[page].age.wrap == wrap && 354 dev_priv->dma_pages[page].age.event > event)) { 355 if (dev_priv->wait_evnt(dev_priv, 356 dev_priv->dma_pages[page].age.event) 357 < 0) 358 DRM_ERROR("wait_evnt failed!\n"); 359 } 360} 361 362uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) 363{ 364 unsigned int cur = dev_priv->current_dma_page; 365 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 366 dev_priv->dma_pages[cur].used; 367 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / 368 SAVAGE_DMA_PAGE_SIZE; 369 uint32_t *dma_ptr; 370 unsigned int i; 371 372 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", 373 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 374 375 if (cur + nr_pages < dev_priv->nr_dma_pages) { 376 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 377 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 378 if (n < rest) 379 rest = n; 380 dev_priv->dma_pages[cur].used += rest; 381 n -= rest; 382 cur++; 383 } else { 384 dev_priv->dma_flush(dev_priv); 385 nr_pages = 386 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; 387 for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 388 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 389 dev_priv->dma_pages[i].used = 0; 390 dev_priv->dma_pages[i].flushed = 0; 391 } 392 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; 393 dev_priv->first_dma_page = cur = 0; 394 } 395 for (i = cur; nr_pages > 0; ++i, --nr_pages) { 396#if SAVAGE_DMA_DEBUG 397 if (dev_priv->dma_pages[i].used) { 398 DRM_ERROR("unflushed page %u: used=%u\n", 399 i, dev_priv->dma_pages[i].used); 400 } 401#endif 402 if (n > SAVAGE_DMA_PAGE_SIZE) 403 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; 404 else 405 dev_priv->dma_pages[i].used = n; 406 n -= SAVAGE_DMA_PAGE_SIZE; 407 } 408 dev_priv->current_dma_page = --i; 409 410 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", 411 i, dev_priv->dma_pages[i].used, n); 412 413 savage_dma_wait(dev_priv, dev_priv->current_dma_page); 414 415 return dma_ptr; 416} 417 418static void savage_dma_flush(drm_savage_private_t * dev_priv) 419{ 420 unsigned int first = dev_priv->first_dma_page; 421 unsigned int cur = dev_priv->current_dma_page; 422 uint16_t event; 423 unsigned int wrap, pad, align, len, i; 424 unsigned long phys_addr; 425 BCI_LOCALS; 426 427 if (first == cur && 428 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) 429 return; 430 431 /* pad length to multiples of 2 entries 432 * align start of next DMA block to multiles of 8 entries */ 433 pad = -dev_priv->dma_pages[cur].used & 1; 434 align = -(dev_priv->dma_pages[cur].used + pad) & 7; 435 436 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " 437 "pad=%u, align=%u\n", 438 first, cur, dev_priv->dma_pages[first].flushed, 439 dev_priv->dma_pages[cur].used, pad, align); 440 441 /* pad with noops */ 442 if (pad) { 443 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 444 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 445 dev_priv->dma_pages[cur].used += pad; 446 while (pad != 0) { 447 *dma_ptr++ = BCI_CMD_WAIT; 448 pad--; 449 } 450 } 451 452 DRM_MEMORYBARRIER(); 453 454 /* do flush ... */ 455 phys_addr = dev_priv->cmd_dma->offset + 456 (first * SAVAGE_DMA_PAGE_SIZE + 457 dev_priv->dma_pages[first].flushed) * 4; 458 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 459 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; 460 461 DRM_DEBUG("phys_addr=%lx, len=%u\n", 462 phys_addr | dev_priv->dma_type, len); 463 464 BEGIN_BCI(3); 465 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); 466 BCI_WRITE(phys_addr | dev_priv->dma_type); 467 BCI_DMA(len); 468 469 /* fix alignment of the start of the next block */ 470 dev_priv->dma_pages[cur].used += align; 471 472 /* age DMA pages */ 473 event = savage_bci_emit_event(dev_priv, 0); 474 wrap = dev_priv->event_wrap; 475 for (i = first; i < cur; ++i) { 476 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 477 dev_priv->dma_pages[i].used = 0; 478 dev_priv->dma_pages[i].flushed = 0; 479 } 480 /* age the current page only when it's full */ 481 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { 482 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); 483 dev_priv->dma_pages[cur].used = 0; 484 dev_priv->dma_pages[cur].flushed = 0; 485 /* advance to next page */ 486 cur++; 487 if (cur == dev_priv->nr_dma_pages) 488 cur = 0; 489 dev_priv->first_dma_page = dev_priv->current_dma_page = cur; 490 } else { 491 dev_priv->first_dma_page = cur; 492 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; 493 } 494 SET_AGE(&dev_priv->last_dma_age, event, wrap); 495 496 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, 497 dev_priv->dma_pages[cur].used, 498 dev_priv->dma_pages[cur].flushed); 499} 500 501static void savage_fake_dma_flush(drm_savage_private_t * dev_priv) 502{ 503 unsigned int i, j; 504 BCI_LOCALS; 505 506 if (dev_priv->first_dma_page == dev_priv->current_dma_page && 507 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) 508 return; 509 510 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", 511 dev_priv->first_dma_page, dev_priv->current_dma_page, 512 dev_priv->dma_pages[dev_priv->current_dma_page].used); 513 514 for (i = dev_priv->first_dma_page; 515 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 516 ++i) { 517 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + 518 i * SAVAGE_DMA_PAGE_SIZE; 519#if SAVAGE_DMA_DEBUG 520 /* Sanity check: all pages except the last one must be full. */ 521 if (i < dev_priv->current_dma_page && 522 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { 523 DRM_ERROR("partial DMA page %u: used=%u", 524 i, dev_priv->dma_pages[i].used); 525 } 526#endif 527 BEGIN_BCI(dev_priv->dma_pages[i].used); 528 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { 529 BCI_WRITE(dma_ptr[j]); 530 } 531 dev_priv->dma_pages[i].used = 0; 532 } 533 534 /* reset to first page */ 535 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 536} 537 538int savage_driver_load(struct drm_device *dev, unsigned long chipset) 539{ 540 drm_savage_private_t *dev_priv; 541 542 dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL); 543 if (dev_priv == NULL) 544 return -ENOMEM; 545 546 dev->dev_private = (void *)dev_priv; 547 548 dev_priv->chipset = (enum savage_family)chipset; 549 550 return 0; 551} 552 553 554/* 555 * Initialize mappings. On Savage4 and SavageIX the alignment 556 * and size of the aperture is not suitable for automatic MTRR setup 557 * in drm_addmap. Therefore we add them manually before the maps are 558 * initialized, and tear them down on last close. 559 */ 560int savage_driver_firstopen(struct drm_device *dev) 561{ 562 drm_savage_private_t *dev_priv = dev->dev_private; 563 unsigned long mmio_base, fb_base, fb_size, aperture_base; 564 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist 565 * in case we decide we need information on the BAR for BSD in the 566 * future. 567 */ 568 unsigned int fb_rsrc, aper_rsrc; 569 int ret = 0; 570 571 dev_priv->mtrr[0].handle = -1; 572 dev_priv->mtrr[1].handle = -1; 573 dev_priv->mtrr[2].handle = -1; 574 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 575 fb_rsrc = 0; 576 fb_base = pci_resource_start(dev->pdev, 0); 577 fb_size = SAVAGE_FB_SIZE_S3; 578 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 579 aper_rsrc = 0; 580 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 581 /* this should always be true */ 582 if (pci_resource_len(dev->pdev, 0) == 0x08000000) { 583 /* Don't make MMIO write-cobining! We need 3 584 * MTRRs. */ 585 dev_priv->mtrr[0].base = fb_base; 586 dev_priv->mtrr[0].size = 0x01000000; 587 dev_priv->mtrr[0].handle = 588 drm_mtrr_add(dev_priv->mtrr[0].base, 589 dev_priv->mtrr[0].size, DRM_MTRR_WC); 590 dev_priv->mtrr[1].base = fb_base + 0x02000000; 591 dev_priv->mtrr[1].size = 0x02000000; 592 dev_priv->mtrr[1].handle = 593 drm_mtrr_add(dev_priv->mtrr[1].base, 594 dev_priv->mtrr[1].size, DRM_MTRR_WC); 595 dev_priv->mtrr[2].base = fb_base + 0x04000000; 596 dev_priv->mtrr[2].size = 0x04000000; 597 dev_priv->mtrr[2].handle = 598 drm_mtrr_add(dev_priv->mtrr[2].base, 599 dev_priv->mtrr[2].size, DRM_MTRR_WC); 600 } else { 601 DRM_ERROR("strange pci_resource_len %08llx\n", 602 (unsigned long long) 603 pci_resource_len(dev->pdev, 0)); 604 } 605 } else if (dev_priv->chipset != S3_SUPERSAVAGE && 606 dev_priv->chipset != S3_SAVAGE2000) { 607 mmio_base = pci_resource_start(dev->pdev, 0); 608 fb_rsrc = 1; 609 fb_base = pci_resource_start(dev->pdev, 1); 610 fb_size = SAVAGE_FB_SIZE_S4; 611 aper_rsrc = 1; 612 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 613 /* this should always be true */ 614 if (pci_resource_len(dev->pdev, 1) == 0x08000000) { 615 /* Can use one MTRR to cover both fb and 616 * aperture. */ 617 dev_priv->mtrr[0].base = fb_base; 618 dev_priv->mtrr[0].size = 0x08000000; 619 dev_priv->mtrr[0].handle = 620 drm_mtrr_add(dev_priv->mtrr[0].base, 621 dev_priv->mtrr[0].size, DRM_MTRR_WC); 622 } else { 623 DRM_ERROR("strange pci_resource_len %08llx\n", 624 (unsigned long long) 625 pci_resource_len(dev->pdev, 1)); 626 } 627 } else { 628 mmio_base = pci_resource_start(dev->pdev, 0); 629 fb_rsrc = 1; 630 fb_base = pci_resource_start(dev->pdev, 1); 631 fb_size = pci_resource_len(dev->pdev, 1); 632 aper_rsrc = 2; 633 aperture_base = pci_resource_start(dev->pdev, 2); 634 /* Automatic MTRR setup will do the right thing. */ 635 } 636 637 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS, 638 _DRM_READ_ONLY, &dev_priv->mmio); 639 if (ret) 640 return ret; 641 642 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER, 643 _DRM_WRITE_COMBINING, &dev_priv->fb); 644 if (ret) 645 return ret; 646 647 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 648 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, 649 &dev_priv->aperture); 650 return ret; 651} 652 653/* 654 * Delete MTRRs and free device-private data. 655 */ 656void savage_driver_lastclose(struct drm_device *dev) 657{ 658 drm_savage_private_t *dev_priv = dev->dev_private; 659 int i; 660 661 for (i = 0; i < 3; ++i) 662 if (dev_priv->mtrr[i].handle >= 0) 663 drm_mtrr_del(dev_priv->mtrr[i].handle, 664 dev_priv->mtrr[i].base, 665 dev_priv->mtrr[i].size, DRM_MTRR_WC); 666} 667 668int savage_driver_unload(struct drm_device *dev) 669{ 670 drm_savage_private_t *dev_priv = dev->dev_private; 671 672 kfree(dev_priv); 673 674 return 0; 675} 676 677static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init) 678{ 679 drm_savage_private_t *dev_priv = dev->dev_private; 680 681 if (init->fb_bpp != 16 && init->fb_bpp != 32) { 682 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); 683 return -EINVAL; 684 } 685 if (init->depth_bpp != 16 && init->depth_bpp != 32) { 686 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); 687 return -EINVAL; 688 } 689 if (init->dma_type != SAVAGE_DMA_AGP && 690 init->dma_type != SAVAGE_DMA_PCI) { 691 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); 692 return -EINVAL; 693 } 694 695 dev_priv->cob_size = init->cob_size; 696 dev_priv->bci_threshold_lo = init->bci_threshold_lo; 697 dev_priv->bci_threshold_hi = init->bci_threshold_hi; 698 dev_priv->dma_type = init->dma_type; 699 700 dev_priv->fb_bpp = init->fb_bpp; 701 dev_priv->front_offset = init->front_offset; 702 dev_priv->front_pitch = init->front_pitch; 703 dev_priv->back_offset = init->back_offset; 704 dev_priv->back_pitch = init->back_pitch; 705 dev_priv->depth_bpp = init->depth_bpp; 706 dev_priv->depth_offset = init->depth_offset; 707 dev_priv->depth_pitch = init->depth_pitch; 708 709 dev_priv->texture_offset = init->texture_offset; 710 dev_priv->texture_size = init->texture_size; 711 712 dev_priv->sarea = drm_getsarea(dev); 713 if (!dev_priv->sarea) { 714 DRM_ERROR("could not find sarea!\n"); 715 savage_do_cleanup_bci(dev); 716 return -EINVAL; 717 } 718 if (init->status_offset != 0) { 719 dev_priv->status = drm_core_findmap(dev, init->status_offset); 720 if (!dev_priv->status) { 721 DRM_ERROR("could not find shadow status region!\n"); 722 savage_do_cleanup_bci(dev); 723 return -EINVAL; 724 } 725 } else { 726 dev_priv->status = NULL; 727 } 728 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { 729 dev->agp_buffer_token = init->buffers_offset; 730 dev->agp_buffer_map = drm_core_findmap(dev, 731 init->buffers_offset); 732 if (!dev->agp_buffer_map) { 733 DRM_ERROR("could not find DMA buffer region!\n"); 734 savage_do_cleanup_bci(dev); 735 return -EINVAL; 736 } 737 drm_core_ioremap(dev->agp_buffer_map, dev); 738 if (!dev->agp_buffer_map) { 739 DRM_ERROR("failed to ioremap DMA buffer region!\n"); 740 savage_do_cleanup_bci(dev); 741 return -ENOMEM; 742 } 743 } 744 if (init->agp_textures_offset) { 745 dev_priv->agp_textures = 746 drm_core_findmap(dev, init->agp_textures_offset); 747 if (!dev_priv->agp_textures) { 748 DRM_ERROR("could not find agp texture region!\n"); 749 savage_do_cleanup_bci(dev); 750 return -EINVAL; 751 } 752 } else { 753 dev_priv->agp_textures = NULL; 754 } 755 756 if (init->cmd_dma_offset) { 757 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 758 DRM_ERROR("command DMA not supported on " 759 "Savage3D/MX/IX.\n"); 760 savage_do_cleanup_bci(dev); 761 return -EINVAL; 762 } 763 if (dev->dma && dev->dma->buflist) { 764 DRM_ERROR("command and vertex DMA not supported " 765 "at the same time.\n"); 766 savage_do_cleanup_bci(dev); 767 return -EINVAL; 768 } 769 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset); 770 if (!dev_priv->cmd_dma) { 771 DRM_ERROR("could not find command DMA region!\n"); 772 savage_do_cleanup_bci(dev); 773 return -EINVAL; 774 } 775 if (dev_priv->dma_type == SAVAGE_DMA_AGP) { 776 if (dev_priv->cmd_dma->type != _DRM_AGP) { 777 DRM_ERROR("AGP command DMA region is not a " 778 "_DRM_AGP map!\n"); 779 savage_do_cleanup_bci(dev); 780 return -EINVAL; 781 } 782 drm_core_ioremap(dev_priv->cmd_dma, dev); 783 if (!dev_priv->cmd_dma->handle) { 784 DRM_ERROR("failed to ioremap command " 785 "DMA region!\n"); 786 savage_do_cleanup_bci(dev); 787 return -ENOMEM; 788 } 789 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { 790 DRM_ERROR("PCI command DMA region is not a " 791 "_DRM_CONSISTENT map!\n"); 792 savage_do_cleanup_bci(dev); 793 return -EINVAL; 794 } 795 } else { 796 dev_priv->cmd_dma = NULL; 797 } 798 799 dev_priv->dma_flush = savage_dma_flush; 800 if (!dev_priv->cmd_dma) { 801 DRM_DEBUG("falling back to faked command DMA.\n"); 802 dev_priv->fake_dma.offset = 0; 803 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; 804 dev_priv->fake_dma.type = _DRM_SHM; 805 dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE, 806 GFP_KERNEL); 807 if (!dev_priv->fake_dma.handle) { 808 DRM_ERROR("could not allocate faked DMA buffer!\n"); 809 savage_do_cleanup_bci(dev); 810 return -ENOMEM; 811 } 812 dev_priv->cmd_dma = &dev_priv->fake_dma; 813 dev_priv->dma_flush = savage_fake_dma_flush; 814 } 815 816 dev_priv->sarea_priv = 817 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle + 818 init->sarea_priv_offset); 819 820 /* setup bitmap descriptors */ 821 { 822 unsigned int color_tile_format; 823 unsigned int depth_tile_format; 824 unsigned int front_stride, back_stride, depth_stride; 825 if (dev_priv->chipset <= S3_SAVAGE4) { 826 color_tile_format = dev_priv->fb_bpp == 16 ? 827 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 828 depth_tile_format = dev_priv->depth_bpp == 16 ? 829 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 830 } else { 831 color_tile_format = SAVAGE_BD_TILE_DEST; 832 depth_tile_format = SAVAGE_BD_TILE_DEST; 833 } 834 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); 835 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); 836 depth_stride = 837 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); 838 839 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 840 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 841 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 842 843 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 844 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 845 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 846 847 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 848 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 849 (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 850 } 851 852 /* setup status and bci ptr */ 853 dev_priv->event_counter = 0; 854 dev_priv->event_wrap = 0; 855 dev_priv->bci_ptr = (volatile uint32_t *) 856 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); 857 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 858 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 859 } else { 860 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; 861 } 862 if (dev_priv->status != NULL) { 863 dev_priv->status_ptr = 864 (volatile uint32_t *)dev_priv->status->handle; 865 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 866 dev_priv->wait_evnt = savage_bci_wait_event_shadow; 867 dev_priv->status_ptr[1023] = dev_priv->event_counter; 868 } else { 869 dev_priv->status_ptr = NULL; 870 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 871 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; 872 } else { 873 dev_priv->wait_fifo = savage_bci_wait_fifo_s4; 874 } 875 dev_priv->wait_evnt = savage_bci_wait_event_reg; 876 } 877 878 /* cliprect functions */ 879 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) 880 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; 881 else 882 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; 883 884 if (savage_freelist_init(dev) < 0) { 885 DRM_ERROR("could not initialize freelist\n"); 886 savage_do_cleanup_bci(dev); 887 return -ENOMEM; 888 } 889 890 if (savage_dma_init(dev_priv) < 0) { 891 DRM_ERROR("could not initialize command DMA\n"); 892 savage_do_cleanup_bci(dev); 893 return -ENOMEM; 894 } 895 896 return 0; 897} 898 899static int savage_do_cleanup_bci(struct drm_device * dev) 900{ 901 drm_savage_private_t *dev_priv = dev->dev_private; 902 903 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { 904 kfree(dev_priv->fake_dma.handle); 905 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle && 906 dev_priv->cmd_dma->type == _DRM_AGP && 907 dev_priv->dma_type == SAVAGE_DMA_AGP) 908 drm_core_ioremapfree(dev_priv->cmd_dma, dev); 909 910 if (dev_priv->dma_type == SAVAGE_DMA_AGP && 911 dev->agp_buffer_map && dev->agp_buffer_map->handle) { 912 drm_core_ioremapfree(dev->agp_buffer_map, dev); 913 /* make sure the next instance (which may be running 914 * in PCI mode) doesn't try to use an old 915 * agp_buffer_map. */ 916 dev->agp_buffer_map = NULL; 917 } 918 919 kfree(dev_priv->dma_pages); 920 921 return 0; 922} 923 924static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 925{ 926 drm_savage_init_t *init = data; 927 928 LOCK_TEST_WITH_RETURN(dev, file_priv); 929 930 switch (init->func) { 931 case SAVAGE_INIT_BCI: 932 return savage_do_init_bci(dev, init); 933 case SAVAGE_CLEANUP_BCI: 934 return savage_do_cleanup_bci(dev); 935 } 936 937 return -EINVAL; 938} 939 940static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) 941{ 942 drm_savage_private_t *dev_priv = dev->dev_private; 943 drm_savage_event_emit_t *event = data; 944 945 DRM_DEBUG("\n"); 946 947 LOCK_TEST_WITH_RETURN(dev, file_priv); 948 949 event->count = savage_bci_emit_event(dev_priv, event->flags); 950 event->count |= dev_priv->event_wrap << 16; 951 952 return 0; 953} 954 955static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) 956{ 957 drm_savage_private_t *dev_priv = dev->dev_private; 958 drm_savage_event_wait_t *event = data; 959 unsigned int event_e, hw_e; 960 unsigned int event_w, hw_w; 961 962 DRM_DEBUG("\n"); 963 964 UPDATE_EVENT_COUNTER(); 965 if (dev_priv->status_ptr) 966 hw_e = dev_priv->status_ptr[1] & 0xffff; 967 else 968 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 969 hw_w = dev_priv->event_wrap; 970 if (hw_e > dev_priv->event_counter) 971 hw_w--; /* hardware hasn't passed the last wrap yet */ 972 973 event_e = event->count & 0xffff; 974 event_w = event->count >> 16; 975 976 /* Don't need to wait if 977 * - event counter wrapped since the event was emitted or 978 * - the hardware has advanced up to or over the event to wait for. 979 */ 980 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) 981 return 0; 982 else 983 return dev_priv->wait_evnt(dev_priv, event_e); 984} 985 986/* 987 * DMA buffer management 988 */ 989 990static int savage_bci_get_buffers(struct drm_device *dev, 991 struct drm_file *file_priv, 992 struct drm_dma *d) 993{ 994 struct drm_buf *buf; 995 int i; 996 997 for (i = d->granted_count; i < d->request_count; i++) { 998 buf = savage_freelist_get(dev); 999 if (!buf) 1000 return -EAGAIN; 1001 1002 buf->file_priv = file_priv; 1003 1004 if (DRM_COPY_TO_USER(&d->request_indices[i], 1005 &buf->idx, sizeof(buf->idx))) 1006 return -EFAULT; 1007 if (DRM_COPY_TO_USER(&d->request_sizes[i], 1008 &buf->total, sizeof(buf->total))) 1009 return -EFAULT; 1010 1011 d->granted_count++; 1012 } 1013 return 0; 1014} 1015 1016int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1017{ 1018 struct drm_device_dma *dma = dev->dma; 1019 struct drm_dma *d = data; 1020 int ret = 0; 1021 1022 LOCK_TEST_WITH_RETURN(dev, file_priv); 1023 1024 /* Please don't send us buffers. 1025 */ 1026 if (d->send_count != 0) { 1027 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1028 DRM_CURRENTPID, d->send_count); 1029 return -EINVAL; 1030 } 1031 1032 /* We'll send you buffers. 1033 */ 1034 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1035 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1036 DRM_CURRENTPID, d->request_count, dma->buf_count); 1037 return -EINVAL; 1038 } 1039 1040 d->granted_count = 0; 1041 1042 if (d->request_count) { 1043 ret = savage_bci_get_buffers(dev, file_priv, d); 1044 } 1045 1046 return ret; 1047} 1048 1049void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) 1050{ 1051 struct drm_device_dma *dma = dev->dma; 1052 drm_savage_private_t *dev_priv = dev->dev_private; 1053 int i; 1054 1055 if (!dma) 1056 return; 1057 if (!dev_priv) 1058 return; 1059 if (!dma->buflist) 1060 return; 1061 1062 /*i830_flush_queue(dev); */ 1063 1064 for (i = 0; i < dma->buf_count; i++) { 1065 struct drm_buf *buf = dma->buflist[i]; 1066 drm_savage_buf_priv_t *buf_priv = buf->dev_private; 1067 1068 if (buf->file_priv == file_priv && buf_priv && 1069 buf_priv->next == NULL && buf_priv->prev == NULL) { 1070 uint16_t event; 1071 DRM_DEBUG("reclaimed from client\n"); 1072 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); 1073 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); 1074 savage_freelist_put(dev, buf); 1075 } 1076 } 1077 1078 drm_core_reclaim_buffers(dev, file_priv); 1079} 1080 1081struct drm_ioctl_desc savage_ioctls[] = { 1082 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1083 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1084 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), 1085 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), 1086}; 1087 1088int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); 1089